A method for grouping and splitting through-hole design in guided self-assembly chips based on generational solution

Abstract

A method for grouping and splitting a self-assembling chip through-hole design based on generational solution, by applying generational solution and graph theory algorithm, the unprocessed chip through-hole design is processed, and the through-holes in the design are grouped and split; forming a fast processing method that can balance the number of coloring and the number of grouping. The present invention can form a fast processing method that can balance the number of coloring and the number of grouping, and can group and split a large-scale layout in a short time.

Description

[0001] Technology Neighborhood

[0002] The invention relates to a photolithography resolution enhancement technology, and in particular to a through-hole pattern grouping and splitting method processed by a guided self-assembly technology. Background Art

[0003] Photolithography is a key technology in the manufacture of very large-scale integrated circuits. Photolithographic resolution determines the characteristic size of integrated circuits. Guided self-assembly (DSA) technology is one of the hot candidate technologies for the next generation of material-driven resolution enhancement technology, and is regarded by the semiconductor industry as the next generation of photolithography technology. The key technologies involved in DSA technology include grouping and splitting of chip design drawings, template manufacturing, and microphase separation structure control. Grouping and splitting of chip design drawings is the first step in the implementation of the DSA process. The main function of this technology is to transform traditional chip designs into designs that can be applied to DSA, which is one of the key steps in the application of DSA technology.

[0004] The periodic structure processed by DSA technology has strong uniformity of size, low line edge roughness and line width roughness, and has great potential in integrated circuit manufacturing. However, it is difficult to achieve precise control of the structure with current technology, and the defect rate of the current mainstream technology is about 1 to 10 / cm 2 Much higher than the 0.01 / cm required for mass production of logic circuits 2 . In view of the above advantages and disadvantages, DSA technology was first applied to the processing of the through-hole layer. In accordance with the technical requirements of DSA, it is necessary to first use traditional photolithography technology to process the guide template. Due to material and process limitations, only through holes with a certain spacing range can be assigned to the same guide template. In addition, the number of through holes in the same template is also limited to three due to the yield. In addition, if only 193nm photolithography technology is used to process the template, the template direction can only be horizontal or vertical, and the shape can only be linear. Under the above design rule requirements, the through holes first need to be grouped to form a guide template, and then the guide templates of different through holes are assigned to different masks, so as to finally convert the original design drawing into a conflict-free guide template design drawing on multiple masks.

[0005] The method of grouping and splitting through holes is one of the key technologies to ensure the implementation of DSA technology. There are currently many technical solutions. For example, methods based on integer linear programming (prior art 1, BadrY, TorresA, Gupta. Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts / Vias. Proc. of 52nd ACM / EDAC / IEEE Design Automation Conference (DAC). IEEE, 2015; 1-6), methods based on maximum cardinality matching (prior art 2. BadrY, TorresA, Gupta. Mask Assignment and Synthesis of DSA-MP Hybrid Lithography for sub-7nm Contacts / Vias. Proc. of 52nd ACM / EDAC / IEEE Design Automation Conference (DAC). IEEE, 2015; 1-6), and methods based on tree solving (prior art 3. Karageorgos, I. et al., 2016. Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7nm circuits. Journal of micro / nanolithography, MEMS, and MOEMS, 15(4), p.043506.), based on maximal independent subsets (prior art 4. Kuang J, Ye J, Young E FY Simultaneous Template Optimization and Mask Assignment for DSA with Multiple Patterning. Proc. of IEEE / ACM Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2016; 75-82), based on table lookup (prior art 5. Kuang J, Ye J, Young E FY Simultaneous Template Optimization and Mask Assignment for DSA with Multiple Patterning. Proc.of IEEE / ACM Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2016, 75-82) etc. Prior art 1 uses mathematical modeling and linear programming to solve, but the solution complexity is very high and is not suitable for large-scale layouts; Prior art 3 searches for the optimal solution by traversing the set of solutions composed of all possible groups, but the complexity is very high and is not suitable for large-scale layouts; Prior art 4 first exhaustively enumerates all combinations of compatible edges, calls the odd-degree vertex solver for each compatible edge set, and finally selects the solution with the lowest cost as the final solution. Since the number of compatible edges grows exponentially with the size of the layout, this method is also not suitable for large-scale layouts. Prior art 5 builds an optimal solution library for all possible subgraphs with a vertex number not greater than 7. For the part of the conflicting subgraph in the library, it is solved by table lookup, and the part not in the library is solved by heuristic method. However, for all possible subgraphs with a vertex number greater than 7, the complexity of building the library is too high, and this method is also not suitable for large-scale layouts. .

[0006] Prior art 2 first calculates the maximum cardinality match, then removes the edges in the result (edges indicate that two connected points conflict and cannot be assigned to the same template), and then uses the existing mask assignment method to assign masks to all points. If two through holes are assigned to the same mask and can be divided into the same group, the two through holes are assigned to the same group. This method is not complex and is suitable for large-scale layouts, but it will cause many conflicts to be unresolved and high-quality results cannot be obtained. Summary of the invention

[0007] The purpose of the present invention is to provide a method for grouping and splitting through-hole design of guided self-assembly chip based on generational solution, propose a grouping algorithm and a splitting algorithm based on generational solution, and form a fast processing technology that can balance the number of layers and the number of groups.

[0008] The technical solution of the present invention is as follows:

[0009] A method for grouping and splitting through-hole design of guided self-assembly chip based on generational solution, comprising the following steps:

[0010] Step 1. Read the GDS chip file, sort all the through holes on the chip from 1 to n, and use the geometric center point of each through hole as the position of each through hole; set the lithography resolution Litho_distance and the distance interval TwoVias_distance of the double hole grouping;

[0011] The process of dividing the guide template into different masks is represented by the guide template coloring, that is, the guide templates colored with the same color are assigned to the same mask, and the coloring number represents the number of masks required; the maximum coloring number n and the minimum distance at which the coloring does not affect each other are set as Color_distance;

[0012] Step 2. Construct the adjacency distance matrix decomp_result_matrix: the serial number of the through hole is used as the number of rows and columns of the matrix, the element value of the nth row and the mth column in the matrix is ​​the Euclidean distance between the position of the nth through hole and the position of the mth through hole, and when n=m, the element value is 0;

[0013] Step 3. Construct the adjacency matrix cluster_result_matrix: set the value of the element in the adjacency distance matrix decomp_result_matrix that is less than or equal to the lithography resolution Litho_distance to "1", and set the value that is greater than the lithography resolution Litho_distance to "0";

[0014] Step 4. Obtain the maximum connected graph of the adjacency matrix cluster_result_matrix through the Kosaraju algorithm, and record the points in each connected graph; the points in each connected graph constitute a sequence cluster i , all the series cluster i Construct the array set clusters;

[0015] Step 5. Traverse all the sequence clusters in the sequence set clusters i , and group and split each sequence cluster, including:

[0016] Step 5.1 Randomly select a random number of vias, treat a single via or two vias within the distance interval TwoVias_distance as a group, record it as match, and enumerate the group matches containing the selected vias i , and store it in the list matches;

[0017] Step 5.2 Randomly select a random number of group matches from the list matches j , and store it in the list Generation;

[0018] Step 5.3 Match each group in the list Generation j All adjacent through holes are merged to form a boundary pattern;

[0019] Step 5.4 Randomly select a random number of through holes from the boundary shape and enumerate the group matches containing the selected through holes k , and store it in the list match_candidate;

[0020] Step 5.5 Randomly select a random number from the list match_candidate and match the groups in the list Generation j Non-overlapping groups matchg, and g∈k, group match g Store in list Generation;

[0021] Step 5.6 Match each group newly added to the list Generation g The adjacent through holes are added to the boundary graphics, and the boundary graphics are updated;

[0022] Step 5.7 Repeat steps 5.4-5.6 until all through holes in the current cluster are grouped;

[0023] Step 6. Use the vertex coloring method to color all groups: select the vertex with the smallest degree, color it with the first color, then find a vertex that does not conflict with its coloring and randomly select a vertex to color with the same color, then find a vertex that does not conflict with the coloring of the two colored vertices, and color one of the vertices with the same color, until no vertex that can be colored with the current color is found; then find the uncolored vertex with the smallest degree, change the color, and repeat the above process until all vertices are colored.

[0024] Step 7. Repeat steps 5-6 until all through-holes on the chip are grouped and dyed.

[0025] Step 8. Write the processing grouping and staining results to the GDS file output.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] Compared with the prior arts 1, 3, 4, 5, the present invention reduces the complexity by using graph theory and random boundary growth instead of mathematical modeling or enumeration solutions, and is suitable for solving large-scale layouts with a high number of through holes.

[0028] Compared with the prior art 2, the present invention generates groups in a generational manner, avoiding the situation of conflict points and being able to quickly generate a group splitting result of a large-scale layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Group dyeing flow chart of the present invention

[0030] Figure 2 Example diagram of the adjacency matrix of the present invention

[0031] Figure 3 Flowchart of the generational solution algorithm of the present invention

[0032] Figures 4.1 to 4.3 This is an example diagram of the generational solution algorithm of the present invention, wherein: Figure 4.1 It means that the two figures in the oval box are grouped together. The square box represents a figure, and the oval box represents a group; Figure 4.2 Indicates the selected boundary shape in the circle; Figure 4.3 Indicates the group selected in the ellipse;

[0033] Figure 5 Final effect illustration of the present invention DETAILED DESCRIPTION

[0034] The present invention will be further described below in conjunction with embodiments and drawings, but the protection scope of the present invention should not be limited by these embodiments.

[0035] The group dyeing process of the embodiment of the present invention is as follows Figure 1 As shown. Figure 2 The adjacency matrix shown is grouped and colored. Figure 2 The value in represents the distance between the center points of the two through holes. In the example, a rectangular through hole with a size of 16*16nm is used, the optical resolution distance is 120nm, the dyeing distance is 60nm, and the double hole grouping distance interval is 32~60nm.

[0036] The steps of the embodiment are as follows:

[0037] Step 1. Read the GDS chip file, sort all the through holes on the chip from 1 to n, and use the geometric center point of each through hole as the position of each through hole; set the lithography resolution Litho_distance = 120, and the distance interval TwoVias_distance of the double hole grouping to [32, 60];

[0038] The process of dividing the guide template into different masks is represented by the guide template coloring, that is, the guide templates colored with the same color are assigned to the same mask, and the coloring number represents the number of masks required; the maximum coloring number n and the minimum distance at which the coloring does not affect each other are set to Color_distance=60;

[0039] Step 2. Figure 2 The adjacency distance matrix decomp_result_matrix is ​​constructed as shown: the serial number of the through hole is used as the number of rows and columns of the matrix, the element value of the nth row and the mth column in the matrix is ​​the Euclidean distance between the position of the nth through hole and the position of the mth through hole, and when n=m, the element value is 0;

[0040] Step 3. Construct the adjacency matrix cluster_result_matrix: set the value of the element in the adjacency distance matrix decomp_result_matrix that is less than or equal to the lithography resolution Litho_distance to "1", and set the value that is greater than the lithography resolution Litho_distance to "0";

[0041] Step 4. Obtain the maximum connected graph of the adjacency matrix cluster_result_matrix through the Kosaraju algorithm, and record the points in each connected graph; the points in each connected graph constitute a sequence cluster i , all the series cluster i Construct the array set clusters;

[0042] Step 5. Traverse all the sequence clusters in the sequence set clusters i , and group and split each sequence cluster, including:

[0043] The generational solution algorithm of the present invention is shown in the flowchart as follows: Figure 3 As shown, the following steps are included:

[0044] Step 5.1 Randomly select a random number of vias, treat a single via or two vias in the distance zone TwoVias_distance as a group, record it as match, and enumerate the group matches containing the selected vias i , and store it in the list matches;

[0045] Step 5.2 Randomly select a random number of group matches from the list matches j like Figure 4.1 As shown, and stored in the list Generation;

[0046] Step 5.3 Match each group in the list Generation j All adjacent through holes are merged to form a boundary pattern such as Figure 4.2 As shown;

[0047] Step 5.4 Randomly select a random number of through holes from the boundary shape and enumerate the group matches containing the selected through holes k , and store it in the list match_candidate;

[0048] Step 5.5 Randomly select a random number from the list match_candidate and match the groups in the list Generation jNon-overlapping groups matchg, and g∈k, group match g Stored in list Generation, such as Figure 4.3 As shown;

[0049] Step 5.6 Match each group newly added to the list Generation g The adjacent through holes are added to the boundary graphics, and the boundary graphics are updated;

[0050] Step 5.9: Repeat steps 5.4-5.6 until all through holes in the current cluster are grouped;

[0051] Step 6. Use the vertex coloring method to color all groups: select the vertex with the smallest degree, color it with the first color, then find a vertex that does not conflict with its coloring and randomly select a vertex to color with the same color, then find a vertex that does not conflict with the coloring of the two colored vertices, and color one of the vertices with the same color, until no vertex that can be colored with the current color is found; then find the uncolored vertex with the smallest degree, change the color, and repeat the above process until all vertices are colored.

[0052] Step 7. Repeat steps 5-6 until all through-holes on the chip are grouped and dyed.

[0053] Step 8. Write the processing grouping and staining results to the GDS file output.

[0054] like Figure 5 As shown, the left and right dashes and solid boxes represent the groups that are split into different layers. This method groups 10066 through holes into several groups within 400 seconds and splits them onto a multi-layer mask. All through hole groups and splits meet the given constraints such as the spacing between through holes in the group and the spacing between groups.

Claims

1. A method for grouping and splitting through-hole design of guided self-assembly chips based on generational solution, characterized in that: The steps include: Step 1. Read the GDS chip file, sort all the through holes on the chip from 1 to n, and use the geometric center point of each through hole as the position of each through hole; set the lithography resolution Litho_distance and the distance interval TwoVias_distance of the double hole grouping; The process of dividing the guide template into different masks is represented by the guide template coloring, that is, the guide templates colored with the same color are assigned to the same mask, and the coloring number represents the number of masks required; the maximum coloring number n and the minimum distance at which the coloring does not affect each other are set as Color_distance; Step 2. Construct the adjacency distance matrix decomp_result_matrix: the serial number of the through hole is used as the number of rows and columns of the matrix, the element value of the nth row and the mth column in the matrix is ​​the Euclidean distance between the position of the nth through hole and the position of the mth through hole, and when n=m, the element value is 0; Step 3. Construct the adjacency matrix cluster_result_matrix: set the value of the element in the adjacency distance matrix decomp_result_matrix that is less than or equal to the lithography resolution Litho_distance to "1", and set the value that is greater than the lithography resolution Litho_distance to "0"; Step 4. Obtain the maximum connected graph of the adjacency matrix cluster_result_matrix through the Kosaraju algorithm, and record the points in each connected graph; the points in each connected graph constitute a sequence cluster i , all the series cluster i Construct the array set clusters; Step 5. Traverse all the sequence clusters in the sequence set clusters i , and group and split each sequence cluster, including: Step 5.1 Randomly select a random number of vias, treat a single via or two vias within the distance interval TwoVias_distance as a group, record it as match, and enumerate the group matches containing the selected vias i , and store it in the list matches; Step 5.2 Randomly select a random number of group matches from the list matches j , and store it in the list Generation; Step 5.3 Match each group in the list Generation j All adjacent through holes are merged to form a boundary pattern; Step 5.4 Randomly select a random number of through holes from the boundary shape and enumerate the group matches containing the selected through holes k , and store it in the list match_candidate; Step 5.5 Randomly select a random number from the list match_candidate and match the groups in the list Generation j Non-overlapping group matches g , and g∈k, the grouping match g Store in list Generation; Step 5.6 Match each group newly added to the list Generation g The adjacent through holes are added to the boundary graphics, and the boundary graphics are updated; Step 5.8: Repeat steps 5.4-5.6 until all through holes in the current cluster are grouped; Step 6. Use vertex coloring method to color all groups; Step 7. Repeat steps 5-6 until all through-holes on the chip are grouped and dyed.

2. The method for grouping and splitting through-hole design of guided self-assembly chip based on generational solution according to claim 1 is characterized in that: Step 6: Use the vertex coloring method to color all groups. Specifically, select the vertex with the smallest degree, color it with the first color, then find a vertex that does not conflict with its coloring and randomly select a vertex to color with the same color, then find a vertex that does not conflict with the coloring of the two colored vertices, and color one of the vertices with the same color, until no vertex that can be colored with the current color is found; Then find the uncolored vertex with the smallest degree, change its color, and repeat the above process until all vertices are colored.

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