A pixel address encoding circuit with time information suitable for SPAD array

Abstract

The present invention provides a pixel address encoding circuit with time information suitable for a SPAD array. The circuit includes a SPAD detection array composed of N SPAD detection units, two delay chains, two TDC circuits and a readout circuit. The SPAD detection unit is used to detect photons and output voltage pulses; the two delay chains transmit delays in opposite directions, each delay chain includes N basic delay units with a delay time of τ, each SPAD detection unit is simultaneously connected to the corresponding basic delay units in the two delay chains, and the voltage pulse output by the SPAD detection unit is simultaneously transmitted in the two delay chains in the reverse direction; the ends of the two delay chains are respectively connected to a TDC circuit; the readout circuit reads the data of the two TDC circuits. The present invention adopts a digital circuit solution, has a simple structure, does not require a special decoding circuit to extract address data, and can directly obtain pixel address information by calculation.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits of a single photon avalanche diode detector array, and in particular to a pixel address coding circuit with time information suitable for a SPAD array. Background Art

[0002] Single Photon Avalanche Diode (SPAD) is a photoelectric detection device with the characteristics of fast response and high gain. The SPAD device works in Geiger mode. When the SPAD detects a photon input, it outputs a pulse signal under the joint action of the quenching circuit. The rise time of the pulse signal is extremely short, and it can effectively carry time information after the shaping circuit, and is often used in time-of-flight ranging laser radar.

[0003] In the process of SPAD array integration, the matching problem of SPAD devices and TDC circuits needs to be considered. Usually, a single pixel is configured with a TDC circuit or a pixel array array is configured with a column of TDC circuits. However, the method of configuring a single pixel with a TDC circuit has the disadvantages of large array layout area, low pixel duty cycle, and high power consumption; the method of configuring a pixel array array with a column of TDC circuits has the disadvantage that the array array cannot work at the same time. For this reason, a pixel address encoding circuit with time information suitable for SPAD array is needed. A SPAD array is configured with several TDC circuits. The position information of the device that responds is inferred through the address encoding information, so that the array can work simultaneously while reducing the layout area, improving the pixel duty cycle, and reducing power consumption. If the existing encoding circuit is implemented by combinational logic, the circuit generally requires a more complex circuit and needs to be coordinated with a dedicated decoding circuit; if it is implemented by analog methods such as resistor voltage division, the circuit response speed is slow and there is a certain static power consumption. Summary of the invention

[0004] In view of the problems existing in device and circuit matching during the array integration process of SPAD detectors and the shortcomings of existing address coding circuits, the present invention proposes a pixel address coding circuit with time information suitable for SPAD arrays, which can convert optical signals into signals with address information at high speed for external output, and obtain corresponding address information by reverse deducing the time information of the signal.

[0005] The technical solution adopted by the present invention is:

[0006] A pixel address encoding circuit with time information suitable for a SPAD array comprises a SPAD detection array composed of N SPAD detection units, two delay chains, two TDC circuits and a readout circuit, wherein the SPAD detection units are used to detect photons and output voltage pulses; the two delay chains transmit delays in opposite directions, each delay chain comprises N basic delay units with a delay time of τ, each SPAD detection unit is simultaneously connected to the corresponding basic delay units in the two delay chains, and the voltage pulses output by the SPAD detection units are simultaneously transmitted in the reverse direction in the two delay chains; the ends of the two delay chains are respectively connected to a TDC circuit; the readout circuit reads the data of the two TDC circuits, and obtains the pixel address information and the pulse time information through calculation.

[0007] Furthermore, each delay chain uses a two-input OR gate as a basic delay unit, the first input end of the two-input OR gate is connected to the output end of the SPAD detection unit, and the second input end is connected to the output end of the two-input OR gate of the previous level, and the output end of the two-input OR gate is connected to the second input end of the two-input OR gate of the next level. A column of two-input OR gates are connected in the above manner to form a delay chain; the second input end of the two-input OR gate of the first level of the delay chain is grounded, and "0" is always input; the output end of the two-input OR gate of the last level is connected to the TDC circuit.

[0008] Furthermore, the SPAD detection unit includes a SPAD device, a quenching circuit and a shaping circuit. After the SPAD device responds, under the action of the quenching circuit and the shaping circuit, it outputs a voltage pulse to the outside. The voltage pulse carries time information and is transmitted reversely to two TDC circuits in two delay chains, triggering the TDC circuit to generate time information.

[0009] Furthermore, the time when the photon reaches the i-th SPAD detection unit is T ti , is transmitted to the upper TDC circuit through the upward delay chain, and the detected time is T1 = T ti +iτ, is transmitted to the lower end TDC circuit through the delay chain, and the detected time is T2 = T ti +(N-i+1)τ, the position of the SPAD detection unit that responds is calculated as At the same time, the photon arrival time is

[0010] Furthermore, the readout circuit is composed of 2 D flip-flops, 1 AND gate and 1 FIFO circuit. The pulse signal generated by the SPAD detection unit is transmitted in reverse along the two delay chains transmitted upward and downward, and reaches the corresponding two TDC circuits to trigger TDC timing. At the same time, the two signals respectively trigger the two D flip-flops to generate a high level, indicating that a trigger is generated in the pixel cluster at this time; then, the FIFO circuit reads the data in the two TDC circuits under the drive of the system clock, and resets the two D flip-flop circuits by the Reset signal after the data reading is completed, so as to realize the detection of the next data.

[0011] Furthermore, N SPAD detection units are arranged in a column or a row in a one-dimensional direction to form a single-column or single-row linear SPAD detection array, and two delay chains, two TDC circuits and a readout circuit are configured to form a linear SPAD detector; the two delay chains are composed of 2N basic delay units arranged in two columns or two rows on one side of the linear SPAD detection array, and the two TDC circuits are respectively arranged on the upper and lower sides of the area composed of the linear SPAD detection array and the two delay chains; the output of each SPAD detection unit is simultaneously connected to the basic delay unit at the corresponding position of the two delay chains, and the time information recorded by the two TDC circuits is used to reversely infer the one-dimensional address information and time information of the SPAD detection unit that responds.

[0012] Furthermore, M linear SPAD detection arrays are closely arranged in the two-dimensional direction to form an N×M planar array, and each linear SPAD detection array is configured with 2 delay chains, 2 TDC circuits and a readout circuit to form M columns of planar SPAD detectors working in parallel; each column of the linear array can work independently to generate a one-dimensional address information, which can be combined with the address information of the column in which it is located to obtain the two-dimensional address information.

[0013] Furthermore, N SPAD detection units are arranged in sequence in a serpentine or Hilbert curve manner to form a two-dimensional array with a single-chain structure, forming an array SPAD detection array, and two delay chains, two TDC circuits and a readout circuit are configured to form an array SPAD detector; the two delay chains are composed of 2N basic delay units tightly arranged in the same form in the array SPAD detection array, and the two TDC circuits are respectively arranged on the upper and lower sides of the area composed of the array SPAD detection array and the two delay chains; the output of each SPAD detection unit is simultaneously connected to the basic delay unit at the corresponding position of the two delay chains, and the one-dimensional address information and time information of the responding SPAD detection unit are reversed from the time information recorded by the two TDC circuits, and then the two-dimensional address information of the responding SPAD detection unit is reversed based on the known arrangement information.

[0014] The present invention adopts SPAD device as photoelectric detection device, utilizes the easy excitation characteristic of SPAD device to accurately detect light signal and generate pulse voltage signal, uses the generated pulse voltage signal as the input signal of delay chain, and calculates the position information of SPAD device that responds by reading the time information recorded by TDC circuit at the end of two delay chains, so as to achieve address coding effect. The present invention adopts digital circuit to read out pixel address information, does not need special decoding circuit to extract address data, can directly obtain pixel address information by calculation, so the circuit is easy to standardize, easy to migrate, and has strong anti-interference ability. At the same time, the time information of original photoelectric response signal can be output in the address coding process, and the signal can be processed in subsequent processing, which is suitable for SPAD arrays that need time information and address coding information, such as time of flight (ToF) arrays.

[0015] Compared with the existing area array reading technology, the present invention uses address coding technology, the whole frame reading time is short, which is conducive to high frame rate reading; at the same time, the digital circuit structure is relatively simple, which is conducive to on-chip integration and fidelity. In addition, the technology of the present invention can also be used for position sensor design. Compared with the existing position sensor technology, the present invention uses SPAD devices as detection units, which have higher sensitivity and are more susceptible to photon triggering. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of a pixel address encoding circuit with time information applicable to a SPAD array proposed by the present invention.

[0017] Figure 2 It is a schematic diagram of the working principle of a pixel address encoding circuit with time information applicable to a SPAD array proposed by the present invention.

[0018] Figure 3 It is a structural schematic diagram of a SPAD detection unit in a pixel address encoding circuit proposed by the present invention.

[0019] Figure 4 It is a structural schematic diagram of a readout circuit in a pixel address encoding circuit proposed by the present invention.

[0020] Figure 5 It is a schematic diagram of a linear array SPAD detector formed by arranging the pixel address encoding circuits proposed in the present invention in a linear array form.

[0021] Figure 6 It is a schematic diagram of a planar array SPAD detector formed by arranging the pixel address encoding circuits proposed in the present invention in a planar array form.

[0022] Figure 7 The present invention proposes a planar array formed by (a) serpentine arrangement and (b) Hilbert curve arrangement taking 16 SPAD detection units as an example.

[0023] Figure 8 It is a schematic diagram of a two-dimensional array sensor formed by multiple linear array SPAD detectors proposed in the present invention. DETAILED DESCRIPTION

[0024] The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The described specific embodiments are only used to explain the present invention and are not used to limit the present invention.

[0025] Figure 1 It is a schematic diagram of the structure of a pixel address encoding circuit with time information suitable for a SPAD array proposed by the present invention. The circuit includes a SPAD detection array composed of N SPAD detection units, 2 delay chains, 2 TDC circuits and a readout circuit. The SPAD detection unit includes a SPAD device, a quenching circuit and a shaping circuit, and outputs a voltage pulse at the output end after detecting a photon. The delay chain uses a two-input OR gate (or gate) as a basic delay unit, the first input end of the two-input OR gate is connected to the output end of the SPAD detection unit, the second input end is connected to the output end of the two-input OR gate of the previous level, the output end of the two-input OR gate is connected to the second input end of the two-input OR gate of the next level, and a column of two-input OR gates is connected in the described manner to form a delay chain. The second input end of the two-input OR gate of the first level of the delay chain is grounded, and "0" is always input; the output end of the two-input OR gate of the last level is connected to the TDC circuit. The voltage pulse output by the SPAD detection unit is simultaneously connected to the two delay chains for upward and downward transmission for reverse transmission; the two pulses transmitted in the reverse direction pass through the two delay chains and reach the corresponding two TDC circuits respectively, triggering TDC timing; the readout circuit reads the data of the two TDC circuits, and obtains the pixel address information and pulse time information through calculation.

[0026] Figure 2 This is a schematic diagram of the working principle of the pixel address encoding circuit with time information suitable for the SPAD array proposed in the present invention. The pixel address encoding circuit is composed of 2 delay chains and 2 TDC circuits, and each delay chain circuit is composed of N identical OR gates and a power ground. Each OR gate serves as a basic delay unit, and its delay time is τ. One end of the two-input OR gate of each delay chain is connected to the pulse output end of the SPAD, and the other end is connected to the output end of the previous OR gate. The output time of the SPAD detection unit at different positions after responding through the delay chain is also different. The time when the photon reaches the i-th SPAD detection unit is taken as T ti , is transmitted to the upper TDC circuit through the upward delay chain, and the detected time is T1 = T ti +iτ, is transmitted to the lower end TDC circuit through the delay chain, and the detected time is T2 = Tti +(N-i+1)τ, the position of the SPAD detection unit that responds is calculated as At the same time, the photon arrival time is

[0027] Figure 3 It is a structural schematic diagram of the SPAD detection unit in the pixel address encoding circuit proposed in the present invention. The SPAD detection unit includes a SPAD device, a quenching circuit and a shaping circuit. The SPAD device is a single-photon avalanche diode, which works in Geiger mode. After the single-photon avalanche diode avalanches, it is quenched by the quenching circuit and shaped by the shaping circuit to generate a pulse voltage signal, and the pulse voltage signal is connected to an input end of the OR gate. When a photon reaches the SPAD device and responds, the SPAD device will avalanche breakdown and output a continuous large current. The quenching circuit includes active quenching and passive quenching. The figure takes the simplest passive quenching resistor quenching as an example. When the SPAD device avalanche breakdown occurs, the current passes through the resistor voltage divider, so that the voltage at both ends of the SPAD device is reduced to near or below the breakdown point, thereby quenching occurs and gradually recovers to the waiting mode. The shaping circuit is used to convert the voltage output during the entire process of SPAD avalanche breakdown and quenching recovery into a pulse voltage signal. When the SPAD responds, the shaping circuit outputs a voltage signal of "1", and when there is no response, the shaping circuit outputs a voltage signal of "0".

[0028] Figure 4 It is a structural schematic diagram of the readout circuit in the pixel address encoding circuit proposed in the present invention. The readout circuit is composed of 2 D flip-flops, 1 AND gate and 1 FIFO circuit. The pulse signal generated by the SPAD detection unit is transmitted in reverse along the two delay chains transmitted upward and downward, and reaches the corresponding two TDC circuits to trigger TDC timing. At the same time, the two signals respectively trigger the two D flip-flops to generate a high level, indicating that a trigger is generated in the pixel cluster at this time. Afterwards, the FIFO circuit reads the data in the two TDC circuits under the drive of the system clock, and resets the two flip-flop circuits by the Reset signal after the data reading is completed, so as to realize the detection of the next data.

[0029] Figure 5It is a schematic diagram of a linear array SPAD detector formed by arranging the pixel address encoding circuit proposed in the present invention in the form of a linear array. N SPAD detection units are arranged in a column or a row in a one-dimensional direction to form a single-column or single-row linear array SPAD detection array, and two delay chains, two TDC circuits and a readout circuit are configured to form a linear array SPAD detector. The two delay chains are composed of 2N basic delay units arranged in two columns or two rows on one side of the linear array SPAD detection array, and the two TDC circuits are arranged on the upper and lower sides of the area composed of the linear array SPAD detection array and the two delay chains respectively; the output of each SPAD detection unit is simultaneously connected to the basic delay unit at the corresponding position of the two delay chains, and the time information recorded by the two TDC circuits is used to reversely infer the one-dimensional address information and time information of the SPAD detection unit that responded.

[0030] Figure 6 It is a schematic diagram of a planar array SPAD detector formed by arranging the pixel address encoding circuit proposed in the present invention in the form of a planar array. N SPAD detection units are arranged in sequence in a serpentine or Hilbert curve manner to form a two-dimensional planar array of a single-chain structure to form a planar array SPAD detection array, and two delay chains, two TDC circuits and a readout circuit are configured to form a planar array SPAD detector. The two delay chains are composed of 2N basic delay units tightly arranged in the planar array SPAD detection array in the same form, and the two TDC circuits are arranged on the upper and lower sides of the area composed of the planar array SPAD detection array and the two delay chains. The output of each SPAD detection unit is simultaneously connected to the basic delay unit at the corresponding position of the two delay chains, and the time information recorded by the two TDC circuits is used to reversely infer the one-dimensional address information and time information of the SPAD detection unit that responds, and then the two-dimensional address information of the SPAD detection unit that responds is reversed based on the known specific arrangement information.

[0031] Figure 7 The present invention proposes a planar array formed by (a) serpentine arrangement and (b) Hilbert curve arrangement using 16 SPAD detection units as an example. Both planar array structures are arranged in a certain order, and can be essentially converted into a one-dimensional single-chain structure. The time information recorded by the two TDC circuits can be used to derive the one-dimensional address information of the SPAD detection unit that responds, and combined with the known specific arrangement information, the two-dimensional address information can be calculated. For example: in the serpentine structure of Figure (a), if the obtained device position i=6, then its two-dimensional coordinates are (3, 2), indicating the third row and second column; in the Hilbert curve structure of Figure (b), if the obtained device position i=6, then its corresponding two-dimensional coordinates are (4, 1), indicating the fourth row and first column.

[0032] Figure 8It is a schematic diagram of a two-dimensional array sensor formed by multiple linear array SPAD detectors proposed by the present invention. M linear array SPAD detection arrays are closely arranged in the two-dimensional direction to form an N×M area array. Each linear array SPAD detection array is configured with 2 delay chains, 2 TDC circuits and a readout circuit to form M columns of parallel-operating area array SPAD detectors. Each column of the linear array can work independently to generate a one-dimensional address information. Combined with the address information of the column in which it is located, the two-dimensional address information can be obtained. For example, if the second SPAD detection unit in the third column responds, the coordinate can be inferred from the TDC data to be 2, and the column coordinate can be inferred from the position of the TDC circuit that generates the data to be 3, thereby obtaining a two-dimensional coordinate of (2, 3), indicating the second row and the third column. The N×M array can work in multiple columns at the same time to generate multiple address coding information for detecting multiple position information at the same time.

Claims

1. A pixel address encoding circuit with time information suitable for a SPAD array, characterized in that: It includes a SPAD detection array composed of N SPAD detection units, 2 delay chains, 2 TDC circuits and a readout circuit, wherein the SPAD detection unit is used to detect photons and output voltage pulses; the two delay chains transmit delays in opposite directions, each delay chain includes N basic delay units with a delay time of τ, each SPAD detection unit is simultaneously connected to the corresponding basic delay units in the two delay chains, and the voltage pulses output by the SPAD detection unit are simultaneously transmitted in the reverse direction in the two delay chains; the ends of the two delay chains are respectively connected to a TDC circuit; the readout circuit reads the data of the two TDC circuits, and obtains the pixel address information and the pulse time information through calculation; The SPAD detection unit includes a SPAD device, a quenching circuit and a shaping circuit. After the SPAD device responds, it outputs a voltage pulse under the action of the quenching circuit and the shaping circuit. The voltage pulse carries time information and is reversely transmitted to two TDC circuits in two delay chains to trigger the TDC circuit to generate time information. The time when the photon reaches the i-th SPAD detection unit is T ti , is transmitted to the upper TDC circuit through the upward delay chain, and the detected time is T1 = T ti +iτ, is transmitted to the lower end TDC circuit through the delay chain, and the detected time is T2 = T ti +(N-i+1)τ, the position of the SPAD detection unit that responds is calculated as At the same time, the photon arrival time is 2. A pixel address encoding circuit with time information suitable for a SPAD array according to claim 1, characterized in that: Each delay chain uses a two-input OR gate as a basic delay unit, the first input end of the two-input OR gate is connected to the output end of the SPAD detection unit, and the second input end is connected to the output end of the two-input OR gate of the previous level, and the output end of the two-input OR gate is connected to the second input end of the two-input OR gate of the next level. A column of two-input OR gates are connected in the above manner to form a delay chain; the second input end of the two-input OR gate of the first level of the delay chain is grounded, and "0" is always input; the output end of the two-input OR gate of the last level is connected to the TDC circuit.

3. A pixel address encoding circuit with time information suitable for a SPAD array according to claim 1, characterized in that: The readout circuit is composed of 2 D flip-flops, 1 AND gate and 1 FIFO circuit. The pulse signal generated by the SPAD detection unit is transmitted in reverse along the two delay chains transmitted upward and downward, and reaches the corresponding two TDC circuits to trigger TDC timing. At the same time, the two signals respectively trigger the two D flip-flops to generate a high level, indicating that a trigger is generated in the pixel cluster at this time; then, the FIFO circuit reads the data in the two TDC circuits under the drive of the system clock, and resets the two D flip-flop circuits by the Reset signal after the data reading is completed, so as to realize the detection of the next data.

4. A pixel address encoding circuit with time information suitable for a SPAD array according to any one of claims 1 to 3, characterized in that: N SPAD detection units are arranged in one column or one row in one dimension to form a single-column or single-row linear SPAD detection array, which is equipped with two delay chains, two TDC circuits and a readout circuit to form a linear SPAD detector; the two delay chains are composed of 2N basic delay units arranged in two columns or two rows on one side of the linear SPAD detection array, and the two TDC circuits are respectively arranged on the upper and lower sides of the area composed of the linear SPAD detection array and the two delay chains; the output of each SPAD detection unit is simultaneously connected to the basic delay unit at the corresponding position of the two delay chains, and the time information recorded by the two TDC circuits is used to reversely infer the one-dimensional address information and time information of the SPAD detection unit that responds.

5. A pixel address encoding circuit with time information suitable for a SPAD array according to claim 4, characterized in that: M linear SPAD detection arrays are closely arranged in the two-dimensional direction to form an N×M planar array. Each linear SPAD detection array is configured with 2 delay chains, 2 TDC circuits and a readout circuit to form M columns of parallel-operating planar SPAD detectors. Each column of the linear array can work independently to generate a one-dimensional address information, which can be combined with the address information of its own column to obtain the two-dimensional address information.

6. A pixel address encoding circuit with time information suitable for a SPAD array according to any one of claims 1 to 3, characterized in that: N SPAD detection units are arranged in sequence in a serpentine or Hilbert curve manner to form a two-dimensional array with a single-chain structure, forming an array SPAD detection array, and two delay chains, two TDC circuits and a readout circuit are configured to form an array SPAD detector; the two delay chains are composed of 2N basic delay units tightly arranged in the same form in the array SPAD detection array, and the two TDC circuits are respectively arranged on the upper and lower sides of the area composed of the array SPAD detection array and the two delay chains; the output of each SPAD detection unit is simultaneously connected to the basic delay unit at the corresponding position of the two delay chains, and the time information recorded by the two TDC circuits is used to reversely infer the one-dimensional address information and time information of the SPAD detection unit that responds, and then the two-dimensional address information of the SPAD detection unit that responds is reversed based on the known arrangement information.

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