A storage device

Abstract

This application provides a storage device including multiple storage cells, a write circuit, and a power feedback circuit. The storage cells are used to store data. The write circuit is connected to the multiple storage cells and is used to write multiple bits of data to the multiple storage cells in one write cycle. The power feedback circuit is connected to the write circuit and the multiple storage cells and is used to adjust the write voltage of the multiple storage cells when the write circuit performs a write operation, so that the write circuit writes multiple bits of data to the multiple storage cells in one write cycle. Because multiple bits of data can be written in one write cycle, the write efficiency is improved, and the reconfiguration time of the storage device is shortened.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a storage device. Background Technology

[0002] With the development of integrated circuit technology, Field-Programmable Gate Arrays (FPGAs), as reconfigurable computing devices, can be configured with the flexibility of their reconfigurable hardware. This allows them to achieve different functions by changing only the internal configuration information without changing the hardware architecture, thus enabling the system to have high performance for most applications.

[0003] Spin Transfer Torque (STT) Magnetic Random Access Memory (MRAM) has become one of the most promising contenders for next-generation memory due to its advantages such as non-volatility and unlimited erasure and rewriting capabilities. FPGA architectures based on STT-MRAM are also being widely studied.

[0004] For FPGA architectures based on STT-MRAM, reconfiguration of reconfigurable hardware requires writing new configuration information into the corresponding STT-MRAM. Currently, the write cycle of STT-MRAM is generally long, resulting in a longer reconfiguration time for the corresponding reconfigurable hardware. Summary of the Invention

[0005] This application provides a configuration method and apparatus for shortening the reconfiguration time of reconfigurable configuration hardware in an FPGA.

[0006] In a first aspect, embodiments of this application provide a storage device, which includes a first storage module, a write circuit, and a power feedback circuit. The first storage module includes multiple storage cells for storing data; the write circuit is connected to the multiple storage cells and is used to write multiple bits of data to the multiple storage cells in one write cycle; the power feedback circuit is connected to the write circuit and the multiple storage cells and is used to adjust the write voltage of the multiple storage cells when the write circuit performs a write operation to the multiple storage cells, so that the write circuit writes multiple bits of data to the multiple storage cells in one write cycle.

[0007] With the above design, the storage device can write multiple bits of data in one write cycle, which improves write efficiency and shortens the reconfiguration time of the storage device compared to the method of writing only one bit of data in one write cycle.

[0008] In one possible implementation, the first storage module includes a spin transfer torque (STT) magnetic random access memory (MRAM), and multiple storage cells include magnetic tunnel junctions (MTJs).

[0009] Through the above design, this STT-MRAM possesses advantages such as non-volatility and unlimited erasure / rewriting capability. Due to its non-volatility, STT-MRAM does not require reprogramming during each system sleep-wake cycle, significantly reducing the power-on latency of STT-MRAM-based FPGA systems. Secondly, since STT-MRAM is based on 1T1MTJ storage, its area is primarily determined by the area of ​​a single transistor, resulting in a significantly higher storage density than static random access memory (SRAM). This also offers a clear advantage in increasing FPGA logic density. Finally, due to its non-volatility, the FPGA system does not need to maintain the stored data during operation, significantly reducing leakage current and power consumption. Therefore, STT-MRAM-based storage devices, as reconfigurable hardware, offer numerous advantages such as low wake-up latency, high density, and low power consumption.

[0010] In one possible implementation, the storage device further includes a first configuration module; the first configuration module is used to store first configuration data, the first configuration data including data to be written to a plurality of storage cells, wherein the first configuration module includes SRAM or MRAM.

[0011] In one possible implementation, the storage device further includes a second storage module, a second configuration module, and a selection circuit; wherein the storage medium of the second storage module is different from the storage medium of the first storage module; the second configuration module is used to store second configuration data; the selection circuit is connected to the first configuration module and the second configuration module and is used to select to output the first configuration data or the second configuration data; the write circuit is connected to the selection circuit and is used to receive the first configuration data or the second configuration data output by the selection circuit and write the first configuration data or the second configuration data into the first storage module or the second storage module respectively.

[0012] The above design, employing a hybrid modular architecture, can meet the different needs of the same device.

[0013] In one possible implementation, the storage device includes a look-up table (LUT) in the FPGA.

[0014] In one possible implementation, the second storage module includes SRAM, and the second configuration module includes MRAM; wherein, the selection circuit is used to select and output second configuration data from the second configuration module during FPGA operation; and the write circuit is used to receive the second configuration data output by the selection circuit and write the second configuration data into the second storage module.

[0015] Through the above design, a hybrid modular architecture can meet the different needs of the same device. For example, by utilizing the advantages of MRAM and SRAM, corresponding LUTs, first configuration modules (e.g., SRAM and Flash), and second configuration modules (e.g., MRAM) can be designed based on MRAM and SRAM respectively. Due to the large storage capacity of Flash, the fast read and write speed of SRAM, and the non-volatility of MRAM, the hybrid STT-MRAM LUT and SRAM LUT, as well as Flash, SRAM, and MRAM, can work together efficiently. When this architecture is applied to FPGA, it can meet the large capacity requirements of FPGA initialization configuration and the requirements of rapid partial dynamic reconfiguration of FPGA system.

[0016] In one possible implementation, multiple storage cells in the first storage module are connected in series.

[0017] In one possible implementation, a write cycle is one on-cycle of the first storage module.

[0018] Secondly, embodiments of this application provide a computing device, which includes a communication interface and a storage device as described in the first aspect and any embodiment of the first aspect; the communication interface is used to acquire data to be written to a plurality of storage units. Attached Figure Description

[0019] Figure 1 (a) is a schematic diagram of the architecture of a logical cluster;

[0020] Figure 1 (b) is a schematic diagram of a BLE architecture;

[0021] Figure 1 (c) is a schematic diagram of an STT-LUT architecture;

[0022] Figure 2 This is a schematic diagram showing the input-output correspondence of a 4-input STT-LUT;

[0023] Figure 3 (a) is based on Figure 1 (c) shows a schematic diagram of a write operation performed by the STT-LUT;

[0024] Figure 3(b) is based on Figure 1 The diagram shown in (c) illustrates another write operation performed by the STT-LUT;

[0025] Figure 4 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0026] Figure 5 (a) is a schematic diagram of a BLE structure provided in an embodiment of this application;

[0027] Figure 5 (b) is an example of a storage device provided in an embodiment of this application;

[0028] Figure 6 Another example of a storage device provided in the embodiments of this application;

[0029] Figure 7A This is a schematic diagram of a write operation of a storage device provided in an embodiment of this application;

[0030] Figure 7B This is another schematic diagram of a write operation of the storage device provided in the embodiments of this application;

[0031] Figure 8 A schematic diagram of a decoding circuit for a storage device provided in an embodiment of this application;

[0032] Figure 9 (a) is a schematic diagram of a MOS transistor;

[0033] Figure 9 (b) is a voltage-current characteristic curve of a MOSFET;

[0034] Figure 9 (c) is a schematic diagram of the working principle of a write circuit provided in an embodiment of this application;

[0035] Figure 10 A schematic diagram of the architecture of a power feedback circuit provided in an embodiment of this application;

[0036] Figure 11 (a) is a schematic diagram of an application scenario for a power feedback module provided in an embodiment of this application;

[0037] Figure 11 (b) is a schematic diagram of another application scenario for a power feedback module provided in this application embodiment;

[0038] Figure 12 This is a schematic diagram of a read operation of a storage device provided in an embodiment of this application;

[0039] Figure 13A schematic diagram illustrating the structure of another storage device provided in an embodiment of this application;

[0040] Figure 14 A schematic diagram illustrating the structure of the third storage device provided in the embodiments of this application;

[0041] Figure 15 This is a schematic diagram of an operating scenario for a storage device provided in an embodiment of this application;

[0042] Figure 16 This application provides a schematic diagram of the structure of a computing device. Detailed Implementation

[0043] A field-programmable gate array (FPGA) is a reconfigurable computing device that includes reconfigurable hardware. It can be flexibly configured using its reconfigurable hardware, allowing different functions to be achieved by changing only the internal configuration information without changing the hardware architecture.

[0044] A logic cluster is a type of logic functional module in an FPGA architecture. Figure 1 This is a schematic diagram of a logic cluster within an FPGA. (Example) Figure 1 As shown in (a), the logic cluster may include a fully cross-connected switch matrix and multiple Basic Logic Elements (BLEs), where each BLE is the smallest digital circuit unit used to complete user logic. Those skilled in the art will recognize that digital circuits can be further divided into combinational logic and sequential logic. In FPGAs, combinational logic is implemented using lookup tables (LUTs), while sequential logic is implemented using registers. Please continue to the next section. Figure 1 (b) Figure 1 (b) is a schematic diagram of a BLE structure, which includes a 4-input LUT and multiple registers. Figure 1 (b) contains triggers and selectors). The four inputs of the LUT come from a fully cross-connected switch matrix. Of course, Figure 1 The BLE structure shown in (b) is merely an example. In reality, there are various types of LUTs and registers. This application does not limit the types and structures of components included in the BLE. Registers are not the focus of this application; LUTs will be discussed further below.

[0045] At the hardware level, a LUT is a reconfigurable hardware component. At the functional level, an LUT is a functional module that can be used to implement a logical function, such as y = a & b. In essence, an LUT is a storage resource, specifically a random access memory (RAM). Specifically, an LUT stores data in a truth table. The input to the LUT is equivalent to an "index" of this truth table, and the value corresponding to that index is the result of the logical function, i.e., the output of the LUT. For example, implementing the logical function y = a & b is equivalent to looking up information in a table, as shown in Table 1 below.

[0046] Table 1

[0047]

[0048] This can be understood as follows: When a user describes a logic circuit (e.g., y=a&b) using a hardware description language (Verilog or VHDL), the programmable logic device (PLD) / FPGA development software automatically calculates all possible results for that logic circuit, thus converting the description y=a &b into a table. Subsequently, a bitstream configuration file corresponding to this table is generated and pre-written into a LUT. Therefore, each input signal (a, b) performing a logical operation is equivalent to inputting an address (index) to look up the corresponding value in the table, and then outputting it. Thus, while it appears that a logical operation has been completed, it is actually a table lookup operation. In other words, the LUT implements logic functions through table lookups, or the FPGA uses a large amount of storage resources to simulate digital circuits.

[0049] The above describes the implementation principle of the LUT's logical functions. The process of writing the bitstream configuration file to the LUT can also be understood as a reconfiguration (or reconstruction) process of the LUT. The following describes the methods for reconfiguring an existing LUT. For ease of explanation, the LUT reconfiguration operation will be referred to as a write operation, and the table lookup operation as a read operation.

[0050] Please see below. Figure 1 (c) Figure 1 (c) is a circuit diagram of an existing STT-LUT.

[0051] The so-called STT-LUT refers to a LUT whose storage medium is spin transfer torque (STT) magnetic random access memory (MRAM). As mentioned earlier, an LUT is a type of storage resource, and its storage medium can be static random access memory (SRAM) or MRAM, etc. Here, STT-MRAM is a product type belonging to MRAM. Compared with SRAM, STT-MRAM has advantages such as non-volatility and unlimited erasure and rewriting capability, while SRAM has a relatively fast read and write speed. For ease of explanation, LUTs with SRAM storage medium are referred to as SRAM-LUTs, and LUTs with STT-MRAM storage medium are referred to as STT-LUTs. This article uses STT-LUTs as an example for description.

[0052] Specifically, the core of STT-MRAM is the Magnetic Tunnel Junction (MTJ), which is used to store data. One MTJ can store one bit of data (binary data 0 or 1). Figure 1 (c) shows a 4-input STT-LUT, where the 4 inputs are A, B, C, and D. Each input takes the value of either binary data 0 or 1. Therefore, the 4 input signals have a total of 16 (2) inputs. 4 There are 16 possible combinations, corresponding to 16 results in the LUT. Therefore, a 4-input STT-LUT requires 16 MTJs, each storing the result corresponding to one input. In other words, the MTJ stores the output of the truth table, and reconfiguring the LUT involves writing the output of the truth table corresponding to one logic function into the MTJ.

[0053] For example, see Figure 2 As shown, Figure 2 Showing Figure 1 The diagram (c) shows the correspondence between each input and output of the STT-LUT. A, B, C, and D correspond to 16 combinations, which are also 16 input addresses. For example, ... Figure 2 As shown, the 16 input addresses (ABCD) are ordered as (1111), (1110), (1101), (1100)...(0000). Given the logic function of this LUT, y= +ab Based on the given logical function, calculate the result corresponding to each input address. Specifically, for example, substitute (1111) into y= +ab In the middle, the result is 1; substituting (1110) into y= +ab In the middle, the result is 0, and so on. For example... Figure 2 As shown, the results corresponding to the 16 input addresses are 1000010100001101, and these 16 bits constitute the bitstream configuration file for this logical function. When reconfiguring the LUT, it is only necessary to write these 16 bits sequentially. Figure 1 The MTJ1-MTJ16 in (c) are sufficient. In other words, reconfiguring the LUT essentially involves performing a write operation on each of its MTJs. Subsequently, during read operations, whenever an input address arrives, its corresponding MTJ will be activated. For example, in... Figure 1 In (c), when the input address is (1111), MTJ1 will be turned on, when the input address is (1110), MTJ2 will be turned on, and so on. Since the MTJ stores the result corresponding to the input address, the accurate result can be read from the turned-on MTJ.

[0054] The following is based on Figure 1 Section (c) introduces how MTJ performs write operations.

[0055] First, let's introduce the MTJ. It should be understood that this introduction to the MTJ is for illustrative purposes only, and the embodiments in this application do not limit the structure of the MTJ. The MTJ consists of two ferromagnetic layers and one oxide layer. One ferromagnetic layer is called the reference layer (or fixed layer), and its magnetization remains fixed along the easy magnetization axis. The other ferromagnetic layer is called the free layer, and its magnetization has two stable orientations: parallel to the reference layer or antiparallel to the reference layer. This places the MTJ in a low-resistance state or a high-resistance state, which can represent "0" and "1" of binary data, respectively. The magnetization direction of the free layer can be changed by current flowing in different directions, thereby changing the data stored in the MTJ, thus enabling data to be written to the MTJ. Figure 3 This illustrates the current conduction path during a write operation on the MTJ. Specifically, given WL1=1, different states of the MTJ can be written by applying a forward or reverse voltage between BL and BL' to change the direction of the current flowing through the MTJ. For example, as shown... Figure 3 As shown in (a), assuming BL=1 and BL'=0, the first MTJ will be written with data 0; as another example, as Figure 3 As shown in (b), assuming BL=0 and BL'=1, data 1 will be written to the first MTJ.

[0056] by Figure 3 For example, in Figure 3In the circuit shown, applying a voltage continuously between BL and BL' once can be called a write cycle, or a voltage application cycle or a conduction cycle. For Figure 1 As shown in (c), the STT-LUT can perform a write operation on one MTJ in each write cycle, that is, one write cycle can write 1 bit of data. Therefore, when reconfiguring the 4-input STT-LUT, according to the bit stream configuration file, the write operation is performed on one MTJ in sequence in each write cycle. Therefore, configuring 16 MTJs requires 16 write cycles.

[0057] In summary, the write cycle of MTJs is generally long. When reconfiguring an STT-LUT, data needs to be written to all MTJs sequentially, resulting in a long reconstruction time for the entire STT-LUT. Therefore, embodiments of this application provide a storage device that can write multiple bits of data in a single write cycle, thereby shortening the reconstruction time.

[0058] The storage device provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0059] See Figure 4 , Figure 4 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application. Figure 4 As shown, the storage device 100 includes a first storage module 110, a write circuit 120, and a power feedback circuit (or power compensation circuit) 130.

[0060] The first storage module 110 includes multiple storage units ( Figure 4 Taking storage units 1101 and 1102 as examples (but this application embodiment does not limit this), each storage unit is used to store data. This application embodiment does not limit the type of storage unit; for example, the storage unit can be an MTJ, memristor, ferroelectric memory, etc., and any storage unit capable of storing data is applicable to this application embodiment. Furthermore, in this application embodiment, the storage device 100 may include one or more first storage modules 110. In implementable embodiments, the number of storage units included in each first storage module 110 may be the same or different, and this application embodiment does not limit this.

[0061] The write circuit 120 connects the first storage module 110 (or multiple storage cells of the first storage module 110) and the power feedback circuit 130. Specifically, the write circuit 120 is used to write multiple bits of data to multiple storage cells in one write cycle.

[0062] It should be understood that, Figure 4The connection method shown is merely an example. This application does not limit the structure and connection method of the write circuit 120. When the structure of the write circuit 120 differs, its actual connection method with the first storage module 110 and the power feedback circuit 130 may also differ. For example, the write circuit 120 may include a power module, whose power lines are connected to both ends of the first storage module 110 to provide a write voltage to the first storage module 110. Correspondingly, a write cycle refers to executing multiple write operations serially or in parallel under a single input write voltage. For example, in... Figure 4 In this context, the process of continuously applying voltage to both ends of the first storage module 110 can be called a write cycle. The write cycle can also be understood as a conduction cycle or a voltage application cycle of the first storage module 110. Correspondingly, in one implementable method, if a storage cell can be used to store one bit of data, for example, storage cells 1101 and 1102 are MTJs, and the data stored in the MTJ is binary data 0 or 1, then when writing multiple bits of data to multiple storage cells in one write cycle, it can be that data 0 is written to multiple storage cells in one write cycle; or, data 1 is written to multiple storage cells in one write cycle.

[0063] The power feedback circuit 130 is connected to the first storage module 110 and the write circuit 120. Specifically, the power feedback circuit 130 is used to adjust the write voltage of the multiple storage cells when the write circuit 120 performs a write operation to the multiple storage cells, so that the write circuit 120 can write multiple bits of data to the multiple storage cells (e.g., to storage cells 1101 and 1102) in one write cycle.

[0064] The above design enables the writing of multiple bits of data in a single write cycle, improving the efficiency of data writing. When reconfiguring the storage device, it can shorten the total write cycle required for the storage unit, thereby reducing the reconfiguration time of the storage device.

[0065] The storage device 100 provided in this application embodiment can be applied to various systems, such as FPGA, GPU, or CPU systems. This application embodiment does not limit the system architecture to which the storage device 100 is adapted. For example, the storage device 100 can be a LUT in an FPGA. Specifically, this application embodiment can be applied to all reconfiguration scenarios of an FPGA system, or to partial dynamic reconfiguration scenarios of an FPGA system. Partial dynamic reconfiguration refers to the ability to reconfigure a certain logic functional unit in an FPGA system without affecting the normal operation of other parts. The following describes the structure of the storage device provided in this application embodiment using the storage device 100 including an STT-LUT as an example.

[0066] like Figure 5 As shown in (a), this is a schematic diagram of a BLE provided in an embodiment of this application. The BLE includes a storage device 100, which includes, as shown in (a)... Figure 5 The 4-input STT-LUT and power feedback circuit 130 are shown in (b). All four inputs of the STT-LUT come from a fully cross-connected switch matrix (…). Figure 5 (Not shown in the diagram, and the full cross switch matrix is ​​only one example, and this application does not limit it.) The four inputs are referred to as input addresses below. In addition to the input addresses, the input signals of the STT-LUT also include control signals, which will be described below and will not be repeated here.

[0067] Please see Figure 5 (b) is a circuit example of a storage device 100 provided in an embodiment of this application. Please refer to [the example]. Figure 6 Understandably, the STT-LUT includes four first memory modules 110, such as 110a, 110b, 110c, and 110d. Each first memory module includes four STT-MRAMs, and each STT-MRAM includes one MTJ and a corresponding switching unit. The switching unit is used to control the shorting of the corresponding memory cell. Each switching unit is independently controllable. For example, in the STT-MRAM, the switching unit can be a MOS-type switching transistor (hereinafter referred to as a MOS transistor, which will be described below). The four MTJs (or STT-MRAMs) within each first memory module are connected in series. For example, continue referring to... Figure 6 Within the first storage module 110a, MTJ1, MTJ2, MTJ3, and MTJ4 are connected in series; within the first storage module 110b, MTJ5, MTJ6, MTJ7, and MTJ8 are connected in series, and so on. It should be understood that... Figure 5 (b) is merely an example. This application does not limit the structure of the storage device 100. For example, the STT-LUT can be 4-input, 6-input, or 8-input, etc. This application does not limit the type of LUT, nor the number or structure of its included first storage modules. Any type of LUT is applicable to this application. Furthermore, this application uses STT-MRAM as an example to describe the structure of the first storage module. In fact, other non-volatile memories with similar characteristics, such as SOT-MRAM, are also applicable to this application.

[0068] As previously described, the write circuit 120 may include a power supply circuit for providing a power supply voltage (including a write voltage) to the first storage module; further exemplarily, the write circuit 120 may also include a switch for controlling the direction of current within the first storage module 110 (e.g., ...). Figure 6This includes N1-N16, inputs (WL1-WL16) connected to multiple storage units, and control signals. The control signals can be used to control the on / off state of N1-N16. Assuming that for switches N1-N16, the switch is on when the input is 1 and off when the input is 0, it should be understood that when the switch is on, the corresponding MTJ terminals are short-circuited.

[0069] Based on the circuit structure of the aforementioned storage device 100, the following describes a method for writing multiple bits of data to multiple storage cells within a single write cycle. Please refer to [link to documentation]. Figure 7A , Figure 7A This shows the current path of the circuit when a write operation is performed within a write cycle (e.g., Figure 7A (As shown by the thicker black solid line). In Figure 7A In the given scenario, N1=N4=0, N2=N3=1, WL1=WL2=0, WL3=WL4=1. For example... Figure 7A As shown, MTJ1 and MTJ2 are in the ON state. At this time, the current flowing through MTJ1 and MTJ2 will simultaneously write data '0' to both MTJs, thus achieving the writing of multiple bits of data in a single write cycle. It should be understood that if data '1' needs to be written to MTJ3 and MTJ4, then N1=N4=1, N2=N3=0, WL1=WL2=1, and WL3=WL4=0 must be set. In this case, a write current flowing in the opposite direction will be generated in the selected MTJ3 and MTJ4 to simultaneously write data '1' to both MTJ3 and MTJ4. Please refer to [link to documentation]. Figure 7B As shown. Similarly, the method of performing multi-bit writes in the storage cells of other first storage modules such as 110b, 110c or 110d can be found in the relevant description of the first storage module 110a, and will not be repeated here.

[0070] The above method allows for reconfiguration of the entire 4-input STT-LUT in 8 write cycles, which is relatively... Figure 3 The reconstruction time required for the LUT shown (16 write cycles) is reduced by at least half, thus shortening the LUT reconstruction time. Of course, the storage device 100 in this embodiment can also write single-bit data in one write cycle, for example, in... Figure 6 or Figure 7A or Figure 7B In this process, only one MTJ is activated in a single write cycle, as detailed above, and will not be repeated here.

[0071] It should be noted that, Figure 5 , Figure 6 , Figure 7A , Figure 7BThe storage device 100 shown is for illustrative purposes only. This application embodiment does not limit the structure of the storage device 100. In fact, the storage device 100 in this application embodiment can be more... Figures 5-7B It may contain more or fewer components. For example, when the storage device 100 is a LUT, it may also include decoding circuitry, which translates binary code into specific objects, such as translating control signals into signals for strobing N1-N16.

[0072] The following describes the methods for controlling the conduction of N1-N16 and MTJ.

[0073] See Figure 8 , Figure 8 This diagram illustrates the principle of the decoding circuit provided in an embodiment of this application. A, B, C, and D are address lines, which can be input via a full-cross switch matrix; Ctrl.1, Ctrl.2, WR0, WR1, and RE are control signals, where WR0 is the write '0' operation control line, WR1 is the write '1' operation control line, and RE is the read control line. For example, when performing a read operation, RE can be set to 1, and when performing a write operation, RE can be set to 0.

[0074] like Figure 8 As shown, A, B, C, and D are connected to switches corresponding to multiple MTJs, used to select the MTJ corresponding to the connected switches. Ctrl.1, Ctrl.2, WR0, WR1, and RE are decoded by one or more hardware gates such as NOT gates, NAND gates, and NOR gates to produce eight outputs. These eight outputs are used to select two switches from N1 to N16. When two switches are selected, the other switches are in the off state. For example, to implement... Figure 6 The shown conduction mode requires A, B=0, C=D=1, ctrl0=ctrl1=1, WR1=1, WR0=0, RE=0. Correspondingly, after decoding by this decoding circuit, N2=N3=1, N1, N4, and N5-N16 are all 0. That is to say, in... Figures 5-7B In the circuit shown, the decoding circuit selects only two switches at a time, thereby achieving individual control of each first memory module. It should be understood that... Figure 8The decoding circuit shown is merely an example, and this application does not limit its functionality. For instance, address line A can be connected to WL2, WL6, WL9, WL13, etc. Each address line can be connected to a switch corresponding to an MTJ at the same location or with the same function in each first memory module, or it can be connected to a switch corresponding to an MTJ at different locations or with different functions. Any connection method that can realize the function of this decoding circuit is applicable to this application. Furthermore, the names of the devices or signals within each circuit in this application are merely approximations, and this application does not limit their use; they may have different names in different scenarios or situations.

[0075] The operation of the writing circuit 120 and the power feedback circuit 130 is described below.

[0076] Please see Figure 5 The write circuit 120 is connected to the first storage module and is specifically used to provide power supply voltage (including write voltage) to the first storage module 110 (e.g., 110a, 110b, 110c, 110d). Taking the first storage module 110a as an example, see [link to example circuit]. Figure 5 The power supply voltage across the first storage module 110a is V. D The voltage between Vs. The power feedback circuit 130 is used to adjust the power supply voltage across the first storage module 110a when the write circuit 120 performs a write operation to multiple storage cells in the first storage module 110a, so that the write circuit 120 writes multiple bits of data to multiple storage cells in one write cycle. It should be understood that since MTJs are resistive components, each write operation performed by the write circuit 120 on one MTJ will cause a voltage drop across the power supply. If a write operation is to be performed on multiple MTJs in one write cycle, the total write voltage required is relatively large. However, directly supplying a sufficiently large power supply voltage to the multiple MTJs may break down the MTJs, causing them to be damaged. Therefore, in this embodiment, the power feedback circuit 130 dynamically adjusts the power supply voltage across the multiple MTJs to ensure that the MTJs operate at a normal power supply voltage, guaranteeing the write voltage required by the write circuit 120 when performing a write operation on multiple MTJs in one write cycle.

[0077] The above describes the implementation principle of the power feedback circuit 130. Next, we will illustrate the specific implementation of the power feedback circuit 130 with examples. Since the power feedback circuit 130 is used to regulate the write voltage, which is related to the power supply circuit, to better understand this technical solution, before introducing the working circuit of the power feedback circuit 130, we will first introduce the power supply circuit in the write circuit 120. It can be composed of two MOSFETs with the same specifications (or parameters), for example, referred to as T1 and T2 respectively. See [link to documentation]. Figure 9 As shown, Figure 9(a) shows the symbol for a MOSFET, where G represents the gate, D represents the drain, and S represents the source, where V GS V represents the voltage between the gate and source (or simply gate-source voltage). DS This represents the voltage between the drain and source terminals (or simply drain-source voltage). See also... Figure 9 Figure (b) shows the voltage-current characteristic curve of the MOSFET. Figure 9 As shown in (b), when devices with the same parameters have the same gate-source voltage, the transistors will operate on the same voltage-current characteristic curve. Figure 9 In (c), assuming T1 and T2 have the same device parameters, when the V of T1 GS and T2's V GS At the same time, T1 and T2 have the same voltage-current characteristic curves. When T1 and T2 are in the saturation region, their current magnitudes are only related to V. GS Since they are related, the current I1 flowing through T1 and the current I2 flowing through T2 are the same.

[0078] Typically, the source is used for grounding (GND), and the voltage at the grounding point is usually 0, therefore... Figure 5 I understand that, for T2, V DS The voltage value is V D Point voltage, as mentioned earlier, since MTJ is a resistive component, writing one MTJ will cause a voltage drop. If V D If the point voltage continues to decrease, it will cause the V of T2 to... DS This decrease causes T2 to enter the resistance region or even result in I2 becoming 0, opening the power supply circuit and preventing the provision of write voltage to the first memory module. Therefore, this embodiment uses a power feedback circuit 130 to stabilize V. D The point voltage ensures that T1 and T2 always operate in the saturation region while the power supply circuit provides power to the first storage module. At the same time, it can dynamically adjust the write voltage to achieve voltage fluctuation, which ensures the stability of the device when writing single-bit data, and can provide a high voltage value when writing multiple bits of data in one write cycle, thereby reducing write power consumption loss.

[0079] For example, see Figure 10 , Figure 10 This is a specific structural example of a power feedback circuit 130 provided in an embodiment of this application. The power feedback circuit 130 is connected to the write circuit 120 and the first storage module 110.

[0080] Specifically, the power feedback circuit 130 includes components such as a differential amplifier, resistors, and voltage followers. For details on the components included in the power feedback circuit and their connection methods, please refer to [link to relevant documentation]. Figure 10 As shown, it will not be elaborated further here.

[0081] The process of adjusting the write voltage by the power feedback circuit 130 is described below.

[0082] Taking the first storage module 110a as an example, assume that the number of MTJs to be written in one write cycle is n, where n is a positive integer, and given... ,in, Let represent the resistance value of one MTJ, assuming that the resistance value of each MTJ in the circuit is equal; based on the above conditions, we can obtain:

[0083] When n increases, ↓

[0084] ;when When ↓, ↓

[0085] ;when When ↓, ↑

[0086] ;when When ↓, ↑

[0087] The above text introduces the power feedback circuit 130 adjustment. It should be noted that, in this regard, Figure 10 The circuit structure shown is for illustrative purposes only. This application does not limit the structure of the power feedback circuit 130; any structure capable of providing stable power feedback is acceptable. Voltage, or power feedback circuits that provide the write voltage for the write circuit 120 when performing write operations on multiple memory cells, are all applicable to the embodiments of this application.

[0088] In this embodiment of the application, one or more of the storage devices 100 may be included in the same computing device. One possible implementation method is described in [reference needed]. Figure 11 In (a), each storage device 100 (e.g., a LUT within a BLT) can have its own dedicated power feedback circuit 130, meaning that a power feedback circuit 130 is connected to only one storage device 100 and operates solely for that storage device 100. Thus, when a logic cluster contains multiple LUTs, the power feedback circuits of these multiple LUTs are independent of each other, and the multiple LUTs do not interfere with each other. This allows the multiple LUTs to perform write operations in parallel. For example, when a LUT in BLE1 performs a multi-bit write operation, it will not affect the multi-bit write operation performed in BLE2, thereby improving the overall FPGA reconfiguration efficiency.

[0089] Another feasible approach is for multiple storage devices to share the same power feedback circuit 130, see [link to relevant documentation]. Figure 11 (b) Multiple BLEs are connected to the same power feedback circuit 130. Specifically, the power feedback circuit 130 operates for one storage device within a BLE at a time. It should be understood that for multiple storage devices sharing a single power feedback circuit 130, when reconfiguring these multiple storage devices, the reconfiguration should be performed sequentially. For example, when reconfiguring the STT-LUT within BLE0, the power feedback circuit 130 is only used to adjust the write voltage within the STT-LUT within BLE0, and BLE1-BLT3 are in an off state. After the STT-LUT within BLE0 is configured, the STT-LUT within BLE1 is then turned on. At this time, the power feedback circuit 130 is only used to adjust the write voltage within the STT-LUT within BLE1, and BLE0, BLE2, and BLT3 are in an off state, and so on.

[0090] Although the power feedback circuit 130 introduced in this embodiment increases the size of the peripheral circuit, in reality, read operations are still the primary function in a reconfigurable architecture, while write operations are relatively infrequent. Therefore, the increased size overhead of the power feedback circuit can be distributed among multiple storage devices by sharing the power feedback circuit. On the other hand, the storage device provided in this embodiment simplifies the write circuit, saving significant hardware overhead. Compared to existing designs, it can still reduce the circuit size while introducing the power feedback circuit, further reducing hardware costs and demonstrating strong practicality.

[0091] This application embodiment also includes a read circuit, which is described below. Please refer to... Figure 12 This is a partial structural diagram of the read circuit included in the storage device 100 provided in this application embodiment, as shown below. Figure 12 As shown, the read circuit includes a comparator. Figure 12 It also shows the current path for performing a single read operation. Figure 12 In this context, given input addresses WL1=0, WL2=WL3=WL4=1, the enable read signal RE controls N1=N4=0 and N2=N3=1. Here, I1 and I2 are mirror currents, and they are identical. The principle behind I1=I2 is explained above and will not be repeated here. Furthermore, since:

[0092]

[0093]

[0094] We can obtain: Therefore, based on the two resistance states of MTJ1, the data stored by MTJ1 can be determined. It should be noted that the read circuit... With the power feedback circuit 130 They can be the same or different, depending on the actual circuit. This application does not limit this in its embodiments.

[0095] Please see Figure 13 , Figure 13 This is a schematic diagram of another storage device 200 provided in an embodiment of this application. The storage device 200 may include a first configuration module 201 and a storage device 100. The storage device 100 may be as described above. Figures 5-12 In any of the storage devices 100 described herein, a first configuration module 201 is used to store first configuration data. The first configuration data includes data to be written to multiple storage cells within the storage device 100, such as a bitstream configuration file. Exemplarily, the first configuration module 201 may include, but is not limited to, SRAM or MRAM. SRAM has a faster read / write speed; when the first configuration module 201 is SRAM, the write speed can be improved. MRAM is non-volatile, and the system does not need to maintain its leakage current during operation. Therefore, when the first configuration module 201 is MRAM, the power consumption of the storage device 200 can be reduced.

[0096] Based on the above architecture, this application also provides another system architecture to shorten the reconstruction time.

[0097] See Figure 14 , Figure 14 This is a schematic diagram of the structure of a storage device 300 provided in an embodiment of this application. The storage device 300 includes a first configuration module 301, a second configuration module 302, a selection circuit 303, a storage device 304, and a storage device 305. The storage device 304 can be one of the above-mentioned... Figures 5-12 The storage device 100 described herein includes a first storage module 3041, which may be the first storage module 110 in the storage device 100; the storage device 305 includes a second storage module 3051; the performance of the first storage module 3041 and the second storage module 3051 may be different, for example, they may use different storage media.

[0098] For example, the first storage module 3041 may include STT-MRAM, and the second storage module 3051 may include SRAM, or include both SRAM and Flash. In this case, storage device 304 may be an STT-LUT, and storage device 305 may be an SRAM-LUT. Because STT-LUTs are non-volatile, they do not require reprogramming during each system sleep-wake cycle, significantly reducing the power-on latency of the FPGA system. Furthermore, the system does not need to maintain its stored data during operation, significantly reducing leakage current and power consumption. SRAM-LUTs, on the other hand, have a faster write speed compared to STT-LUTs. Therefore, in storage device 300, STT-LUTs can serve as static modules with stable logic functions; while SRAM-LUTs, due to their faster write speed, can serve as dynamic modules for rapid reconfiguration of logic functions.

[0099] The first configuration module 301 is used to store first configuration data, which may include data to be written to the first storage module 3041 or the second storage module 3051. The second configuration module 302 is used to store second configuration data. Specifically, the storage media of the first configuration module 301 and the second configuration module 302 may be different, and they may be used to store different types of data or to implement different functions. For example, when the capacity of the first configuration module is larger than that of the second configuration module, the first configuration data and the second configuration data may be data with different amounts of data. When the read / write speed of the first storage module is faster than that of the second configuration module, the first configuration data and the second configuration data may be data with different latency requirements.

[0100] Selection circuit 303, connected to first configuration module 301 and second configuration module 302, is used to select output of first configuration data or second configuration data. In one possible implementation, the other end of selection circuit 303 is connected to a write circuit. For example, when selection circuit 303 inputs a bitstream configuration file to storage device 100, selection circuit 303 can be connected to write circuit 120 of storage device 100. In this case, write circuit 120 is also used to receive the bitstream configuration file output by selection circuit 303 and write the bitstream configuration file to first storage module 110. Optionally, first storage module 3041 and second storage module 3051 can share a write circuit 120. In this case, write circuit 120 is also used to receive the first configuration data or second configuration data output by selection circuit and write the first configuration data or second configuration data to the first storage module or the second storage module, respectively.

[0101] Through the above design, a hybrid modular architecture can meet the different needs of the same device. For example, by leveraging the advantages of STT-MRAM and SRAM, corresponding LUT units, a first configuration module (e.g., SRAM and Flash), and a second configuration module (e.g., MRAM) can be designed based on STT-MRAM and SRAM, respectively. Due to the large storage capacity of Flash, the fast read and write speed of SRAM, and the non-volatility of MRAM, the hybrid STT-MRAM LUT and SRAM LUT, as well as Flash, SRAM, and MRAM, can work together efficiently. When this architecture is applied to FPGA, it can meet the large capacity requirements of FPGA initialization configuration and the requirements of rapid partial dynamic reconfiguration of FPGA system.

[0102] For example, such as Figure 15 The diagram shown illustrates an application scenario of an FPGA system architecture provided in this application embodiment. The first configuration module 301 includes SRAM and Flash, the second configuration module 302 includes STT-MRAM, the storage device 304 includes STT-LUT, and the storage device 305 includes an SRAM-LUT.

[0103] Among these, SRAM has a faster read / write speed than STT-MRAM, which in turn has a faster read / write speed than flash; flash has a larger storage capacity than STT-MRAM, which in turn has a larger storage capacity than SRAM. Flash can be used to store large bitstream configuration files during FPGA system initialization. These bitstream configuration files can then be written to STT-LUT and SRAM-LUT via the faster SRAM. It should be understood that the bitstream configuration files written to STT-LUT and SRAM-LUT can be different. STT-MRAM, on the other hand, can be used to store smaller bitstream configuration files.

[0104] For example, during FPGA initialization configuration, the bitstream configuration file is first read from the Flash configuration memory and written to the SRAM. Then, the corresponding bitstream configuration files for the SRAM LUT and STT-LUT are read from the SRAM and configured separately. This satisfies the large capacity requirement of the bitstream configuration file during initialization while ensuring a fast write speed. Of course, since the STT-MRAM is non-volatile memory, if the relevant functions are already configured in the STT-LUT during initialization, then there is no need to configure the STT-LUT at this time. See [link to relevant documentation]. Figure 15 The dotted line is used to represent this.

[0105] During FPGA operation, for submodules requiring dynamic configuration, the bitstream configuration file is small, and the FPGA operation requires high configuration speed. Since Flash read speed is slow and SRAM storage capacity is small, considering both storage capacity and write speed, the smaller bitstream configuration file can be stored in the MRAM configuration memory. At this time, the selection circuit 1405 needs to read the bitstream configuration file from the MRAM configuration memory and write it into the SRAM LUT to achieve fast partial dynamic reconfiguration function.

[0106] It should be understood that the second configuration module 302 can also be SRAM, but SRAM has a smaller capacity, and the bitstream configuration file it can carry may be very small. The method of using flash configuration memory + SRAM configuration memory is slower than directly reading through STT-MRAM configuration memory. Therefore, using STT-MRAM configuration memory to store smaller bitstream configuration files is a better approach. Here, the smaller bitstream configuration file can be a bitstream configuration file with a capacity lower than a first preset threshold. The flash configuration memory can be used to store bitstream configuration files with a capacity higher than the first preset threshold. The first preset threshold can be set according to the performance of the actual product, and this application embodiment does not limit this. Furthermore, this description uses flash, STT-MRAM, and SRAM as examples to illustrate the first configuration module 301 and the second configuration module 302. It should be understood that this application embodiment does not limit the type and structure of the first configuration module 301 and the second configuration module 302.

[0107] The above architecture satisfies both the high-capacity initial configuration requirements of the FPGA and the need for rapid partial dynamic reconfiguration. Based on the non-volatility of the STT-LUT, system power consumption can also be reduced. Furthermore, if the STT-LUT (first storage module 3041) can also be... Figures 4 to 12 The storage device 100 shown in any of the accompanying figures can achieve low power consumption and shorten the reconfiguration time of the STT-LUT, thereby enabling rapid reconfiguration.

[0108] It is understood that, in practical applications, the storage device provided in the embodiments of the present invention may exist in the form of a circuit or a chip, for example, it may be a standalone storage chip. Furthermore, the storage device provided in the embodiments of the present invention may also be integrated into a chip, for example, it may be integrated into an FPGA, for example, it may be used as a LUT in an FPGA.

[0109] like Figure 16As shown, a computing device 1600 provided in an embodiment of this application is illustrated. The computing device 1600 includes a communication interface 1601 and a storage device 1602. The storage device 1602 may include any one of the storage device 100, storage device 200, or storage device 300 as described in the foregoing embodiments. The communication interface 1601 is used to acquire data to be written to multiple storage units. The storage device 1602 is used to implement the functions of storage device 100, storage device 200, or storage device 300 in any of the above embodiments, which will not be elaborated further here.

[0110] It should be noted that the embodiments provided in this application are merely illustrative. Those skilled in the art will understand that, for the sake of convenience and brevity, the descriptions of each embodiment have different focuses, and parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The features disclosed in the embodiments, claims, and drawings of this invention can exist independently or in combination. Features described in hardware form in the embodiments of this invention can be executed by software, and vice versa. No limitations are imposed here.

Claims

1. A storage device, characterized in that, include: The logic cluster module includes multiple basic logic units (BLEs), and each BLE includes a lookup table (LUT) circuit. A power feedback circuit, connected to the LUT circuit, is used to provide a dynamically adjusted floating voltage during data writing, so that the write circuit can write the same data to multiple memory cells simultaneously in a single write operation. The LUT circuit includes: Multiple storage cells are selectively connected in series via control signals; A decoding circuit is used to receive address signals and control signals, and generate strobe signals and current direction signals based on the address signals and control signals; wherein, the strobe signals are used to select multiple target memory cells from multiple memory cells to form a series path; the current direction signal is a signal indicating the current direction and is used to identify the value of the data to be written; A write circuit is used to write the same data to the multiple target memory cells in series in a single write operation when the multiple target memory cells are selected.

2. The storage device according to claim 1, characterized in that, The LUT circuit includes a spin-transfer torque magnetic random access memory (STT-MRAM), and the plurality of memory cells include magnetic tunnel junctions (MTJs).

3. The storage device according to claim 1 or 2, characterized in that, Also includes: A first configuration module is used to store first configuration data, which includes data to be written to the plurality of storage units. The first configuration module includes static random access memory (SRAM) or magnetic random access memory (MRAM).

4. The storage device according to claim 3, characterized in that, Also includes: A storage module, wherein the storage medium of the storage module is different from the storage medium of the plurality of storage units; The second configuration module is used to store the second configuration data; The selection circuit connects the first configuration module and the second configuration module, and is used to select the output of the first configuration data or the second configuration data. The write circuit is connected to the selection circuit and is used to receive the first configuration data or the second configuration data output by the selection circuit, and write the first configuration data or the second configuration data into the plurality of storage units or the storage module respectively.

5. The storage device according to claim 4, characterized in that, The lookup table (LUT) circuit is a LUT in a field-programmable gate array (FPGA). The storage module includes SRAM, and the second configuration module includes MRAM; The selection circuit is used to select and output the second configuration data from the second configuration module when the FPGA is running. The write circuit is used to receive the second configuration data output by the selection circuit and write the second configuration data into the storage module.

6. The storage device according to any one of claims 1-5, characterized in that, The multiple target storage units are multiple storage units selected within one conduction cycle.

7. A computing device, characterized in that, The device includes a communication interface and a storage device as described in any one of claims 1 to 6, wherein the communication interface is used to acquire data to be written to the plurality of storage units.

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