Storage device, flash memory controller and control method thereof

Abstract

A storage device, a flash memory controller and a control method thereof are disclosed. The flash memory controller is used to access a flash memory module. The control method includes receiving a setting instruction from a host device to set at least a part of the flash memory module as a region namespace, and determining the number of blocks included in each super block according to the size of each region of the region namespace and the size of each block in the flash memory module.

Description

Technical Field

[0001] This invention relates to flash memory. Background Technology

[0002] The Non-Volatile Memory Express (NVMe) specification defines a zoned namespace. However, since this zoned namespace and each zone within it are viewed solely from the perspective of the host device, the size of each zone defined by the host device does not have a fixed relationship with the size of each block within the flash memory module. Therefore, when the host device prepares to write data corresponding to a zone to the flash memory module, the flash memory controller needs to establish a large number of logical address to physical address mapping tables, such as recording the mapping relationship between logical addresses and physical addresses in units of data pages. This places a burden on the flash memory controller in data processing and also occupies storage space in Static Random Access Memory (SRAM) and / or Dynamic Random Access Memory (DRAM). Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a flash memory controller that can efficiently manage data written by the host device to the region namespace within the flash memory module, and the established logical address to physical address mapping table has a small size, thereby solving the problems described in the prior art.

[0004] In one embodiment of the present invention, a control method for a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprising multiple data planes, each data plane comprising multiple blocks, and each block comprising multiple data pages, and the control method comprising: receiving a setting instruction from a master device, wherein the setting instruction sets at least a portion of the flash memory module as a region namespace, wherein the region namespace logically comprises multiple regions, the master device must perform data write and access to the region namespace on a region-by-region basis, each region is of the same size, the logical addresses corresponding to each region must be contiguous, and there must be no overlapping logical addresses between regions; naming the region. The space is configured to plan multiple first superblocks, each first superblock containing multiple blocks located in at least two data planes, and the number of blocks contained in each first superblock is determined according to the size of each region and the size of each block; data corresponding to a specific region from the master device is received, wherein the data is all the data of the specific region; the data is sequentially written into a specific first superblock among the multiple first superblocks of the flash memory module according to the logical address order of the data; and after the data is written, invalid data is written to the remaining data pages of the last block contained in the specific first superblock, or the remaining data pages are kept blank and no data from the master device is written according to the write instruction of the master device before erasure.

[0005] In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprising multiple data planes, each data plane comprising multiple blocks, and each block comprising multiple data pages, and the flash memory controller comprising: a read memory for storing program code; a microprocessor for executing the program code to control access to the flash memory module; and a buffer memory. The microprocessor receives a setting instruction from a host device, wherein the setting instruction sets at least a portion of the flash memory module as a region namespace, wherein the region namespace logically contains multiple regions, the host device must perform data write and access to the region namespace on a region-by-region basis, each region is of the same size, the logical addresses corresponding to each region must be contiguous, and there are no overlapping logical addresses between regions; wherein the microprocessor configures the region namespace to plan multiple first superblocks, wherein each first superblock contains multiple blocks located in at least two data planes, and each first superblock... The number of blocks contained in a block is determined by the size of each region and the size of each block; the microprocessor receives data from the host device corresponding to a specific region, wherein the data is all the data of the specific region, and the microprocessor writes the data sequentially into a specific first superblock among the plurality of first superblocks of the flash memory module according to the logical address order of the data; and after the data is written, the microprocessor writes invalid data into the remaining data pages of the last block contained in the specific first superblock, or keeps the remaining data pages blank and does not write data from the host device according to the write instruction of the host device before erasing.

[0006] In another embodiment of the present invention, a storage device is disclosed, comprising a flash memory module and a flash memory controller. The flash memory module includes multiple data planes, each data plane includes multiple blocks, and each block includes multiple data pages. The flash memory controller is used to access the flash memory module. The flash memory controller receives a setting instruction from a host device, wherein the setting instruction sets at least a portion of the flash memory module as a region namespace. The region namespace logically contains multiple regions. The host device must perform data write and access to the region namespace on a region-by-region basis. Each region is of the same size, and the logical addresses corresponding to each region must be contiguous, with no overlapping logical addresses between regions. The flash memory controller configures the region namespace to plan multiple first superblocks, each first superblock containing multiple blocks located in at least two data planes. The number of blocks included is determined by the size of each region and the size of each block; the flash memory controller receives data from the host device corresponding to a specific region, wherein the data is all the data of the specific region, and the flash memory controller sequentially writes the data into a specific first superblock among the plurality of first superblocks of the flash memory module according to the logical address order of the data; and after the data is written, the flash memory controller writes invalid data into the remaining data pages of the last block included in the specific first superblock, or keeps the remaining data pages blank and does not write data from the host device according to the write instruction of the host device before erasing. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0008] Figure 2A This is a schematic diagram of a flash memory controller in a storage device according to an embodiment of the present invention.

[0009] Figure 2B This is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention.

[0010] Figure 3 This is a schematic diagram showing the general storage space and region namespaces of a flash memory module.

[0011] Figure 4 A diagram illustrating how a region namespace is divided into multiple regions.

[0012] Figure 5This is a flowchart illustrating the writing of data from a future autonomous device to a regional namespace according to an embodiment of the present invention.

[0013] Figure 6 A schematic diagram showing the writing of data for a region into blocks within the flash memory module.

[0014] Figure 7A This is a schematic diagram of an L2P mapping table according to an embodiment of the present invention.

[0015] Figure 7B This is a schematic diagram of an L2P mapping table according to another embodiment of the present invention.

[0016] Figure 7C This is a schematic diagram of an L2P mapping table according to another embodiment of the present invention.

[0017] Figure 7D This is a schematic diagram of an L2P mapping table according to another embodiment of the present invention.

[0018] Figure 8 This is a flowchart illustrating data reading from a region namespace according to an embodiment of the present invention.

[0019] Figure 9 This is a flowchart illustrating the writing of data from a future autonomous device to a regional namespace according to another embodiment of the present invention.

[0020] Figure 10 A schematic diagram showing the writing of data for a region into blocks within the flash memory module.

[0021] Figure 11A This is a schematic diagram of an L2P mapping table and a shared block table according to an embodiment of the present invention.

[0022] Figure 11B This is a schematic diagram of an L2P mapping table and a shared block table according to an embodiment of the present invention.

[0023] Figure 12 This is a schematic diagram of a shared block table according to another embodiment of the present invention.

[0024] Figure 13 This is a flowchart illustrating data reading from a region namespace according to an embodiment of the present invention.

[0025] Figure 14 This is a flowchart illustrating the writing of data from a future autonomous device to a regional namespace according to another embodiment of the present invention.

[0026] Figure 15 A schematic diagram showing the writing of data for a region into blocks within the flash memory module.

[0027] Figure 16 This is a schematic diagram of an L2P mapping table according to an embodiment of the present invention.

[0028] Figure 17 This is a flowchart illustrating data reading from a region namespace according to another embodiment of the present invention.

[0029] Figure 18 This is a flowchart illustrating the writing of data from a future autonomous device to a regional namespace according to another embodiment of the present invention.

[0030] Figure 19 A schematic diagram showing the writing of data for a region into blocks within the flash memory module.

[0031] Figure 20 This is a schematic diagram of an L2P mapping table according to an embodiment of the present invention.

[0032] Figure 21 This is a flowchart illustrating data reading from a region namespace according to an embodiment of the present invention.

[0033] Figure 22 This is a schematic diagram of a superblock within a typical storage space.

[0034] Figure 23 This is a flowchart of a method for configuring a flash memory module according to an embodiment of the present invention.

[0035] Figure 24 A diagram illustrating a superblock within a region namespace.

[0036] Figure 25 This is a flowchart of a control method applied to a flash memory controller according to an embodiment of the present invention.

[0037] [Symbol Explanation]

[0038] 100: Electronic devices

[0039] 110: Main unit

[0040] 120_1, 120_2, 120_N: Storage devices

[0041] 122: Flash memory controller

[0042] 124: Flash memory module

[0043] 212: Microprocessor

[0044] 212C: Program Code

[0045] 212M: Read-Only Memory

[0046] 214: Control Logic

[0047] 216: Buffer memory

[0048] 218: Interface Logic

[0049] 232: Encoder

[0050] 234: Decoder

[0051] 240: Dynamic Random Access Memory

[0052] 200: Block

[0053] BL1, BL2, BL3: Bit lines

[0054] WL0~WL2, WL4~WL6: Character lines

[0055] 310_1, 310_2: Region namespaces

[0056] 320_1, 320_2: General storage space

[0057] Z0, Z1, Z2, Z3: Regions

[0058] LBA_k~LBA_(k+x-1): Logical address

[0059] 500-508: Steps

[0060] B3, B7, B8, B12, B99, B6: Blocks

[0061] P1~PM: Data Page

[0062] 700, 710, 720, 730: L2P mapping table

[0063] 800~806: Steps

[0064] 900~906: Steps

[0065] 1100A, 1100B: L2P Mapping Table

[0066] 1130A, 1130B: Shared Block Table

[0067] 1230: Shared Block Table

[0068] 1300~1306: Steps

[0069] 1400~1408: Steps

[0070] B20, B30, B35: Blocks

[0071] 1600: L2P Mapping Table

[0072] 1700-1706: Steps

[0073] 1800–1806: Steps

[0074] 2000: L2P Mapping Table

[0075] 2100~2106: Steps

[0076] 2210, 2220, 2230, 2240: Flash memory chips

[0077] 2212,2214,2222,2224,2232,2234,2242,2244: Data plane

[0078] 2261, 2262: Superblock

[0079] 2300~2306: Steps

[0080] 2412, 2414, 2422, 2424, 2432, 2434, 2442, 2444: Data plane

[0081] 2461, 2462: Superblock Detailed Implementation

[0082] Figure 1 This is a schematic diagram of an electronic device 100 according to an embodiment of the present invention. Figure 1 As shown, the electronic device includes a main device 110 and multiple storage devices 120_1 to 120_N. Each storage device, taking storage device 120_1 as an example, includes a flash memory controller 122 and a flash memory module 124. In this embodiment, each of the multiple storage devices 120_1 to 120_N can be a solid-state drive (SSD) or any storage device with a flash memory module. The main device can be a central processing unit or other electronic device or component that can access the storage devices 120_1 to 120_N. The electronic device 100 itself can be a server, a personal computer, a laptop computer, or any portable electronic device. It should be noted that although... Figure 1 Multiple storage devices 120_1 to 120_N are shown, but in one embodiment, the electronic device 100 may have only a single storage device 120_1.

[0083] Figure 2A This is a schematic diagram of a flash memory controller 122 within a storage device 120_1 according to an embodiment of the present invention. Figure 2AAs shown, the flash memory controller 122 includes a microprocessor 212, a read-only memory (ROM) 212M, control logic 214, a buffer memory 216, and interface logic 218. The ROM 212M stores program code 212C, and the microprocessor 212 executes program code 212C to control access to the flash memory module 124. The control logic 214 includes an encoder 232 and a decoder 234. The encoder 232 encodes the data written to the flash memory module 220 to generate a corresponding check code (or error correction code, ECC), and the decoder 234 decodes the data read from the flash memory module 124.

[0084] In a typical configuration, the flash memory module 124 comprises multiple flash memory chips, and each flash memory chip contains multiple blocks. The flash memory controller 122 erases data from the flash memory module 124 on a block-by-block basis. Additionally, a block can record a specific number of data pages, and the flash memory controller 122 writes data to the flash memory module 124 on a page-by-page basis. In this embodiment, the flash memory module 124 is a 3D NAND-type flash memory module.

[0085] In practice, the flash memory controller 210, which executes program code 212C via microprocessor 212, can perform various control operations using its internal components. For example, it can use control logic 214 to control the access operations of flash memory module 124 (especially access operations to at least one block or at least one data page), use buffer memory 216 for necessary buffering, and use interface logic 218 to communicate with host device 110. Buffer memory 216 is implemented as random access memory (RAM). For example, buffer memory 216 can be SRAM, but the invention is not limited thereto. Furthermore, flash memory controller 122 is coupled to a DRAM 240. Note that DRAM 240 may also be included within flash memory controller 122, for example, existing in the same package as flash memory controller 122.

[0086] In this embodiment, the storage device 120_1 supports the NVMe specification, that is, the interface logic 218 can conform to a specific communication standard (such as the Peripheral Component Interconnect (PCI) standard or the PCIe standard), and can communicate according to the specific communication standard, for example, through a connector to communicate with the host device 110.

[0087] Figure 2B This is a schematic diagram of a block 200 in a flash memory module 124 according to an embodiment of the present invention, wherein the flash memory module 124 is a stereo NAND flash memory. Figure 2B As shown, block 200 contains multiple memory cells (such as the floating gate transistor 202 shown in the figure or other charge trap elements), which form a three-dimensional NAND flash memory architecture through multiple bit lines (only BL1 to BL3 are shown in the figure) and multiple word lines (such as WL0 to WL2, WL4 to WL6 shown in the figure). Figure 2B In the above-ground plane, for example, all floating-gate transistors on word line WL0 constitute at least one data page, all floating-gate transistors on word line WL1 constitute at least another data page, and all floating-gate transistors on word line WL2 constitute at least another data page, and so on. Furthermore, depending on the flash memory writing method, the definition between word line WL0 and data pages (logical data pages) will differ. Specifically, when writing using Single-Level Cell (SLC), all floating-gate transistors on word line WL0 correspond to only one logical data page; when writing using Multi-Level Cell (MLC), all floating-gate transistors on word line WL0 correspond to two logical data pages; when writing using Triple-Level Cell (TLC), all floating-gate transistors on word line WL0 correspond to three logical data pages; and when writing using Quad-Level Cell (QLC), all floating-gate transistors on word line WL0 correspond to four logical data pages. Since those skilled in the art should be able to understand the structure of 3D NAND flash memory and the relationship between word lines and data pages, the relevant details will not be elaborated here.

[0088] In this embodiment, the main device 110 can configure at least a portion of the flash memory module 124 as a zoned namespace by sending a configuration command set, such as a zoned namespaces command set. (See reference...) Figure 3As shown, the master device 110 can send a set of configuration instructions to the flash memory controller 122, so that the flash memory module 124 has at least one zone namespace (taking zone namespaces 310_1 and 310_2 as examples in this embodiment) and at least one general storage space (taking general storage spaces 320_1 and 320_2 as examples in this embodiment). Zone namespace 310_1 is divided into multiple zones for access, and the master device 110 must write data to zone namespace 310_1 in units of logical block addresses (LBAs). One logical block address (or simply logical address) can represent 512 bytes of data, and the master device 110 needs to write continuously to a zone. Specifically, refer to... Figure 4 The region namespace 310_1 is divided into multiple regions (e.g., Z0, Z1, Z2, Z3, etc.). The size of each region is set by the master device 110, but each region is the same size. The logical addresses corresponding to each region must be contiguous, and there will be no overlapping logical addresses between regions (that is, a logical address will only exist in one region). For example, assuming that the size of each region is x logical addresses, and the starting logical address of region Z3 is LBA_k, then region Z3 is used to store data corresponding to logical addresses LBA_k, LBA_(k+1), LBA_(k+2), LBA_(k+3), ..., LBA_(k+x-1). In one embodiment, the logical addresses of adjacent regions are also contiguous. For example, region Z0 is used to store data with logical addresses LBA_1 to LBA_2000, region Z1 is used to store data with logical addresses LBA_2001 to LBA_4000, region Z2 is used to store data with logical addresses LBA_4001 to LBA_6000, region Z3 is used to store data with logical addresses LBA_6001 to LBA_8000, and so on. Furthermore, the amount of data corresponding to a logical address can be determined by the main device 110. For example, the amount of data corresponding to a logical address can be 4 kilobytes (KB).

[0089] Furthermore, data in each region must be written in logical address order. Specifically, the flash memory controller 122 sets a writepoint based on the data being written to control the writing order. For instance, assuming region Z1 stores data with logical addresses LBA_2001 to LBA_4000, when the host device 110 transmits data corresponding to logical addresses LBA_2001 to LBA_2051 to the flash memory controller 122, the flash memory controller 122 sets the writepoint to the next logical address LBA_2052. If the master device 110 subsequently transmits data belonging to the same region but without a logical address LBA_2052 (for example, if the master device 110 transmits data with a logical address LBA_3000), the flash memory controller 122 will reject this data write and send a write failure message back to the master device 110. In other words, the flash memory controller 122 will only allow data writing if the logical address of the received data is the same as the logical address pointed to by the write indicator. Furthermore, if data from multiple regions is written alternately, each region can have its own write indicator.

[0090] As described above, the host device 110 communicates with the storage device 120_1 on a region-by-region basis to access the region namespace 310_1. However, since the region namespace 310_1 and each region are viewed from the perspective of the host device 110, the size of each region defined by the host device 110 does not have a fixed relationship with the size of each physical block within the flash memory module 124 in the storage device 120_1. Specifically, flash memory modules manufactured by different manufacturers are not the same, and different memory modules have physical blocks of different sizes. These physical block sizes are not necessarily integer multiples. For example, the physical block size of a flash memory module of type A may be 1.3 times larger than that of a flash memory module of type B, while the physical block size of a flash memory module of type C may be 3.7 times larger than that of a flash memory module of type B. As a result, it is very difficult for the regions defined by the host device 110 to be aligned with the physical blocks. At this point, the flash memory controller 122 will face significant difficulties in mapping logical blocks to physical blocks. For example, it may result in many redundant spaces in storage device 120_1 becoming unusable by the user. Alternatively, when the host device 110 prepares to write data corresponding to a region to the flash memory module 124, it will increase the complexity of the flash memory controller 122 in establishing the logical address to physical address (L2P) mapping table. In the following embodiments, this invention proposes a method that allows the flash memory controller 122 to efficiently access the region namespace 310_1 according to the access instructions of the host device 110.

[0091] Figure 5 This is a flowchart illustrating the writing of data from a future autonomous device 110 to a region namespace 310_1 according to an embodiment of the present invention. In this embodiment, it is assumed that the amount of data corresponding to each region is greater than the size of each physical block in the flash memory module 124, and the amount of data corresponding to each region is not an integer multiple of the size of each physical block in the flash memory module 124. In step 500, the process begins, the main device 110 and the storage device 120_1 are powered on and initialized. The main device 110 sets basic settings such as the size of each region, the number of regions, and the logical block address size for at least a portion of the storage regions in the storage device 120_1, for example, using a ZonedNamespaces Command Set. In step 502, the main device 110 sends a write command and corresponding data to the flash memory controller 122, wherein the data corresponds to one or more regions, for example... Figure 4The data in region Z3 corresponds to logical addresses LBA_k to LBA_(k+x-1). In step 504, the flash memory controller 122 selects at least one block (blank block, or spare block) from the flash memory module 124 and sequentially writes the data from the host device 110 into the at least one block. Since it is very difficult for the size of the region set by the host device 110 to match the size of the physical block, when the host device issues write instructions to all logical addresses in region Z3, the data that the host device 110 wants to write usually still cannot fill the storage space of the physical block. In other words, the amount of data stored in a region is usually not an integer multiple of the size of the region in a physical block used to store the data written by the host device 110. In step 506, after the data is written to the last block and the data writing is completed, the flash memory controller 122 will write invalid data to the remaining data pages of the last block, or directly leave the remaining data pages blank. Note that each block usually reserves a number of data pages to store system management information, such as write schedules, logical entity mapping tables, error correction code check bits, RAID parity, and other data required for management. The remaining data pages referred to here are the data pages that are still left after writing the system management information and the data that the master device 110 wants to store.

[0092] For example, refer to Figure 6Assuming that the amount of data corresponding to each region is between two and three blocks in the flash memory module 124, the flash memory controller 122 can sequentially write the data of region Z1 into blocks B3, B7, and B8 in response to the write command sent by the master device 110 for region Z1. Note that in one embodiment, the write command sent by the master device 110 for region Z1 includes the starting logical address of region Z1, and the flash memory controller 122 maps the starting logical address of region Z1 to the starting physical storage space of physical block B3, such as the first physical data page. Furthermore, the flash memory controller 122 stores the data corresponding to the starting logical address of region Z1 into the starting physical storage space of physical block B3, such as the first physical data page. Blocks B3, B7, and B8 each contain data pages P1 to PM. Data in region Z1 is written sequentially according to logical addresses, starting from the first data page P1 of block B3 and ending at the last data page PM. After block B3 is written, writing continues from the first data page P1 of block B7 to the last data page PM. Note that even if the master device 110 writes continuously to logical addresses within region Z1, the flash memory controller 122 can still select non-contiguous blocks B3 and B7 to store this logically continuous data. After block B7 is written, writing continues from the first data page P1 of block B8 until the end of region Z1; furthermore, the remaining data pages in block B8 will remain blank or be written with invalid data. Similarly, the flash memory controller 122 can sequentially write data from region Z3 into blocks B12, B99, and B6, where each block contains data pages P1 to PM. Data in region Z3 is written sequentially according to logical addresses, starting from the first data page P1 of block B12 and ending with the last data page PM. After block B12 is written, the process continues from the first data page P1 of block B99 to the last data page PM. After block B99 is written, the process continues from the first data page P1 of block B6 until the end of region Z3. Furthermore, the remaining data pages in block B6 remain blank or are written with invalid data. Note that the flash memory controller 122 may not establish logical page-to-physical page links for the physical data pages containing invalid data. These physical blocks containing blank or invalid data pages are typically mapped by the flash memory controller 122 to the last part of each region. In other words, the flash memory controller 122 stores the data corresponding to the last logical address of a region in a physical block containing blank or invalid data pages. For example... Figure 7BAs shown in the diagram (to be detailed later), the logical address Z1_LBA+S+2*y corresponds to the physical block address PBA8. Furthermore, if the data at the last logical address of a region is stored in the Xth storage unit (e.g., a physical page or segment) of a physical block, then the (X+1)th storage unit of that physical block will be reserved as a blank page or have invalid data written to it. That is, blank pages or pages with invalid data written to them are contiguous after the physical storage unit where the data at the last logical address of the corresponding region is stored. In another embodiment, the main device 110 defines a larger zone size and a smaller zone capacity, for example, a zone size of 512MB and a zone capacity of 500MB. In this example, the flash memory controller 122 may not directly contiguous blank pages or pages with invalid data written to them after the physical storage unit where the data at the last logical address of the corresponding region is stored.

[0093] In another embodiment, the master device 110 sends write commands to consecutive logical addresses in regions Z1 and Z2, while the flash memory controller 122 selects blocks B3, B7, B8, B12, B99, and B6 to store data belonging to regions Z1 and Z2. Since the region size set by device 110 is not the same as the physical block size, the data that the master device 110 wants to write cannot fill the storage space of the physical blocks. For example, it cannot fill the storage space in physical block B8 used to store host data. Therefore, the flash memory controller 122 still needs to leave those storage spaces in physical block B8 blank or fill them with invalid data. So, even though the master device 110 sends write commands to consecutive logical addresses in regions Z1 and Z2, and physical block B8 still has space to store data, the flash memory controller 122 will still not write the data to the starting logical address of region Z2. The corresponding data is stored in physical block B8. In other words, even if the host device 110 sends a write command for consecutive logical addresses (e.g., a write command containing the last logical address of region Z1 and the first logical address of region Z2), and a specific physical block (e.g., physical block B8) has enough space to store the data corresponding to these consecutive logical addresses, the flash memory controller 122 will still not store the data corresponding to these consecutive logical addresses consecutively in that specific physical block. Instead, it will skip over the data corresponding to the first logical address of region Z2 and write it to another physical block, such as block B20. Correspondingly, if the host device 110 sends a read command for consecutive logical addresses in regions Z1 and Z2 (e.g., a read command containing the last logical address of region Z1 and the first logical address of region Z2), after reading the data stored in physical block P8 corresponding to the last logical address of region Z1, the flash memory controller 122 will also skip over the first storage location in block B20 to obtain the data of the first logical address of region Z2.

[0094] In step 508, the flash memory controller 122 establishes or updates an L2P mapping table to record the mapping relationship between logical addresses and physical addresses for subsequent data reading from the region namespace 310_1. Figure 7A This is a schematic diagram of an L2P mapping table 700 according to an embodiment of the present invention. The L2P mapping table 700 includes two fields: one field records the starting logical address of the region, and the other field records the physical block address of the block. See also... Figure 6Since the data of region Z1 is written sequentially to blocks B3, B7 and B8, and the data of region Z3 is written sequentially to blocks B12, B99 and B6, the L2P mapping table 700 records the starting logical address Z1_LBA_S of region Z1 and the physical block addresses PBA3, PBA7 and PBA8 of blocks B3, B7 and B8, and also records the starting logical address Z3_LBA_S of region Z3 and the physical block addresses PBA12, PBA99 and PBA6 of blocks B12, B99 and B6. For example, assuming region Z1 is used to store data with logical addresses LBA_2001 to LBA_4000, and region Z3 is used to store data with logical addresses LBA_6001 to LBA_8000, then the starting logical address Z1_LBA_S of region Z1 is LBA_2001, and the starting logical address Z3_LBA_S of region Z3 is LBA_6001. Note that the steps in the flowchart for writing data from the autonomous device 110 to the region namespace 310_1 do not necessarily need to be performed in a fixed order as long as they achieve the same purpose. For example, step 508 can be executed after step 502. Those skilled in the art will understand this under the guidance of this invention. Note that in this embodiment, each entity block corresponds to only one region. For example, blocks B3, B7, and B8 correspond only to region Z1, and blocks B12, B99, and B6 correspond only to region Z3. In other words, a single block stores data for only one region. For example, blocks B3, B7, and B8 store data corresponding to region Z1, while blocks B12, B99, and B6 store data corresponding to region Z3.

[0095] In addition, if the host device 110 wants to reset a region, such as region Z1, the flash memory controller 122 will typically modify the L2P mapping table 700 to delete the fields corresponding to the physical block addresses of region Z1. For example, it will delete physical block addresses PBA3, PBA7, and PBA8 from the L2P mapping table 700, indicating that the host no longer needs the data stored in these physical blocks. The flash memory controller 122 can then erase these physical blocks later. Note that physical block B8 stores the data that the host device 110 wants to store, as well as invalid data, even though region Z1, which the host device 110 wants to reset, does not contain this invalid data. For management convenience, after receiving the reset command for region Z1 from the host device 110, the flash memory controller 122 will still delete the physical block address PBA8 from the L2P mapping table 700 as a whole, even though region Z1, which the host device 110 wants to reset, does not contain the invalid data stored in physical block B8. Furthermore, before erasing physical block B8, the flash memory controller 122 will not move invalid data not included in the reset command issued by the master device 110 to other physical blocks, but will directly delete the entire physical block.

[0096] In the above embodiments, the data stored in any entity block within the region namespace 310_1 must belong to the same region; that is, the logical addresses corresponding to all the data stored in any entity block will belong to the same region. Furthermore, since the main device 110 can only continuously write to logical addresses within a single region, the L2P mapping table 700 in this embodiment can contain only the entity block addresses of the region namespace 310_1, without containing any data page addresses. In other words, the L2P mapping table 700 does not record any data page sequence numbers or related data page information within any block. In addition, the L2P mapping table 700 only records the starting logical address of each region. Therefore, the L2P mapping table 700 itself has a very small amount of data, and thus it can reside permanently in the buffer memory 216 or DRAM 240 without placing a significant burden on the storage space of the buffer memory 216 or DRAM 240. Please note that since the starting logical address of each region is fixed after the main device 110 sets the region size and number of regions, the L2P mapping table 700 can be further simplified to a single field, namely, only the entity block address field. The starting logical address field of the region can then be represented using table entries, such as... Figure 7B The L2P mapping table 710 shown does not require actually storing the starting logical addresses of multiple regions.

[0097] In the above embodiments, the L2P mapping table 700 may only contain the entity block address of the region namespace 310_1, without containing any data page addresses. However, in another embodiment, the L2P mapping table 700 may contain the starting logical address of each region, the corresponding entity block address, and the entity data page address of the first data page. Since a region in the L2P mapping table only contains one entity block address and one entity data page address, it also has a very small amount of data.

[0098] Figure 7C This is a schematic diagram of an L2P mapping table 720 according to an embodiment of the present invention. The L2P mapping table 720 includes two fields, one field recording the logical address and the other field recording the physical block address of the block. See also... Figure 6Since data in region Z1 is written sequentially to blocks B3, B7, and B8, and data in region Z3 is written sequentially to blocks B12, B99, and B6, the L2P mapping table 720 records the starting logical address Z1_LBA_S of region Z1 and the physical block address PBA3 of block B3, the logical address (Z1_LBA_S+y) of region Z1 and the physical block address PBA7 of block B7, and the logical address (Z1_LBA_S+2*y) of region Z1 and the physical block address PBA8 of block B8. The logical address (Z1_LBA_S+y) can be the first logical address of the data written to block B7 (i.e., the logical address corresponding to data page P1 in block B7), and the logical address (Z1_LBA_S+2*y) can be the first logical address of the data written to block B8. That is, the logical address of data page P1 corresponding to block B8; similarly, L2P mapping table 720 records the starting logical address Z3_LBA_S of region Z3 and the entity block address PBA12 of block B12, the logical address (Z3_LBA_S+y) of region Z3 and the entity block address PBA99 of block B99, and the logical address (Z3_LBA_S+2*y) of region Z6 and the entity block address PBA6 of block B6, where the logical address (Z3_LBA_S+y) can be the first logical address of the data written to block B99 (that is, the logical address of data page P1 corresponding to block B99), and the logical address (Z3_LBA_S+2*y) can be the first logical address of the data written to block B6 (that is, the logical address of data page P1 corresponding to block B6). It should be noted that the "y" mentioned above can represent how many logical addresses of data can be stored in a block, specifically referring to the data that the master device 110 transmits to the storage device 120_1, requesting that the storage device 120_1 store. Please note that after the master device 110 sets the region size and number of regions, the starting logical address of each region is fixed, and the starting logical address of each sub-region is also fixed, such as Z1_LBA_S, Z1_LBA_S+y, Z1_LBA_S+2*y, Z2_LBA_S, Z2_LBA_S+y, Z2_LBA_S+2*y, etc. Therefore, similarly, the L2P mapping table 720 can be further simplified to a single field, namely, only the physical block address field. The logical address field can be represented using table entries, without actually storing the starting logical addresses of multiple sub-regions, for example... Figure 7D The L2P mapping table 740 is shown.

[0099] It should be noted that the L2P mapping table 720 in this embodiment only contains the physical block addresses of the region namespace 310_1, and does not contain any data page addresses. That is, the L2P mapping table 720 does not record any data page sequence numbers or related data page information within any block. Furthermore, the L2P mapping table 720 only records the first logical address corresponding to each block. Therefore, the L2P mapping table 720 itself has a very small amount of data, so it can reside in the buffer memory 216 or DRAM 240 without placing a significant burden on the storage space of the buffer memory 216 or DRAM 240. In one embodiment, the physical block addresses recorded in the L2P mapping table 720 can be combined with the physical data page address of the first data page, and adding an extra physical data page address will not practically place a significant burden on storage space.

[0100] Figure 8 This is a flowchart illustrating the process of reading data from a region namespace 310_1 according to an embodiment of the present invention, wherein this embodiment assumes that the region namespace 310_1 has already stored... Figure 6 The data in regions Z1 and Z3 are shown. In step 800, the process begins, the main device 110 and the storage device 120_1 are powered on and complete initialization operations (e.g., boot procedure). In step 802, the main device 110 sends a read instruction to request the reading of data with a specific logical address. In step 804, the microprocessor 212 in the flash memory controller 122 determines which region the specific logical address belongs to, and calculates the physical data page address corresponding to the specific logical address based on the logical address recorded in the L2P mapping table 700 or L2P mapping table 720. Figure 7A Using the L2P mapping table 700 as an example, since the L2P mapping table 700 records the starting logical address of each region, and the number of logical addresses in each region is known, the microprocessor 212 can use the above information to determine which region a specific logical address belongs to. Figure 6 , 7ATo illustrate with an example, suppose the specific logical address is LBA_2500, a region contains 2000 logical addresses, and the L2P mapping table 700 records the starting logical address Z1_LBA_S of region Z1 as LBA_2001. Then, the microprocessor 212 can determine that the specific logical address belongs to region Z1. Next, the microprocessor 212 determines the entity data page address corresponding to the specific logical address based on the difference between the specific logical address and the starting logical address Z1_LBA_S of region Z1, and based on how much logical address data each data page of the block can store. For ease of explanation, assuming that each data page in the block can only store data at one logical address, the difference between this specific logical address and the starting logical address Z1_LBA_S of region Z1 is 500 logical addresses. Then, the microprocessor 212 can calculate the physical data page address of the 500th data page P500 in block B3 corresponding to this specific logical address. If the number of data pages in block B3 is less than 500, then the 500th data page is counted from the first data page P1 of block B3 to obtain the physical data page address in block B7.

[0101] On the other hand, with Figure 7B Using the L2P mapping table 720 as an example, since the L2P mapping table 720 records multiple logical addresses for each region, and these logical addresses correspond to the first data page P1 of blocks B3, B7, and B8 respectively, the microprocessor 212 can determine from the above information which region and block the specific logical address belongs to. Next, the microprocessor 212 determines the entity data page address corresponding to the specific logical address based on the difference between the specific logical address and the logical address of region Z1 (e.g., Z1_LBA_S, (Z1_LBA_S+y) or (Z1_LBA_S+2y)), and based on how much data from each logical address can be stored in each data page of the block. For ease of explanation, assuming that each data page in the block can only store data at one logical address, the difference between this specific logical address and the starting logical address Z1_LBA_S of region Z1 is 500 logical addresses. Then, the microprocessor 212 can calculate the physical data page address of the 500th data page P500 of block B3 corresponding to this specific logical address.

[0102] In step 806, the microprocessor 212 reads the corresponding data from the region namespace 310_1 according to the entity block address and entity data page address determined in step 804, and sends the read data back to the main device 110.

[0103] As described above, through the embodiments above, the flash memory controller 122 can still effectively complete data writing and reading of the region namespace 310_1 even when only a very small L2P mapping table 700 / 710 / 720 / 730 is established. However, in this embodiment, many remaining data pages of physical blocks are wasted, such as blank or invalid data pages in physical blocks B8 and B6. These remaining data pages will greatly reduce the memory space available to the user. Although this method can reduce the management burden of the flash memory controller 122, it will reduce the memory space available to the user. In some extreme cases, due to the high proportion of remaining data pages, the flash memory controller 122 may not be able to allocate enough memory space for the user.

[0104] Figure 9 This is a flowchart illustrating the writing of data from a future autonomous device 110 to a region namespace 310_1 according to another embodiment of the present invention. In this embodiment, it is assumed that the amount of data corresponding to each region is greater than the size of each block in the flash memory module 124, and the amount of data corresponding to each region is not an integer multiple of the size of each block in the flash memory module 124. In step 900, the process begins, the main device 110 and the storage device 120_1 are powered on and initialized. The main device 110 sets basic settings for the storage device 120_1, such as the size of each region, the number of regions, and the logical block address size, for example, using a Zoned Namespaces Command Set. In step 902, the main device 110 sends a write command and corresponding data to the flash memory controller 122, wherein the data corresponds to one or more regions, for example... Figure 4 The data in region Z3 corresponds to logical addresses LBA_k to LBA_(k+x-1). In step 904, the flash memory controller 122 selects at least one block (blank block, or spare block) from the flash memory module 124, or selects at least one blank block or at least one shared block, and sequentially writes the data from the autonomous device 110 into these blocks. For example, refer to... Figure 10Assuming that the amount of data corresponding to each region is between two and three blocks in the flash memory module 124, the flash memory controller 122 can sequentially write the data of region Z1 into blocks B3, B7, and B8. Block B3 records the first part of the data Z1_0 from region Z1, block B7 records the second part of the data Z1_1 from region Z1, and block B8 records the third part of the data Z1_2 from region Z1. In this embodiment, since the data stored in blocks B3 and B7 is entirely from region Z1, while only a portion of the data pages in block B8 store the data from region Z1, the microprocessor 212 sets block B8 as a shared block to fully utilize the remaining data pages. That is, the remaining data pages in block B8 can be used to store data from other regions. (Continue to refer to...) Figure 10 The flash memory controller 122 prepares to write the data of region Z3 to the region namespace 310_1. Since there is still space remaining in the shared block B8, the microprocessor 212 selects two blank blocks B12 and B99, as well as the shared block B8, to store the data of region Z3. Specifically, the flash memory controller 122 writes the data of region Z3 sequentially into blocks B12, B99, and B8. Block B12 records the first part of the data Z3_0 of region Z3, block B99 records the second part of the data Z3_1 of region Z3, and block B8 records the third part of the data Z3_2 of region Z3. In this embodiment, the data stored in blocks B12 and B99 is entirely the data of region Z3, while block B8 simultaneously records the third part of the data Z1_2 of region Z1 and the third part of the data Z3_2 of region Z3. Please note that, for ease of management, the flash memory controller 122 does not store the first data entry of any region in a shared block, as this would increase the complexity of establishing the L2P mapping table. Instead, the flash memory controller 122 stores the first data entry of each region in a dedicated block, such as blocks B3 and B12. These dedicated blocks only store data belonging to the same region, hence the name "dedicated blocks." The last data entry of any region (corresponding to the last logical address of that region) is stored in a shared block, such as block B8, which also stores the last data entry of another region. In this embodiment, the shared block stores data from more than one region, or in other words, the shared block stores the last data entry of more than one region, while the dedicated blocks store data from only a single region.

[0105] In step 906, the flash memory controller 122 establishes or updates an L2P mapping table to record the mapping relationship between logical addresses and physical addresses, and records a shared block table for subsequent data reading from the region namespace 310_1. Figure 11A This is a schematic diagram of an L2P mapping table 1100A and a shared block table 1130A according to an embodiment of the present invention. The L2P mapping table 1100A includes two fields, one field recording the logical address and the other field recording the physical block address of the block. See also... Figure 10Since the data in region Z1 is written sequentially to blocks B3, B7, and B8, and the data in region Z3 is written sequentially to blocks B12, B99, and B8, the L2P mapping table 1100A records the starting logical address Z1_LBA_S of region Z1 and the physical block address PBA3 of block B3, the logical address (Z1_LBA_S+y) of region Z1 and the physical block address PBA7 of block B7, and the logical address (Z1_LBA_S+2*y) of region Z1 and the physical block address PBA8 of block B8. The logical address (Z1_LBA_S+y) can be the first logical address of the data written to block B7 (i.e., the first logical address of the second part of data Z1_1, and also the logical address corresponding to the first data page P1 of block B7), while the logical address (Z1_LBA_S+2*y) can be the first logical address of the data written to block B8. That is, the first logical address of the third part of data Z1_2); similarly, the L2P mapping table 1100A records the starting logical address Z3_LBA_S of region Z3 and the physical block address PBA12 of block B12, the logical address (Z3_LBA_S+y) of region Z3 and the physical block address PBA99 of block B99, and the logical address (Z3_LBA_S+2*y) of region Z6 and the physical block address PBA6 of block B6. The logical address (Z3_LBA_S+y) can be the first logical address of the data written to block B99 (that is, the first logical address of the second part of data Z3_1, and also the logical address of the first data page P1 of block B99), while the logical address (Z3_LBA_S+2*y) can be the first logical address of the data written to block B8 (that is, the first logical address of the third part of data Z3_2). It should be noted that the "y" mentioned above can represent how many logical addresses from the host can be stored in a block. Note that after the host device 110 sets the region size and number of regions, the starting logical address of each region is fixed, and the starting logical address of each sub-region is also fixed, such as Z1_LBA_S, Z1_LBA_S+y, Z1_LBA_S+2*y, Z2_LBA_S, Z2_LBA_S+y, Z2_LBA_S+2*y, etc. Therefore, similarly, the L2P mapping table 1100 can be further simplified to a single field, that is, only the entity block address field. The logical address field can be represented by the table entries, without actually storing the starting logical addresses of multiple sub-regions. Please refer to [reference needed]. Figure 11BThe L2P mapping table 1100B has fixed fields for each logical address, sorted from lowest to highest (or highest to lowest) logical address. For example, Z0_LBA_S represents the starting logical address of region 0, which is the lowest logical address in the system. Z0_LBA_S+y represents the starting logical address of the second sub-region of region 0, where y represents the number of addresses used by each entity block to store host data. Z0_LBA_S+2*y represents the starting logical address of the third sub-region of region 0. Since the region size is fixed, the value of y is also fixed. Figure 11B The values ​​in the logical address field are highly predictable, so this field can be omitted and represented only by the entry in L2P mapping table 1100B.

[0106] Additionally, the shared block table 1130A contains two fields: one field records the logical address, and the other field records the entity block address and entity data page address corresponding to the logical address. Figure 11A In the block table 1130A, the shared block table records the first logical address (Z1_LBA_S+2*y) of the third part of data Z1_2 in region Z1, along with the corresponding entity block address PBA8 and entity data page address P1. That is, the data in the third part of data Z1_2 corresponding to the first logical address is written to the first data page P1 of block B8. Similarly, the shared block table 1130A records the first logical address (Z3_LBA_S+2*y) of the third part of data Z3_2 in region Z3, along with the corresponding entity block address PBA8 and entity data page address P120. That is, the data in the third part of data Z3_2 corresponding to the first logical address is written to the 120th data page P120 of block B8. (Note that this assumes each data page in the block can only store data at one logical address; the actual situation can be adjusted based on how many logical addresses a data page can store.) Similar to... Figure 11B L2P mapping table 1100B in the middle, Figure 11A The shared block table 1130A in the middle is also available. Figure 11B The Chinese Communist Party uses the form of block table 1130B for the same reason, which will not be repeated here.

[0107] Additionally, it should be noted that during the writing process of data in regions Z1 and Z3, the writing process may not begin only after all the data in region Z1 has been written. In other words, the flash memory controller 122 may need to start writing the data in region Z3 to region namespace 310_1 before the data in region Z1 has been completely written. Therefore, in another embodiment of the present invention, the shared block table 1130 may additionally include a completion indicator field, which is used to indicate whether the data of the region has been completely written in the shared block. (See reference...) Figure 12 As shown, where Figure 12 The shared block table 1230 shown is a continuation Figure 10 Examples of implementations. In Figure 12 In (a), after the third part of data Z1_2 in region Z1 is completely written to the common block B8, the microprocessor 212 changes the completion indicator from '0' to '1'. Then, when the microprocessor 212 needs to write the third part of data Z3_2 in region Z3 to region namespace 310_1, since the completion indicator for the third part of data Z1_2 in region Z1 corresponding to common block B8 is '1', the microprocessor 212 can determine that common block B8 is currently available for data writing. Therefore, it writes the third part of data Z3_2 in region Z3 to common block B8 and records the third part of data Z3_2 and the corresponding entity block address and entity data page address in the shared block table 1230. On the other hand, in Figure 12 In (b), when the third part of data Z1_2 in region Z1 is being written to common block B8, its completion indicator is '0' (meaning that the third part of data Z1_2 in region Z1 has not yet been fully written to common block B8). If microprocessor 212 needs to write the third part of data Z3_2 in region Z3 to region namespace 310_1 at this time, since the completion indicator of the third part of data Z1_2 in region Z1 corresponding to common block B8 is '0', microprocessor 212 can determine that common block B8 is currently not available for the third part of data Z3_2 to be written. Therefore, microprocessor 212 selects another blank block (e.g., block B15) and writes the third part of data Z3_2 in region Z3 to block B15, and records the three parts of data Z3_2 and the corresponding entity block address PBA15 and entity data page address P1 in the common block table 1230. Please note that... Figure 12 The shared block table 1230 in the middle is also similar. Figure 11B The shared block table 1130B is presented with an additional completion indicator field, replacing the logical address field with a fixed logical address location. The reason for this is the same as that for L2P mapping table 1100B and shared block table 1130B, and will not be repeated here.

[0108] In one embodiment, if the host device 110 wants to reset a region, such as region Z1, the flash memory controller 122 typically modifies the L2P mapping tables 1100A / 1100B to delete the fields corresponding to the physical block addresses of region Z1. For example, it deletes physical block addresses PBA3, PBA7, and PBA8 from the L2P mapping tables 1100A / 1100B, indicating that the host no longer needs the data stored in these physical blocks. The flash memory controller 122 can then erase these physical blocks later. Note that physical block B8 stores the data that the host device 110 wants to store, as well as the data for region Z3, even though region Z1, which the host device 110 wants to reset, does not contain the data for region Z3. For ease of management, after receiving a reset command from the master device 110 for region Z1, the flash memory controller 122 still needs to modify the physical block addresses and physical data page addresses in the common block tables 1130A / 1130B / 1230, deleting PBA8 and P1, for example, rewriting them to FFFF. Note that the completion index in the common block table 1230 remains at 1 because the third part of region Z1, Z1_3, still occupies part of the space in physical block B8, and this space cannot be written to before physical block B8 is erased. Furthermore, before erasing physical block B8, the flash memory controller 122 does not need to move valid data not included in the reset command issued by the master device 110 (such as data in region Z3) to other physical blocks.

[0109] In the above embodiments, since common blocks are used to store data corresponding to different regions, it can be considered that data with logical addresses belonging to different regions can be stored in the same physical block. Therefore, the space of the physical block can be effectively utilized, avoiding the waste caused by the inconsistency between the region size and the physical block size, which would result in the space of an integer number of physical blocks not being filled when the logical address corresponding to a region has been completely written.

[0110] It should be noted that the L2P mapping tables 1100A / 1100B in this embodiment only contain the entity block addresses of the region namespace 310_1, and do not contain any data page addresses. That is, the L2P mapping tables 1100A / 1100B do not record any data page sequence numbers or related data page information within any block. In addition, the common block tables 1130A / 1130B / 1230 will only record a small number of logical addresses. In fact, because the logical addresses of the common block tables 1130A / 1130B / 1230 are extremely regular, the logical address fields can be omitted, and only the table entries can be used to represent them. Therefore, the L2P mapping tables 1100A / 1100B and the common block tables 1130A / 1130B / 1230 themselves have only a small amount of data, so the L2P mapping tables 1100A / 1100B and the common block tables 1130A / 1130B / 1230 can reside in the buffer memory 216 or the DRAM 240 without putting too much burden on the storage space of the buffer memory 216 or the DRAM 240.

[0111] Furthermore, since the entity block addresses corresponding to the last part of the fields in the L2P mapping table 1100A / 1100B, such as (Z1_LBA_S+2*y), (Z3_LBA_S+2*y), etc., are not precise entity addresses, the microprocessor 212 needs to find the correct entity page address by searching the common block table 1130A / 1130B / 1230. Therefore, the entity address corresponding to the last part of the fields in the L2P mapping table 1100A / 1100B, such as (Z1_LBA_S+2*y), (Z3_LBA_S+2*y), etc., such as PBA8, can be directly changed to the corresponding entry address in the common block table 1130A / 1130B / 1230, allowing the microprocessor 212 to directly access the corresponding entry address in the common block table 1130A / 1130B / 1230. For example, the PBA8 corresponding to the (Z1_LBA_S+2*y) field in L2P mapping table 1100A / 1100B can be directly changed to the memory address corresponding to the (Z1_LBA_S+2*y) field in common block table 1130A / 1130B. Similarly, the PBA8 corresponding to the (Z3_LBA_S+2*y) field in L2P mapping table 1100A / 1100B can be directly changed to the memory address (e.g., an address in DRAM or SRAM) corresponding to the (Z3_LBA_S+2*y) field in common block table 1130A / 1130B, thus accelerating the lookup speed.

[0112] Figure 13 This is a flowchart illustrating the process of reading data from a region namespace 310_1 according to an embodiment of the present invention, wherein this embodiment assumes that the region namespace 310_1 has already stored... Figure 10The data in regions Z1 and Z3 are shown. In step 1300, the process begins, the main device 110 and the storage device 120_1 are powered on and complete initialization operations (e.g., boot procedure). In step 1302, the main device 110 sends a read instruction to request the reading of data with a specific logical address. In step 1304, the microprocessor 212 in the flash memory controller 122 determines which region the specific logical address belongs to, and calculates the physical data page address corresponding to the specific logical address based on the logical addresses recorded in the L2P mapping tables 1100A / 1100B and / or the common block tables 1130A / 1130B / 1230. Figure 11AUsing L2P mapping table 1100A as an example, since L2P mapping table 1100A records multiple logical addresses of multiple regions, and these logical addresses correspond to which data page of blocks B3, B7, and B8 respectively, and the number of logical addresses that each block can store is known, the microprocessor 212 can use the above information to determine which region and block a specific logical address belongs to. Next, assuming that the specific logical address belongs to region Z1, the microprocessor 212 determines the entity data page address corresponding to the specific logical address based on the difference between the specific logical address and the logical address of region Z1 (e.g., Z1_LBA_S, (Z1_LBA_S+y) or (Z1_LBA_S+2y)), and based on how many logical addresses of data each data page of the block can store. For ease of explanation, assume that each data page in the block can only store data for one logical address. The difference between this specific logical address and the starting logical address Z1_LBA_S of region Z1 is 500 logical addresses, and this specific logical address is between Z1_LBA_S and (Z1_LBA_S+y) (where y represents the number of addresses used by each entity block to store host data, and in this example y>500). Then, the microprocessor 212 can calculate the entity data page address of the 500th data page P500 of block B3 corresponding to this specific logical address. In this example, the microprocessor 212 divides the difference 500 by y, obtaining a quotient of 0 and a remainder of 500. The microprocessor 212 can then know that the entity block address corresponding to the specific logical address should be the first entry in the L2P mapping table 1100A. After searching, the microprocessor 212 finds that the entity block address corresponding to the specific logical address is entity block address PBA3. Since the remainder is 500, the microprocessor 212 can determine that the physical page address corresponding to the specific logical address is P500. Note that in addition to physical pages, smaller read units can also be used for addressing, such as sectors or 4Kbytes or other addressing units that conform to the NVMe specification. On the other hand, assuming that the specific logical address belongs to region Z3, the microprocessor 212 determines the physical data page address corresponding to the specific logical address based on the difference between the specific logical address and the logical address of region Z3 (e.g., Z3_LBA_S, (Z3_LBA_S+y) or (Z3_LBA_S+2y)), and based on how much data of a logical address can be stored in each data page of the block.For ease of explanation, assume that each data page in the block can only store data at one logical address. This specific logical address is greater than (Z3_LBA_S+2y) and less than or equal to the maximum logical address of region Z3. The difference between this specific logical address and the logical address (Z3_LBA_S+2y) of region Z3 is eighty logical addresses. Then, the microprocessor 212 can refer to the physical data page address P120 corresponding to the third part of the data Z3_2 of region Z3 recorded in the shared block table 1130, and calculate the physical data page address of the two hundredth data page P200 of shared block B8 corresponding to this specific logical address.

[0113] In step 1306, the microprocessor 212 reads the corresponding data from the region namespace 310_1 according to the entity block address and entity data page address determined in step 1304, and sends the read data back to the main device 110.

[0114] As described above, through the above embodiments, the flash memory controller 122 can still effectively complete the writing and reading of data in the region namespace 310_1 even with only a small L2P mapping table 1100A / 1100B and a common data table 1130A / 1130B / 1230.

[0115] In the above Figures 5-13 In the embodiment, it is assumed that the amount of data corresponding to each region is greater than the size of each block in the flash memory module 124. However, the main device 110 may also have the amount of data corresponding to each region be less than the size of each block in the flash memory module 124. The relevant access methods are as follows.

[0116] Figure 14 This is a flowchart illustrating the writing of data from a future autonomous device 110 to a region namespace 310_1 according to another embodiment of the present invention. In this embodiment, it is assumed that the amount of data corresponding to each region is less than the size of each block in the flash memory module 124. In step 1400, the process begins, the main device 110 and the storage device 120_1 are powered on and initialized. The main device 110 sets basic settings for the storage device 120_1, such as the size of each region, the number of regions, and the logical block address size, for example, using a Zoned Namespaces Command Set. In step 1402, the main device 110 sends a write command and corresponding data to the flash memory controller 122, wherein the data corresponds to one or more regions, for example... Figure 4The data in region Z3 corresponds to logical addresses LBA_k to LBA_(k+x-1). In step 1404, the flash memory controller 122 selects at least one block (blank block, or spare block) from the region namespace 310_1, and sequentially writes the data of the autonomous device 110 to the at least one block according to the logical address order. In this embodiment, a block is only used to write data from a single region, so as to... Figure 15 For example, the flash memory controller 122 writes data from region Z0 to block B20, data from region Z1 to block B30, data from region Z2 to block B35, and so on. In step 1406, after the data in each region is completely written, the flash memory controller 122 writes invalid data to the remaining data pages in each block (excluding those used for system control), or simply leaves the remaining data pages blank. Figure 15 For example, after the flash memory controller 122 writes all the data of region Z0 to block B20, the remaining data pages of B20 will be left blank or filled with invalid data. After the flash memory controller 122 writes all the data of region Z1 to block B30, the remaining data pages of block B30 will be left blank or filled with invalid data. And after the flash memory controller 122 writes all the data of region Z2 to block B35, the remaining data pages of block B35 will be left blank or filled with invalid data.

[0117] Please note that in one embodiment, the master device 110 sends write commands to consecutive logical addresses in regions Z0, Z1, and Z2, while the flash memory controller 122 selects blocks B20, B30, and B35 to store data belonging to regions Z0, Z1, and Z2. Since the region size set by device 110 is not the same as the physical block size, the data that the master device 110 intends to write cannot fill the storage space of the physical block. For example, it cannot fill the storage space in physical block B20 used to store host data. Therefore, the flash memory controller 122 still needs to leave those storage spaces in physical block B20 blank or fill them with invalid data. So, even though the master device 110 sends write commands to consecutive logical addresses in regions Z0 and Z1, and physical block B20 still has space to store data, the flash memory controller 122 will not write data to the starting logical address of region Z1. The corresponding data is stored in physical block B20. In other words, even if the master device 110 sends a write command for consecutive logical addresses (e.g., a write command containing the last logical address of region Z0 and the first logical address of region Z1), and a specific physical block (e.g., physical block B20) has enough space to store the data corresponding to these consecutive logical addresses, the flash memory controller 122 will still not store the data corresponding to these consecutive logical addresses consecutively in that specific physical block. Instead, it will skip over the data corresponding to the first logical address of region Z1 and write it to another physical block, such as block B30. Correspondingly, if the master device 110 sends a read command for consecutive logical addresses in regions Z0 and Z1 (e.g., a read command containing the last logical address of region Z0 and the first logical address of region Z1), after reading the data stored in physical block B20 corresponding to the last logical address of region Z1, the flash memory controller 122 will also skip over the first storage location in block B30 to obtain the data of the first logical address of region Z1.

[0118] In step 1408, the flash memory controller 122 establishes or updates an L2P mapping table to record the mapping relationship between logical addresses and physical addresses for use when reading data from the region namespace 310_1. Figure 16 This is a schematic diagram of an L2P mapping table 1600 according to an embodiment of the present invention. The L2P mapping table 1600 includes two fields: one field records the region number or related identifiable content, and the other field records the physical block address of the block. See also... Figure 6Since the data of regions Z0, Z1, and Z2 are written to blocks B20, B30, and B35 respectively, the L2P mapping table 1600 records the physical block address PBA20 of region Z0 and block B20, the physical block address PBA30 of region Z1 and block B30, and the physical block address PBA35 of region Z2 and block B35. In another embodiment, the aforementioned region number is represented by the starting logical address of the region, or the block number can be linked to the starting logical address of the block through another lookup table. For example, assuming region Z0 is used to store data with logical addresses LBA_1 to LBA_2000, region Z1 is used to store data with logical addresses LBA_2001 to LBA_4000, and region Z2 is used to store data with logical addresses LBA_4001 to LBA_6000, then the starting logical addresses of regions Z0, Z1, and Z2 are LBA_1, LBA_2001, and LBA_4001, respectively. Note that in this embodiment, each entity block corresponds to only one region; for example, blocks B20, B30, and B35 correspond to regions Z0, Z1, and Z2, respectively. In other words, a single block stores data for only one region. For example, block B20 stores data corresponding to region Z0, block B30 stores data corresponding to region Z1, and block B35 stores data corresponding to region Z2.

[0119] In the above embodiments, the data stored in any entity block within region namespace 310_1 must belong to the same region; that is, the logical addresses of all data stored within any entity block belong to the same region. Therefore, the L2P mapping table 1600 in this embodiment may only contain the entity block addresses of region namespace 310_1, without containing any data page addresses. In other words, the L2P mapping table 1600 does not record any data page sequence numbers or related data page information within any block. Furthermore, the L2P mapping table 1600 only records the region number or starting logical address of each region. Therefore, the L2P mapping table 1600 itself has a very small data volume, and thus, the L2P mapping table 1600 can reside in buffer memory 216 or DRAM 240 without placing a significant burden on the storage space of buffer memory 216 or DRAM 240. In one embodiment, the entity block address recorded in the L2P mapping table 1600 can be combined with the entity data page address of the first data page. Adding an extra entity data page address does not practically impose a significant burden on storage space. Note that since the starting logical address of each region is fixed after the main device 110 sets the region size and number of regions, similarly, the L2P mapping table 1600 can be further simplified to a single field—that is, only the entity block address field. The logical address field can then be represented using table entries, eliminating the need to actually store the starting logical addresses of multiple regions.

[0120] In addition, if the host device 110 wants to reset a region, such as region Z1, the flash memory controller 122 will typically modify the L2P mapping table 1600 to delete the field corresponding to the physical block address of region Z1. For example, deleting the physical block address PBA30 in the L2P mapping table 1600 indicates that the host no longer needs the data stored in those physical blocks. The flash memory controller 122 can then erase those physical blocks later. Note that physical block B30 stores the data that the host device 110 wants to store, as well as invalid data, even though region Z1, which the host device 110 wants to reset, does not contain that invalid data. For management convenience, after receiving the reset command for region Z1 from the host device 110, the flash memory controller 122 will still delete the physical block address PBA30 in the L2P mapping table 1600 as a whole, even though region Z1, which the host device 110 wants to reset, does not contain the invalid data stored in physical block B30. Furthermore, before erasing physical block B30, the flash memory controller 122 will not move invalid data not included in the reset command issued by the master device 110 to other physical blocks, but will directly delete the entire physical block.

[0121] Figure 17 This is a flowchart illustrating the reading of data from region namespace 310_1 according to another embodiment of the present invention, wherein this embodiment assumes that region namespace 310_1 has already stored... Figure 15 The data in regions Z0, Z1, and Z2 are shown. In step 1700, the process begins, the main device 110 and the storage device 120_1 are powered on and complete initialization operations (e.g., boot procedure). In step 1702, the main device 110 sends a read instruction to request the reading of data with a specific logical address. In step 1704, the microprocessor 212 in the flash memory controller 122 determines which region the specific logical address belongs to and calculates the physical data page address corresponding to the specific logical address based on the logical address recorded in the L2P mapping table 1600. Figure 16 Using the L2P mapping table 1600 as an example, since the L2P mapping table 1600 records the region number or starting logical address of each region, and the number of logical addresses in each region is known, the microprocessor 212 can use the above information to determine which region a specific logical address belongs to. For example, if a region contains 2000 logical addresses, the microprocessor 212 divides the logical address (the specific logical address) that the host wants to access by 2000, and the quotient is the region where the specific logical address belongs. Figure 15 , 16 To illustrate with an example, suppose microprocessor 212 divides the specific logical address by 2000 and finds the quotient to be 1, indicating that the specific logical address belongs to region Z1. Microprocessor 212 then determines the physical data page address corresponding to the specific logical address based on the difference between the specific logical address and the starting logical address of region Z1 (this difference is also the remainder after dividing the specific logical address by 2000), and based on how many logical addresses of data each data page of the block can store. For ease of explanation, assume that each data page in the block can only store one logical address of data, and the difference between the specific logical address and the starting logical address of region Z1 is two hundred logical addresses. Then, microprocessor 212 can calculate the physical data page address of the two hundredth data page of block B20 corresponding to the specific logical address.

[0122] In step 1706, the microprocessor 212 reads the corresponding data from the region namespace 310_1 according to the entity block address and entity data page address determined in step 1704, and sends the read data back to the main device 110.

[0123] As described above, through the embodiments presented, the flash memory controller 122 can still effectively complete data writing and reading from the region namespace 310_1 even with only a small L2P mapping table 700 / 720. However, in this embodiment, a significant amount of physical block storage space is still wasted, for example... Figure 15 The blank or invalid data page shown.

[0124] Figure 18 This is a flowchart illustrating the writing of data from a future autonomous device 110 to a region namespace 310_1 according to another embodiment of the present invention. In this embodiment, it is assumed that the amount of data corresponding to each region is less than the size of each block in the flash memory module 124. In step 1800, the process begins, the main device 110 and the storage device 120_1 are powered on and initialized. The main device 110 sets basic settings for the storage device 120_1, such as the size of each region, the number of regions, and the logical block address size, for example, using a Zoned Namespaces Command Set. In step 1802, the main device 110 sends a write command and corresponding data to the flash memory controller 122, wherein the data corresponds to one or more regions, for example... Figure 4 The data in region Z3 corresponds to logical addresses LBA_k to LBA_(k+x-1). In step 1804, the flash memory controller 122 selects at least one block (blank block, or spare block) from the region namespace 310_1, or selects multiple blank blocks and a shared block, and sequentially writes the data of the autonomous device 110 into these blocks according to the logical address order within a region. For example, refer to... Figure 19 The flash memory controller 122 can sequentially write data from regions Z0, Z2, and Z1 into blocks B20 and B30 according to their logical address order. Figure 19 For example, the first piece of data in region Z0 is written starting from the first data page of block B20, and after all the data in region Z0 has been written, please refer to... Figure 20The L2P mapping table 2000, which will be detailed below, is used. The flash memory controller 122 changes the available index corresponding to region number Z0 from 0 to 1, indicating that all data in region number Z0 has been written. The remaining space in the physical block PBA20 stored in region number Z0 can be used to store other data. Because the remaining space in physical block PBA20 can be used to store other data, the data in region Z2 can also be written to the remaining data pages of block B20. If the flash memory controller 122 cannot find any physical block with an available index of 1 when processing the write instruction for region Z2, the flash memory controller 122 should extract a blank block or a spare block to write the data in region Z2.

[0125] In this example, since the available index corresponding to physical block PBA20 is 1, the flash memory controller 122 can directly use physical block PBA20 to store the data of region Z2 without extracting another blank block or spare block. However, since the number of remaining data pages in block B20 is insufficient to store all the data in region Z2, the data in region Z2 is divided into a first part Z2_1 and a second part Z2_2. The first part Z2_1 is stored in block B20, while the second part Z2_2 is written to starting from the first data page of block B30 by the flash memory controller 122 extracting another blank block. Because physical block PBA20 is full after the remaining data pages of block B20 are filled with the first part Z2_1, and no more data can be written, the flash memory controller 122 changes the available index corresponding to region Z0 to 0 and keeps the available index corresponding to region Z2_1 at 0. After the second part Z2_2 of region Z2 has been written, the flash memory controller 122 changes the available index corresponding to region number Z2_2 from 0 to 1. Similarly, the data of region Z1 then begins to be written to the remaining data pages of block B30.

[0126] In step 1806, the flash memory controller 122 establishes or updates an L2P mapping table to record the mapping relationship between logical addresses and physical addresses for subsequent data reading from the region namespace 310_1. Figure 20 This is a schematic diagram of an L2P mapping table 2000 according to an embodiment of the present invention. The L2P mapping table 2000 includes two fields: one field records the block number or logical address range, and the other field records the entity block address and entity data page address corresponding to the first logical address of the logical address range. Figure 20In this example, L2P mapping table 2000 records the first logical address of region Z0 or its logical address range, along with the corresponding entity block address PBA20 and entity data page address P1; the logical address range of the first part Z2_1 of region Z2, along with the entity block address PBA20 and entity data page address Pa corresponding to the first logical address of that range; the logical address range of the second part Z2_2 of region Z2, along with the entity block address PBA30 and entity data page address P1 corresponding to the first logical address of that range; and region Z1 or its logical address range, along with the entity block address PBA30 and entity data page address Pb corresponding to the first logical address of that range. Note that in this example, a single entity block filled with data stores data from multiple regions.

[0127] Additionally, it should be noted that during the writing process of data in regions Z0, Z2, and Z1, the writing process may not begin until all the data in region Z0 has been written before starting to write the data in region Z1 to region namespace 310_1. In other words, the flash memory controller 122 may need to start writing the data in region Z1 to region namespace 310_1 before the data in region Z0 has been completely written. Therefore, as described above, in another embodiment of the present invention, the L2P mapping table 2000 may additionally include an available indicator field to indicate whether the data of a region has been completely written in the shared block.

[0128] In the above embodiments, since the L2P mapping table 2000 stores the address relationship of data corresponding to different regions within the block, it can be considered that data with logical addresses belonging to different regions can be stored in the same physical block, thus effectively utilizing the space of the physical block.

[0129] It should be noted that the L2P mapping table 2000 in this embodiment only records a small number of logical addresses (a small number of entity data page addresses). Therefore, the L2P mapping table 2000 itself has a very small amount of data. Thus, the L2P mapping table 2000 can reside in the buffer memory 216 or DRAM 240 without placing too much burden on the storage space of the buffer memory 216 or DRAM 240.

[0130] Figure 21 This is a flowchart illustrating the process of reading data from a region namespace 310_1 according to an embodiment of the present invention, wherein this embodiment assumes that the region namespace 310_1 has already stored... Figure 19The data in regions Z1, Z2, and Z3 are shown. In step 2100, the process begins, the main device 110 and the storage device 120_1 are powered on and complete initialization operations (e.g., boot procedure). In step 2102, the main device 110 sends a read instruction to request the reading of data with a specific logical address. In step 2104, the microprocessor 212 in the flash memory controller 122 determines which region the specific logical address belongs to, and calculates the physical data page address corresponding to the specific logical address based on the region number or logical address recorded in the L2P mapping table 2000. Figure 20 Using the L2P mapping table 2000 as an example, since the L2P mapping table 2000 records the block number or logical address range of each region, and the number of logical addresses that each block can store is known, the microprocessor 212 can use the above information to determine which region and block a specific logical address belongs to. Next, assuming that the specific logical address belongs to region Z0, the microprocessor 212 determines the entity data page address corresponding to the specific logical address based on the difference between the specific logical address and the starting logical address of region Z0, and based on how many logical addresses of data each data page of the block can store.

[0131] In step 2106, the microprocessor 212 reads the corresponding data from the region namespace 310_1 according to the entity block address and entity data page address determined in step 2104, and sends the read data back to the main device 110.

[0132] As described above, through the above embodiments, the flash memory controller 122 can still effectively complete the writing and reading of data in the region namespace 310_1 even when only a very small L2P mapping table 2000 is established.

[0133] Refer to the above Figures 5-21 The embodiment shown, Figure 5 ~7 describes that the amount of data corresponding to each region is greater than the size of each block in the flash memory module 124, and each block in the flash memory module 124 will only store data corresponding to a single region, that is, data from different regions will not be written to the same physical block. Figures 8-12 It describes that the amount of data corresponding to each region is greater than the size of each block in the flash memory module 124, and some blocks in the flash memory module 124 will store data corresponding to multiple regions, that is, data from different regions can be written into the same physical block. Figures 13-17It describes that the amount of data corresponding to each region is less than the size of each block in the flash memory module 124, and each block in the flash memory module 124 will only store data corresponding to a single region, that is, data from different regions will not be written to the same physical block. Figures 18-21 It describes that the amount of data corresponding to each region is less than the size of each block in the flash memory module 124, and the blocks in the flash memory module 124 will store data corresponding to multiple regions, that is, data from different regions can be written into the same physical block.

[0134] In one embodiment, the four access modes described above can be selectively applied to the region namespace of the flash memory module 124, and if the flash memory module 124 has multiple region namespaces, these region namespaces can also employ different access modes. Specifically, refer to... Figure 3 As shown, the microprocessor 212 within the flash memory controller 122 can select the access mode based on the size of each region in the region namespace 310_1. For example, if the amount of data corresponding to each region in the region namespace 310_1 is greater than the size of each block in the flash memory module 124, the microprocessor 212 can use... Figure 5 The access modes mentioned in ~7 or Figures 8-12 The access mode mentioned above is used to access the region namespace 310_1; if the amount of data corresponding to each region of the region namespace 310_2 is smaller than the size of each block in the flash memory module 124, the microprocessor 212 can use Figures 13-17 The access mode mentioned or Figures 18-21 The access modes mentioned above are used to access region namespace 310_2. Similarly, the microprocessor 212 within the flash memory controller 122 can select the access mode based on the size of each region in region namespace 310_2. The access mode used for region namespace 310_2 does not necessarily have to be the same as that used for region namespace 310_1; for example, region namespace 310_1 could use... Figure 5 The access modes mentioned in ~7, and the region namespace 310_2 can adopt Figures 8-12 The access mode mentioned.

[0135] Please note that since the flash memory controller 122 cannot know in advance the size of the region that the host device 110 intends to set, in order for the flash memory controller 122 to be compatible with all compliant host devices, the flash memory controller 122 must be capable of executing... Figures 5-21All access methods of the illustrated embodiment. For example, after learning the size of a single physical block (or superblock size, the concept of which will be detailed below) of the flash memory module 124 and the area size set by the host device 110, the flash memory controller 122 can plan the memory space that the host device can actually use according to the physical block size and the area size, and select which of the four access modes should be used for access.

[0136] If the region size is smaller than the physical block size, then the flash memory controller 122 can select... Figures 13-21 Access is performed in this manner. Because... Figures 13-17 The aforementioned access mode may waste a significant amount of memory space, and may even prevent the flash memory controller 122 from allocating sufficient memory space for the host device. For example, under this access mode, the flash memory controller 122 can only allocate 1.2TB of capacity from the 2TB flash memory module for the host device 110, while the host device may expect at least 1.5TB of capacity. Therefore, the flash memory controller 122 needs to change its access mode. For example, the flash memory controller 122 could be modified to... Figures 18-21 Access is performed in this manner. Because this access mode greatly reduces the waste of flash memory space, the flash memory controller 122 can allocate a larger capacity for the host device 110. For example, the flash memory controller 122 can allocate 1.8TB of capacity from a 2TB flash memory module for the host device 110, thus meeting the host device 110's memory storage requirements. In other words, the capacity that the host device 110 might expect can be considered a standard, and when the region namespace adopts... Figures 13-17 When the planned capacity for the access method is higher than the standard of the main device 110, the flash memory controller 122 can select... Figures 13-17 The access method; in addition, if the region namespace uses Figures 13-17 When the planned capacity is lower than the standard of the main device 110 during the access mode, the flash memory controller 122 can select... Figures 18-21 Access methods.

[0137] If the region size is larger than the physical block size, then the flash memory controller 122 may select... Figures 5-12 Access is performed in this manner. Because... Figure 5The access mode mentioned in section 7 may waste a significant amount of memory space, and may even prevent the flash memory controller 122 from allocating enough memory space for the host device. For example, with this access mode, the flash memory controller 122 can only allocate 1.2TB of capacity from the 2TB flash memory module for the host device 110, while the host device may expect at least 1.5TB of capacity. Therefore, the flash memory controller 122 needs to change its access mode. For example, the flash memory controller 122 could be modified to... Figures 8-12 Access is performed in this manner. Because this access mode greatly reduces the waste of flash memory space, the flash memory controller 122 can allocate a larger capacity for the host device 110. For example, the flash memory controller 122 can allocate 1.8TB of capacity from a 2TB flash memory module for the host device 110, thus meeting the host device 110's memory storage requirements. In other words, the capacity that the host device 110 might expect can be considered a standard, and when the region namespace adopts... Figure 5 When the planned capacity for access mode ~7 is higher than the standard of the main device 110, the flash memory controller 122 can select... Figure 5 ~7 access mode; additionally, if the region namespace is using Figure 5 When the planned capacity for access mode ~7 is lower than the standard of the main device 110, the flash memory controller 122 can select... Figures 8-12 Access methods.

[0138] Figure 25 This is a flowchart of a control method applied to a flash memory controller according to an embodiment of the present invention. Referring to the above embodiments, the flow of the control method is as follows:

[0139] Step 2500: Process begins.

[0140] Step 2502: Receive a setting instruction from a master device, wherein the setting instruction sets at least a portion of the flash memory module as a region namespace, wherein the region namespace logically contains multiple regions, and the master device must perform data write and access to the region namespace on a region-by-region basis, each region being the same size, the logical addresses corresponding to each region being contiguous, and there being no overlapping logical addresses between regions.

[0141] Step 2504: Using one of a first access mode, a second access mode, a third access mode, and a fourth access mode, data from the master device is written to the flash memory module, wherein the data is all data in a specific area.

[0142] Step 2506: If the first access mode is used, the data is written sequentially to multiple specific blocks of the flash memory module according to the logical address order of the data.

[0143] Step 2508: After the data has been written, write invalid data to the remaining data page of the last specific block of the multiple specific blocks, or leave the remaining data page blank without writing any data.

[0144] Step 2510: If the second access mode is used, the data is written sequentially to the multiple specific blocks of the flash memory module according to the logical address order of the data.

[0145] Step 2512: After the data has been written, use a completion indicator to mark the last specific block of the multiple specific blocks as written complete.

[0146] Step 2514: If the third access mode is used, the data is written sequentially to a single specific block of the flash memory module according to the logical address order of the data.

[0147] Step 2516: After the data has been written, write invalid data to the remaining data pages of the specific block, or leave the remaining data pages blank without writing any data.

[0148] Step 2518: If the fourth access mode is used, the data is written sequentially to individual blocks of the flash memory module according to the logical address order of the data.

[0149] Step 2520: Once the data has been written, use a completion indicator to mark the specific block as written.

[0150] Please note that in another embodiment, in order to simplify the design of the controller 122, the controller 122 may support only one of the above four access modes, or the controller 122 may support only two of the above four access modes, or the controller 122 may support only three of the above four access modes, depending on the specific flash memory module and host device.

[0151] Furthermore, in one embodiment of the present invention, the storage device 120_1 may be a Secure Digital Memory Card, which supports data transmission in conventional secure digital mode, that is, it uses the UHS-I input / output communication interface standard to communicate with the host device 110, and also supports PCIe mode that simultaneously supports PCIe channel and NVMe protocol.

[0152] In the implementation of flash memory module 124, flash memory controller 122 configures blocks belonging to different data planes within flash memory module 124 into a superblock to facilitate data access management. Specifically, refer to... Figure 22 This is a schematic diagram of the general storage space 320_1 of the flash memory module 124 shown. (See diagram below.) Figure 22 As shown, the general storage space 320_1 includes two channels, channel 1 and channel 2, which are connected to multiple flash memory chips 2210, 2220, 2230, and 2240, respectively. Flash memory chip 2210 includes two data planes 2212 and 2214; flash memory chip 2220 includes two data planes 2222 and 2224; flash memory chip 2230 includes two data planes 2232 and 2234; and flash memory chip 2240 includes two data planes 2242 and 2244. Each data plane contains multiple blocks B0 to BN. During the configuration or initialization of the general storage space 320_1, the flash memory controller 122 configures the first block B0 of each data plane as a super block 2261, the second block B1 of each data plane as a super block 2262, and so on. Figure 22 As shown, superblock 2261 contains eight physical blocks. When the flash memory controller 122 accesses superblock 2261, it behaves similarly to a regular block. For example, superblock 2261 itself is an erasure unit; that is, although the eight blocks B0 of superblock 2261 can be erased separately, the flash memory controller 122 will always erase all eight blocks B0 together. Furthermore, when writing data to superblock 2261, it can sequentially start from the first data page of data plane 2212, then data plane 2214... The first data page of data plane 2222, the first data page of data plane 2224, and the first data page of data plane 2224 are written to sequentially until the first data page of data plane 2244 is completed. Then, data is written to the second data page of data plane 2212, the second data page of data plane 2214, and so on. In other words, the flash memory controller 122 will fill the first data page of each block B0 in superblock 2261 before writing the second data page of each block B0 in superblock 2261. A superblock is a logically defined set of blocks by the flash memory controller 122 for convenient management of storage space 320_1, not a physical set of blocks. Furthermore, garbage collection, calculation of valid pages in blocks, and calculation of block write time can all be performed on a superblock basis. Under the teachings of this invention, those skilled in the art can... Figures 5-21The illustrated embodiments are understood to be... Figures 5-21 The entity block mentioned in the illustrated embodiment can also be a superblock. All related embodiments can be implemented using superblocks, rather than being limited to a single entity block.

[0153] However, if the flash memory controller 122 configures the blocks within the flash memory module 124 as superblocks, then... Figures 5-8 If the implementation method is used for data access, it is very likely that each block will have a lot of remaining data pages (blank data pages), thus wasting the internal space of the flash memory module 124. For example, assuming that the data size of the region planned by the main device 110 is about six physical blocks, the data stored in the superblock 2261 containing eight blocks will only be the size of six physical blocks. That is, the storage space of about two blocks in the superblock 2261 will be wasted because it is either kept blank or written with invalid data. Therefore, one embodiment of the present invention proposes a method for configuring the region namespace 310_1 according to the data size of the region set by the main device 110, so as to use the region namespace 310_1 efficiently.

[0154] Figure 23This is a flowchart of a method for configuring a flash memory module 124 according to an embodiment of the present invention. In step 2300, the process begins, and the main device 110, flash memory controller 122, and flash memory module 124 have completed their respective initialization operations. In step 2302, the main device 110 sets at least a portion of the flash memory module 124 as a zone namespace by sending a configuration instruction set. In the following description, zone namespace 310_1 is used as an example. For example, the main device 110 sets basic settings such as the size, number of zones, and logical block address size of each zone in zone namespace 310_1 for the storage device 120_1, for example, using a zone namespaces command set. In step 2304, the microprocessor 212 in the flash memory controller 122 determines the number of blocks contained in a superblock based on the zone size set by the host device 110 and the size of each block (physical block) in the flash memory module 124. Specifically, assuming the zone size set by the host device 110 is A, and the amount of data used to store the host in each physical block of the flash memory module 124 is B, if the remainder after dividing A by B by the microprocessor 212 is not zero, then adding one to the quotient of A divided by B gives the number of blocks contained in a superblock. Conversely, if the remainder after dividing A by B by the microprocessor 212 is zero, then the quotient of A divided by B gives the number of blocks contained in a superblock. Figure 24To illustrate, the flash memory module 124 includes multiple flash memory chips 2410, 2420, 2430, and 2440. Flash memory chip 2410 includes two data planes 2412 and 2414; flash memory chip 2420 includes two data planes 2422 and 2424; flash memory chip 2430 includes two data planes 2432 and 2434; and flash memory chip 2440 includes two data planes 2442 and 2444. Each data plane contains multiple blocks B0 to BN. If A is divided by B... If the quotient is '5' and the remainder is '3', then the microprocessor 212 can determine that a superblock contains six blocks. Therefore, during the configuration or initialization of the region namespace 310_1, the flash memory controller 122 will configure the first block B0 of data planes 2412, 2414, 2422, 2424, 2432, and 2434 as a superblock 2461, the second block B1 of data planes 2412, 2414, 2422, 2424, 2432, and 2434 as a superblock 2462, and so on. Furthermore, blocks B0 to BN of data planes 2442 and 2444 do not need to be configured as superblocks, or they can be separately configured as a superblock independent of data planes 2412, 2414, 2422, 2424, 2432, and 2434. In another embodiment, during the configuration or initialization of the region namespace 310_1, the flash memory controller 122 configures the first block B0 of data planes 2412, 2414, 2422, 2424, 2432, and 2434 as a superblock 2461, and the second block B1 of data planes 2422, 2424, 2432, 2434, 2442, and 2444 as a superblock 2462. As long as the blocks within the same superblock can be accessed in parallel, the superblock access speed can be improved. Therefore, superblocks can be configured arbitrarily within this framework.

[0155] In another embodiment, assuming the data size of the region set by the master device 110 is C, and the data size used to store the host in each physical block of the flash memory module 124 is D, if the quotient of C divided by D is '3' and the remainder is '2', then the microprocessor 212 can determine that a superblock contains 4 blocks, i.e., the quotient plus one. After receiving the command from the master device to set the region namespace 310_1, the flash memory controller 122 configures the first block B0 of data planes 2412, 2414, 2422, and 2424 as a superblock 2461, and configures the first block B0 of data planes 2432, 2434, 2442, and 2444 as a superblock 2462, and so on.

[0156] Please note that during the factory initialization process, storage devices 120_1, 120_2, ..., 120_N can perform preliminary superblock configuration on the flash memory modules. Taking storage device 120_1 as an example, the superblock configuration at this time can configure the first block B0 of the simultaneously accessible data planes 2412, 2414, 2422, 2424, 2432, 2434, 2442, 2444 as a superblock 2461, and configure the second block B1 of the simultaneously accessible data planes 2412, 2414, 2422, 2424, 2432, 2434, 2442, 2444 as a superblock 2462 to achieve the maximum access bandwidth. After the storage device 120_1 is connected to the main device 110 and receives commands from the main device 110 regarding the region namespace (e.g., setting the region namespace 310_1), a specific storage region is allocated within the flash memory module 124 as the dedicated space for the region namespace 310_1, based on the size of the region namespace. Furthermore, based on the size settings of each region within the region namespace 310_1 by the main device 110, the size and configuration of the superblocks within this specific storage space are reset. For example, the first block B0 of data planes 2412, 2414, 2422, and 2424 is configured as a superblock 2461, while the first block B0 of data planes 2432, 2434, 2442, and 2444 is configured as a superblock 2462, and so on. At this time, storage device 120_1 will have two superblocks of different sizes. The superblock settings for specific storage areas dedicated to region namespace 310_1 will differ from the superblock settings for specific storage areas not dedicated to region namespace 310_1. Furthermore, the superblock settings for specific storage areas dedicated to region namespace 310_1 will also differ from the initial settings of storage device 120_1 before it leaves the factory.

[0157] As described above, the number of blocks contained in the superblock is determined by the amount of data in the area set by the main device 110, so that the superblock can achieve optimal space utilization.

[0158] It should be noted that, in Figure 22 , 24 The number of flash memory chips and the number of data planes contained in each flash memory chip described in the embodiments are merely illustrative examples and not limitations of the invention. Furthermore, in Figure 22 , 24In this embodiment, the flash memory chips 2410, 2420, 2430, and 2440 included in the region namespace 310_1 and the flash memory chips 2210, 2220, 2230, and 2240 included in the general storage space 320_1 can be integrated. Specifically, the flash memory module 124 may contain only four flash memory chips 2210, 2220, 2230, and 2240, while the flash memory chips 2210, 2220, 2230, and 2240 as a whole include... Figure 3 The region namespace 310_1 and general storage space 320_1 are shown. Therefore, the microprocessor 212 can configure the four flash memory chips 2210, 2220, 2230, and 2240 as superblocks that simultaneously contain multiple superblocks with different numbers of blocks, for example, containing... Figure 22 The superblock shown contains eight blocks and Figure 24 The superblock shown contains six blocks.

[0159] on the other hand, Figure 3 The general storage space 320_1 shown can also be configured as a region namespace by the main device 110 at a later time point, at which point the size of the previously configured superblocks within the general storage space 320_1 will need to be changed. Specifically, at the first time point, the microprocessor will configure the general storage space 320_1 to plan the size of each superblock, so as to... Figure 22 For example, since a superblock can contain a maximum of eight blocks, the microprocessor 212 sets each superblock to contain eight blocks. Next, if the host device 110 reconfigures the general storage space 320_1 as a region namespace, the microprocessor 212 needs to reset the number of blocks contained in each superblock, for example... Figure 22 The six blocks shown.

[0160] Please note that, in order to improve access speed, the flash memory controller 122 can typically temporarily store the data that the main device 110 wants to store into the storage device 120_1 in a single-layer storage cell of the flash memory module 124, or in other words, temporarily store it in the flash memory module 124 in an SLC (Single-Level Cell) storage manner. Finally, this data will still be stored in a multi-layer storage cell, or in other words, stored in the flash memory module 124 in an MLC (Multi-Level Cell) storage manner. In this embodiment of the invention, the process of storing this data in the flash memory module 124 in an SLC storage manner is omitted; the final state of storing the data in the flash memory module 124 in an MLC storage manner is directly described. Those skilled in the art can combine the technology of this invention with the technology of temporarily storing data in the flash memory module 124 in an SLC storage manner under the guidance of this invention.

[0161] In summary, the control method of this invention applied to a flash memory controller can effectively reduce the size of the L2P mapping table by planning the mode of writing region data to the flash memory, thereby reducing the burden on the buffer memory or DRAM. In addition, by determining the number of blocks contained in the superblock based on the amount of data in the region and the size of the physical block, the space of the flash memory module can be utilized more effectively.

[0162] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A control method applied to a flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprising multiple data planes, each data plane comprising multiple blocks, and each block comprising multiple data pages, and the control method comprising: The system receives a setting instruction from a master device, wherein the setting instruction sets at least a portion of the flash memory module as a zoned namespace, wherein the zoned namespace logically contains multiple zones, and the master device must perform data write and access to the zoned namespace on a zone-by-zone basis, wherein each zone is of the same size, the logical addresses corresponding to each zone must be contiguous, and there must be no overlapping logical addresses between zones. The namespace of the region is configured to plan multiple first super blocks, each of which contains multiple blocks located in at least two data planes, and the number of blocks contained in each first super block is determined by the size of each region and the size of each block. Receive data from the master device corresponding to a target area, wherein the data is all the data of the target area; According to the logical address order of the data, the data is sequentially written into a target first superblock among the plurality of first superblocks of the flash memory module; as well as After the data is written, invalid data is written to the remaining data pages of the last block contained in the first superblock of the target, or the remaining data pages are left blank and no data from the master device is written according to the write command of the master device before erasure.

2. The control method as described in claim 1, characterized in that, From the perspective of storing data from the master device, a single first superblock will only store data from a single region.

3. The control method as described in claim 1, characterized in that, The flash memory module contains N data planes, each region having a size of A, and each block having a size of B, where A is greater than B; and the steps of configuring the namespace of the region to plan the multiple first superblocks include: Configure the namespace of this region to plan the multiple first super blocks, such that the number of blocks contained in each first super block is the quotient of A divided by B plus '1', and the blocks contained in each first super block are located in different data planes.

4. The control method as described in claim 1, characterized in that, Also includes: Another portion of the flash memory module is configured as a general storage space; as well as The general storage space is configured to plan multiple second superblocks, each of which contains multiple blocks for the multiple data planes.

5. The control method as described in claim 4, characterized in that, The flash memory module contains N data planes, each region having a size of A, and each block having a size of B, where A is greater than B; and the steps of configuring the namespace of the region to plan the multiple first superblocks include: Configure the namespace of this region to plan the multiple first super blocks, such that the number of blocks contained in each first super block is the quotient of A divided by B plus '1', and the blocks contained in each first super block are located in different data planes. as well as The steps of configuring the general storage space to plan the multiple second superblocks include: The general storage space is configured to plan the multiple second super blocks, such that each first super block contains N blocks, and each second super block contains blocks located on different data planes.

6. The control method as described in claim 4, characterized in that, Also includes: Reconfigure at least a portion of the general storage space into another regional namespace; Configure the other region namespace to plan multiple third superblocks, each of which contains multiple blocks located in at least two data planes, and the number of blocks contained in each third superblock is determined by the size of each region and the size of each block in the other region namespace.

7. The control method as described in claim 6, characterized in that, From the perspective of storing data from the master device, a single third superblock will only store data from a single region.

8. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module including multiple data planes, each data plane including multiple blocks, and each block including multiple data pages, and the flash memory controller including: A read-only memory is used to store a program code; A microprocessor is used to execute the program code to control access to the flash memory module; as well as A buffer memory; The microprocessor receives a setting instruction from a master device, wherein the setting instruction sets at least a portion of the flash memory module as a zoned namespace, wherein the zoned namespace logically contains multiple zones, and the master device must perform data write and access to the zoned namespace on a zone-by-zone basis, wherein each zone is of the same size, the logical addresses corresponding to each zone must be contiguous, and there must be no overlapping logical addresses between zones. The microprocessor configures the namespace of the region to plan multiple first superblocks, each of which contains multiple blocks located in at least two data planes. The number of blocks contained in each first superblock is determined by the size of each region and the size of each block. The microprocessor receives data from the host device corresponding to a target region, wherein the data is all the data of the target region. The microprocessor writes the data sequentially into a target first superblock among the multiple first superblocks of the flash memory module according to the logical address order of the data. And after the data is written, the microprocessor either writes invalid data to the remaining data pages of the last block contained in the first superblock of the target, or keeps the remaining data pages blank and does not write data from the master device according to the write command of the master device before erasing.

9. The flash memory controller as described in claim 8, characterized in that, From the perspective of storing data from the master device, a single first superblock will only store data from a single region.

10. The flash memory controller as described in claim 8, characterized in that, The flash memory module contains N data planes, each region is A in size, and each block is B in size, where A is greater than B. The microprocessor configures the namespace of the region to plan the multiple first super blocks, such that the number of blocks contained in each first super block is the quotient of A divided by B plus '1', and the blocks contained in each first super block are located in different data planes.

11. The flash memory controller as claimed in claim 8, characterized in that, The microprocessor sets another part of the flash memory module as a general storage space and configures the general storage space to plan multiple second superblocks, each of which contains multiple blocks of the multiple data planes respectively.

12. A storage device comprising: A flash memory module, wherein the flash memory module includes multiple data planes, each data plane includes multiple blocks, and each block includes multiple data pages; and A flash memory controller for accessing the flash memory module; The flash memory controller receives a setting instruction from a master device, wherein the setting instruction sets at least a portion of the flash memory module as a zoned namespace, wherein the zoned namespace logically contains multiple zones, and the master device must perform data write and access to the zoned namespace on a zone-by-zone basis, wherein each zone is of the same size, the logical addresses corresponding to each zone must be contiguous, and there must be no overlapping logical addresses between zones; The flash memory controller configures the region namespace to plan multiple first superblocks, each first superblock containing multiple blocks located in at least two data planes, and the number of blocks contained in each first superblock is determined by the size of each region and the size of each block; the flash memory controller receives data from the master device corresponding to a target region, wherein the data is all the data of the target region, and the flash memory controller writes the data sequentially into a target first superblock among the multiple first superblocks of the flash memory module according to the logical address order of the data; And after the data is written, the flash memory controller either writes invalid data to the remaining data pages of the last block contained in the first superblock of the target, or keeps the remaining data pages blank and does not write data from the master device according to the write command of the master device before erasing.

13. The storage device as claimed in claim 12, characterized in that, From the perspective of storing data from the master device, a single first superblock will only store data from a single region.

14. The storage device as claimed in claim 12, characterized in that, The flash memory module contains N data planes, each region is A in size, and each block is B in size, where A is greater than B. The flash memory controller configures the namespace of the region to plan the multiple first super blocks, such that the number of blocks contained in each first super block is the quotient of A divided by B plus '1', and the blocks contained in each first super block are located in different data planes.

15. The storage device as claimed in claim 12, characterized in that, The flash memory controller sets another part of the flash memory module as a general storage space and configures the general storage space to plan multiple second superblocks, each of which contains multiple blocks of the multiple data planes respectively.

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