Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, a metal bit line on the substrate, a bit line spacer on opposite sidewalls of the metal bit line, a contact adjacent to the metal bit line, a contact spacer on opposite sidewalls of the contact, an air gap between the bit line spacer and the contact spacer, a dielectric cap on the air gap, a spacer on the dielectric cap, and a cap layer covering the metal bit line, the spacer, and the contact. A lower surface of the dielectric cap and an upper surface of the contact are coplanar, and the cap layer contacts the dielectric cap. Thus, the semiconductor device can avoid the cap layer filling the air gap, thereby maintaining the integrity of the air gap structure to reduce the parasitic capacitance in the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of forming the same, and more particularly to semiconductor devices including air gaps and methods of forming the same. BACKGROUND

[0002] Dynamic random access memory (DRAM) devices are a type of semiconductor device that stores digital bit information in individual capacitors of a circuit. As the minimum feature width or critical dimension (CD) of DRAMs continues to shrink, memory density is increased and the size of the device is reduced. However, as the spacing between closely packed elements is reduced, parasitic capacitance between the elements can increase. Therefore, a method of forming a semiconductor device includes forming an air gap between elements to reduce the parasitic capacitance of the semiconductor device. SUMMARY

[0003] It is an object of the present disclosure to provide a semiconductor device and a method of forming the same that can avoid a capping layer from filling in an air gap, thereby maintaining the integrity of the air gap structure to reduce parasitic capacitance in the semiconductor device.

[0004] According to an embodiment of the present disclosure, a semiconductor device includes a substrate, a metal bit line on the substrate, a bit line spacer on opposite sidewalls of the metal bit line, a contact adjacent to the metal bit line, a contact spacer on opposite sidewalls of the contact, an air gap between the bit line spacer and the contact spacer, a dielectric capping film over the air gap, a spacer on the dielectric capping film, and a capping layer capping the metal bit line, the spacer, and the contact, wherein a lower surface of the dielectric capping film and an upper surface of the contact are coplanar, and the capping layer contacts the dielectric capping film.

[0005] In an embodiment of the present disclosure, the dielectric capping film includes a spin-on dielectric or an organic dielectric.

[0006] In an embodiment of the present disclosure, the dielectric capping film has a thickness of 10 nm to 50 nm.

[0007] In an embodiment of the present disclosure, the air gap has a width of 3 nm to 7 nm.

[0008] According to an embodiment of the present application, a semiconductor device includes a substrate, a metal bit line on the substrate, a bit line spacer on opposite sidewalls of the metal bit line, a contact adjacent to the metal bit line, a contact spacer on opposite sidewalls of the contact, an air gap between the bit line spacer and the contact spacer, a spacer layer over the air gap, and a cap layer covering the metal bit line, the spacer layer, and the contact, wherein the air gap extends above the contact spacer, a lower surface of the spacer layer is higher than an upper surface of the contact, and the cap layer contacts the air gap.

[0009] In an embodiment of the present application, the cap layer extends between the spacer layer and the contact spacer, and an upper portion of the air gap has a width that is not less than a lower portion of the air gap.

[0010] According to an embodiment of the present application, a method of forming a semiconductor device includes forming a metal bit line and a contact on a substrate, the contact adjacent to the metal bit line. A bit line spacer is formed on opposite sidewalls of the metal bit line and a contact spacer is formed on opposite sidewalls of the contact, wherein a gap is included between the bit line spacer and the contact spacer. A dielectric film is formed on the metal bit line and the contact, the dielectric film on the contact contacting the bit line spacer, such that an air gap is formed between the bit line spacer and the contact spacer. A portion of the dielectric film on the metal bit line is removed. A blanket spacer layer is formed on the metal bit line and the dielectric film. The blanket spacer layer on the metal bit line and the portion of the dielectric film is removed to form a spacer layer on sidewalls of the bit line spacer. The dielectric film is patterned to form a dielectric cap film over the air gap, a side surface of the dielectric cap film coplanar with a side surface of the spacer layer. A cap layer is formed covering the metal bit line, the spacer layer, and the contact.

[0011] In an embodiment of the present application, the dielectric film has a viscosity coefficient between 0.2 cP and 2.0 cP before curing.

[0012] In an embodiment of the present application, the spacer layer has a thickness in a direction that is greater than a width of the air gap in the direction.

[0013] In an embodiment of the present application, the method further includes, before forming the cap layer, removing the dielectric cap film under the spacer layer.

[0014] Compared with the prior art, the present application has the following beneficial effects: the semiconductor device and the method of forming the same can avoid the cap layer of the device filling into the air gap, thereby maintaining the integrity of the air gap structure to reduce the parasitic capacitance in the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0015] Aspects of the application are best understood from the following detailed description when read with the accompanying drawings. It is emphasized that various features are not to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the clarity of presentation and / or discussion.

[0016] Figure 1 A flowchart of a method of forming a semiconductor device is depicted in accordance with an embodiment of the present application.

[0017] Figures 2A to 2G Cross-sectional views of various intermediate stages in the formation of a semiconductor device are depicted in accordance with an embodiment of the present application.

[0018] Figure 3 A flowchart of a method of forming a semiconductor device is depicted in accordance with another embodiment of the present application.

[0019] Figures 4A to 4C Cross-sectional views of various intermediate stages in the formation of a semiconductor device are depicted in accordance with another embodiment of the present application.

[0020] Principal reference numerals:

[0021] 10, 20 - semiconductor device, 100, 200 - substrate, 110, 210 - polysilicon bit line, 120, 220 - polysilicon bit line, 130, 230 - metal bit line, 132, 232 - dielectric layer, 134, 234 - first conductive layer, 136, 236 - second conductive layer, 138, 238 - dielectric layer, 140, 240 - contact, 150, 250 - bit line spacer, 155, 255 - contact spacer, 160 - gap, 165, 265 - air gap, 170 - dielectric film, 175, 275 - dielectric capping film, 180 - blanket spacer, 185, 285 - spacer, 190, 290 - capping layer, 300 - air gap, 1000, 2000 - method, 1002, 1004, 1006, 1008, 1010, 1012, 1014 - step, 2002, 2004, 2006, 2008, 2010, 2012, 2014, 2016 - step. DETAILED DESCRIPTION

[0022] To implement the different features of the subject matter recited, the following summary provides a number of different embodiments or examples. The following description sets forth numerous specific details such as examples of specific components, configurations, etc., in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art, however, that the present invention can be practiced without such specific details. In other instances, well-known components or methods are not described in detail or are presented in a simple manner in order to avoid unnecessarily obscuring the present invention. For example, in the following description, a first feature being formed over or overlying a second feature can include embodiments where the first feature and the second feature are formed in direct contact, and can also include embodiments where additional features are formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. In addition, the present invention can make repeated reference to a number and / or letter. This repetition is for the sake of simplicity and clarity and does not itself convey a relationship between the various embodiments and / or configurations discussed.

[0023] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0024] Reference will now be made to Figure 1 and Figure 2A . Figure 1 A flowchart of a method 1000 of forming a semiconductor device 10 according to an embodiment of the present invention is shown in Figure 2A A cross-sectional view of the semiconductor device 10 at step 1002 in Figure 1 is shown in Figure 2A . As shown, polysilicon bit lines 110, 120, metal bit lines 130, contacts 140, bit line spacer layers 150, and contact spacer layers 155 including gaps 160 are formed on a substrate 100 of the semiconductor device 10. It should be understood that some elements of the semiconductor device 10 are not shown in Figure 1 for the sake of simplicity of the drawing.

[0025] In some embodiments, substrate 100 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., wherein the insulator may be a buried oxide (BOX) layer, a silicon oxide layer, etc. Substrate 100 may be doped (e.g., containing p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of semiconductor substrate 100 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors, or combinations thereof. Substrate 100 may also be formed of other materials, such as sapphire, indium tin oxide, etc.

[0026] Polysilicon bit lines 110 and 120 are formed within substrate 100 and electrically connected to multiple elements of semiconductor device 10 to form a circuit within semiconductor device 10. For example, polysilicon bit line 110 may be disposed below metal bit line 130, while polysilicon bit line 120 may be disposed below metal bit line 130 or contact 140, serving as a conductor to carry current to the element above it. When polysilicon bit line 120 is disposed below contact 140, polysilicon bit line 120 may be referred to as a lower contact, and contact 140 may be referred to as an upper contact, allowing semiconductor device 10 to be connected to conductive features on its upper or lower layers. In some embodiments, the materials forming polysilicon bit lines 110 and 120 include conductive materials, such as metals, metal silicides, metal nitrides, suitable materials, or combinations thereof.

[0027] Metal bit lines 130 are formed above polysilicon bit lines 110 or 120 on substrate 100 and along a first direction D1 (e.g., Figure 2A As shown (perpendicular to the plane of the paper), it extends on the substrate 100. The metal bit line 130 includes a dielectric layer 132, a first conductive layer 134, a second conductive layer 136, and a dielectric layer 138. The dielectric layer 132 isolates the first conductive layer 134 from the underlying structure, such as a polysilicon bit line 110 or a polysilicon bit line 120. The first conductive layer 134 and the second conductive layer 136 are stacked on top of the dielectric layer 132 to serve as the gate structure of the metal bit line 130. The dielectric layer 138 is formed on the second conductive layer 136 to isolate the second conductive layer 136 from other features subsequently formed on the metal bit line 130.

[0028] In some embodiments, the material forming dielectric layer 132 may include silicon oxide, silicon nitride, a high-dielectric-constant dielectric material, other suitable materials, or combinations thereof. In some embodiments, the first conductive layer 134 and the second conductive layer 136 may include different wire materials and together serve as the gate structure of the metal bit line 130. For example, the first conductive layer 134 may include doped polysilicon, and the second conductive layer 136 may include a metal or a metal nitride, with the second conductive layer 136 formed above the first conductive layer 134. In some other embodiments, the metal bit line 130 may include other conductive layers, such as a metal silicide layer formed between the first conductive layer 134 and the second conductive layer 136. In some embodiments, the material forming dielectric layer 138 may include silicon oxide, silicon nitride, other dielectric materials, or combinations thereof.

[0029] Contact 140 is formed on substrate 100 and adjacent to metal bit line 130. For example, such as Figure 2A As shown, contact 140 may be located between two metal bit lines 130 and spaced apart from the two metal bit lines 130. In some embodiments, contact 140 may extend into substrate 100 or further into polysilicon bit lines 120. In some embodiments, the material forming contact 140 includes conductive materials, such as doped polysilicon, metals, metal silicides, metal nitrides, suitable materials, or combinations thereof. In some embodiments, contact 140 may further include a barrier layer (not shown) formed on the side and bottom surfaces of contact 140, such that contact 140 contacts substrate 100 or contact spacer layer 155 through the barrier layer. It should be understood that, although Figure 2A The illustration shows a combination of two metal bit lines 130 and a single contact 140. The semiconductor device 10 may include other numbers of metal bit lines 130 and contacts 140, for example, two metal bit lines 130 and three contacts 140 may be arranged alternately on the substrate 100.

[0030] Bit line spacers 150 are formed on opposite sidewalls of the metal bit line 130. Specifically, the bit line spacers 150 may conformally cover opposite sidewalls of dielectric layer 132, first conductive layer 134, second conductive layer 136, and dielectric layer 138 to protect the structure of the metal bit line 130. In some embodiments, the bit line spacers 150 may extend into the substrate 100, contacting the polysilicon bit line 110, or further connecting to each other with contact spacers 155 to separate multiple regions of the semiconductor device 10. In some embodiments, the metal bit lines 130 located on opposite sides of the contact 140 may have bit line spacers 150 with different structures. For example, such as Figure 2AAs shown, the metal bitlines 130 on one side of the contacts 140 can include bitline spacer layers 150 on the substrate 100, while the metal bitlines 130 on the other side of the contacts 140 can include bitline spacer layers 150 extending into the substrate 100.

[0031] In some embodiments, the material forming the bitline spacer layers 150 can be a suitable dielectric material, such as silicon oxide, silicon nitride, low-k dielectric material, or a combination thereof. In some embodiments, the bitline spacer layers 150 can be a single layer structure, a double layer structure, or a multi-layer structure, and the multi-layer structure thereof can include different materials. In some embodiments, the semiconductor device 10 can include other spacer layers (e.g., contact spacer layers 155) adjacent to the bitline spacer layers 150, such that gaps 160 are formed between the bitline spacer layers 150 and the other spacer layers, and the gaps 160 are formed on opposite sides of the metal bitlines 130. Details of the gaps 160 will be further described below.

[0032] The contact spacer layers 155 are formed on opposite sidewalls of the contacts 140. Specifically, the contact spacer layers 155 are formed on the substrate 100 and conformally cover the opposite sidewalls of the contacts 140 to protect the contacts 140. In some embodiments, the contact spacer layers 155 can extend into the substrate 100, such that the contact spacer layers 155 and the bitline spacer layers 150 are connected to each other. For example, as shown in FIG. 1A, the contact spacer layers 155 on one side of the contacts 140 can include bitline spacer layers 150 on the substrate 100, while the contact spacer layers 155 on the other side of the contacts 140 can include bitline spacer layers 150 extending into the substrate 100 and connected to the bitline spacer layers 150. Figure 2A As shown, the metal bitlines 130 on one side of the contacts 140 can include bitline spacer layers 150 on the substrate 100, while the metal bitlines 130 on the other side of the contacts 140 can include bitline spacer layers 150 extending into the substrate 100.

[0033] In some embodiments, the material forming the bitline spacer layers 150 and the contact spacer layers 155 can be the same material, such as including silicon oxide, silicon nitride, low-k dielectric material, or a combination thereof. In some embodiments, the contact spacer layers 155 can be a single layer structure, a double layer structure, or a multi-layer structure, and the multi-layer structure thereof can include different materials.

[0034] The bitline spacer layers 150 and the contact spacer layers 155 have gaps 160 therebetween in a second direction D2, such that air can be filled between the bitline spacer layers 150 and the contact spacer layers 155, or a vacuum space can be formed in a subsequent process, where the second direction D2 is different from a first direction Dl in which the metal bitlines 130 extend. In some embodiments, as shown in FIG. 1A, the semiconductor device 10 can include contact spacer layers 155 of additional contacts (not shown) adjacent to the metal bitlines 130, such that gaps 160 are formed on opposite sides of the metal bitlines 130, i.e., the bitline spacer layers 150 on opposite sides of the metal bitlines 130 are both adjacent to the gaps 160. Figure 2A As shown, the metal bitlines 130 on one side of the contacts 140 can include bitline spacer layers 150 on the substrate 100, while the metal bitlines 130 on the other side of the contacts 140 can include bitline spacer layers 150 extending into the substrate 100.

[0035] In some embodiments, the gap 160 can be formed using a suitable photolithography process. For example, a sacrificial layer (not shown) can be formed between the metal bitlines 130 and the contacts 140, and after patterning the sacrificial layer using a photoresist, a dielectric material can be deposited to form the bitline spacer layer 150 and the contact spacer layer 155. The remaining sacrificial layer is then removed to form the gap 160 between the bitline spacer layer 150 and the contact spacer layer 155. In some embodiments, the width of the gap 160 in the second direction D2 can be less than 7 nm, for example, between 3 nm and 7 nm. However, it should be understood that the width of the gap 160 can be outside the above-mentioned range depending on the design of the semiconductor device 10.

[0036] Referring to Figure 1 and Figure 2B . Figure 2B A cross-sectional view of the semiconductor device 10 at step 1004 in Figure 1 is shown. As Figure 2B indicated, a dielectric film 170 is formed on the metal bitlines 130, the contacts 140, the bitline spacer layer 150, and the contact spacer layer 155, such that the air gap 165 is formed between the bitline spacer layer 150 and the contact spacer layer 155.

[0037] The formation of the dielectric film 170 includes coating (e.g., spin coating) a dielectric material on the metal bitlines 130, the contacts 140, the bitline spacer layer 150, and the contact spacer layer 155, such that the dielectric film 170 on the contact spacer layer 155 contacts the bitline spacer layer 150. As a result of the dielectric film 170 contacting the bitline spacer layer 150, the substrate 100, the dielectric film 170, the bitline spacer layer 150, and the contact spacer layer 155 collectively form the air gap 165 between the bitline spacer layer 150 and the contact spacer layer 155. In some embodiments, the formation of the dielectric film 170 includes a further curing process such that the thickness of the dielectric film 170 after curing is between 10 nm and 50 nm.

[0038] In some embodiments, the material forming the dielectric film 170 includes a spin on dielectric (SOD), an organic dielectric layer (ODL), or a suitable dielectric material. For example, the dielectric film 170 can include silicon oxide, silicon oxycarbide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, other dielectric materials, or combinations thereof. The dielectric material has a viscosity between 0.2 cP and 2.0 cP before curing, such that when the dielectric film 170 on the contact spacer layer 155 contacts the bit line spacer layer 150, the dielectric film 170 is over the air gap 165 without filling the air gap 165. In other words, the lower surface of the dielectric film 170 is coplanar with the upper surface of the contact 140.

[0039] The width of the air gap 165 corresponds to Figure 2A the width of the intermediate gap 160. In some embodiments, the width of the air gap 165 in the second direction D2 is between 3 nm and 7 nm. In some embodiments, the air gap 165 does not necessarily fill with air, it can fill with other types of gas, or it can be a vacuum. Since the air gap 165 is between the bit line spacer layer 150 and the contact spacer layer 155, parasitic capacitance between the metal bit line 130 and the contact 140 can be reduced.

[0040] Referring to Figure 1 and Figure 2C . Figure 2C A cross-sectional view of the semiconductor device 10 at step 1006 is shown in Figure 1 . As shown in Figure 2C , a portion of the dielectric film 170 on the metal bit line 130 and the bit line spacer layer 150 is removed. In some embodiments, removing the portion of the dielectric film 170 includes forming a photoresist over the contact 140 and the contact spacer layer 155 using a patterning process, and etching the dielectric film 170 on the metal bit line 130 and the bit line spacer layer 150 exposed by the photoresist to leave the dielectric film 170 on the contact 140 and the contact spacer layer 155.

[0041] Referring to Figure 1 and Figure 2D . Figure 2D A cross-sectional view of the semiconductor device 10 at step 1008 is shown in Figure 1 . As shown in Figure 2D , a blanket spacer layer 180 is formed on the metal bit line 130, the bit line spacer layer 150, and the dielectric film 170, and the blanket spacer layer 180 covers the sidewall of the bit line spacer layer 150. The thickness of the blanket spacer layer 180 in the second direction D2 is greater than the width of the air gap 165 in the second direction D2, such that the dielectric film 170 and the blanket spacer layer 180 thereon cover the air gap 165 when viewed from above the semiconductor device 10.

[0042] In some embodiments, forming the blanket spacer layer 180 includes depositing material onto the metal bit line 130, the bit line spacer layer 150, the sidewalls of the bit line spacer layer 150, and the contact 140 using a suitable process (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other processes). In some embodiments, the material forming the blanket spacer layer 180 may include silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the blanket spacer layer 180 may be a single-layer structure, a double-layer structure, or a multilayer structure.

[0043] Please refer to Figure 1 and Figure 2E . Figure 2E Drawn in Figure 1 A cross-sectional view of the semiconductor device 10 in step 1010. (See figure) Figure 2E As shown, the blanket spacer layer 180 on the metal bit line 130 and a portion of the dielectric film 170 is removed to form a spacer layer 185 covering the sidewalls of the bit line spacer layer 150. Specifically, a photoresist is formed on the sidewalls of the bit line spacer layer 150 using a patterning process, and the blanket spacer layer 180 on the metal bit line 130, bit line spacer layer 150, and a portion of the dielectric film 170 is removed using a process such as etching. Thus, a spacer layer 185 is formed on the sidewalls of the bit line spacer layer 150, and the spacer layer 185 covers a portion of the dielectric film 170. The thickness of the spacer layer 185 formed by the patterning process in the second direction D2 is greater than the width of the air gap 165 in the second direction D2. Therefore, when viewed from above the semiconductor device 10, the spacer layer 185 and the contact spacer layer 155 partially overlap.

[0044] Please refer to Figure 1 and Figure 2F . Figure 2F Drawn in Figure 1 A cross-sectional view of the semiconductor device 10 in step 1012. (See figure) Figure 2F As shown, the dielectric film 170 is patterned to form a dielectric capping film 175 above the air gap 165. Specifically, using the spacer layer 185 as a mask, the dielectric film 170 on the contact 140 and the contact spacer layer 155 is etched to form the dielectric capping film 175 above the air gap 165, wherein the side surface of the dielectric capping film 175 and the side surface of the spacer layer 185 are coplanar.

[0045] Because the thickness of the spacer layer 185 in the second direction D2 is greater than the width of the air gap 165 in the second direction D2, the width of the dielectric cap film 175 under the spacer layer 185 in the second direction D2 is also greater than the width of the air gap 165. Thus, the lower surface of the dielectric cap film 175 contacts the upper surface of the contact spacer layer 155 such that the dielectric cap film 175 covers the air gap 165. In other words, when viewed from above the semiconductor device 10, the dielectric cap film 175 and the contact spacer layer 155 partially overlap.

[0046] Referring to Figure 1 and Figure 2G . Figure 2G A cross-sectional view of the semiconductor device 10 at step 1014 in Figure 1 is depicted. As shown in Figure 2G , a cap layer 190 is formed covering the metal bit line 130, the contact 140, the bit line spacer layer 150, the contact spacer layer 155, and the spacer layer 185. Specifically, the cap layer 190 conformally and continuously covers the metal bit line 130, the bit line spacer layer 150, the spacer layer 185, the dielectric cap film 175, and the contact 140 to protect the semiconductor device 10 in subsequent processes. Because the dielectric cap film 175 covers over the air gap 165, the cap layer 190 is prevented from filling in the air gap 165 when formed. In other words, the dielectric cap film 175 isolates the cap layer 190 from the air gap 165. Thus, the air gap 165 can maintain the integrity of the structure between the bit line spacer layer 150 and the contact spacer layer 155, reducing parasitic capacitance between the metal bit line 130 and the contact 140.

[0047] In some embodiments, the material forming the cap layer 190 includes silicon nitride, silicon oxide, silicon oxynitride, metal, metal nitride, or other suitable material to form other features over the semiconductor device 20. In some embodiments, forming the spacer layer 185 and the cap layer 190 can include the same material to increase the adhesion between the spacer layer 185 and the cap layer 190. In some embodiments, forming the cap layer 190 includes depositing a material over the metal bit line 130, the contact 140, the bit line spacer layer 150, the contact spacer layer 155, and the spacer layer 185 using, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or other suitable process.

[0048] Referring to Figure 3 and Figure 4A . Figure 3 A flowchart of a method 2000 of forming a semiconductor device 20 according to another embodiment of the present disclosure is depicted. Figure 4A A cross-sectional view of the semiconductor device 20 at step 2004 in Figure 3A cross-sectional view of the semiconductor device 20 after steps 2002 to 2012. Since steps 2002 to 2012 of the method 2000 for forming the semiconductor device 20 are similar to... Figure 1 Steps 1002 to 1012 of method 1000 can therefore be formed using the above-described process details. Figure 4A Semiconductor device 20.

[0049] like Figure 4A As shown, the semiconductor device 20 after steps 2002 to 2012 includes a substrate 200, polysilicon bit lines 210 and 220, metal bit lines 230, contacts 240, bit line spacers 250, contact spacers 255, air gaps 265, dielectric capping films 275, and spacers 285. Polysilicon bit lines 210 and 220 are formed within the substrate 200 and located below the metal bit lines 230 or contacts 240. The metal bit lines 230 are located on the substrate 200 and include a dielectric layer 232, a first conductive layer 234, a second conductive layer 236, and a dielectric layer 238. Contacts 240 are located on the substrate 200 adjacent to the metal bit lines 230. Bit line spacers 250 are located on opposite sidewalls of the metal bit lines 230, and contact spacers 255 are located on opposite sidewalls of the contacts 240. Air gap 265 is located between bit line spacer layer 250 and contact spacer layer 255, and dielectric cover film 275 under spacer layer 285 covers air gap 265.

[0050] Please refer to Figure 3 and Figure 4B . Figure 4B Drawn in Figure 3 A cross-sectional view of the semiconductor device 20 in step 2014. (See figure) Figure 4B As shown, the dielectric capping film 275 is removed, exposing the lower surface of the spacer layer 285. In other words, the spacer layer 285 is located above the air gap 265, and the lower surface of the spacer layer 285 is higher than the upper surface of the contact 240. Since the thickness of the spacer layer 285 in the second direction D2 is greater than the width of the air gap 265, when viewed from above the semiconductor device 20, the spacer layer 285 and the contact spacer layer 255 partially overlap, with a spacing equal to [missing information]. Figure 4A The thickness of the dielectric cover film 275. In some embodiments, removing the dielectric cover film 275 includes selectively removing the dielectric cover film 275 using an ash process to maintain the integrity of the spacer layer 285 and the contact spacer layer 255.

[0051] Please refer to Figure 3 and Figure 4C . Figure 4C Drawn in Figure 3 A cross-sectional view of the semiconductor device 20 in step 2016. (See figure.)Figure 4C As shown, the capping layer 290 is formed to cover the metal bitlines 230, the contacts 240, the bitline spacer layer 250, the contact spacer layer 255, and the spacer layer 285. In particular, the capping layer 290 is conformally formed on the metal bitlines 230, the bitline spacer layer 250, the spacer layer 285, the sidewalls of the spacer layer 285, the contact spacer layer 255, and the contacts 240, where the capping layer 290 covering the sidewalls of the spacer layer 285 and the contact spacer layer 255 is continuous. In some embodiments, forming the capping layer 290 includes using a deposition process similar to step 1014 to deposit a capping layer material (e.g., silicon nitride or silicon oxide). As a result, the air gap 300 is formed between the capping layer 290, the spacer layer 285, the bitline spacer layer 250, and the contact spacer layer 255. In other words, the capping layer 290 on the contact spacer layer 255 contacts the upper portion of the air gap 300.

[0052] In some embodiments, due to the partial overlap of the spacer layer 285 and the contact spacer layer 255 in the top view of the semiconductor device 20, the side surface of the upper portion of the air gap 300 and the side surface of the spacer layer 285 are coplanar. As a result, the upper portion of the air gap 300 extends onto the contact spacer layer 255, such that the upper portion width of the air gap 300 in the second direction D2 is greater than the lower portion width. For example, the air gap 300 can have an L-shaped structure, where the lower portion of the air gap 300 is between the bitline spacer layer 250 and the contact spacer layer 255, and the upper portion of the air gap 300 is below the spacer layer 285 and above the upper surface of the contact spacer layer 255. In some embodiments, the capping layer 290 can partially extend between the spacer layer 285 and the contact spacer layer 255, and remain on the upper surface of the contact spacer layer 255, such that the upper portion width of the air gap 300 in the second direction D2 is not less than the lower portion width.

[0053] Due to the upper portion width of the air gap 300 in the second direction D2 being not less than the lower portion width, the air gap 300 increases the distance between the capping layer 290 and the bitline spacer layer 250, preventing the capping layer 290 from filling the air gap 300 between the bitline spacer layer 250 and the contact spacer layer 255. As a result, the air gap 300 can maintain the integrity of the structure between the bitline spacer layer 250 and the contact spacer layer 255, reducing the parasitic capacitance between the metal bitlines 230 and the contacts 240.

[0054] According to the above embodiments of the present disclosure, the present disclosure provides a semiconductor device including an air gap and a dielectric capping film, and a method of forming the same. The air gap in the semiconductor device is between a bitline spacer layer and a contact spacer layer, and the dielectric capping film is above the air gap, such that a capping layer formed on metal bitlines and contacts contacts the dielectric capping film. Since the dielectric capping film isolates the capping layer and the air gap, the integrity of the air gap structure can be maintained, and the parasitic capacitance in the semiconductor device can be reduced.

[0055] According to other above-mentioned embodiments of the present application, the present application provides a semiconductor device including an air gap and a method of forming the same. The air gap in the semiconductor device is located between a bit line spacer layer and a contact spacer layer, and the spacer layers are located above the air gap. Since the thickness of the spacer layers is greater than the width of the air gap, the air gap structure can be maintained intact and the parasitic capacitance in the semiconductor device can be reduced by avoiding the cap layer from filling in the air gap.

[0056] The foregoing summary of some embodiments has been presented with the purpose of providing those skilled in the art with a better understanding of the concepts of the present application. It is to be understood that those skilled in the art can readily apply the concepts of the present application as a basis for the designing or modifying other processes and structures to produce the same results and / or accomplish the same advantages as the embodiments introduced herein. It is also to be understood that such equivalent constructions do not depart from the spirit and scope of the present application and that changes can be made in various details, yet amount to modifications and equivalents that fall within the spirit and scope of the present application.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a substrate; a metal bit line on the substrate and extending in a first direction; a bit line spacer on opposite sidewalls of the metal bit line; a contact adjacent to the metal bit line; a contact spacer on opposite sidewalls of the contact; an air gap between the bit line spacer and the contact spacer in a second direction, the first direction being different from the second direction; a dielectric cap on the air gap and not filling the air gap, a lower surface of the dielectric cap being coplanar with an upper surface of the contact, the dielectric cap covering the air gap and having a width in the second direction that is greater than a width of the air gap; a spacer on the dielectric cap; and a cap covering the metal bit line, the spacer, and the contact, the cap contacting the dielectric cap. The dielectric cap comprises a spin-on dielectric or an organic dielectric.

2. The semiconductor device according to claim 1, wherein The dielectric cap has a thickness between 10 nm and 50 nm.

3. The semiconductor device according to claim 1, wherein The air gap has a width between 3 nm and 7 nm.

4. The semiconductor device according to claim 1, wherein Comprising:

5. A semiconductor device, characterized by comprising: a substrate; a metal bit line on the substrate; a bit line spacer on opposite sidewalls of the metal bit line; a contact adjacent to the metal bit line; a contact spacer on opposite sidewalls of the contact; an air gap between the bit line spacer and the contact spacer, wherein the air gap extends above the contact spacer; a spacer on the air gap, wherein the air gap comprises an upper portion and a lower portion, the lower portion being between the bit line spacer and the contact spacer, wherein the upper portion is below the spacer and above an upper surface of the contact spacer, a lower surface of the spacer being above an upper surface of the contact; and a cap covering the metal bit line, the spacer, and the contact, the cap contacting the air gap. The cap extends below the spacer, an upper portion of the air gap having a width that is not less than a lower portion of the air gap.

6. The semiconductor device according to claim 5, wherein Comprising:

7. A method of forming a semiconductor device, comprising: forming a metal bit line and a contact on a substrate, the contact being adjacent to the metal bit line; forming a bit line spacer on opposite sidewalls of the metal bit line and a contact spacer on opposite sidewalls of the contact, wherein a gap is included between the bit line spacer and the contact spacer; forming a dielectric film on the metal bit line and the contact, wherein the dielectric film on the contact contacts the bit line spacer such that an air gap is formed between the bit line spacer and the contact spacer; removing portions of the dielectric film on the metal bit line, wherein the dielectric film on the contact is retained; forming a blanket spacer on the metal bit line and the dielectric film; removing the blanket spacer on the metal bit line and portions of the dielectric film to form a spacer on sidewalls of the bit line spacer; patterning the dielectric film using the spacer as a mask to form a dielectric cap above the air gap, a side surface of the dielectric cap being coplanar with a side surface of the spacer; and ​ ​ A cap layer is formed to cover the metal bit lines, the spacer layer and the contacts.

8. The method of claim 7, wherein, The dielectric film has a viscosity coefficient between 0.2 cP and 2.0 cP before curing.

9. The method of claim 7, wherein, The spacer layer has a thickness in a direction greater than a width of the air gap in the direction.

10. The method of claim 7, wherein, Further comprising removing the dielectric cap film under the spacer layer before forming the cap layer.

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