Fin-based bipolar electrostatic discharge device

Abstract

The present disclosure relates to a fin-based bipolar electrostatic discharge device. The present disclosure relates to semiconductor structures, and more specifically, to electrostatic discharge (ESD) devices and methods of manufacturing the same. The structure (ESD device) includes a bipolar transistor including a collector region, an emitter region, and a base region, and a lateral ballast resistance adjacent to the collector region including a semiconductor material.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures, and more specifically, to fin-based bipolar electrostatic discharge (ESD) devices and methods for manufacturing the same. Background Technology

[0002] To protect semiconductor circuits, features are typically provided to prevent electrostatic discharge (ESD), a sudden, transient flow of charge that can cause electrical short circuits or dielectric breakdown. In fact, ESD events can cause malfunctions in solid-state electronic components on such integrated circuit chips. For example, ESD events can potentially damage core circuitry, leading to gate oxide pinholes, junction damage, metal damage, and surface charge buildup. Furthermore, ESD events can include latch-up, causing permanent damage to the circuitry.

[0003] To prevent such problems, ESD devices can be integrated directly into integrated circuit (IC) chips. These devices can protect circuit elements within the IC chip during manufacturing and / or operation. For example, an ESD device can be designed to be triggered upon exposure to an ESD event, switching from an "off" to an "on" state. Under normal operation, the ESD device is typically in the "off" state.

[0004] ESD devices encompass many different types of devices. For example, an ESD device may include a lateral bipolar transistor using planar technology. In this technology, as an example, a ballast resistor may be provided via a silicide region. Exemplarily, the ballast resistor provided by the silicide region (e.g., a silicide block) provides additional resistance, which in turn increases the additional voltage to increase the voltage drop across the pad. Therefore, if the ESD device typically consists of many parallel fingers, the increased voltage drop will help trigger these parallel fingers to enter the ON state.

[0005] In FinFET technology, there are no horizontal ballast resistors, only vertical ballast resistors. Ballast resistors in ESD devices designed to utilize a large number of parallel ESD fingers are often referred to as multi-finger triggering arrangements to handle large transient current flows. Not all protective ESD devices will turn on after a small number of ESD devices are initially activated. In these cases, insufficient protection cannot be provided because there is not enough ballast resistance in each parallel finger. This situation occurs when the amount of ballast resistance in the ESD device is insufficient to allow all multi-finger devices to be turned on by proper triggering after triggering one or a few devices. Summary of the Invention

[0006] In one aspect of this disclosure, a structure includes: a bipolar transistor comprising a collector region, an emitter region, and a base region; and a lateral ballast resistor adjacent to the collector region, comprising a semiconductor material.

[0007] In one aspect of this disclosure, a structure includes: a fin-based bipolar electrostatic discharge (ESD) device comprising: a collector fin structure located above a first well having a first dopant type, and a ballast resistor fin structure located above a second well having a second dopant type and in contact with the collector fin structure, wherein the collector fin structure and the ballast resistor fin structure have the second dopant type.

[0008] In one aspect of this disclosure, a method includes: forming a bipolar transistor including a collector region, an emitter region, and a base region; and forming a lateral ballast resistor comprising a semiconductor material adjacent to the collector region. Attached Figure Description

[0009] In the following detailed description, the present disclosure is described with reference to the various accompanying drawings, using non-limiting examples of exemplary embodiments of the present disclosure.

[0010] Figures 1A-1E Fin-based bipolar electrostatic discharge (ESD) devices and corresponding manufacturing processes are shown according to some aspects of this disclosure.

[0011] Figures 2A-2D The present disclosure illustrates a fully depleted (or partially depleted) silicon-on-insulator (hybrid SOI) bipolar electrostatic discharge (ESD) device having a bulk CMOS region and a corresponding fabrication process, according to some aspects of the present disclosure.

[0012] Figure 3 A graph comparing the ESD device of this disclosure with an ESD FinFET device without a lateral ballast resistor is shown. Detailed Implementation

[0013] This disclosure relates to semiconductor structures, and more specifically, to fin-based bipolar electrostatic discharge (ESD) devices and methods for fabricating the same. More specifically, this disclosure relates to fin-based ESD bipolar devices with lateral ballast resistance and fully depleted silicon-on-insulator (FDSOI) or partially depleted silicon-on-insulator (PDSOI) bipolar devices. Advantageously, this disclosure provides improvements in ESD performance in FinFET, FDSOI, and PDSII technologies.

[0014] In embodiments, the ESD device may be a fin-based bipolar transistor with lateral ballast resistance. The lateral ballast resistance can be formed in a fin-based bipolar structure for improving ESD performance in FinFET technology. For example, in the implementation described in this disclosure, the bipolar structure includes an N+ fin located in the emitter region, collector region, and ballast resistance region, and a P+ fin located in the base region. The collector region, emitter region, and base region may be formed in a P-well region; while the ballast resistance region may be formed in an N-well region having multiple ballast resistance fins, thereby providing both vertical and lateral ballast resistance through the fins themselves. Specifically, to increase the lateral ballast resistance, an epitaxial semiconductor layer may be provided to connect the surfaces of multiple ballast resistance fins and one or more adjacent collector fins to merge the ballast resistance fins and collector fins.

[0015] In embodiments, NPN transistors can be formed using FinFET technology, which uses dummy-combined ballast resistor fins to generate ballast resistance for multi-finger triggering. Laterally ballasted NPN transistors can be constructed using FinFET technology, where ballast is provided via epitaxially combined ballast resistor fins. Such lateral bipolar devices include multiple fins adjacent to each other, where the innermost fin includes a collector fin located in a P-well and adjacent fins include ballast resistor fins located in an N-well. In this structure, the epitaxial region above the ballast resistor fins can be silicided and contacted to serve as a collector contact via an epitaxial region extending above a connection fin between the collector fin and the outermost ballast resistor fin. Furthermore, in this structure, the ballast resistance can be adjusted by the number of ballast fins having silicided regions and contact regions located on the epitaxially combined ballast fin regions. In other aspects, the lateral ballast resistance can be provided by a fully depleted (FD) or partially depleted (PD) SOI structure.

[0016] In FDSOI or PDSOI structures, for example, a lateral ballast resistor layer can be disposed as a thin semiconductor layer above a buried oxide layer constructed using FDSOI technology, adjacent to and in contact with one or both of the collector and emitter of a lateral bipolar transistor device formed in the bulk region of the substrate. In this way, hybrid ESD devices can be formed. For example, a lateral NPN bipolar transistor can be constructed using FDSOI or PDSOI technology, where the ballast resistor can be formed, for example, through a thin semiconductor layer in the SOI region, and the NPN transistor can be located in an adjacent bulk / hybrid region, where the additional ballast resistor enables the device to operate via finger-to-finger scaling.

[0017] In other examples, laterally ballasted NPNs can be constructed using fully depleted SOI (FDSOI) or partially depleted SOI (PDSOI) techniques, where the ballast resistors are located on the core portion of the NPN within the SOI region and the adjacent body region. Such lateral bipolar devices include emitter and collector electrodes formed within the body region of the wafer forming the core NPN transistor, with emitter and collector ballast resistors positioned on the FDSOI / PDSOI region adjacent to the NPN. In such an arrangement, the body NPN and FDSOI / PDSOI ballast regions can be merged / integrated to form a ballasted NPN, where the ballast can be integrated with the body NPN transistor region to provide ballast within the collector and emitter silicon regions.

[0018] The ESD devices disclosed herein can be fabricated using a variety of different tools and in a variety of ways. However, generally, methods and tools are used to form structures with micron and nanometer scale dimensions. Methods (i.e., techniques) for fabricating the ESD devices of this disclosure have been adopted according to integrated circuit (IC) technology. For example, these structures are built on a wafer and realized using a material film patterned by a photolithography process on top of the wafer. Specifically, the fabrication of the ESD devices uses three basic building blocks: (i) depositing a thin film material on a substrate; (ii) applying a patterned mask on top of the thin film by photolithography imaging; and (iii) selectively etching the thin film according to the mask.

[0019] Figure 1A An initial structure and corresponding manufacturing process according to some aspects of this disclosure are shown. More specifically, Figure 1A Structure 10 includes a substrate 12 made of any suitable semiconductor material, including but not limited to Si, SiGe, SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. Substrate 12 may include any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientations). Substrate 12 may be a single semiconductor material such as bulk silicon or may be constructed using semiconductor-on-insulator (SOI) technology.

[0020] Still referencing Figure 1A Substrate 12 includes wells 14 and 16. In lateral NPN bipolar applications, well 14 is a P-well and well 16 is an N-well. In lateral PNP bipolar applications, well 14 can be an N-well and well 16 can be a P-well. Wells 14 and 16 can be formed by introducing different dopant types into substrate 12, for example, through ion implantation. For example, P-well 14 can be doped with a p-type dopant, such as boron (B), and N-well 16 can be doped with an n-type dopant, such as arsenic (As), phosphorus (P), and antimony (Sb), as well as other suitable examples.

[0021] In the ion implantation process, a corresponding patterned implantation mask can be used to define selected areas exposed for implantation. The implantation mask used to select the exposed area with respect to well 14 is stripped after implantation and before the implantation mask used for well 16 (and vice versa). Similarly, the implantation mask used to select the exposed area with respect to well 16 is stripped after implantation. The implantation mask may comprise a layer of photosensitive material, such as an organic photoresist, which is applied by spin coating, then pre-baked, exposed to light projected through the photomask, post-baked, and developed with a chemical developer. Each implantation mask has sufficient thickness and blocking capability to prevent the masked area from receiving a certain dose of implanted ions. For illustrative purposes only, N-well 14 and P-well 16 may be in the form of 10 -17 Horizontal doping.

[0022] Figure 1B Multiple fin structures 20 formed through substrate 12 are shown. The multiple fin structures 20 can be formed before or after forming wells 14, 16. In an embodiment, the multiple fin structures 20 can be formed using conventional photolithography and etching processes including sidewall imaging technology (SIT). In an example of SIT technology, a mandrel material (e.g., SiO2) is deposited on substrate 12 using a conventional chemical vapor deposition (CVD) process. A resist is formed on the mandrel material, and the resist is exposed to light to form a pattern (opening). An etching process, such as reactive ion etching (RIE), can be performed through the openings to form the mandrel. Spacers are formed on the sidewalls of the mandrel, the material of which is preferably different from the mandrel and can be formed using conventional deposition processes known to those skilled in the art. Using a conventional etching process, the mandrel is selectively removed or stripped from the spacers. Etching can then be performed within the spacers to form sub-photolithographic features, such as fin structures 20. The sidewall spacers can then be stripped. In the embodiments, the height of the fin structure can be between 20 and 50 nm, although these values ​​are for illustrative purposes only and are not intended to limit this disclosure.

[0023] In this embodiment, the fin structure 20 can be used in different regions of the structure to be formed of the ESD device. For example, as Figure 1BAs shown, the different regions include a ballast resistance region 22 with ballast resistance fins 23 (e.g., dummy fins) above the N-well 16, an emitter region 26 with one or more emitter fins 27, a base region 28 with one or more base fins 29 above the P-well 14, and a collector region 24 with one or more collector fins 25 above the P-well 14. Furthermore, in NPN applications, the ballast resistance fin structure 23, collector fin 25, and emitter fin 27 in the ballast resistance region 22 can be n-doped fin structures; while the base fin 29 can be p-doped fin structures. In any case, preferably after the fin formation process, and preferably after a deep ion implantation process that forms wells 14, 16 using the different masking steps described above, the fin structure 20 can be doped by performing a shallow ion implantation process. In an embodiment, the fin structure 20 can be doped at approximately 10 -20 Horizontal doping.

[0024] refer to Figure 1C Multiple shallow trench isolation structures 18a, 18b can be formed in the substrate 12 to separate fins 23, 25, 27, 29. In an embodiment, the shallow trench isolation structure 18a extends into (i) the well 14 between the collector region 24 and the emitter region 26 to provide the base width Wb between the collector fin 25 and the emitter fin 27, and extends into (ii) the well 14 between the emitter fin 27 and the base fin 29 to provide the width Wb, as per [reference to...]. Figure 1D More detailed description; while the shallow trench isolation structure 18b extends into the trap 16 in the ballast resistor region 22 between the ballast resistor fins 23 themselves and between the ballast resistor fins 23 and the collector fins 25.

[0025] Figure 1C The shallow trench isolation structures 18a and 18b shown can be formed using conventional etching and deposition methods known to those skilled in the art. For example, one or more trenches can be formed in the substrate 12 using an etching process with selective chemical action (e.g., RIE). After the etching process, an insulating material can be deposited using any conventional deposition process (e.g., CVD process) to form the shallow trench isolation structures 18a, 18b, and 18c.

[0026] refer to Figure 1DIn an embodiment, fins 23 and 25 can be shorted together via the epitaxial semiconductor layer 30 to increase the lateral ballast resistance of the collector fin 25. As described in more detail herein, the growth of the epitaxial semiconductor layer 30 will merge over fins 23 and 25, resulting in the shorting of fins 23 and 25 due to the minimum spacing between them. In this way, lateral ballast resistance is achieved by the epitaxial semiconductor layer 30, which is formed in direct contact with and merged with the ballast resistance fins 23 and the collector fins 25. Conversely, due to the increased distance Wb, the epitaxial semiconductor layer 30 will not merge between fins 25, 27, and 29. In an embodiment, the upper portions of fins 23 and 25 can be recessed before the growth of the epitaxial semiconductor layer 30 occurs.

[0027] More specifically, an epitaxial layer 30 can be formed on the upper surfaces of the ballast resistor fin 23 and the collector fin 25 using an epitaxial growth process. This formation continues until the individual epitaxial regions on each of the fins 23 and 25 merge together and are thus shorted by the merged epitaxial semiconductor layer 30. The epitaxial semiconductor layer 30 can be any semiconductor material and can be doped with the same type of dopant as the ballast resistor fin 23 and the collector fin 25. For example, the epitaxial semiconductor layer 30 can be phosphorus-doped silicon or silicon-germanium on the surface of each of the fins 23, 25, 27, and 29. According to an alternative embodiment, the epitaxial layer 30 can be a group III-V compound semiconductor material, such as GaAs, InP, GaN, InGaAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof.

[0028] In an embodiment, the width Wb can be adjusted to ensure that the epitaxial material 30 does not merge with fins 25, 27 or fins 27, 29. For example, in an embodiment, the base width Wb can be greater than the distance between the collector fin 25 and the nearest adjacent ballast resistor fin 23. The base width Wb can also be greater than the distance between the ballast resistor fins 23 themselves. This ensures that the epitaxial growth occurring on the upper surface of the collector fin 25 does not extend to and merge with the adjacent emitter fin 27 or base fin 29, which would otherwise cause a short circuit between the collector region and emitter regions 24, 26 or a short circuit between the emitter region 26 and the base region 28.

[0029] For example, if the fin spacing between the individual ballast resistor fins 23 and between the collector fin 25 and the nearest adjacent ballast resistor fin 23 is 14 nm (e.g., in a 14 nm technology), then Wb can be set in the range of 15 nm to 100 nm. In a preferred embodiment, Wb can be at least three (3) to four (4) times larger than the distance between the ballast resistor fins 23 and between the collector fin 25 and the nearest adjacent ballast resistor fin 23 to ensure that the epitaxial layer 30 does not short-circuit the collector fin 25 and the emitter fin 27. Furthermore, the height of the epitaxial layer 30 can be determined by the time required for the epitaxial growth process of merging the respective epitaxial regions on each of the ballast resistor fins 23 and the collector fin 25 to form the ballast resistor epitaxial layer 30. Typically, in a 14 nm technology, the height of the epitaxial layer 30 can be approximately 25 nm, although this is not intended to limit this disclosure. In other technologies, such as 7 nm technology, the fin spacing, base width Wb, and height of the ballast resistor epitaxial layer 30 can be scaled accordingly.

[0030] Still referencing Figure 1D The P-well 14 in collector region 24 and the N-well 16 in ballast resistor region 22 can be in contact with each other. Alternatively, in a PNP application where well 16 can be a P-well and well 14 can be an N-well, the ballast resistor fin 23, collector fin 25, and emitter fin 27 can be p-doped fin structures; while the base fin 29 in base region 28 can be an n-doped fin structure. Figure 1D As further shown, multiple ballast resistor fins 23, a base fin 29, a collector fin 25, and an emitter fin 27 are provided; however, it should be understood that a different number of fin structures may be used in each region.

[0031] Those skilled in the art will understand that the combination of the ballast resistor fin 23 in the ballast resistor region 22 with a well 16 (e.g., an N-well) having a different type of implanted dopant can form a lateral ballast resistor at the ballast resistor region 22, such as a lateral N-well resistor and a vertical dummy fin resistor in the ballast resistor fin 23. The lateral ballast resistor provides stability to the circuit by preventing overcurrent faults. The lateral ballast resistor can also be formed without a silicide block region. In this arrangement, the N-well 16 prevents the ballast resistor fin 23 from acting as a collector fin by preventing undesirable avalanche breakdown, thus rendering the ballast resistor fin 23 a dummy fin.

[0032] refer to Figure 1E Contacts 32a, 32b, and 32c are respectively provided on the epitaxial semiconductor layer 30, the emitter fin 27, and the base fin 29. Since the epitaxial semiconductor layer 30 connects the upper surface of the ballast resistor fin 23 and the collector fin 25, the metal contact 32a also serves as a contact for the collector region 24.

[0033] Contacts 32a, 32b, and 32c can be formed using a siliconization process. Those skilled in the art will understand that the siliconization process begins on a fully formed and patterned semiconductor device (e.g., Figure 1E A thin transition metal layer, such as nickel, cobalt, or titanium, is deposited on the doped or ion-implanted ballast resistor epitaxial layer 30, emitter fin 27, and base fin 29 in the illustrated ESD device. After material deposition, the structure is heated to react the transition metal with the exposed silicon (or other semiconductor materials described herein) in the epitaxial semiconductor layer 30, emitter fin 27, and base fin 29, thereby forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, thereby creating a low-resistance transition metal silicide. Figure 1E The ballast resistor epitaxial layer 30, emitter fin 27, and base fin 29 in the illustrated ESD device have silicide contacts 32a, 32b, and 32c. Although not shown, these metal contacts to the silicide regions can be formed using conventional CMOS processes known to those skilled in the art, so that this disclosure can be fully understood without further explanation.

[0034] Figure 2A The initial structure of an ESD device using semiconductor-on-insulator (SOI) substrate technology and the corresponding fabrication process are shown. More specifically, Figure 2A The ESD device 40 includes a substrate 42 made of a silicon layer 44 or any other suitable semiconductor material, including but not limited to SiGe, SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. The substrate 42 may include any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). An insulating layer 45 is disposed over the semiconductor layer 44, and a semiconductor layer 47 is disposed over the insulating layer 45. The semiconductor layer 47 may be a partially or fully depleted SOI technology. The insulating layer 45 includes any suitable material, including silicon oxide, sapphire, other suitable insulating materials, and / or combinations thereof. An exemplary insulating layer 45 may be a buried oxide layer (BOX). The insulating layer 45 may be formed by any suitable process, such as oxygen implantation isolation (SIMOX), oxidation, deposition, and / or other suitable processes.

[0035] In lateral NPN bipolar applications, semiconductor layer 44 may include a P-well. In lateral PNP bipolar applications, semiconductor layer 44 may include an N-well. Semiconductor layer 44 can be formed by introducing different dopant types into semiconductor layer 44, for example, through ion implantation processes already described herein.

[0036] refer to Figure 2BThe insulating layer 45 and semiconductor layer 47 in the emitter region 51 and base region 53 can be removed. The insulating layer 45 and semiconductor layer 47 can be removed using conventional photolithography and etching processes (e.g., RIE) known in the art, and therefore this disclosure is fully understood without further explanation. In an embodiment, the etching process exposes the underlying semiconductor layer 44, allowing epitaxial semiconductor material 43 to be grown in the emitter region 51 and base region 53 using conventional epitaxial growth processes. In an embodiment, the epitaxial semiconductor material 43 can represent the bulk region of a substrate made of any suitable material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other group III / V or II / VI compound semiconductors. Furthermore, the epitaxial semiconductor material 43 can be planarized to form a planar surface using, for example, chemical mechanical planarization (CMP) processes known in the art.

[0037] like Figure 2C As shown, a plurality of shallow trench isolation structures 52 extending into the epitaxial semiconductor material 43 are formed in the emitter region 51 and the base region 53. In an embodiment, the shallow trench isolation structures 52 are formed using conventional photolithography, etching, and deposition processes already described herein. Subsequently, a collector 46, an emitter 48, and a base 50 are formed in the epitaxial semiconductor material 43 to form a lateral bipolar transistor adjacent to an FDSOI technique consisting of a collector-side ballast resistor 47a and an emitter-side ballast resistor 47b formed through the semiconductor layer 47. In this way, a hybrid device is formed comprising a lateral bipolar transistor structure located in the semiconductor layer 44, and a ballast resistor structure formed using the FDSOI technique adjacent to the lateral bipolar transistor structure.

[0038] In embodiments, collector 46, emitter 48, and base 50 can be formed using conventional diffusion or ion implantation processes already described herein. Alternatively, regions 46, 48, and 50 can be formed by doped epitaxial deposition of epitaxial semiconductor material 43. In lateral NPN bipolar applications, emitter 46 and collector 48 can be N+ regions, while base 50 can be a P+ region. In lateral PNP bipolar applications, emitter 46 and collector 48 can be P+ regions, while base 50 can be an N+ region.

[0039] like Figure 2CAs shown, the collector-side ballast resistor 47a can contact the side surface of the collector 46, and the emitter-side ballast resistor 47b can contact the side surface of the emitter 48. Additionally, in the NPN lateral bipolar transistor embodiment, the collector-side ballast resistor 47a and the emitter-side ballast resistor 47b can be N+ doped diffusion regions defined by epitaxial growth. In the PNP lateral bipolar transistor embodiment, the collector-side ballast resistor 47a and the emitter-side ballast resistor 47b can be P+ doped diffusion regions defined by epitaxial growth.

[0040] By using a thin semiconductor layer 47 in FDSOI / PDSOI technology, for example, between 3 nm and 15 nm, the collector ballast resistor 47a and emitter ballast resistor 47b can have high resistances, such as 350 ohms, without requiring doping of the semiconductor layer 47. Furthermore, in embodiments, the semiconductor layer 47 can be doped to provide control over the amount of ballast resistance based on the amount of doping.

[0041] refer to Figure 2D The ESD device 40 also includes contacts 58a, 58b, and 58c formed on the collector-side ballast resistor 47a, the emitter-side ballast resistor 47b, and the base region 50, respectively. These contacts 58a, 58b, and 58c are designed to interact with the contacts formed on the collector-side ballast resistor 47a, the emitter-side ballast resistor 47b, and the base region 50. Figure 1E The same manner of contact as described in sections 32a, 32b, and 32c is formed, and no further explanation is needed here.

[0042] By utilizing information Figure 1E and 2D The lateral ballast resistor arrangement discussed can significantly increase the ballast resistance compared to known ESD devices. For example, in a lateral NPN bipolar ESD device using FinFET technology (where the ballast resistance is only the vertical resistance within the fin itself), a typical ballast resistance is 100 ohms with a threshold voltage of 8.75 volts and a holding voltage of 5.0 volts. This is generally insufficient to allow the use of, for example, hundreds of individual ESD devices to trigger all devices in a multi-fin ESD device arrangement. In contrast, using… Figure 1E The simulation of the arrangement shown employs a ballast resistance of 350 ohms for each ESD device at similar threshold and holding voltages. Similarly, in Figure 2D In the arrangement shown with lateral collector-side ballast resistor 47a and lateral emitter-side ballast resistor 47b, the ballast resistor for each ESD device is 300 ohms under similar threshold and holding voltages.

[0043] In each case, use Figure 1E and 2DThe arrangement shown in the diagram uses an increased lateral ballast resistor. This increase in ballast resistor is sufficient to ensure that all ESD devices in the multi-finger ESD arrangement are triggered, as described below. Figure 3 The resistance values ​​discussed herein should be understood to be exemplary and may increase or decrease based on different variables, such as material type and doping distribution.

[0044] Figure 3 This illustrates the ESD device of this disclosure in relation to... Figure 1E and Figure 2D A graph comparing the ESD FinFET devices without lateral ballast resistors discussed. Figure 3 In the diagram, the ESD device described in this disclosure is depicted as line "B," and the ESD FinFET device without a lateral ballast resistor is depicted as line "A." The x-axis represents voltage, and the y-axis represents current. As the comparison diagram shows, lines "A" and "B" behave similarly because line "A" has a trigger voltage similar to that of line "B" at point "1," then bounces back at point "2," and then fails at point "3." At point #3, the voltage on the x-axis of line "B" is higher than that of line "A." In other words, the voltage of line "B" will rise above point #1 after point #2, and then the voltage at point #3 will be much higher than that of line "A." This leads to multi-finger triggering using a device with multiple parallel fingers for forming a wide device (i.e., 10 fingers, each 20 μm, for a total width of 200 μm).

[0045] More specifically, point 1 represents Vt1, where the transistor is on; point 2 represents Vh, at which point the transistor (NPN) voltage will bounce back to a lower voltage; and point 3 represents Vt2, which is the circuit fault point. This can be achieved by using information about... Figures 1A-2D The technique discussed uses a lateral ballast resistor to increase resistance, which can increase Vt2, thereby allowing subsequent fingers in multi-finger applications (e.g., ESD devices) to turn on. This effectively allows all fingers (NPN) in a multi-finger device to turn on, thus improving ESD performance.

[0046] With further examples, it should be understood that Vt may vary slightly between different devices due to process variations. Furthermore, assume the NPN triggers at 6V to 7V and bounces back to approximately 2V. In this example, without the additional ballast resistor provided by the arrangement of this disclosure, once bounce-back occurs on the first transistor (NPN) and the voltage drops to approximately 5V, subsequent transistors in the multi-finger device will be prevented from triggering (e.g., turning on). However, by using the above-described... Figure 1E and 2DThe discussed structure, by increasing the lateral ballast resistance, can increase the trigger voltage for switching on, thus allowing subsequent devices in a multi-finger device to switch on even in the presence of springback. Therefore, in Figure 1E fin-based bipolar structure and Figure 2D The lateral ballast resistor formed in the FDSOI structure improves ESD performance in FinFET technology. In summary, regarding... Figure 3 Ron is increased after the initial triggering of one or more transistors in a multi-finger device to enable multi-finger triggering of all transistors in the multi-finger device.

[0047] TCAD simulations have confirmed that the above arrangement using FDSOI technology can increase Ron by approximately 3 times (3X). Similarly, in a finned ballast NPN arrangement, Ron increases by approximately 3.5 times. The end result is that the above FDSOI and finned ballast devices show an increase in Ron in the 3-3.5x range, enabling both devices to handle finger-to-finger current (good width scaling), which the basic lateral NPN structure cannot achieve. For example, in a device with 10 fingers, the ballast device using the above arrangement can handle nearly 10 times more current than the basic lateral NPN device, thus converting it from a non-operating device to an operating device to provide ESD protection.

[0048] ESD devices can be utilized in System-on-Chip (SoC) technology. Those skilled in the art will understand that an SoC is an integrated circuit (also called a "chip") that integrates all components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes significantly less power and occupies a much smaller area compared to a multi-chip design with the same functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things (IoT).

[0049] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0050] Descriptions of various embodiments of this disclosure have been given for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or process improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: A bipolar transistor includes a collector region, an emitter region, and a base region; as well as The lateral ballast resistor adjacent to the collector region comprises a semiconductor material. The collector region includes a collector fin structure with a first dopant type, the emitter region includes an emitter fin structure with the first dopant type, the base region includes a base fin structure with a second dopant type, and the lateral ballast resistor includes a lateral ballast fin structure with the first dopant type adjacent to the collector fin structure.

2. The semiconductor structure according to claim 1, wherein, The lateral ballast resistor comprises an epitaxial semiconductor material connecting the surface of the collector fin structure and the surface of the lateral ballast fin structure.

3. The semiconductor structure according to claim 1, wherein, The collector region, the emitter region, and the base region are located in a first well having the second dopant type, the lateral ballast fin structure is located in a second well having the first dopant type, and the second well is adjacent to and in contact with the first well having the second dopant type in the collector region.

4. The semiconductor structure according to claim 3, wherein, The second well having the first dopant type includes an N-well, and the first well having the second dopant type includes a P-well.

5. The semiconductor structure according to claim 1, further comprising: A shallow trench isolation region that separates the emitter region from the collector region and the emitter region from the base region.

6. The semiconductor structure according to claim 5, wherein, The width of one of the shallow trench isolation regions that separates the emitter region from the collector region is greater than the distance between the collector fin structure and the adjacent ballast fin structure.

7. The structure according to claim 1, wherein, The collector region, the emitter region, and the base region include a bulk semiconductor substrate, and the semiconductor material of the lateral ballast resistor includes a semiconductor-on-insulator (SOI) adjacent to the collector region.

8. The semiconductor structure according to claim 7, wherein, The semiconductor material of the SOI includes one of the following: partially depleted SOI and fully depleted SOI, wherein the semiconductor material contacts the side surface of the collector region.

9. A semiconductor structure, comprising: Fin-based bipolar electrostatic discharge (ESD) devices include: The collector fin structure located above the first well having a first dopant type, and The ballast resistor fin structure is located above the second well having a second dopant type and in contact with the collector fin structure. The collector fin structure and the ballast resistor fin structure include the second dopant type.

10. The semiconductor structure according to claim 9, further comprising: The collector fin structure is connected to the epitaxial semiconductor material of the ballast resistor fin structure.

11. The semiconductor structure according to claim 10, wherein, The first well and the second well include an n-doped type, and the epitaxial semiconductor material includes a lateral ballast resistance region.

12. The semiconductor structure according to claim 10, further comprising: A shallow trench isolation structure separates the base region from the emitter region of the fin-based bipolar ESD device, and also separates the collector region from the emitter region of the fin-based bipolar ESD device.

13. The semiconductor structure according to claim 9, wherein, The first dopant type includes the P dopant type and the second dopant type includes the N dopant type.

14. The semiconductor structure according to claim 9, wherein, The fin-based bipolar electrostatic discharge (ESD) device includes a lateral bipolar device, which includes the collector fin structure, the base fin structure, and the emitter fin structure.

15. The semiconductor structure according to claim 9, wherein, The ballast resistor fin structure contacts the second well and is separated from each other by at least one shallow trench that contacts the second well.

16. The semiconductor structure according to claim 15, further comprising: An epitaxial semiconductor layer extending over each of the ballast resistor fin structure, the collector fin structure, the first shallow trench isolation region, and the second shallow trench isolation region, wherein the collector fin structure contacts the first well and is separated from the adjacent ballast resistor fin structure in the ballast resistor fin structure by the second shallow trench isolation region.

17. A method for manufacturing a semiconductor structure, comprising: This forms a bipolar transistor comprising a collector region, an emitter region, and a base region. as well as A lateral ballast resistor comprising semiconductor material is formed adjacent to the collector region. The collector region includes a collector fin structure with a first dopant type, the emitter region includes an emitter fin structure with the first dopant type, the base region includes a base fin structure with a second dopant type, and the lateral ballast resistor includes a lateral ballast fin structure with the first dopant type adjacent to the collector fin structure.

18. The method according to claim 17, wherein, The lateral ballast resistor comprises a semiconductor material in contact with the collector region.

19. The method of claim 17, wherein, The collector fin structure is formed from a substrate material, and the lateral ballast resistor includes a dummy fin that is incorporated into the collector fin structure through a semiconductor epitaxial growth process.

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