Optimization design method of non-uniform emitter structure

Abstract

According to the non-uniform emitter structure optimization design method provided by the invention, collaborative optimization design is carried out on a non-uniform emitter contact structure based on the heat distribution characteristic in the preset working state, and differentiated configuration is carried out on the distance and length of emitter fingers and the resistance value of a ballast resistor according to high-temperature and low-temperature regions; under the action of electrothermal coupling, the current density of a high-temperature area of the device is effectively suppressed, and the conductivity of a low-temperature area is fully called, so that the current distribution and temperature field of the whole emitter junction surface are remarkably balanced, the hot spot effect and the positive feedback risk caused by the hot spot effect are fundamentally weakened, and the reliability of the device is improved. And the thermal stability, the reliability and the service life of the heterojunction bipolar transistor under a high-power working condition are greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a non-uniform emitter structure optimization design method. BACKGROUND

[0002] As the core device of modern high-frequency and high-power electronic systems, the performance and reliability of heterojunction bipolar transistors directly determine the efficiency and service life of the entire circuit. With the increasing demand for output power and efficiency in wireless communication, radar and other applications, the operating current density of the device is increasing, and the self-heating effect caused thereby has become a key bottleneck restricting its development.

[0003] In traditional design, the multi-emitter finger structure commonly used to improve current capacity is usually designed based on the principles of geometric symmetry and uniform distribution, for example, each emitter finger has the same pitch, length, and uniform ballast resistance. However, in actual operation, due to the combined effects of various physical factors such as the thermal conductivity limitation of the device material, the difference in edge heat dissipation conditions, and the uneven distribution of power dissipation, a highly non-uniform temperature field will be formed inside the chip, resulting in a local high-temperature region, i.e. "hot spot". This inherent non-uniformity of thermal distribution will be further exacerbated under a uniform emitter structure, because the current density in the high-temperature region will spontaneously increase due to the positive feedback effect of temperature, causing the temperature in this region to continue to rise, forming a vicious cycle of thermal runaway. This phenomenon not only causes the degradation of device performance parameters, such as a sharp drop in current gain, but more seriously, it accelerates device aging and causes permanent damage, thereby significantly shortening the service life. SUMMARY

[0004] Therefore, the present application provides a non-uniform emitter structure optimization design method to solve the technical defects in the prior art.

[0005] The present application provides a non-uniform emitter structure optimization design method, comprising: providing a device wafer, the device wafer comprising a substrate, a gallium arsenide collector region, and a gallium indium phosphide emitter region in sequence; determining the layout of the emitter contact structure based on the thermal distribution characteristics of the heterojunction bipolar transistor under a preset operating state; the layout includes the pitch of the plurality of emitter fingers, the length of the plurality of emitter fingers, and the resistance value of each ballast resistor in the ballast resistor network connecting the plurality of emitter fingers; wherein the step of determining the layout comprises: configuring the pitch of the plurality of emitter fingers to be non-uniform, so that the pitch of the emitter fingers in the high-temperature region identified in the thermal distribution characteristics is greater than the pitch of the emitter fingers in the low-temperature region identified in the thermal distribution characteristics; The lengths of the plurality of emitter fingers are configured to be non-uniform, such that the lengths of the emitter fingers in the high-temperature region are shorter than the lengths of the emitter fingers in the low-temperature region; The resistances of the ballast resistors in the ballast resistor network are configured to be non-uniform, such that the resistance of the ballast resistor corresponding to the high-temperature region is greater than the resistance of the ballast resistor corresponding to the low-temperature region; According to the determined layout of the emitter contact structure, an emitter contact structure is formed on the indium gallium phosphide emission region.

[0006] In some embodiments, based on the thermal distribution characteristics of the heterojunction bipolar transistor in the preset working state, the step of determining the layout of the emitter contact structure specifically comprises: An initial temperature distribution map of the heterojunction bipolar transistor in the preset working state is obtained through a coupled simulation model; Based on the initial temperature distribution map, the high-temperature region and the low-temperature region are identified; According to the distribution of the high-temperature region and the low-temperature region, a first non-uniform spacing configuration scheme, a first non-uniform finger length configuration scheme, and a first non-uniform resistance configuration scheme are generated; The first non-uniform spacing configuration scheme, the first non-uniform finger length configuration scheme, and the first non-uniform resistance configuration scheme are input into the coupled simulation model for iterative optimization until the final temperature distribution map output satisfies the preset uniformity threshold; The non-uniform configuration scheme corresponding to the time when the preset uniformity threshold is satisfied is determined as the final layout.

[0007] In some embodiments, in the iterative optimization process, whether the final temperature distribution map satisfies the preset uniformity threshold is determined by a thermal stability comprehensive evaluation function, and the calculation formula of the thermal stability comprehensive evaluation function is as follows:

[0008] wherein, is the thermal stability comprehensive evaluation value, the lower the value, the better the thermal stability, the value is calculated by the coupled simulation model based on the simulation output of the current non-uniform configuration scheme; is the total number of the plurality of emitter fingers; is the average temperature of the i-th emitter finger in the temperature distribution output by the coupled simulation model; is the average value of the average temperatures of all emitter fingers; is the temperature distribution sensitivity index; is the total number of resistors in the ballast resistor network; is the resistance value of the j-th ballast resistor, which is derived from the non-uniform resistance configuration scheme used in the current iteration; is a resistance influence coefficient, which is a preset constant; is a resistance nonlinear adjustment factor, which is a preset constant greater than 1; is a resistance normalization factor, which is a preset reference resistance value; is the total number of selected monitoring points in the heat flow distribution output by the coupling simulation model; is the heat flux density of the kth monitoring point; is the minimum heat flux density among all monitoring points; is the average heat flux density of all monitoring points; is a heat flow distribution form factor, which is an even preset constant greater than or equal to 2.

[0009] In some embodiments, the value of the temperature distribution sensitivity index is determined through a dynamic adjustment process, and the corresponding calculation formula is as follows:

[0010] wherein, is a basic sensitivity constant, which is a preset initial value; M is the number of temperature gradient regions divided in the initial temperature distribution map; is the maximum temperature difference in the mth temperature gradient region; is a temperature difference normalization factor, which is a preset reference temperature difference value; is a gradient weight index, which is a preset constant greater than 1; is a geometric mean adjustment coefficient, which is a preset constant greater than 1; is a calculation stability constant, which is a preset minimum constant greater than zero; is a calculation stability constant, which is a preset minimum constant greater than zero.

[0011] In some embodiments, the foregoing method further comprises: based on the thermal stability comprehensive evaluation value, generating a device reliability level identifier, wherein the device reliability level identifier L is determined by the following calculation formula:

[0012] wherein, L is the device reliability level identifier, which is a positive integer; is an evaluation value reference benchmark, which is a preset constant; is a level division adjustment factor, which is a preset constant greater than zero is a floor function.

[0013] In some embodiments, the coupling simulation model is an electro-thermal-mechanical multi-physical field coupling model.

[0014] In some embodiments, the material parameters used by the electro-thermal-mechanical multi-physical field coupling model include an interface defect density of the indium gallium phosphide at a heterojunction formed by the indium gallium phosphide emission region and the gallium arsenide collection region.

[0015] In some embodiments, according to the determined layout of the emitter contact structure, the step of forming the emitter contact structure on the indium gallium phosphide emission region includes: forming a plurality of emitter fingers with non-uniform spacing and non-uniform finger length on the indium gallium phosphide emission region by using a photolithography and etching process; forming a ballast resistance network with non-uniform resistance values by a thin film process, and connecting the ballast resistance network with the plurality of emitter fingers.

[0016] In some embodiments, in the step of providing the device wafer, the indium gallium phosphide emission region is formed by a metal organic chemical vapor deposition process.

[0017] In some embodiments, the preset working state is a rated maximum continuous wave working state of the heterojunction bipolar transistor.

[0018] At least one embodiment of the present application optimizes the non-uniform emitter contact structure by designing the spacing, length of the emitter fingers, and the resistance values of the ballast resistance according to the high-temperature and low-temperature regions based on the thermal distribution characteristics in the preset working state, so that the current density in the high-temperature region is effectively suppressed, and the conduction ability in the low-temperature region is fully utilized under the electro-thermal coupling effect, thereby significantly balancing the current distribution and temperature field of the entire emission junction surface, fundamentally weakening the hot spot effect and the risk of positive feedback it causes, and greatly improving the thermal stability, reliability, and service life of the heterojunction bipolar transistor under high-power working conditions. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a flowchart of a non-uniform emitter structure optimization design method provided by the present application. DETAILED DESCRIPTION

[0020] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced without the specific details, and it is understood that the present application is not limited to the embodiments described herein. Furthermore, it is understood that well-known methods, procedures and components have not been described in detail in order to avoid obscuring the present application.

[0021] The terminology used in this disclosure, one or more embodiments of the specification, is for the purpose of describing particular embodiments only and is not intended to be limiting of one or more embodiments of the specification. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or," as used in this disclosure, refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "one" and "a" are intended to refer to "one or more" unless otherwise indicated by context.

[0022] It is to be understood that, although the terms first, second, etc. can be employed in this disclosure, one or more embodiments of the specification, to describe various information, these information should not be limited to these terms. These terms are only used to differentiate one piece of information from another piece of information. For example, without departing from the scope of one or more embodiments of the specification, first can also be referred to as second, and similarly, second can also be referred to as first. Depending on the context, the word "if" as used herein can be interpreted to mean "when" or "in response to determining" as in this manner.

[0023] Referring to Figure 1 , Figure 1 A flowchart of a non-uniform emitter structure optimization design method according to some embodiments of the specification is shown, which specifically includes the following steps: providing a device wafer, the device wafer sequentially includes a substrate, a gallium arsenide collection region, and a gallium indium phosphide emission region; determining the layout of the emitter contact structure based on the thermal distribution characteristics of the heterojunction bipolar transistor under the preset working state; the layout includes the spacing of the plurality of emitter fingers, the length of the plurality of emitter fingers, and the resistance value of each ballast resistor in the ballast resistor network connecting the plurality of emitter fingers; wherein the step of determining the layout includes: configuring the spacing of the plurality of emitter fingers to be non-uniform, so that the spacing of the emitter fingers in the high-temperature region identified in the thermal distribution characteristics is greater than the spacing of the emitter fingers in the low-temperature region identified in the thermal distribution characteristics; configuring the length of the plurality of emitter fingers to be non-uniform, so that the length of the emitter fingers in the high-temperature region is shorter than the length of the emitter fingers in the low-temperature region; configuring the resistance value of each ballast resistor in the ballast resistor network to be non-uniform, so that the resistance value of the ballast resistor corresponding to the high-temperature region is greater than the resistance value of the ballast resistor corresponding to the low-temperature region; forming an emitter contact structure on the gallium indium phosphide emission region according to the determined layout of the emitter contact structure. The emitter contact structure can refer to an electrode system that realizes the electrical connection between the metal and the semiconductor, for example, a complete contact system composed of the emitter finger and the ballast resistor network, which is used to inject carriers and regulate current distribution.

[0024] Device wafer can refer to a base substrate containing multiple layers of semiconductor material, such as a composite structure of sequentially grown gallium arsenide collector region and indium gallium phosphide emitter region by metal organic chemical vapor deposition to provide a foundation for a heterojunction bipolar transistor. Substrate can refer to a base material that carries a semiconductor epitaxial layer, such as a mechanically supporting platform formed with semi-insulating gallium arsenide or silicon material to ensure the crystal quality of the epitaxial layer and achieve electrical isolation. Gallium arsenide collector region can refer to a collector region of a heterojunction bipolar transistor, such as a GaAs_{1-x}Sb_x alloy layer grown on a substrate by molecular beam epitaxy for efficient collection and transport of charge carriers. Indium gallium phosphide emitter region can refer to an emitter region of a heterojunction bipolar transistor, such as a In_{0.49}Ga_{0.51}P ternary compound semiconductor layer formed by metal organic chemical vapor deposition for enhanced electron injection efficiency. Heterojunction bipolar transistor can refer to a three-terminal device constructed with different bandgap materials, such as a transistor with GaAs-based collector region and InGaP emitter region band structure to achieve high frequency and high power amplification functionality.

[0025] The preset operating condition can refer to a specific working condition targeted by the device design, such as a voltage-current parameter combination determined under a rated maximum continuous wave operating condition, for establishing thermal simulation boundary conditions. The thermal distribution characteristic can refer to the spatial variation law of the internal temperature field of the device, such as an isotherm distribution map obtained by finite element analysis, which can reveal the location and range of local high-temperature areas. The layout of the emitter contact structure can refer to the geometric arrangement scheme of the metal electrode and the semiconductor surface, such as an asymmetric finger electrode pattern formed by photolithography process, for realizing optimized control of current distribution. The pitch of the plurality of emitter fingers can refer to the center distance between adjacent emitter metal strips, such as a gradient varying pitch of 4 microns in the high-temperature area and 2.5 microns in the low-temperature area, to adjust the thermal coupling strength. The length of the plurality of emitter fingers can refer to the longitudinal dimension of a single emitter metal strip, such as a differentiated length of 15 microns in the edge area of the chip and 10 microns in the center area, for balancing the current density. The ballast resistance network can refer to an impedance array connected in series in the emitter path, such as a distributed attenuation structure formed by a tantalum nitride thin film resistor, which can suppress the thermal runaway phenomenon. The resistance value of each ballast resistance can refer to the impedance size of a single ballast element, such as a gradient resistance value of 15 ohms in the hot spot area and 8 ohms in the low-temperature area, for realizing dynamic current sharing. The high-temperature area can refer to a local heating area with high power density, such as a chip center area exceeding 150 degrees Celsius identified by infrared thermal imaging, which is the main occurrence location of thermal failure. The low-temperature area can refer to an edge area with good heat dissipation conditions, such as a heat dissipation channel area with a chip peripheral temperature below 100 degrees Celsius, which has higher current carrying potential. The non-uniform pitch configuration can refer to the differentiated setting of the emitter finger spacing, such as expanding the high-temperature area pitch to 1.5 times that of the low-temperature area according to the thermal simulation results, to reduce the thermal coupling effect. The non-uniform finger length configuration can refer to the gradient design of the emitter finger size, such as shortening the high-temperature area finger length to 70% of the low-temperature area, for adjusting the local current density. The non-uniform resistance value configuration can refer to the adaptive allocation of the ballast resistance value, such as dynamically adjusting the resistance value distribution according to real-time temperature feedback, to realize negative feedback regulation of thermal stability. Forming on the indium gallium phosphide emission region can refer to the process of preparing the electrode structure on the semiconductor surface, such as using electron beam evaporation of Ti / Pt / Au metal stack and photolithography shaping, for establishing ohmic contact.

[0026] As a specific example: in the InGaP / GaAs heterojunction bipolar transistor design, first, the initial temperature distribution of the device at a working frequency of 2 GHz and a collector-emitter voltage of 5 V is obtained through Sentaurus TCAD electro-thermal coupling simulation. It is identified that the center region of the chip forms a high temperature area of 125℃ due to poor heat dissipation, while the edge region is only 85℃. Accordingly, a non-uniform layout scheme is generated: the center region is set to an emitter finger spacing of 3μm, a finger length of 10μm, and a ballast resistance of 12Ω; the edge region is set to a spacing of 2μm, a finger length of 15μm, and a ballast resistance of 6Ω. After three iterations of optimization, the ICP etching is used to pattern the emitter fingers on the In_{0.49}Ga_{0.51}P emission region, and the sputtering TaN thin film is used to form a gradient resistance ballast resistance network, finally reducing the maximum temperature difference of the chip from 40℃ to 15℃.

[0027] The beneficial effects of one of the embodiments in the specification at least include: by optimizing the design of the non-uniform emitter contact structure based on the thermal distribution characteristics under the preset working state, the spacing, length and resistance value of the emitter finger are differentiated according to the high temperature and low temperature regions, so that under the electro-thermal coupling effect, the current density in the high temperature region is effectively suppressed, and the conduction ability in the low temperature region is fully utilized, thereby significantly balancing the current distribution and temperature field of the entire emission junction surface, fundamentally weakening the hot spot effect and the risk of positive feedback it causes, and greatly improving the thermal stability, reliability and service life of the heterojunction bipolar transistor under high power working conditions.

[0028] In some embodiments, based on the thermal distribution characteristics of the heterojunction bipolar transistor under the preset working state, the step of determining the layout of the emitter contact structure specifically includes: obtaining an initial temperature distribution map of the heterojunction bipolar transistor under the preset working state through a coupling simulation model; identifying a high temperature region and a low temperature region based on the initial temperature distribution map; generating a first non-uniform spacing configuration scheme, a first non-uniform finger length configuration scheme and a first non-uniform resistance value configuration scheme according to the distribution of the high temperature region and the low temperature region; inputting the first non-uniform spacing configuration scheme, the first non-uniform finger length configuration scheme and the first non-uniform resistance value configuration scheme into the coupling simulation model for iterative optimization until the final temperature distribution map output satisfies the preset uniformity threshold; determining the non-uniform configuration scheme corresponding to the preset uniformity threshold as the final layout.

[0029] The coupled simulation model can refer to a numerical calculation system of multi-physical field interaction, such as an electrical-thermal-force coupling analysis module established through the ANSYS or COMSOL platform, for accurately simulating the physical field distribution of the device in the working state. The initial temperature distribution map can refer to the original thermal field visualization data before optimization, such as the temperature contour distribution in the form of color cloud map obtained through finite element analysis, which can directly display the hot spot position on the chip surface. The high-temperature region and the low-temperature region can refer to the device partitions divided according to the temperature threshold, for example, the region exceeding the average temperature by 20% is marked as a red high-temperature region, and the region below the average temperature by 15% is marked as a blue low-temperature region, for guiding differentiated design. The first non-uniform spacing configuration scheme can refer to the first iteration of the emitter finger spacing adjustment strategy, for example, setting the high-temperature region spacing to be 1.8 times the initial scheme of the low-temperature region, to preliminarily reduce the thermal coupling strength. The first non-uniform finger length configuration scheme can refer to the first iteration of the emitter finger size adjustment strategy, for example, reducing the high-temperature region finger length to 65% of the initial proportion of the low-temperature region, for preliminarily adjusting the local current density. The first non-uniform resistance configuration scheme can refer to the first iteration of the ballast resistance distribution strategy, for example, setting the high-temperature region resistance to be 2.2 times the initial ratio of the low-temperature region, to achieve the preliminary current sharing effect. The final temperature distribution map can refer to the stable thermal field data after optimization, for example, the uniform temperature field distribution with a temperature difference of less than 5% obtained after 5 iterations, representing the simulation result reaching the design target. The preset uniformity threshold can refer to the acceptance standard of temperature uniformity, for example, setting the judgment condition that the temperature difference between any two points on the chip surface does not exceed 8% of the maximum temperature, for automatically terminating the iteration process. The non-uniform configuration scheme can refer to the parameter combination set determined by optimization, for example, the complete parameter package containing the spacing gradient, the finger length proportion, and the resistance coefficient, as the basis for the final layout design.

[0030] As a specific example: in the design process of InGaP / GaAs HBT, first, the initial temperature distribution map of the device under the working frequency of 3 GHz is obtained through the ANSYS Workbench electrical-thermal coupling simulation, and the central region 135℃ high-temperature region and the edge 90℃ low-temperature region are identified. According to this, the first non-uniform configuration scheme is generated: high-temperature region spacing 3.2μm / finger length 9μm / resistance 14Ω, low-temperature region spacing 2.1μm / finger length 16μm / resistance 7Ω. The scheme is input into the simulator for iterative optimization, and the temperature field is recalculated after adjusting the parameters each time. After 4 iterations, when the maximum temperature difference is reduced to 12℃, it meets the preset uniformity threshold (less than 10% of the highest temperature), at this time, the corresponding non-uniform configuration scheme is determined as the final layout parameter.

[0031] Through automatic iterative optimization by the coupled simulation model, the initial temperature distribution is converted into an accurate non-uniform configuration scheme, ensuring that the emitter structure design reaches an optimal balance in electrical and thermal characteristics, significantly improving design accuracy and efficiency.

[0032] In some embodiments, in the iterative optimization process, a final temperature distribution is determined to meet a preset uniformity threshold by a thermal stability comprehensive evaluation function, the calculation formula of the thermal stability comprehensive evaluation function is as follows:

[0033] wherein, is the thermal stability comprehensive evaluation value, the lower the value, the better the thermal stability, the value is calculated by the coupling simulation model based on the simulation output of the current non-uniform configuration scheme; is the total number of multiple emitter fingers; is the average temperature of the i-th emitter finger in the temperature distribution output by the coupling simulation model; is the average value of the average temperature of all emitter fingers; is the temperature distribution sensitivity index; is the total number of resistors in the ballast resistor network; is the resistance value of the j-th ballast resistor, which is derived from the non-uniform resistance value configuration scheme used in the current iteration; is the resistance influence coefficient, which is a preset constant; is the resistance non-linear adjustment factor, which is a preset constant greater than 1; is the resistance value normalization factor, which is a preset reference resistance value; is the total number of selected monitoring points in the heat flow distribution output by the coupling simulation model; is the heat flow density of the k-th monitoring point; is the minimum heat flow density among all monitoring points; is the average heat flow density of all monitoring points; is the heat flow distribution form factor, which is an even preset constant greater than or equal to 2.

[0034] The thermal stability comprehensive evaluation function can refer to a mathematical evaluation model for quantifying the thermal performance of a device, for example, by combining the composite indicators of temperature uniformity, resistance influence, and heat flow distribution through weighted combination, for objective comparison of the thermal stability of different design schemes. The thermal stability comprehensive evaluation value can refer to the specific calculation result of the evaluation function, such as a dimensionless numerical value calculated by substituting simulation data, which directly reflects the thermal stability degree of the design scheme. The total number of emitter fingers can refer to the number of emitter metal strips arranged in parallel in the device, for example, a multi-finger structure HBT usually contains 8-16 fingers, which affects the current distribution and thermal coupling complexity. The average temperature can refer to the average value of the thermal energy of the surface of a single emitter finger, for example, the thermal parameters of the finger strip area are obtained by integrating the temperature of the finite element grid nodes, which reflects the local heating intensity. The average of the average temperature can refer to a centralized trend indicator of the temperature of all emitter fingers, such as the overall thermal load level obtained by taking the arithmetic mean of the temperature of multiple finger areas, which is used as a judgment basis for temperature uniformity. The temperature distribution sensitivity index can refer to an influence factor for adjusting the weight of temperature uniformity, for example, a penalty coefficient that amplifies the temperature deviation by an even power, which is used to enhance the sensitivity of the evaluation function to hot spot phenomena. The total number of resistors in the ballast resistor network can refer to the number of discrete resistor elements integrated in the emitter path, which is usually matched with the number of emitter fingers and each finger corresponds to an independent ballast resistor, achieving precise current regulation. The resistance influence coefficient can refer to a regulation parameter for balancing resistance power consumption and thermal stability, for example, a weight coefficient determined by experimental data fitting, which is used to coordinate the contradiction between resistance heating and current sharing effect. The resistance nonlinearity adjustment factor can refer to an amplification index representing the degree of resistance influence, for example, a power greater than 1 is used to enhance the penalty of large resistance, preventing excessive dependence on resistance current sharing. The resistance value normalization factor can refer to a reference benchmark for dimensionless resistance value, for example, selecting a typical ballast resistance value of 10 ohms as the standardization base, eliminating the influence of dimension on the evaluation function. The selected monitoring points in the heat flow distribution can refer to a set of spatial positions for sampling heat flux, for example, 50 heat flux detection points evenly distributed on the chip surface according to the grid, which fully captures the characteristics of heat energy transmission. The heat flux density can refer to the heat energy transmission rate per unit area, for example, the magnitude of the heat flux vector at a specific location inside the semiconductor device obtained by simulation, which reflects the local heat dissipation intensity. The minimum heat flux density can refer to the minimum value of the heat flux in the monitoring point set, for example, the heat flux value of less than 1e5 W / m^2 in the poor heat dissipation area, which identifies the potential risk area of heat accumulation. The average heat flux density can refer to the statistical average of the heat flux of all monitoring points, for example, a centralized trend indicator of the overall heat dissipation level of the chip, which is used as a judgment basis for heat flow distribution uniformity. The heat flow distribution form factor can refer to a shape parameter for adjusting the weight of heat flow uniformity, for example, a regulation coefficient that amplifies the local heat dissipation difference by a high power, which is used to enhance the identification ability of uneven heat dissipation.

[0035] As a specific example: in the evaluation of an 8-finger InGaP / GaAs HBT design, the temperature of each finger is obtained by COMSOL simulation, respectively 128K, 131K, 135K, 142K, 138K, 133K, 129K, 126K, and the average temperature is 133K. The temperature distribution sensitivity index is set to 4, the resistance influence coefficient is 0.3, the nonlinear adjustment factor is 2, and the normalized resistance is 10Ω. The heat flux density of 36 monitoring points is collected, the minimum heat flux is 8e4 W / m^2, the average heat flux is 1.2e5 W / m^2, and the form factor is 4. The comprehensive evaluation value calculated by substituting the evaluation function is 0.15, which is significantly lower than the initial design of 0.28, proving that the thermal stability has been effectively improved.

[0036] By establishing a multi-parameter evaluation function that comprehensively considers temperature distribution, resistance influence and heat flow form, a quantitative evaluation standard is provided for the optimization process, ensuring that the design scheme achieves the best balance among various indicators of thermal stability, and significantly improving the thermal reliability of the device.

[0037] In some embodiments, the value of the temperature distribution sensitivity index is determined by a dynamic adjustment process, and the corresponding calculation formula is as follows:

[0038] wherein, is the basic sensitivity constant, which is a preset initial value; M is the number of temperature gradient regions divided in the initial temperature distribution map; is the maximum temperature difference in the mth temperature gradient region; is the temperature difference normalization factor, which is a preset reference temperature difference value; is the gradient weight index, which is a preset constant greater than 1; is the geometric mean adjustment coefficient, which is a preset constant greater than 1; is the calculation stability constant, which is a small preset constant greater than zero; is the calculation stability constant, which is a small preset constant greater than zero.

[0039] The dynamic adjustment process can refer to an automatic adjustment method of the index according to real-time parameters, such as an adaptive algorithm that updates the sensitive index in real time through temperature difference data feedback, for enhancing the response capability of the evaluation model to thermal distribution changes. The value of the temperature distribution sensitive index can refer to the specific numerical value of the weight coefficient of the temperature term in the evaluation function, such as a variable parameter between 2-6 obtained by dynamic calculation, which directly affects the proportion of temperature uniformity in the evaluation. The basic sensitivity constant can refer to the benchmark parameter in the calculation of the sensitive index, such as the initial weight value set to 2.0, which provides a basic offset for the sensitive index. The number of temperature gradient regions can refer to the number of blocks divided according to the temperature change rate, such as dividing the chip surface into 5 characteristic regions according to the temperature change slope, for fine calculation of the temperature distribution characteristics. The maximum temperature difference in the temperature gradient region can refer to the difference between the highest and lowest temperatures in a single gradient zone, such as a temperature fluctuation range of 35K in a certain gradient zone, reflecting the severity of the thermal distribution in that region. The temperature difference normalization factor can refer to a reference value for temperature difference normalization, such as selecting a typical temperature difference of 20K as the normalization benchmark to eliminate the influence of dimensions on the calculation. The gradient weight index can refer to an amplification parameter that adjusts the influence degree of each gradient zone, such as using a power of 3.0 to enhance the contribution of large temperature difference regions and highlight the role of hot spot regions. The geometric mean adjustment coefficient can refer to a regulation parameter that balances the sensitivity of geometric mean calculation to abnormal values, such as taking the root of 1.5 to control the sensitivity of geometric mean to abnormal values. The calculation stability constant can refer to a small offset that prevents mathematical calculation abnormalities, such as adding a very small positive value of 1e-10 to avoid division by zero errors and logarithmic calculation overflow.

[0040] As a specific example: when optimizing a certain 10-finger HBT, the chip temperature field is divided into 8 gradient regions, and the maximum temperature differences of each region are measured as 12K, 18K, 25K, 32K, 15K, 22K, 28K, and 13K, respectively. The basic sensitivity constant is set to 2.0, the temperature difference normalization factor is set to 20K, the gradient weight index is set to 2.5, the geometric mean adjustment coefficient is set to 1.8, and the calculation stability constant is set to 1e-8. The real-time temperature distribution sensitive index calculated by the dynamic adjustment formula is 4.3, which automatically adjusts with the thermal distribution changes, and can more accurately reflect the actual thermal stability requirements compared to a fixed index.

[0041] By establishing a dynamic adjustment mechanism based on temperature gradient characteristics, the temperature distribution sensitive index can adapt to the thermal field change characteristics, enhance the response accuracy of the evaluation function to the thermal distribution characteristics under actual working conditions, and improve the accuracy and adaptability of the optimization design.

[0042] In some embodiments, the foregoing method further comprises: based on the thermal stability comprehensive evaluation value, generating a device reliability level identifier, wherein the device reliability level identifier L is determined by the following calculation formula:

[0043] wherein L is a device reliability level identifier, being a positive integer; is an evaluation value reference benchmark, being a pre-set constant; is a level division adjustment factor, being a pre-set constant greater than zero is a floor function.

[0044] The device reliability level identifier can refer to a classification mark representing the thermal reliability level of the device, such as a 1-5 classification code obtained by calculating the thermal stability evaluation value and taking the floor, which is used to quickly identify the reliability level of the device. The thermal stability comprehensive evaluation value can refer to a mathematical evaluation result quantifying the thermal performance of the device, such as a specific numerical value of 0.12 obtained by calculating a multi-parameter evaluation function, which directly reflects the thermal stability level. The evaluation value reference benchmark can refer to a comparison standard value for level division, such as a reference threshold of 0.25 set according to historical data, which is used as the baseline for level calculation. The level division adjustment factor can refer to a parameter for fine-tuning the sensitivity of level division, such as a decimal offset of 0.01, which is used to avoid level jumps at boundary values. The floor function can refer to a mathematical operation that takes the maximum integer not greater than the original value, such as the rounding operation that converts the calculated value 3.7 to 3, ensuring that the level identifier is an integer.

[0045] As a specific example: when evaluating an InGaP / GaAs HBT device, the current evaluation value is calculated by the thermal stability comprehensive evaluation function to be 0.18. Set the evaluation value reference benchmark to 0.25 and the level division adjustment factor to 0.02. Substituting into the calculation formula floor(0.25 / (0.18+0.02)) gives a calculation result of 1.25, and after taking the floor, the device reliability level identifier is determined to be level 1, representing that the design has excellent thermal reliability.

[0046] By converting the continuous thermal stability evaluation value into discrete reliability level identifiers, an intuitive quality grading standard is provided for device design and screening, facilitating quick evaluation and comparison of the thermal reliability level of different design schemes.

[0047] In some embodiments, the coupled simulation model is an electro-thermal-mechanical multi-physical field coupled model.

[0048] The electro-thermal-mechanical multi-physical field coupled model can refer to a simulation system that simultaneously solves electrical, thermal, and mechanical equations, such as a coupled solver established through the ANSYS Multiphysics or COMSOL platform, which is used to accurately simulate the interaction of potential distribution, temperature field, and stress field of the device under working conditions.

[0049] As a specific example: in InGaP / GaAs heterojunction bipolar transistor design, a multi-physics coupling model of electro-thermal-mechanical is established by ANSYS Workbench platform. In the electrical module, carrier transport equation is set to calculate the current density distribution; in the thermal module, heat conduction equation is solved to obtain the temperature field; in the mechanical module, thermal elastic equation is solved to analyze the stress distribution caused by thermal expansion. The three physical fields are coupled with each other through material parameters: current density affects heat generation power, temperature change affects carrier mobility and material resistivity, and thermal stress in turn changes the band structure and thermal conductivity of the material. Through this full coupling simulation, the thermal mechanical reliability of the device under 5V working voltage can be accurately predicted, and the maximum stress is identified to be concentrated in the emitter edge region, providing accurate basis for structure optimization.

[0050] By using the electro-thermal-mechanical multi-physics coupling model, the interaction between electrical heating, heat conduction and thermal stress can be considered comprehensively, and the thermal mechanical behavior of the device under actual working conditions can be more accurately predicted, providing a more perfect simulation basis for reliability design.

[0051] In some embodiments, the material parameters used by the electro-thermal-mechanical multi-physics coupling model include the interface defect density of indium gallium phosphide at the heterojunction formed by the indium gallium phosphide emitter region and the gallium arsenide collector region.

[0052] The material parameters used by the electro-thermal-mechanical multi-physics coupling model can refer to a set of numerical values of physical properties defined in the simulation model, for example, including thermal conductivity, Young's modulus, Poisson's ratio, and other constitutive parameters, which are used to accurately describe the behavior characteristics of the material in the multi-physics field. The interface defect density of indium gallium phosphide at the heterojunction formed by the indium gallium phosphide emitter region and the gallium arsenide collector region can refer to the lattice mismatch defect concentration at the interface of InGaP and adjacent semiconductor layers, for example, the surface defect density of the order of 10^12 cm^{-2} obtained by deep level transient spectrum measurement, which seriously affects the carrier transport and heat generation.

[0053] As a specific example: when building the electro-thermal-mechanical multi-physical field coupling model of InGaP / GaAs HBT, in addition to defining the conventional material parameters such as the thermal conductivity of GaAs (44 W / m·K) and the thermal expansion coefficient of InGaP (5.6×10^{-6} / K), the interface defect density of indium gallium phosphide at the heterojunction formed by the indium gallium phosphide emitter region and the gallium arsenide collector region is particularly input as a key parameter. The actual interface defect density of 3×10^{12} cm^{-2} is obtained through X-ray diffraction and transmission electron microscopy characterization, which directly affects the calculation of the recombination current, the estimation of the interface thermal resistance, and the prediction of the stress distribution of the model. After setting this parameter in the ANSYS simulation, the model can more accurately simulate the non-ideal recombination heating and thermal resistance increase at the interface, and the agreement between the simulation results and the measured temperature distribution is improved by about 18%.

[0054] By including the key material parameter of the interface defect density of the indium gallium phosphide heterojunction in the multi-physical field coupling model, the non-ideal electro-thermal behavior at the interface can be more accurately simulated, and the agreement between the simulation results and the actual device performance is significantly improved, providing a more accurate prediction basis for reliability design.

[0055] In some embodiments, according to the determined layout of the emitter contact structure, the step of forming the emitter contact structure on the indium gallium phosphide emitter region includes: using photolithography and etching processes to form a plurality of emitter fingers with non-uniform spacing and non-uniform finger length on the indium gallium phosphide emitter region; and forming a ballast resistor network with non-uniform resistance values through a thin film process and connecting the ballast resistor network with the plurality of emitter fingers.

[0056] The determined layout of the emitter contact structure can refer to the final design scheme determined after optimization iteration, such as a complete parameter set containing non-uniform spacing, non-uniform finger length, and non-uniform resistance value configuration, which serves as a direct basis for process implementation. The indium gallium phosphide emitter region can refer to the surface layer region of the indium gallium phosphide semiconductor material, such as the In_{0.49}Ga_{0.51}P compound semiconductor surface layer formed by epitaxial growth, which serves as the basis for forming ohmic contact. The plurality of emitter fingers with non-uniform spacing and non-uniform finger length can refer to a finger electrode array with optimized design in size and arrangement, such as a Ti / Pt / Au metal electrode system with gradient spacing and variable finger length design, which realizes adaptive distribution of current density. The thin film process can refer to a manufacturing technology for depositing functional layers on the surface of a substrate, such as a process method for forming a tantalum nitride resistor thin film on a wafer through sputtering or evaporation, which is used to prepare a ballast resistor element. The ballast resistor network with non-uniform resistance values can refer to a resistance array with resistance values set according to an optimization scheme, such as a TaN thin film resistor network with gradient resistance value distribution achieved by laser tuning, which provides differentiated current regulation function.

[0057] As a specific example: in the implementation of the optimized layout scheme, first spin-coat photoresist on the surface of the indium gallium phosphide emitter region, using i-line photolithography machine exposure non-uniform spacing and finger length pattern, through reactive ion etching to form the emitter finger window. Subsequently, electron beam evaporation Ti / Pt / Au metal layer, stripping after forming a gradient spacing and variable finger length of the emitter finger array. Then using magnetron sputtering deposition of 100 nm of tantalum nitride film, through the second lithography and ion etching to form a non-uniform resistance ballast resistor network, finally through the third lithography and aluminum metallization process to achieve the emitter finger and ballast resistor interconnection, complete the preparation of the entire emitter contact structure.

[0058] By converting the optimized non-uniform layout scheme into specific process implementation steps, using a combination of lithography, etching and thin film process, the gradient spacing, variable finger length and differential resistance of the emitter contact structure are accurately realized, ensuring that the design optimization effect is accurately reflected in the actual device.

[0059] In some embodiments, in the step of providing a device wafer, the indium gallium phosphide emitter region is formed by a metal organic chemical vapor deposition process.

[0060] Metal organic chemical vapor deposition process can refer to a crystal growth technology of Metalorganic Chemical Vapor Deposition (MOCVD), such as an advanced process of growing a single crystal thin film of indium gallium phosphide by vapor phase epitaxy in a high temperature reaction chamber using trimethylgallium, trimethylindium and phosphine as precursors.

[0061] As a specific example: in the step of providing a device wafer, first prepare a semi-insulating GaAs substrate, and then use a metal organic chemical vapor deposition process to epitaxially grow a 300 nm thick In_{0.49}Ga_{0.51}P emitter region on a gallium arsenide collection region at 650°C and 100mbar reaction chamber pressure, using trimethylgallium, trimethylindium and phosphine as precursors. By accurately controlling the V / III ratio to about 200 and the growth rate to 1.5μm / h, an indium gallium phosphide emitter region with good crystal quality and accurate composition is obtained, providing an ideal semiconductor surface for the subsequent preparation of the emitter contact structure.

[0062] By using a metal organic chemical vapor deposition process to prepare the indium gallium phosphide emitter region, the material composition, thickness and crystal quality can be accurately controlled, providing an emitter structure with excellent electron injection characteristics for the heterojunction bipolar transistor, ensuring that the device has high current gain and good thermal stability.

[0063] In some embodiments, the predetermined operating state is the rated maximum continuous wave operating state of the heterojunction bipolar transistor.

[0064] The maximum continuous wave rated operating condition of a heterojunction bipolar transistor can refer to the maximum safe operating condition allowed by the device in a continuous mode of operation, such as the maximum combination of collector current, collector-emitter voltage and junction temperature specified in the product manual, representing the most severe thermal loading condition.

[0065] As a specific example: in the optimization of a certain X-band InGaP / GaAs heterojunction bipolar transistor, the preset operating condition is set as the maximum continuous wave rated operating condition, with specific parameters of collector-emitter voltage 5.5V, collector current density 1.2x104A / cm2, base-emitter voltage 1.3V, and ambient temperature 85℃. Under this extreme operating condition, the steady-state temperature distribution of the device is obtained through thermal simulation, and a hot spot region with a maximum temperature of 155℃ in the center region is identified, based on which the non-uniform emitter structure is optimized and designed to ensure that the device can still operate reliably at maximum power output.

[0066] By setting the preset operating condition as the maximum continuous wave rated operating condition, the most severe condition, the optimized non-uniform emitter structure can effectively suppress the hot spot effect at maximum power output of the device, ensuring the reliability and service life of the product under extreme operating conditions.

[0067] The preferred embodiments of the present specification disclosed above are only used to help explain the present specification. Alternative embodiments do not describe all the details and do not limit the invention to only the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the present invention. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present specification. The present specification is limited only by the claims and their full scope and equivalents.

Claims

1. A method of optimizing a non-uniform emitter structure, comprising: Comprise: A device wafer is provided, which comprises a substrate, a gallium arsenide collector region, and a gallium indium phosphide emitter region in sequence; Based on the preset thermal distribution characteristics of the heterojunction bipolar transistor in the preset working state, the layout of the emitter contact structure is determined; the layout includes the pitch of the plurality of emitter fingers, the length of the plurality of emitter fingers, and the resistance value of each ballast resistor in the ballast resistor network connecting the plurality of emitter fingers; Wherein, the step of determining the layout includes: configuring the pitch of the plurality of emitter fingers as non-uniform, so that the pitch of the emitter fingers in the high-temperature region identified in the thermal distribution characteristics is greater than the pitch of the emitter fingers in the low-temperature region identified in the thermal distribution characteristics; The length of the plurality of emitter fingers is configured to be non-uniform, so that the length of the emitter fingers in the high-temperature region is shorter than the length of the emitter fingers in the low-temperature region; The resistance value of each ballast resistor in the ballast resistor network is configured to be non-uniform, so that the resistance value of the ballast resistor corresponding to the high-temperature region is greater than the resistance value of the ballast resistor corresponding to the low-temperature region; According to the determined layout of the emitter contact structure, the emitter contact structure is formed on the gallium indium phosphide emitter region.

2. The method of claim 1, wherein, Based on the thermal distribution characteristics of the heterojunction bipolar transistor in the preset working state, the step of determining the layout of the emitter contact structure, specifically includes: An initial temperature distribution map of the heterojunction bipolar transistor in the preset working state is obtained through a coupled simulation model; Based on the initial temperature distribution map, the high-temperature region and the low-temperature region are identified; According to the distribution of the high-temperature region and the low-temperature region, a first non-uniform pitch configuration scheme, a first non-uniform finger length configuration scheme and a first non-uniform resistance value configuration scheme are generated; The first non-uniform pitch configuration scheme, the first non-uniform finger length configuration scheme and the first non-uniform resistance value configuration scheme are input into the coupled simulation model for iterative optimization until the final temperature distribution map output meets the preset uniformity threshold; When the preset uniformity threshold is met, the corresponding non-uniform configuration scheme is determined as the final layout.

3. The method of claim 2, wherein, In the iterative optimization process, whether the final temperature distribution map meets the preset uniformity threshold is determined by a thermal stability comprehensive evaluation function, and the calculation formula of the thermal stability comprehensive evaluation function is as follows: wherein, is a thermal stability comprehensive evaluation value, The lower the value, the better the thermal stability, The value is calculated by the coupling simulation model based on the simulation output of the current non-uniform configuration scheme; is the total number of the plurality of emitter fingers; is the average temperature of the i-th emitter finger in the temperature distribution output by the coupling simulation model; is the average value of the average temperatures of all the emitter fingers; is a temperature distribution sensitivity index; is the total number of resistors in the ballast resistor network; is the resistance value of the j-th ballast resistor, derived from the non-uniform resistance value configuration scheme used in the current iteration; is a resistance influence coefficient, which is a preset constant; is a resistance non-linear adjustment factor, which is a preset constant greater than 1; is a resistance value normalization factor, which is a preset reference resistance value; is the total number of selected monitoring points in the heat flow distribution output by the coupling simulation model; is the heat flux density of the k-th monitoring point; is the minimum heat flux density among all the monitoring points; is the average heat flux density of all the monitoring points; is a heat flow distribution form factor, which is an even preset constant greater than or equal to 2.

4. The method of claim 3, wherein, The value of the temperature distribution sensitivity index is determined through a dynamic adjustment process, and the corresponding calculation formula is as follows: wherein, is a base sensitivity constant, which is a preset initial value; M is the number of temperature gradient regions divided in the initial temperature distribution map; is the maximum temperature difference in the mth temperature gradient region; is a temperature difference normalization factor, which is a preset reference temperature difference value; is a gradient weight index, which is a preset constant greater than 1; is a geometric mean adjustment coefficient, which is a preset constant greater than 1; is a calculation stability constant, which is a preset minimum constant greater than zero; is a calculation stability constant, which is a preset minimum constant greater than zero.

5. The method of claim 3, wherein, Also include: Based on the thermal stability comprehensive evaluation value, a device reliability level identifier is generated, and the device reliability level identifier L is determined by the following calculation formula: Wherein, L is a device reliability level identifier, being a positive integer; is an evaluation value reference benchmark, being a preset constant; is a level division adjustment factor, being a preset constant greater than zero is a floor function.

6. The method of claim 2, wherein, The coupled simulation model is an electro-thermal-mechanical multi-physical field coupled model.

7. The method of claim 6, wherein, The material parameters used by the electro-thermal-mechanical multi-physical field coupled model include the interface defect density of gallium indium phosphide at the heterojunction formed by the gallium indium phosphide emitter region and the gallium arsenide collector region.

8. The method of claim 1, wherein, The step of forming the emitter contact structure on the gallium indium phosphide emitter region according to the determined layout of the emitter contact structure includes: The plurality of emitter fingers with non-uniform spacing and non-uniform finger length are formed on the indium gallium phosphide emitting region by using a lithography and etching process; The ballast resistor network with non-uniform resistance is formed by a thin film process, and the ballast resistor network is connected with the plurality of emitter fingers.

9. The method of claim 1, wherein, In the step of providing a device wafer, the indium gallium phosphide emitting region is formed by a metal organic chemical vapor deposition process.

10. The method of claim 1, wherein, The preset working state is a rated maximum continuous wave working state of the heterojunction bipolar transistor.

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