Step voltage recognition for multiple inputs

Abstract

Methods for determining fuse states are provided herein. In some embodiments, a system may include: a first fuse electrically connected to a first node and a first resistor; and a second fuse electrically connected to a second node and a second resistor, wherein the first fuse and the second fuse are connected in parallel to the same port of a multiplexer. The system may also include: a controller communicatively coupled to the multiplexer, the controller being operable to read voltage levels at the first node and the second node.

Description

Technical Field

[0001] The present disclosure relates generally to fuses, and more particularly to systems, circuits, and methods for determining fuse status. Background Art

[0002] Today's modern vehicles require an increasing number of control modules to monitor voltage levels. One existing design uses a single digital input port to detect the voltage at a single node. Consequently, the increasing number of ports requires the use of one or more multiplexers, leading to increasingly difficult layouts and increased costs. Summary of the Invention

[0003] In view of the foregoing, systems, circuits, and methods for determining fuse states are described herein. In one aspect, a system may include: a first fuse electrically connected to a first node and a first resistor; and a second fuse electrically connected to a second node and a second resistor, wherein the first fuse and the second fuse are connected in parallel to the same port of a multiplexer. The system may also include: a controller communicatively coupled to the multiplexer, the controller being operable to read the voltage levels of the first node and the second node.

[0004] In another aspect, a circuit may include: a first fuse electrically connected between a first node and a first resistor; and a second fuse electrically connected between a second node and a second resistor, wherein the first fuse and the second fuse are connected in parallel to the same port of a multiplexer, and wherein the multiplexer is communicatively connected to a controller that is operable to read the voltage levels of the first node and the second node.

[0005] In yet another aspect, a method for determining a fuse state may include electrically connecting a first fuse between a first node and a first resistor, and electrically connecting a second fuse between a second node and a second resistor, wherein the first fuse and the second fuse are connected in parallel to the same port of a multiplexer. The method may also include electrically connecting a controller to the multiplexer, and reading, by the controller, the voltage levels of the first node and the second node. The method may also include determining whether the first fuse or the second fuse is open by comparing the voltage levels of the first node and the second node with a predetermined voltage level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram including a system / circuit for determining a fuse state according to an exemplary embodiment.

[0007] Figure 2 is a schematic diagram including a system / circuit for determining a fuse state according to an exemplary embodiment.

[0008] Figure 3 is a method for determining a fuse state according to an exemplary embodiment.

[0009] The accompanying drawings are not necessarily to scale. The accompanying drawings are merely representations and are not intended to depict specific parameters of the present disclosure. The accompanying drawings are intended to depict typical embodiments of the present disclosure and should not be considered to limit the scope. In the accompanying drawings, like reference numerals represent like elements.

[0010] In addition, for the sake of clarity, some elements in some drawings may be omitted or not shown in scale. In addition, for the sake of clarity, some figure numerals may be omitted in some drawings. DETAILED DESCRIPTION

[0011] Embodiments according to the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. The systems / circuits and methods may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the systems and methods to those skilled in the art.

[0012] As mentioned above, the current existing voltage monitoring method uses a digital input port to detect the voltage of a single node. A multiplexer can be added, which is a simple way to expand the I / O ports of the control unit, but the multiplexer cannot reduce the number of I / Os used for the COM port to the control unit. In addition, one multiplexer can monitor no more than eight nodes. Therefore, the current technology system may require 6-8 multiplexers for a single control module. However, too many multiplexers require too much printed circuit board (PCB) space, which makes the design difficult and expensive.

[0013] The embodiments herein advantageously use a single port to provide step voltage identification to monitor multiple nodes (eg, three nodes). This approach can effectively identify the status of each node, thereby reducing multiplexer cost and saving PCB space.

[0014] Now refer to Figure 1, a schematic diagram of a circuit / system (hereinafter referred to as "system") 100 according to an embodiment of the present disclosure will be described. In an exemplary embodiment, the system 100 may include: a first fuse 102 connected between a first node 104 and a first diode 106. A first resistor 110 is connected in series with the first fuse 102 and the first diode 106. In some embodiments, the resistance value of the first resistor 110 is 33K. The system 100 may also include: a second fuse 112 connected between a second node 114 and a second diode 116. A second resistor 118 is connected in series with the second fuse 112 and the second diode 116. In some embodiments, the resistance value of the first resistor 110 is 33K. The system 100 may also include: a second fuse 112 connected between a second node 114 and a second diode 116. A second resistor 118 is connected in series with the second fuse 112 and the second diode 116. In one embodiment, the resistance value of the second resistor 118 is 47K. The system 100 may further include: a third fuse 120 connected between the third node 122 and the third diode 124. A third resistor 126 is connected in series with the third fuse 120 and the third diode 122. In some embodiments, the resistance value of the third resistor 126 is 68K. As shown, the first resistor 110, the second resistor 118, and the third resistor 126 are electrically connected in parallel to the same port (AO) 130 of the multiplexer 132. Similarly, the first diode 106, the second diode 116, and the third diode 124 are electrically connected in parallel.

[0015] The multiplexer 132 may receive a status signal 134 indicating the status of each of the first fuse 102, the second fuse 112, and the third fuse 120. As further shown, the multiplexer 132 may be connected to a processor or controller 138, with a fourth resistor 140 connected between the multiplexer 132 and the controller 138. Although not limiting, the resistance value of the fourth resistor 140 may be 10K.

[0016] The controller 138 may include processing circuitry for storing and processing information, including a microprocessor and memory. It will be appreciated that the processing circuitry may include additional components, including processors, memories, error and parity / CRC checkers, data encoders, anti-collision algorithms, controllers, command decoders, security primitives, and anti-tampering hardware, as necessary to perform the functions described herein.

[0017] During use, the controller 138 is operable to read the voltage levels of the first node 104, the second node 114, and the third node 122. In some embodiments, the controller 138 is also operable to determine an AD value, i.e., a value obtained by converting the analog value of the node voltage into a digital value. Advantageously, the controller 138 can monitor all three nodes simultaneously using a single port 130 of the multiplexer 132. Although not specifically shown, the controller 138 can monitor a total of twenty-four (24) nodes because there are eight (8) ports (e.g., A0-A7) on the multiplexer 132.

[0018] In one example, the controller 138 can identify whether any of the first, second, or third fuses is disconnected. By setting the resistance value (e.g., setting R1 / R2 / R3 to 33K / 47K / 68K), if any fuse is disconnected, the total resistance at the same port 130 will be different, and the controller 138 will obtain a voltage and / or AD value different from the predetermined or expected value. Therefore, the system 100 can find which node or nodes are disconnected. Although non-limiting, the resistance value (e.g., 33K / 47K / 68K) can also be the optimal value, causing the system 100 to have more redundancy for component tolerances and voltage fluctuations. For example, the system 100 can tolerate +1-3.4% for a given component (e.g., a 33K / 47K / 68K resistor). Due to the + / - 1% component tolerance, the system can also tolerate +1-6% voltage fluctuations. In some embodiments, when the component is a diode, the main tolerance may be the forward voltage drop (Vf) of the diode. When the component is a resistor, the primary tolerance might be the resistance. When the component is a multiplexer, the primary tolerance is the channel on-resistance (Ron) when the channel is turned on. When the component is a controller, the primary tolerance is the reference voltage used for A / D conversion.

[0019] Now refer to Figure 2 , a schematic diagram of a circuit / system (hereinafter referred to as "system") 200 according to an embodiment of the present disclosure will be described. In an exemplary embodiment, the system 200 may include: a first fuse 202 connected between a first node 204 and a first resistor 210. In some embodiments, the resistance value of the first resistor 210 is 33K. The system 200 may also include: a second fuse 212 connected between a second node 214 and a second resistor 218. In some embodiments, the resistance value of the second resistor 218 is 47K. The system 200 may also include: a third fuse 220 connected between a third node 222 and a third resistor 226. In some embodiments, the resistance value of the third resistor 226 is 68K. As shown in the figure, the first resistor 210, the second resistor 218, and the third resistor 226 are electrically connected in parallel to the same port (AO) 230 of the multiplexer 232.

[0020] The system 200 may further include a first opto-isolator 240 electrically connected to the first resistor 210, a second opto-isolator 242 electrically connected to the second resistor 218, and a third opto-isolator 244 electrically connected to the third resistor 226. The system 200 may further include a first control and protection circuit 250 (e.g., a MOSFET and a transient voltage suppressor) connected to the first opto-isolator 240, a second control and protection circuit 252 connected to the second opto-isolator 242, and a third control and protection circuit 256 connected to the third opto-isolator 244.

[0021] As further shown, a fifth resistor 260 may be positioned between the first fuse 202 and the first optoisolator 240 to protect the diode of the first optoisolator 240, a sixth resistor 262 may be positioned between the second fuse 212 and the second optoisolator 242 to protect the diode of the second optoisolator 242, and a seventh resistor 264 may be positioned between the third fuse 220 and the third optoisolator 244 to protect the diode of the third optoisolator 244. A fourth resistor 266 may be positioned between the multiplexer 232 and the controller 238.

[0022] During exemplary operation of the system 200, if the first fuse 202, the second fuse 212, and the third fuse 220 are all normal / closed, the first resistor 210, the second resistor 218, and the third resistor 226 are connected in parallel with VCC, and the equivalent resistance is minimal. The equivalent resistance is connected in series with the fourth resistor 266 and provides a portion of the analog voltage to the port 230.

[0023] If one or more fuses are open, the associated resistor will be disconnected from port 230, so the equivalent resistance will be greater and the divided voltage on port 230 will be lower. When different fuses are open, different divided voltages are provided to port 230. Controller 238 can then identify which fuse is open based on the divided voltage at port 230.

[0024] Now go to Figure 3 , a method 300 for determining a fuse state according to an exemplary embodiment will be described in more detail. As shown, at block 301, method 300 may include electrically connecting a first fuse between a first node and a first resistor. At block 303, method 300 may include electrically connecting a second fuse between a second node and a second resistor, wherein the first fuse and the second fuse are connected in parallel to the same port of a multiplexer. In some embodiments, method 300 may include electrically connecting a third fuse between a third node and a third resistor, wherein the third fuse is connected in parallel with the first fuse and the second fuse, and wherein the third fuse is electrically connected to the same port of the multiplexer.

[0025] At block 305, method 300 may include electrically connecting a controller to the multiplexer. At block 307, method 300 may include reading, by the controller, a voltage level at a first node and a second node. At block 309, method 300 may include determining whether the first fuse or the second fuse is blown by comparing the voltage levels at the first node and the second node with a predetermined voltage level. In some embodiments, method 300 may include reading, by the controller, a voltage level at a third node and determining whether the first fuse, the second fuse, or the third fuse is blown by comparing the voltage levels at the first, second, and third nodes with a predetermined voltage level. In some embodiments, the first resistor, the second resistor, and the third resistor each have a different resistance value.

[0026] In some embodiments, method 300 may include electrically connecting a first diode between a first fuse and a first resistor, electrically connecting a second diode between a second fuse and a second resistor, and electrically connecting a third diode between a third fuse and a third resistor, wherein the first diode, the second diode, and the third diode are electrically connected in parallel.

[0027] In some embodiments, method 300 may further include electrically connecting the first opto-isolator to the first resistor, electrically connecting the second opto-isolator to the second resistor, and electrically connecting the third opto-isolator to the third resistor. In some embodiments, method 300 may further include electrically connecting a fifth resistor between the first opto-isolator and the first fuse, electrically connecting a sixth resistor between the second opto-isolator and the second fuse, and electrically connecting a seventh resistor between the third opto-isolator and the third fuse.

[0028] Although the illustrative method 300 is described above as a series of actions or events, the present disclosure is not limited to the illustrated order of these actions or events unless otherwise stated. For example, according to the present disclosure, some actions may occur in a different order and / or other actions or events other than those illustrated and / or described herein may occur simultaneously. In addition, not all illustrated actions or events may be required according to the method of the present disclosure.

[0029] As used herein, an element or step recited in the singular and preceded by the word "a" or "an" should be understood as not excluding plural elements or steps, unless such exclusion is explicitly stated. Furthermore, reference to "one embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0030] The use of "including," "comprising," or "having" and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Thus, the terms "including," "comprising," or "having" and variations thereof are open-ended expressions and can be used interchangeably herein.

[0031] As used herein, the phrases "at least one," "one or more," and "and / or" are open-ended expressions and function as both conjunctions and transitional conjunctions. For example, the expressions "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," and "A, B, and / or C" mean A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0032] All directional references (e.g., proximal, distal, up, down, upward, downward, left, right, lateral, longitudinal, front, back, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are used for identification purposes only to assist the reader's understanding of the present disclosure. Directional references do not impose limitations, particularly with respect to the position, orientation, or use of the present disclosure. Unless otherwise indicated, connection references (e.g., attachment, coupling, connection, and engagement) should be interpreted broadly and may include intermediate members between sets of elements and relative motion between elements. As such, connection references do not necessarily infer that two elements are directly connected and in a fixed relationship to each other.

[0033] Furthermore, identifying references (e.g., primary, secondary, first, second, third, fourth, etc.) is not intended to denote importance or priority, but rather is used to distinguish one feature from another. The drawings are for illustration purposes only, and the size, position, order, and relative sizes reflected in the drawings attached hereto may vary.

[0034] In addition, the terms "substantially" or "approximately" and the terms "approximately" or "approximately" can be used interchangeably in some embodiments and can be described using any relative measure acceptable to one of ordinary skill in the art. For example, these terms can be used as a comparison with a reference parameter to indicate a deviation from the ability to provide the intended function. Although not limiting, the deviation from the reference parameter can be, for example, less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, etc.

[0035] The foregoing description of example embodiments has been presented for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the present disclosure. It is intended that the scope of the present disclosure be limited not by the detailed description, but rather by the appended claims. Future applications claiming priority from the present application may claim the disclosed subject matter in various ways and may generally include any combination of one or more limitations as variously disclosed or otherwise presented herein.

Claims

1. A system for determining a state of a fuse, comprising: a first fuse electrically connected in series between the first node and the first resistor; a second fuse electrically connected in series between a second node and a second resistor, wherein the first fuse and the second fuse are connected in parallel to a same port of a multiplexer, and wherein the first resistor is positioned between the first fuse and the multiplexer; as well as A controller is communicatively coupled to the multiplexer, the controller being operable to read the voltage levels of the first node and the second node.

2. The system of claim 1 , further comprising a third fuse electrically connected to a third node and a third resistor, wherein the third fuse is connected in parallel with the first fuse and the second fuse, and wherein the third fuse is electrically connected to the same port of the multiplexer.

3. The system according to claim 2, wherein: The controller is operable to read a voltage level of the third node.

4. The system according to claim 2, further comprising: a first diode connected between the first fuse and the first resistor; a second diode connected between the second fuse and the second resistor; as well as A third diode is connected between the third fuse and the third resistor, wherein the first diode, the second diode, and the third diode are electrically connected in parallel. 5 . The system of claim 2 , further comprising a first opto-isolator electrically connected to the first resistor, a second opto-isolator electrically connected to the second resistor, and a third opto-isolator electrically connected to the third resistor.

6. The system of claim 5, further comprising a first control and protection circuit connected to the first optical isolator, a second control and protection circuit connected to the second optical isolator, and a third control and protection circuit connected to the third optical isolator.

7. The system of claim 5, further comprising a fifth resistor between the first optoisolator and the first fuse, a sixth resistor between the second optoisolator and the second fuse, and a seventh resistor between the third optoisolator and the third fuse.

8. The system according to claim 2, wherein: The first resistor, the second resistor, and the third resistor each have a different resistance value.

9. A circuit for determining a state of a fuse, comprising: a first fuse electrically connected in series between the first node and the first resistor; and a second fuse electrically connected in series between a second node and a second resistor, wherein the first fuse and the second fuse are connected in parallel to a same port of a multiplexer, wherein the first resistor is positioned between the first fuse and the multiplexer, and wherein the multiplexer is communicatively connected to a controller operable to read the voltage levels of the first node and the second node.

10. The circuit of claim 9, further comprising a third fuse electrically connected between a third node and a third resistor, wherein the third fuse is connected in parallel with the first fuse and the second fuse, and wherein the third fuse is electrically connected to the same port of the multiplexer.

11. The circuit of claim 10 , further comprising: a first diode connected between the first fuse and the first resistor; a second diode connected between the second fuse and the second resistor; as well as A third diode is connected between the third fuse and the third resistor, wherein the first diode, the second diode, and the third diode are electrically connected in parallel.

12. The circuit of claim 10, further comprising a first opto-isolator electrically connected to the first resistor, a second opto-isolator electrically connected to the second resistor, and a third opto-isolator electrically connected to the third resistor.

13. The circuit of claim 12, further comprising a fourth resistor between the controller and the multiplexer.

14. The circuit of claim 12, further comprising a fifth resistor between the first optoisolator and the first fuse, a sixth resistor between the second optoisolator and the second fuse, and a seventh resistor between the third optoisolator and the third fuse.

15. The circuit of claim 10, wherein: The first resistor, the second resistor, and the third resistor each have a different resistance value.

16. A method for determining a state of a fuse, comprising: electrically connecting a first fuse in series between the first node and the first resistor; electrically connecting a second fuse in series between a second node and a second resistor, wherein the first fuse and the second fuse are connected in parallel to a same port of a multiplexer, and wherein the first resistor is positioned between the first fuse and the multiplexer; and electrically connecting a controller to the multiplexer; reading, by the controller, voltage levels of the first node and the second node; and By comparing the voltage levels of the first node and the second node with a predetermined voltage level, it is determined whether the first fuse or the second fuse is broken.

17. The method according to claim 16, further comprising: electrically connecting a third fuse between a third node and a third resistor, wherein the third fuse is connected in parallel with the first fuse and the second fuse, and wherein the third fuse is electrically connected to the same port of the multiplexer; reading, by the controller, a voltage level of the third node; and By comparing the voltage levels of the first node, the second node and the third node with the predetermined voltage level, it is determined whether the first fuse, the second fuse or the third fuse is broken, wherein the first resistor, the second resistor and the third resistor each have a different resistance value.

18. The method according to claim 17, further comprising electrically connecting a first diode between the first fuse and the first resistor; electrically connecting a second diode between the second fuse and the second resistor; and A third diode is electrically connected between the third fuse and the third resistor, wherein the first diode, the second diode, and the third diode are electrically connected in parallel.

19. The method according to claim 18, further comprising: A first opto-isolator is electrically connected to the first resistor, a second opto-isolator is electrically connected to the second resistor, and a third opto-isolator is electrically connected to the third resistor.

20. The method according to claim 19, further comprising: A fifth resistor is electrically connected between the first optical isolator and the first fuse, a sixth resistor is electrically connected between the second optical isolator and the second fuse, and a seventh resistor is electrically connected between the third optical isolator and the third fuse.

Images