Solid-state imaging device, method of driving solid-state imaging device, and electronic device

Abstract

According to an embodiment, a solid-state imaging device is provided with: a photoelectric conversion unit; a charge transfer unit for transferring charge stored in the photoelectric conversion unit; a first charge modulation unit through which charge is transferred from the photoelectric conversion unit to the first charge modulation unit; a second charge modulation unit; a charge storage unit for storing charge overflowing from the photoelectric conversion unit during a storage period; a modulation switch unit for coupling or separating the first and second charge modulation units; and a capacitance connection unit for coupling or separating the second charge modulation unit and the charge storage unit. The charge stored in the photoelectric conversion unit is modulated into a voltage signal in a state where the first charge modulation unit is independent and in a state where the first and second charge modulation units are coupled via the modulation switch unit, and the voltage signals having different conversion efficiencies are continuously read. The charge stored in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the storage period are modulated into a voltage signal, and the voltage signal is read at a capacitance obtained by coupling the first, second, and charge modulation units.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device, a method of driving the solid-state imaging device, and an electronic device. Background Art

[0002] In automotive image sensors, a problem known as "LED flicker" has become prominent, in which flickering objects, such as LED light sources, cannot be imaged according to the flicker timing. This LED flicker is a defect that occurs because conventional image sensors have a low dynamic range and require adjusting the exposure time for each object.

[0003] Incidentally, in order to cope with objects with various illuminances, the exposure time is set to be long for low-illuminance objects and short for high-illuminance objects. In this way, the image sensor is designed to cope with various objects even in a low dynamic range.

[0004] On the other hand, the readout speed remains constant regardless of the exposure time. Therefore, when the exposure time is set to a value shorter than the readout time, light incident on the photodiode at times other than the exposure time is photoelectrically converted into charge, but is not read out after the charge-to-voltage conversion and is discarded. Therefore, even if the LED light source flickers during inactive periods other than the exposure time, the LED light source is not imaged and LED flicker does not occur.

[0005] To cope with LED flicker, it is necessary to expand the dynamic range. Various dynamic range expansion technologies are known, and examples include a time division method (e.g., see Patent Document 1), a space division method (e.g., see Patent Document 2), and a method of providing a memory in a pixel to directly increase the amount of charge handled (e.g., see Patent Document 3).

[0006] Reference List

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent No. 4973115

[0009] Patent Document 2: Japanese Patent No. 3071891

[0010] Patent Document 3: Japanese Patent Application Publication No. 2006-253876

[0011] Patent Document 4: Japanese Patent No. 4317115

[0012] Patent Document 5: Japanese Patent No. 5066704 Summary of the Invention

[0013] Problems to be solved by the present invention

[0014] For example, image synthesis is necessary to ensure a dynamic range of, for example, 120 dB, but artifacts from moving objects cannot be avoided with time-division methods. Without time-division, sensitivity and capacitance differences are used, but due to pixel miniaturization, achieving a sufficient dynamic range with these differences alone is difficult.

[0015] In addition, even in the case of expanding the dynamic range on the high illumination side by providing a memory in the pixel to increase the charge processing amount (for example, see patent documents 4 and 5), low illumination characteristics are also required at the same time, but in order to improve the conversion efficiency and ensure the low illumination characteristics, the capacity of the floating diffusion needs to be reduced as much as possible. However, if the capacitance of the floating diffusion is reduced, the photocharge accumulated in the photodiode cannot be fully received. At this time, the photocharge that cannot be fully received is combined with the photocharge accumulated in the capacitance within the pixel and read out. However, since the signal reading from the capacitance within the pixel is performed by incremental data sampling, the signal is susceptible to kTC noise and white current and dark current caused by the interface state, and the photocharge accumulated in the photodiode and that can be initially read out by correlated double sampling is wasted.

[0016] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device that is excellent in low-illuminance characteristics and capable of extending a dynamic range, a method of driving the solid-state imaging device, and an electronic device.

[0017] Solution to the problem

[0018] According to an embodiment, a solid-state imaging device includes: a photoelectric conversion unit; a charge transfer unit configured to transfer charge accumulated in the photoelectric conversion unit; a first charge modulation unit, to which charge is transferred from the photoelectric conversion unit via the charge transfer unit; a second charge modulation unit; a modulation switch unit configured to couple or separate the first charge modulation unit and the second charge modulation unit; a charge accumulation unit configured to accumulate charge overflowing from the photoelectric conversion unit during an accumulation period; and a capacitance connection unit configured to couple or separate the second charge modulation unit and the charge accumulation unit, wherein, in a state where the first charge modulation unit is independent and a state where the first charge modulation unit and the second charge modulation unit are coupled via the modulation switch unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and the voltage signals having different conversion efficiencies are continuously read, and further, the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal, and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit via the modulation switch unit and the capacitance connection unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic configuration diagram showing an example of pixels constituting the solid-state imaging device according to the first embodiment.

[0020] Figure 2 It is a processing sequence diagram of the first embodiment.

[0021] Figure 3A is a potential diagram according to the first embodiment.

[0022] Figure 3B is a potential diagram according to the first embodiment.

[0023] Figure 4 is a schematic configuration diagram illustrating an example of pixels constituting a solid-state imaging device according to a first modification example of the first embodiment.

[0024] Figure 5 This is a processing sequence diagram of the first modified example of the first embodiment.

[0025] Figure 6A 3 is a potential diagram of a first modified example of the first embodiment.

[0026] Figure 6B 3 is a potential diagram of a first modified example of the first embodiment.

[0027] Figure 7 is a schematic configuration diagram illustrating an example of pixels constituting a solid-state imaging device according to a second modification example of the first embodiment.

[0028] Figure 8 This is a processing sequence diagram of the second modified example of the first embodiment.

[0029] Figure 9 This is a potential diagram of a second modified example of the first embodiment.

[0030] Figure 10 is a schematic configuration diagram showing an example of pixels constituting the solid-state imaging device according to the second embodiment.

[0031] Figure 11 It is a processing sequence diagram of the second embodiment.

[0032] Figure 12A is a potential diagram according to the second embodiment.

[0033] Figure 12B is a potential diagram according to the second embodiment.

[0034] Figure 13 This is a diagram illustrating the processing sequence of the short-term exposure time integration and the long-term exposure time integration in the embodiment.

[0035] Figure 14It is an explanatory diagram of a modified example of the processing time of the short-term exposure time integration and the long-term exposure time integration in the embodiment.

[0036] Figure 15 is a diagram for describing a configuration example of an imaging device as an electronic device.

[0037] Figure 16 is a diagram for describing a configuration example of an imaging device as another electronic device. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0039] [1] First embodiment

[0040] Figure 1 is a schematic configuration diagram showing an example of pixels constituting the solid-state imaging device according to the first embodiment.

[0041] A plurality of pixels 10 (e.g., N rows x M columns, where N and M are integers of 2 or greater) are provided to constitute a pixel array unit in a solid-state imaging device. The pixels 10 then photoelectrically convert incident light and generate pixel signals corresponding to the amount of incident light received.

[0042] For example, Figure 1 As shown, the pixel 10 includes a photodiode 21 as a photoelectric conversion unit, a floating diffusion (FD) region 22-1 as a first charge modulation unit, a floating diffusion region 22-2 as a second charge modulation unit, a transfer transistor 23 as a charge transfer unit, an in-pixel capacitor 24 as a charge accumulation unit, a conversion efficiency switching transistor 25 as a modulation switching unit, an accumulation transistor 26 as a capacitance connection unit, a reset transistor 27, an amplification transistor 28, and a selection transistor 29.

[0043] In the above-described configuration, the photodiode 21 generates electric charge according to the light amount of received incident light.

[0044] The floating diffusion region 22 and the in-pixel capacitance 24 accumulate photocharges overflowing from the photodiode 21 during the charge accumulation period.

[0045] The transfer transistor 23 transfers the photocharge accumulated in the photodiode 21 to the floating diffusion area 22 .

[0046] The conversion efficiency switching transistor 25 modulates the photocharge accumulated in the photodiode 21 into a voltage signal in a state where only the floating diffusion 22 - 1 exists and in a state where the floating diffusion 22 - 1 and the floating diffusion 22 - 2 are potential-coupled, thereby switching the conversion efficiency.

[0047] The accumulation transistor 26 functions as a capacitance connection unit, and couples or separates the potential between the floating diffusion area 22 and the in-pixel capacitance 24 .

[0048] The reset transistor 27 resets the accumulated charge and shifts to an initial state.

[0049] The amplification transistor 28 amplifies a voltage signal obtained by modulating the charge and outputs the amplified voltage signal as a pixel signal.

[0050] The selection transistor 29 has a low potential side connected to the constant current source 30 , and outputs the pixel signal output from the amplification transistor 28 to the subsequent stage when turned on.

[0051] Figure 2 It is a processing sequence diagram of the first embodiment.

[0052] exist Figure 2 , the upper stage is a processing timing chart corresponding to pixels of a row (SH row) performing an exposure start operation, and the lower stage is a processing timing chart corresponding to pixels of a row (RD row) performing a signal read operation.

[0053] Figure 3A and 3B is a potential diagram according to the first embodiment.

[0054] In the exposure start operation, Figure 2 At the timing indicated by the arrow (a) in FIG. 1 , the accumulation transistor 26 is set to the on state (conduction state) by the control signal FCG, the reset transistor 27 is set to the on state (conduction state) by the control signal RST, and the charge accumulated in the pixel capacitance 24 is set to the reset state, as shown in FIG. Figure 3B As shown in (a), the transfer transistor 23 is set to the on state (conducting state) by the control signal TRG, and the conversion efficiency switching transistor 25 is set to the on state (conducting state) by the control signal FDG, so the charge accumulated in the photodiode 21 is also set to the reset state, as shown in FIG. Figure 3A As shown in (a).

[0055] Then, if Figure 2 As indicated by the reference symbol (b) in FIG, exposure is performed between a row for performing an exposure start operation (SH row) and a row for performing a signal reading operation (RD row), as shown in FIG. Figure 3A (b) and Figure 3B (b) shown.

[0056] Then, after a certain exposure time, the selection transistor 29 is set to the conductive state by the control signal SEL to start the signal reading operation. Then, the conversion efficiency switching transistor 25 is set to the open state (conductive state) by the control signal FDG, and Figure 2 At the timing indicated by the arrow (c), the reset level R2 of low conversion efficiency is obtained, as shown in FIG. Figure 3A (c) shown.

[0057] At this time, by Figure 2 At the timing indicated by the arrow (c), the floating diffusion area 22-1 (denoted by Figure 3A ) and the floating diffusion region 22-2 (denoted by reference symbol FD1 in FIG. Figure 3A and Figure 3B The potential of the reference symbol FD2 in the figure is as follows Figure 3A The coupling is shown in (c).

[0058] In this case, the floating diffusion area 22-1 (by Figure 3A ) and the floating diffusion region 22-2 (denoted by reference symbol FD1 in FIG. Figure 3A and Figure 3B The potential (denoted by reference symbol FD2 in FIG) is supplied as a gate voltage of the amplifying transistor 28, and the gate voltage is supplied as a pixel signal to a subsequent stage (eg, an AD converter) via the selecting transistor 29 and the vertical signal line.

[0059] Next, in Figure 2 At the timing indicated by the arrow (d) in FIG, the conversion efficiency switching transistor 25 is set to the off state (non-conducting state) by the control signal FDG, and the reset level R1 of the high conversion efficiency is obtained, as shown in FIG. Figure 3A (d) shown.

[0060] Next, the transfer transistor 23 is set to an on state (conductive state) by the control signal TRG to transfer the charge accumulated in the photodiode 21 to the floating diffusion 22 - 1 , and then is set to an off state (non-conductive state) by the control signal TRG.

[0061] Next, in Figure 2 At the time sequence indicated by the arrow (e), the Figure 3A (e) shows a signal level S1 with high conversion efficiency.

[0062] Next, in Figure 2 At the timing indicated by the arrow (f) in FIG, the conversion efficiency switching transistor 25 is set to the on state (conductive state) by the control signal FDG, and at the same time, the transfer transistor 23 is set to the on state (conductive state) again by the control signal TRG, thereby transferring all the charges accumulated in the photodiode 21 to the floating diffusion area 22, and then, the transfer transistor 23 is set to the off state (non-conductive state) by the control signal TRG, and then the signal level S2 with low conversion efficiency is read, as shown in FIG. Figure 3A (f) shown.

[0063] Here, in the case of high illuminance, the photocharge overflowing from the photodiode 21 is accumulated in the pixel internal capacitance 24. Figure 2 At the timing indicated by the arrow (g) in FIG, the pixel capacitance 24, the floating diffusion area 22-1 and the floating diffusion area 22-2 are potential-coupled by setting the accumulation transistor to the on state (conduction state) by the control signal FCG, and the signal level S4 is read out, as shown in FIG. Figure 3B As shown in (g).

[0064] Next, in a state where the selection transistor 29 is set to an off state by the control signal SEL, the reset transistor 27 is set to an on state (conductive state) by the control signal RST, and the accumulated charge is set to a reset state.

[0065] Then, the reset transistor is set to an off state (non-conducting state) by the control signal RST, and Figure 2 The arrow (h) in the figure indicates the timing of the acquisition. Figure 3B The reset level R4 is shown in (h).

[0066] The difference between the signal level S1 for high conversion efficiency and the reset level R1 for high conversion efficiency, ie,

[0067] For S1-R1,

[0068] The image signal is generated by correlated double sampling (CDS).

[0069] Similarly, for the difference between the signal level S4 and the reset level R4, that is,

[0070] For S4-R4,

[0071] The image signal is generated by incremental data sampling (DDS).

[0072] On the contrary, for the difference between the signal level S2 at low conversion efficiency and the reset level R2 at low conversion efficiency, that is,

[0073] For S2-R2,

[0074] The image signal is generated by correlated double sampling (CDS), but the signal level S2 of low conversion efficiency and the reset level R2 of low conversion efficiency are not continuously read, so the reset level R2 of low conversion efficiency needs to be temporarily held in a line memory or the like.

[0075] Therefore, by combining three images corresponding to image signals corresponding to S1 - R1 , S2 - R2 , and S4 - R4 , an image having excellent low-illuminance characteristics, a high dynamic range, and no artifacts of an object can be configured.

[0076] As described above, according to the first embodiment, in a state where the floating diffusion 22-1 functions only as a first charge modulation element, and in a state where the floating diffusion 22-1 functioning as the first charge modulation element and the floating diffusion 22-2 functioning as the second charge modulation element are coupled via the conversion efficiency switching transistor 25 functioning as a modulation switching element, the charge accumulated in the photodiode 21 functioning as a photoelectric conversion element is modulated into a voltage signal, and voltage signals having different conversion efficiencies (high conversion efficiency and low conversion efficiency) are continuously read. Furthermore, the charge accumulated in the photodiode 21 functioning as a photoelectric conversion element and the charge overflowing from the photodiode 21 during the accumulation period and accumulated in the in-pixel capacitor 24 are modulated into a voltage signal, and the voltage signal is read from the capacitor in which the floating diffusion 22-1, the floating diffusion 22-2, and the in-pixel capacitor 24 are coupled via the conversion efficiency switching transistor 25 functioning as a modulation switching element and the accumulation transistor 26 functioning as a capacitance connection element. Therefore, excellent low-light characteristics and an extended high dynamic range can be achieved.

[0077] [1.1] First Modification of the First Embodiment

[0078] Figure 4 is a schematic configuration diagram illustrating an example of pixels constituting a solid-state imaging device according to a first modification example of the first embodiment.

[0079] Figure 4 The Pixel 10A with Figure 1 The pixel 10 of the first embodiment is different in that a second accumulation transistor 31 serving as a third charge transfer unit is provided between the photodiode 21 and the in-pixel capacitance 24 .

[0080] As described above, according to the configuration in which the second accumulation transistor 31 is provided, the floating diffusion area 22-1 and the floating diffusion area 22-2 can be reset before reading the charge accumulated in the photodiode 21, which is advantageous in terms of charge transfer from the photodiode 21 to the floating diffusion area 22-1 and the floating diffusion area 22-2 and the dark current white point of the floating diffusion area 22-1 and the floating diffusion area 22-2.

[0081] Figure 5 This is a processing sequence diagram of the first modified example of the first embodiment.

[0082] Figure 6A and Figure 6B 3 is a potential diagram of a first modified example of the first embodiment.

[0083] In the exposure start operation, Figure 5At the timing indicated by the arrow (a) in FIG. 1 , the accumulation transistor 26 is set to the on state (conduction state) by the control signal FCG. Furthermore, the reset transistor 27 is set to the on state (conduction state) by the control signal RST, and the charge accumulated in the pixel capacitance 24 is set to the reset state, as shown in FIG. Figure 6B As shown in (a), and in the on-state (conducting state) of the conversion efficiency switching transistor 25 by the control signal FDG, the transfer transistor 23 is set to the on-state (conducting state) by the control signal TRG, and therefore, the charge accumulated in the photodiode 21 is also set to the reset state, as shown in FIG. Figure 6A As shown in (a).

[0084] Then, if Figure 5 As indicated by the reference symbol (b) in Figure 6A (b) and Figure 6B As shown in (b), exposure is performed between a row where an exposure start operation is performed (SH row) and a row where a signal reading operation is performed (RD row).

[0085] Then, after a certain exposure time, the selection transistor 29 is set to the on state by the control signal SEL to start the signal reading operation. The conversion efficiency switching transistor 25 is set to the on state (conduction state) by the control signal FDG, and Figure 5 At the timing indicated by the arrow (c), the reset level R2 of low conversion efficiency is obtained, as shown in FIG. Figure 6A (c) shown.

[0086] At this time, by Figure 5 At the timing indicated by the arrow (c), the floating diffusion area 22-1 (denoted by Figure 6A ) and the floating diffusion region 22-2 (denoted by reference symbol FD1 in FIG. Figure 6A and Figure 6B Reference symbol FD2 in the figure represents the potential coupling of the circuit, as shown in FIG. Figure 6A As shown in (c).

[0087] Next, the conversion efficiency switching transistor 25 is set to an off state by the control signal FDG, and Figure 5 At the timing indicated by the arrow (d), the reset level R1 with high conversion efficiency is obtained, as shown in FIG. Figure 6A (d) shown.

[0088] Furthermore, the transfer transistor 23 is set to an on state (conductive state) by the control signal TRG to transfer the charge accumulated in the photodiode 21 to the floating diffusion area 22 - 1 .

[0089] Next, the transfer transistor 23 is set to an off state (non-conducting state) by the control signal TRG, and Figure 5 The arrow (e) in the figure indicates the timing of the acquisition. Figure 6A (e) shows a signal level S1 with high conversion efficiency.

[0090] Next, in Figure 5 At the timing indicated by the arrow (f) in FIG, the conversion efficiency switching transistor 25 is set to the on state (conduction state) by the control signal FDG, and at the same time, the transfer transistor 23 is set to the on state (conduction state) again by the control signal TRG, so that all the charges accumulated in the photodiode 21 are transferred to the floating diffusion area 22, and the signal level S2 with low conversion efficiency is read, as shown in FIG. Figure 6A (f) shown.

[0091] Here, in the case of high illuminance, the photocharge overflowing from the photodiode 21 is accumulated in the pixel internal capacitance 24. Figure 5 At the timing indicated by the arrow (g) in FIG, the pixel capacitance 24, the floating diffusion area 22-1 and the floating diffusion area 22-2 are potential-coupled by setting the accumulation transistor 26 to the on state (conduction state) by the control signal FCG, and the signal level S4 is read, as shown in FIG. Figure 6B As shown in (g).

[0092] Next, in a state where the selection transistor 29 is set to an off state by the control signal SEL, the reset transistor 27 is set to an on state (conductive state) by the control signal RST, and the accumulated charge is set to a reset state.

[0093] Then, the reset transistor 27 is set to an off state (non-conductive state) by the control signal RST, and Figure 5 The arrow (h) in the figure indicates the timing of the acquisition. Figure 6B The reset level R4 is shown in (h).

[0094] Thereafter, the difference between the signal level S1 for high conversion efficiency and the reset level R1 for high conversion efficiency, ie,

[0095] For S1-R1,

[0096] The image signal is generated by correlated double sampling (CDS).

[0097] Similarly, for the difference between the signal level S4 and the reset level R4, that is,

[0098] For S4-R4,

[0099] The image signal is generated by incremental data sampling (DDS).

[0100] On the contrary, for the difference between the signal level S2 at low conversion efficiency and the reset level R2 at low conversion efficiency, that is,

[0101] For S2-R2,

[0102] The image signal is generated by correlated double sampling (CDS), but the signal level S2 of low conversion efficiency and the reset level R2 of low conversion efficiency are not continuously read, so the reset level R2 of low conversion efficiency needs to be temporarily held in a line memory or the like.

[0103] As a result, by combining three images corresponding to the image signals of S1 - R1 , S2 - R2 , and S4 - R4 , an image having excellent low-illuminance characteristics, a high dynamic range, and no artifacts of an object can be configured.

[0104] As described above, according to the first modification of the first embodiment, since the second accumulation transistor 31 serving as the third charge transfer unit is provided between the photodiode 21 serving as the first photoelectric conversion unit and the in-pixel capacitor 24 serving as the charge accumulation unit, it becomes possible to reset the floating diffusion area 22-1 and the floating diffusion area 22-2 before reading the charge accumulated in the photodiode 21, and in addition to the effects of the first embodiment, this is advantageous in terms of charge transfer from the photodiode 21 to the floating diffusion area 22-1 and the floating diffusion area 22-2 and in terms of the dark current white point of the floating diffusion area 22-1 and the floating diffusion area 22-2.

[0105] [1.2] Second Modification of the First Embodiment

[0106] Figure 7 is a schematic configuration diagram illustrating an example of pixels constituting a solid-state imaging device according to a second modification example of the first embodiment.

[0107] Figure 7 The Pixel 10B with Figure 1 The pixel 10 of the first embodiment is different in that, without providing the accumulation transistor 26 , the in-pixel capacitance 24 is connected to the connection point between the conversion efficiency switching transistor 25 and the reset transistor 27 .

[0108] Figure 8 This is a processing sequence diagram of the second modified example of the first embodiment.

[0109] exist Figure 8 , the upper stage is a processing timing chart corresponding to pixels of a row (SH row) performing an exposure start operation, and the lower stage is a processing timing chart corresponding to pixels of a row (RD row) performing a read operation.

[0110] Figure 9 This is a potential diagram of a second modified example of the first embodiment.

[0111] In the exposure start operation, Figure 8 At the timing indicated by the arrow (a) in FIG, the reset transistor 27 is set to the on state (conducting state) by the control signal RST, the charge accumulated in the pixel internal capacitor 24 is set to the reset state, the conversion efficiency switching transistor 25 is set to the on state (conducting state) by the control signal FDG, and the transfer transistor 23 is set to the on state (conducting state) by the control signal TRG, so that the charge accumulated in the photodiode 21 is also set to the reset state, as shown in FIG. Figure 9 As shown in (a).

[0112] Then, if Figure 8 As indicated by the reference symbol (b) in Figure 9 As shown in (b) of FIG. 1 , exposure is performed between a row where an exposure start operation is performed (SH row) and a row where a signal reading operation is performed (RD row).

[0113] Then, after a certain exposure time, the selection transistor 29 is set to the on state by the control signal SEL to start the signal reading operation. The conversion efficiency switching transistor 25 is set to the on state (conduction state) by the control signal FDG, and Figure 8 At the timing indicated by the arrow (c), the reset level R2 of low conversion efficiency is obtained, as shown in FIG. Figure 9 (c) shown.

[0114] At this time, by Figure 8 At the timing indicated by the arrow (c), the floating diffusion area 22-1 (denoted by Figure 9 ) and the floating diffusion region 22-2 (denoted by reference numeral FD1 in FIG. Figure 9 Reference numeral FD2 in FIG) indicates a potential coupling, such as Figure 9 As shown in (c).

[0115] In this case, the floating diffusion area 22-1 (by Figure 9 ) and the floating diffusion region 22-2 (denoted by reference numeral FD1 in FIG. Figure 9 The potential (denoted by reference symbol FD2 in FIG) is supplied as a gate voltage of the amplifying transistor 28, and the gate voltage is supplied as a pixel signal to a subsequent stage (eg, an AD converter) via the selecting transistor 29 and the vertical signal line.

[0116] Next, in Figure 8 At the timing indicated by the arrow (d) in FIG, the conversion efficiency switching transistor 25 is set to the off state (non-conducting state) by the control signal FDG, and the reset level R1 of the high conversion efficiency is obtained, as shown in FIG. Figure 9 (d) shown.

[0117] Next, in Figure 8 The arrow (e) indicates the timing, such as Figure 9 As shown in (e), a signal level S1 with high conversion efficiency is obtained.

[0118] Next, in Figure 8 At the timing indicated by the arrow (f) in FIG, the conversion efficiency switching transistor 25 is set to the on state (conductive state) by the control signal FDG, and at the same time, the transfer transistor 23 is set to the on state (conductive state) again by the control signal TRG, thereby transferring all the charges accumulated in the photodiode 21 to the floating diffusion area 22, and then, the transfer transistor 23 is set to the off state (non-conductive state) by the control signal TRG, and then the signal level S2 with low conversion efficiency is read, as shown in FIG. Figure 9 As shown in (f).

[0119] Here, in the case of high illumination, since the photocharge overflowed from the photodiode 21 is accumulated in the pixel internal capacitor 24, Figure 8 The arrow (g) in the figure indicates the timing, as shown in Figure 9 As shown in (g), the signal level S3 is read.

[0120] Next, in a state where the selection transistor 29 is set to an off state by the control signal SEL, the reset transistor 27 is set to an on state (conductive state) by the control signal RST, and the accumulated charge is set to a reset state.

[0121] Then, the reset transistor 27 is set to an off state (non-conductive state) by the control signal RST, and Figure 8 The reset level R3 is obtained at the timing indicated by the arrow (h) in FIG. Figure 9 (h) shown.

[0122] The difference between the signal level S1 for high conversion efficiency and the reset level R1 for high conversion efficiency, ie,

[0123] For S1-R1,

[0124] The image signal is generated by correlated double sampling (CDS).

[0125] Similarly, for the difference between the signal level S3 and the reset level R3, that is,

[0126] For S3-R3,

[0127] The image signal is generated by incremental data sampling (DDS).

[0128] On the contrary, for the difference between the signal level S2 at low conversion efficiency and the reset level R2 at low conversion efficiency, that is,

[0129] For S2-R2,

[0130] The image signal is generated by correlated double sampling (CDS), but the signal level S2 of low conversion efficiency and the reset level R2 of low conversion efficiency are not continuously read, so the reset level R2 of low conversion efficiency needs to be temporarily held in a line memory or the like.

[0131] As a result, according to the second modification of the first embodiment, by combining three images corresponding to the image signals of S1-R1, S2-R2 and S3-R3, an image with excellent low illumination characteristics, high dynamic range and no object artifacts can be configured.

[0132] As described above, according to the second modification of the first embodiment, since the in-pixel capacitance 24 is connected to the connection point between the conversion efficiency switching transistor 25 and the reset transistor 27 without providing the accumulation transistor 26, in addition to the effects of the first embodiment, the pixel size can be reduced.

[0133] [2] Second embodiment

[0134] Figure 10 is a schematic configuration diagram showing an example of pixels constituting the solid-state imaging device according to the second embodiment.

[0135] A plurality of pixels 40 according to the first embodiment (e.g., N rows × M columns, where N and M are integers of 2 or greater) are arranged to constitute a pixel array unit in a solid-state imaging device, similar to the first embodiment. The pixels 10 then photoelectrically convert incident light and generate pixel signals corresponding to the amount of light received by the incident light.

[0136] For example, Figure 10 As shown, the pixel 40 includes a high-sensitivity photodiode 41 as a first photoelectric conversion unit, a first floating diffusion area 42 as a first charge modulation unit, a transfer transistor 43 as a charge transfer unit, a conversion efficiency switch transistor 44 as a modulation switch unit, a second floating diffusion area 45 as a second charge modulation unit, an accumulation transistor 46 as a capacitance connection unit, a reset transistor 47, an in-pixel capacitor 48 as a charge accumulation unit, a low-sensitivity photodiode 50 as a second photoelectric conversion unit, a third floating diffusion area 51 as a third charge modulation unit, an amplification transistor 52 and a selection transistor 53.

[0137] In the above-described configuration, the high-sensitivity photodiode 41 generates electric charges corresponding to the light amount of received incident light having high sensitivity.

[0138] The first floating diffusion area 42 functions as a first charge modulation unit and simultaneously stores charges overflowing from the high-sensitivity photodiode 41 .

[0139] The transfer transistor 43 functions as a charge transfer unit, and transfers the photocharges accumulated in the high-sensitivity photodiode 41 to the first floating diffusion area 42 .

[0140] The conversion efficiency switching transistor 44 serves as a modulation switching unit and switches the conversion efficiency by modulating the photocharge accumulated in the high-sensitivity photodiode 41 into a voltage signal in a state where only the first floating diffusion area 42 is present, a state where the potentials of the first floating diffusion area 42 and the second floating diffusion area 45 are coupled, or a state where the potentials of the first floating diffusion area 42, the second floating diffusion area 45 and the third floating diffusion area 51 are coupled.

[0141] The first floating diffusion area 42 and the second floating diffusion area 45 function as a first charge modulation unit and a second charge modulation unit and simultaneously store charges overflowing from the high-sensitivity photodiode 41 .

[0142] The accumulation transistor 46 functions as a capacitance connection unit, and couples or separates the potentials of the second floating diffusion area 45 and the third floating diffusion area 51 .

[0143] The reset transistor 47 resets the accumulated charge and shifts to an initial state.

[0144] The low-sensitivity photodiode 50 functions as a second photoelectric conversion unit and generates charges according to the light amount of received incident light.

[0145] The third floating diffusion region 51 functions as a third charge modulation unit and simultaneously functions as a charge accumulation unit to which the in-pixel capacitance 48 is connected and stores charges generated by photoelectric conversion in the low-sensitivity photodiode 50 .

[0146] The amplification transistor 52 amplifies a voltage signal obtained by modulating the charge and outputs the amplified voltage signal as a pixel signal.

[0147] The selection transistor 53 has a low potential side connected to the constant current source 54 , and outputs the pixel signal output from the amplification transistor 52 to the subsequent stage when turned on.

[0148] Figure 11 It is a processing sequence diagram of the second embodiment.

[0149] Figure 12A and Figure 12B is a potential diagram according to the second embodiment.

[0150] In the exposure start operation, Figure 11At the timing indicated by the arrow (a) in FIG, the reset transistor 47 is set to the on state (conducting state) by the control signal RST, and the third floating diffusion area 51 is set to the reset state by the control signal FCG, while the accumulation transistor 46 is in the on state (conducting state), as shown in FIG. Figure 12B As shown in (a), the conversion efficiency switching transistor 44 is set to the on state (conducting state) by the control signal FDG, and the transfer transistor 43 is set to the on state (conducting state) by the control signal TGL, as shown in FIG. Figure 12A As shown in (a), the high-sensitivity photodiode 41 is set to a reset state.

[0151] Then, if Figure 11 As shown in the reference symbol (b), Figure 12A (b) and Figure 12B As shown in (b) of FIG. 1 , exposure is performed between a row where an exposure start operation is performed (SH row) and a row where a signal reading operation is performed (RD row).

[0152] Then, after a certain exposure time, the selection transistor 53 is set to the conductive state by the control signal SEL to start the signal reading operation. The conversion efficiency switching transistor 44 is set to the open state (conductive state) by the control signal FDG, and Figure 11 At the timing indicated by the arrow (c), a reset level R2 with low conversion efficiency is obtained, as shown in FIG. Figure 12A As shown in (c).

[0153] At this time, by Figure 11 At the timing indicated by the arrow (c), the first floating diffusion region 42 (denoted by Figure 12A The second floating diffusion region 45 (denoted by reference symbol FD1 in FIG. Figure 12A and Figure 12B The potential of the reference symbol FD2 in the figure is as follows Figure 12A The coupling is shown in (c).

[0154] Next, in Figure 11 At the timing indicated by the arrow (d), the conversion efficiency switching transistor 44 is set to the off state (non-conducting state) by the control signal FDG, and the reset level R1 of the high conversion efficiency is obtained, as shown in FIG. Figure 12A As shown in (d).

[0155] Next, the transfer transistor 43 is set to an on state (conductive state) by the control signal TGL to transfer the charge accumulated in the high-sensitivity photodiode 41 to the first floating diffusion area 42, and then is set to an off state (non-conductive state) by the control signal TGL.

[0156] Next, in Figure 11The arrow (e) in the figure indicates the timing, as shown in Figure 12A As shown in (e), a signal level S1 with high conversion efficiency is obtained.

[0157] Next, in Figure 11 At the timing indicated by the arrow (f) in FIG, the conversion efficiency switching transistor 44 is set to the on state (conductive state) by the control signal FDG, and at the same time, the transfer transistor 43 is set to the on state (conductive state) again by the control signal TGL, so that all the charges accumulated in the high-sensitivity photodiode 41 are transferred to the first floating diffusion area 42 and the second floating diffusion area 45, and then, the transfer transistor 43 is set to the off state (non-conductive state) by the control signal TGL, and then, the signal level S2 of the low conversion efficiency is read, as shown in FIG. Figure 12A (f) shown.

[0158] Next, the signal level S3 is read while the potentials of the first floating diffusion 42 and the second floating diffusion 45 are kept coupled.

[0159] Next, the selection transistor 53 is set to an off state by the control signal SEL, the reset transistor 47 is set to an on state (conductive state) by the control signal RST, and the charges accumulated in the first and second floating diffusion areas 42 and 45 are set to a reset state.

[0160] Then, the reset transistor 47 is set to an off state (non-conductive state) by the control signal RST, and Figure 11 The arrow (h) in the figure indicates the timing of reading Figure 12A (h) shows the reset level R3.

[0161] Then, in Figure 11 At the timing indicated by the arrow (i) in FIG, the accumulation transistor 46 is set to the on state (conduction state) by the control signal FCG, the potentials of the second floating diffusion area 45 and the third floating diffusion area 51 are combined, and the signal level S4 is read, as shown in FIG. Figure 12B As shown in (i).

[0162] Next, in a state where the selection transistor 53 is set to an off state by the control signal SEL, the reset transistor 47 is set to an on state (conductive state) by the control signal RST, and the accumulated charge is set to a reset state.

[0163] Next, in Figure 11 At the timing indicated by the arrow (j) in FIG. 1 , the selection transistor 53 is set to the on state (conduction state) again by the control signal SEL, and the reset level R4 is obtained, as shown in FIG. Figure 12B (j) shown.

[0164] Thereafter, for the difference between the signal level S1 at high conversion efficiency and the reset level R1 at high conversion efficiency corresponding to the high-sensitivity photodiode 41, that is,

[0165] For S1-R1,

[0166] The image signal is generated by correlated double sampling (CDS).

[0167] On the contrary, for the difference between the signal level S2 at low conversion efficiency corresponding to the high-sensitivity photodiode 41 and the reset level R2 at low conversion efficiency, that is,

[0168] For S2-R2,

[0169] The image signal is generated by correlated double sampling (CDS), but the signal level S2 of low conversion efficiency and the reset level R2 of low conversion efficiency are not continuously read, so the reset level R2 of low conversion efficiency needs to be temporarily held in a line memory or the like.

[0170] Similarly, for the difference between the signal level S3 corresponding to the high-sensitivity photodiode 41 and the reset level R3, that is,

[0171] For S3-R3,

[0172] The image signal is generated by incremental data sampling (DDS).

[0173] Thereafter, for the difference between the signal level S4 of the low-sensitivity photodiode 50 and the reset level R4, that is,

[0174] For S4-R4,

[0175] The image signal is generated by incremental data sampling (DDS).

[0176] As a result, by combining four images corresponding to pixel signals corresponding to S1-R1, S2-R2, S3-R3, and S4-R4, an image having excellent low illumination characteristics, a high dynamic range, and no artifacts of an object can be configured.

[0177] As described above, according to the second embodiment, in a state where the first floating diffusion 42 serving as the first charge modulation unit is independent, and in a state where the first floating diffusion 42 serving as the first charge modulation unit and the second floating diffusion 45 serving as the second charge modulation unit are coupled via the conversion efficiency switching transistor 44 serving as the modulation switching unit, the charge accumulated in the high-sensitivity photodiode 41 serving as the first photoelectric conversion unit is modulated into a voltage signal, and the voltage signals having different conversion efficiencies are continuously read. Furthermore, the charge accumulated in the high-sensitivity photodiode 41 serving as the first photoelectric conversion unit and the charge overflowing from the high-sensitivity photodiode 41 serving as the first photoelectric conversion unit are modulated into a voltage signal, and the voltage signal is read from the capacitance coupled between the first floating diffusion 42 serving as the first charge modulation unit and the second floating diffusion 45 serving as the second charge modulation unit. Furthermore, the charge generated in the low-sensitivity photodiode 50 serving as the second photoelectric conversion unit and accumulated in the in-pixel capacitor 48 serving as the charge accumulation unit is modulated into a voltage signal, and the voltage signal is read from the capacitance coupled between the first floating diffusion region 42 serving as the first charge modulation unit, the second floating diffusion region 45 serving as the second charge modulation unit, and the in-pixel capacitor 48 serving as the charge accumulation unit. Therefore, excellent low-illuminance characteristics and an extended high dynamic range can be achieved.

[0178] [3] Modification of the embodiment

[0179] Figure 13 It is an explanatory diagram of the processing sequence of the short-term exposure operation and the long-term exposure operation applicable to each of the above-described embodiment and modification examples.

[0180] This processing sequence can be applied to each of the above-described embodiment and modifications.

[0181] exist Figure 13 In the embodiment, the short-term exposure operation SEI and the long-term exposure operation LEI are performed alternately.

[0182] Then, the shutter timing SHS for the short-term exposure time is set immediately before the short-term exposure operation SEI, and the signal read timing RDS for the short-term exposure time is set immediately after the short-term exposure operation SEI.

[0183] By providing a short exposure operating SEI as described above, the dynamic range can be further extended.

[0184] Similarly, the shutter timing SHL for the long-term exposure time is set immediately before the long-term exposure operation LEI, and the signal read timing RDL for the long-term exposure time is set immediately after the long-term exposure operation LEI.

[0185] Figure 14It is an explanatory diagram of a modified example of the processing sequence of the short-term exposure operation and the long-term exposure operation.

[0186] This processing sequence can also be applied to each of the above-described embodiment and modifications.

[0187] like Figure 4 As shown, by providing a line memory for the short-term exposure operation, artifacts of a moving object can be reduced without providing an interval between the short-term exposure operation SEI and the long-term exposure operation LEI.

[0188] Figure 15 is a diagram for describing a configuration example of an imaging device as an electronic device.

[0189] The imaging device 60 includes: a solid-state imaging device 61, which includes the pixel 10, 10A, 10B or 40 of each of the above-mentioned embodiments; an optical system 62, which includes a lens group, etc.; a digital signal processor (DSP) 63, which serves as a signal processing circuit for processing imaging data; a display unit 64, which includes a liquid crystal display, an organic EL display, etc., and displays a captured image and various types of information; an operation unit 65, on which a user performs various operations, such as imaging instructions and data settings; a controller 66, which controls the entire imaging device 60; a frame memory 67, which stores image data; a recording unit 68, which records the imaging data on a recording medium such as a hard disk or a memory card (not shown); and a power supply unit 69, which supplies power to the entire imaging device 60.

[0190] In the above-described configuration, the DSP 63 , the display unit 64 , the operation unit 65 , the controller 66 , the frame memory 67 , the recording unit 68 , and the power supply unit 69 are connected to one another via a bus.

[0191] According to the above configuration, since the above solid-state imaging device 61 including the pixels 10 , 10A, 10B, or 40 is used as an imaging element, an image having excellent low-illuminance characteristics, a high dynamic range, and few object artifacts can be captured.

[0192] Examples of actual modes of the imaging device 60 include camera modules for mobile terminal devices such as video cameras, digital still cameras, and smartphones.

[0193] Figure 16 is a diagram for describing an example of a configuration of an imaging device as another electronic device.

[0194] The imaging device 70 includes: a solid-state imaging device 71, including the pixel 10, 10A, 10B or 40 of each of the above-mentioned embodiments; an optical system 72, including a lens group, etc.; a DSP 73, which serves as a signal processing circuit for processing imaging data; an interface unit 74, which performs an interface operation with an external device 80; and a frame memory 75, which stores image data.

[0195] The imaging device 70 of this mode performs imaging under the control of the external device 80 by power supplied from the external device 80, and can be applied as, for example, a camera module, etc., which captures monitoring images around the vehicle by receiving power supply from the vehicle side under the control of the vehicle-mounted ECU, etc. as the external device 80.

[0196] In this case, the external device 80 includes: an interface unit 81, which is interconnected with the imaging device 70; an image processing unit 82, which performs image processing on the imaging data acquired via the interface unit 81 to obtain desired image data (such as surrounding obstacle images, vital sign recognition images, etc.); a power supply unit 83, which supplies operating power to the imaging device 70 and the external device 80; an external controller 84, which controls the imaging device 70 via the interface unit 81; and a recording unit 85, which records the imaging data on a recording medium such as a hard disk and a memory card (not shown).

[0197] Examples of applications of such an imaging device 70 include: an on-vehicle sensor, which is provided on the outer surface (front surface, side surface, or rear surface) of a car, inside the vehicle, etc., to ensure safe driving (e.g., automatic stopping, identifying the driver's status, etc.) and to capture the periphery of the vehicle or the interior of the vehicle; a monitoring camera for remotely monitoring a moving vehicle and a road; and a distance measuring device.

[0198] In addition, the imaging device can be used as an imaging device for detecting and controlling the user's position, action (gesture), etc., for an imaging device having a main body of a home appliance (air conditioner, refrigerator, microwave oven, etc.) as an external device 80.

[0199] In addition, imaging devices can also be used for personnel authentication, skin capture, etc.

[0200] Note that implementation of the present technology is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

[0201] Furthermore, the present technology can be configured as follows. (1)

[0203] A solid-state imaging device comprising:

[0204] Photoelectric conversion unit;

[0205] a charge transfer unit configured to transfer the charge accumulated in the photoelectric conversion unit;

[0206] a first charge modulation unit, to which charges are transferred from the photoelectric conversion unit via the charge transfer unit;

[0207] a second charge modulation unit;

[0208] a modulation switch unit configured to couple or separate the first charge modulation unit and the second charge modulation unit;

[0209] a charge accumulation unit configured to accumulate charges overflowing from the photoelectric conversion unit during an accumulation period; and

[0210] a capacitive connection unit configured to couple or separate the second charge modulation unit and the charge accumulation unit;

[0211] in,

[0212] In a state where the first charge modulation unit is independent and in a state where the first charge modulation unit and the second charge modulation unit are coupled via the modulation switch unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and the voltage signals having different conversion efficiencies are continuously read; and

[0213] In addition, the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal, and the voltage signal is read in the capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit and the charge accumulation unit through the modulation switch unit and the capacitance connection unit. (2)

[0215] A solid-state imaging device comprising:

[0216] a first photoelectric conversion unit;

[0217] a charge transfer unit configured to transfer charges accumulated in the first photoelectric conversion unit;

[0218] a first charge modulation unit, to which charges are transferred from the first photoelectric conversion unit via the charge transfer unit;

[0219] a second charge modulation unit;

[0220] a modulation switch unit configured to couple or separate the first charge modulation unit and the second charge modulation unit;

[0221] a second photoelectric conversion unit;

[0222] a charge accumulation unit directly connected to the second photoelectric conversion unit and configured to accumulate the charges generated in the second photoelectric conversion unit during an accumulation period; and

[0223] a capacitive connection unit configured to couple or separate the second charge modulation unit and the charge accumulation unit;

[0224] in,

[0225] In a state where the first charge modulation unit is independent and in a state where the first charge modulation unit and the second charge modulation unit are coupled via the modulation switch unit, the charge accumulated in the first photoelectric conversion unit is modulated into a voltage signal, and the voltage signals having different conversion efficiencies are continuously read;

[0226] Charge accumulated in the first photoelectric conversion unit and charge overflowed from the first photoelectric conversion unit during an accumulation period are modulated into a voltage signal, and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit and the second charge modulation unit; and

[0227] Furthermore, the charge generated in the second photoelectric conversion unit and accumulated in the charge accumulation unit is modulated into a voltage signal, and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit. (3)

[0229] The solid-state imaging device according to (2), further comprising:

[0230] The second charge transfer unit is provided between the second photoelectric conversion unit and the charge accumulation unit and is configured to transfer the charge accumulated in the second photoelectric conversion unit to the charge accumulation unit. (4)

[0232] The solid-state imaging device according to any one of (1) to (3), further including:

[0233] The charge resetting unit is provided between the second charge modulation unit and the power supply and is configured to reset the charges in the first charge modulation unit, the second charge modulation unit and the charge accumulation unit after reading the charges accumulated in the photoelectric conversion unit and the charges overflowing from the photoelectric conversion unit during the accumulation period. (5)

[0235] The solid-state imaging device according to (1), further comprising:

[0236] The third charge transfer unit is provided between the photoelectric conversion unit and the charge accumulation unit and is configured to transfer the charge overflowing from the photoelectric conversion unit during the accumulation period to the charge accumulation unit. (6)

[0238] The solid-state imaging device according to (5), further comprising:

[0239] The charge resetting unit is provided between the second charge modulation unit and the power supply and is configured to reset the charges of the first charge modulation unit and the second charge modulation unit before reading the charges accumulated in the photoelectric conversion unit. (7)

[0241] A method for driving a solid-state imaging device, the solid-state imaging device comprising:

[0242] Photoelectric conversion unit;

[0243] a charge transfer unit configured to transfer the charge accumulated in the photoelectric conversion unit;

[0244] a first charge modulation unit, to which charges are transferred from the photoelectric conversion unit via the charge transfer unit;

[0245] a second charge modulation unit;

[0246] a charge accumulation unit configured to accumulate charges overflowing from the photoelectric conversion unit during an accumulation period;

[0247] a modulation switch unit configured to couple or separate the first charge modulation unit and the second charge modulation unit; and

[0248] a capacitive connection unit configured to couple or separate the second charge modulation unit and the charge accumulation unit;

[0249] The method includes:

[0250] modulating the charge accumulated in the photoelectric conversion unit and continuously reading voltage signals having different conversion efficiencies in a state where the first charge modulation unit is independent and in a state where the first charge modulation unit and the second charge modulation unit are coupled through the modulation switch unit; and

[0251] The charges accumulated in the photoelectric conversion unit and the charges overflowing from the photoelectric conversion unit during the accumulation period are further modulated into a voltage signal by the modulation switch unit and the capacitance connection unit, and the voltage signal is read from the capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit and the charge accumulation unit. (8)

[0253] An electronic device provided with a solid-state imaging device, comprising:

[0254] Photoelectric conversion unit;

[0255] a charge transfer unit configured to transfer the charge accumulated in the photoelectric conversion unit;

[0256] a first charge modulation unit, to which charges are transferred from the photoelectric conversion unit via the charge transfer unit;

[0257] a second charge modulation unit;

[0258] a charge accumulation unit configured to accumulate charges overflowing from the photoelectric conversion unit during an accumulation period;

[0259] a modulation switch unit configured to couple or separate the first charge modulation unit and the second charge modulation unit; and

[0260] The capacitance connection unit is configured to couple or separate the second charge modulation unit and the charge accumulation unit; wherein,

[0261] In a state where the first charge modulation unit is independent and in a state where the first charge modulation unit and the second charge modulation unit are coupled via the modulation switch unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and the voltage signals having different conversion efficiencies are continuously read; and

[0262] In addition, the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal, and the voltage signal is read in the capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit and the charge accumulation unit through the modulation switch unit and the capacitance connection unit.

[0263] List of Figure Numbers

[0264] 10,10A,10B,40 pixels

[0265] 21 Photodiode (photoelectric conversion unit)

[0266] 22 floating diffusion region (charge accumulation unit)

[0267] 23,43 transfer transistors (transfer units)

[0268] 24,48 pixel internal capacitance

[0269] 25,44 conversion efficiency switching transistors (conversion efficiency switching units)

[0270] 26,46 accumulation transistors

[0271] 27,47 reset transistor (reset unit)

[0272] 28,52 amplifier transistors

[0273] 29,53 selection transistor

[0274] 30,54 constant current source

[0275] 41 High-sensitivity photodiode (first photoelectric conversion unit)

[0276] 42 first floating diffusion region (charge accumulation unit)

[0277] 45 second floating diffusion region (charge accumulation unit)

[0278] 50 low-sensitivity photodiode (second photoelectric conversion unit)

[0279] 51 third floating diffusion region (charge accumulation unit)

Claims

1. A solid-state imaging device comprising: Photoelectric conversion unit; a charge transfer unit configured to transfer charges accumulated in the photoelectric conversion unit; a first charge modulation unit, wherein the charge is transferred from the photoelectric conversion unit to the first charge modulation unit through the charge transfer unit; a second charge modulation unit; a modulation switch unit, configured to couple or separate the first charge modulation unit and the second charge modulation unit; a charge accumulation unit configured to accumulate charges overflowing from the photoelectric conversion unit during an accumulation period; as well as a capacitive connection unit configured to couple or separate the second charge modulation unit and the charge accumulation unit; in, modulating the charge accumulated in the photoelectric conversion unit into a voltage signal in a state where the first charge modulation unit is independent and in a state where the first charge modulation unit and the second charge modulation unit are coupled via the modulation switch unit, and continuously reading the voltage signals having different conversion efficiencies; and Further, the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal, and the voltage signal is read in the capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit and the charge accumulation unit through the modulation switch unit and the capacitance connection unit.

2. A solid-state imaging device comprising: a first photoelectric conversion unit; a first charge transfer unit configured to transfer the charge accumulated in the first photoelectric conversion unit; a first charge modulation unit, wherein the charge is transferred from the first photoelectric conversion unit to the first charge modulation unit through the first charge transfer unit; a second charge modulation unit; a modulation switch unit, configured to couple or separate the first charge modulation unit and the second charge modulation unit; a second photoelectric conversion unit; a charge accumulation unit directly connected to the second photoelectric conversion unit and configured to accumulate the charge generated in the second photoelectric conversion unit during an accumulation period; as well as a capacitive connection unit configured to couple or separate the second charge modulation unit and the charge accumulation unit; in, In a state where the first charge modulation unit is independent and in a state where the first charge modulation unit and the second charge modulation unit are coupled via the modulation switch unit, the charge accumulated in the first photoelectric conversion unit is modulated into a voltage signal, and the voltage signals having different conversion efficiencies are continuously read; the charges accumulated in the first photoelectric conversion unit and the charges overflowing from the first photoelectric conversion unit during the accumulation period are modulated into a voltage signal, and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit and the second charge modulation unit; and Further, the charge generated in the second photoelectric conversion unit and accumulated in the charge accumulation unit is modulated into a voltage signal, and the voltage signal is read in a capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit, and the charge accumulation unit.

3. The solid-state imaging device according to claim 2, further comprising: a second charge transfer unit provided between the second photoelectric conversion unit and the charge accumulation unit and configured to transfer the charge accumulated in the second photoelectric conversion unit to the charge accumulation unit.

4. The solid-state imaging device according to claim 2, further comprising: A charge resetting unit is provided between the second charge modulation unit and a power supply and is configured to reset the charges in the first charge modulation unit, the second charge modulation unit and the charge accumulation unit after the charges accumulated in the photoelectric conversion unit and the charges overflowing from the photoelectric conversion unit during the accumulation period are read.

5. The solid-state imaging device according to claim 2, further comprising: A third charge transfer unit is provided between the photoelectric conversion unit and the charge accumulation unit and is configured to transfer the charge overflowing from the photoelectric conversion unit during the accumulation period to the charge accumulation unit.

6. The solid-state imaging device according to claim 5, further comprising: A charge resetting unit is provided between the second charge modulation unit and a power supply and is configured to reset the charges in the first charge modulation unit and the second charge modulation unit before the charges accumulated in the photoelectric conversion unit are read.

7. A method of driving a solid-state imaging device, the solid-state imaging device comprising: Photoelectric conversion unit; a charge transfer unit configured to transfer charges accumulated in the photoelectric conversion unit; a first charge modulation unit, wherein the charge is transferred from the photoelectric conversion unit to the first charge modulation unit through the charge transfer unit; a second charge modulation unit; a charge accumulation unit configured to accumulate charges overflowing from the photoelectric conversion unit during an accumulation period; a modulation switch unit, configured to couple or separate the first charge modulation unit and the second charge modulation unit; as well as a capacitive connection unit configured to couple or separate the second charge modulation unit and the charge accumulation unit; The method comprises: In a state where the first charge modulation unit is independent and in a state where the first charge modulation unit and the second charge modulation unit are coupled via the modulation switch unit, the charge accumulated in the photoelectric conversion unit is modulated into a voltage signal, and the voltage signals having different conversion efficiencies are continuously read; and Further, the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal and the voltage signal is read in the capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit and the charge accumulation unit through the modulation switch unit and the capacitance connection unit.

8. An electronic device provided with a solid-state imaging device, comprising: Photoelectric conversion unit; a charge transfer unit configured to transfer charges accumulated in the photoelectric conversion unit; a first charge modulation unit, wherein the charge is transferred from the photoelectric conversion unit to the first charge modulation unit through the charge transfer unit; a second charge modulation unit; a charge accumulation unit configured to accumulate charges overflowing from the photoelectric conversion unit during an accumulation period; a modulation switch unit, configured to couple or separate the first charge modulation unit and the second charge modulation unit; as well as a capacitive connection unit configured to couple or separate the second charge modulation unit and the charge accumulation unit; in, modulating the charge accumulated in the photoelectric conversion unit into a voltage signal in a state where the first charge modulation unit is independent and in a state where the first charge modulation unit and the second charge modulation unit are coupled via the modulation switch unit, and continuously reading the voltage signals having different conversion efficiencies; and Further, the charge accumulated in the photoelectric conversion unit and the charge overflowing from the photoelectric conversion unit during the accumulation period are modulated into a voltage signal, and the voltage signal is read in the capacitance obtained by coupling the first charge modulation unit, the second charge modulation unit and the charge accumulation unit through the modulation switch unit and the capacitance connection unit.

Images