Driving circuit, driving method and display panel

Abstract

The present application provides a driving circuit, a driving method and a display panel, wherein the driving circuit includes a driving transistor, a first light-emitting control module, a second light-emitting control module, a light-emitting device and a writing module. The use of the driving circuit can avoid the continuous writing of data signals in a low-frequency state causing the voltage of the first electrode of the driving transistor to change, thereby causing the voltage difference between the first electrode and the gate of the driving transistor to change, causing the threshold voltage of the driving transistor to drift, and thus causing the display panel to flicker.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a driving circuit, a driving method and a display panel. Background Art

[0002] Judging from the current market applications, low-temperature polysilicon products will be used more and more widely in high-end flagships. As the core performance indicators of low-temperature polysilicon products, low power consumption and low-frequency flicker are increasingly becoming important considerations that limit product quality. Therefore, the power consumption and flicker requirements of low-temperature polysilicon products are becoming more and more stringent.

[0003] In the existing pixel driving circuit, the data signal will not be written normally in the low-frequency state. The gate node of the low-frequency (10 Hz or 1 Hz) driving transistor has a long non-writing time, and during the frame skipping period, the data signal will continue to be written to the source of the driving transistor, causing the three-terminal voltage of the driving transistor to change. Affected by the hysteresis characteristics of the transistor, the threshold voltage of the driving transistor will drift, which will eventually manifest as inconsistent luminous brightness between the data signal writing frame and the frame skipping frame. This brightness difference will cause regular changes in brightness, which will cause the display panel to flicker. Summary of the invention

[0004] The present application provides a driving circuit, a driving method and a display panel, which can solve the problem that the threshold voltage of the driving transistor drifts due to continuous writing of data signals in the existing driving circuit, thereby causing flickering of the display panel.

[0005] In a first aspect, the present application provides a driving circuit, which includes: a driving transistor, a first light-emitting control module, a second light-emitting control module, a light-emitting device and a writing module, wherein the gate of the driving transistor is electrically connected to a first node, the first electrode of the driving transistor is electrically connected to a second node, and the second electrode of the driving transistor is electrically connected to a third node; the first light-emitting control module receives a first light-emitting control signal and is electrically connected to the second node and a first power supply terminal, and the first light-emitting control module is used to control the conduction or disconnection between the first power supply terminal and the second node under the control of the first light-emitting control signal; the second light-emitting control module receives a second light-emitting control signal and is electrically connected to the third node to and a fourth node, the second light-emitting control module is used to control the conduction or disconnection between the third node and the fourth node under the control of the second light-emitting control signal; the first end of the light-emitting device is electrically connected to the fourth node, and the second end of the light-emitting device is electrically connected to the second power supply end; the writing module receives the data signal, the first scanning signal and the second scanning signal, and is electrically connected to the first node, the second node and the third node, the writing module is used to output the data signal to the first node under the control of the first scanning signal and the second scanning signal; the writing module is also used to disconnect the line between the data signal and the second node under the control of the second scanning signal.

[0006] Optionally, in an embodiment of the present application, the write module includes a first transistor, a second transistor, a third transistor and a first capacitor, the gate of the first transistor is connected to the first scanning signal, the first electrode of the first transistor is connected to the data signal, and the second electrode of the first transistor is electrically connected to the fifth node; the gate of the second transistor is connected to the second scanning signal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the second node; the gate of the third transistor is connected to the second scanning signal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first node; one end of the first capacitor is connected to the first scanning signal, and the other end of the first capacitor is electrically connected to the first node.

[0007] Optionally, in an embodiment of the present application, the writing module further includes a second capacitor, one end of the second capacitor is electrically connected to the first power supply end, and the other end of the second capacitor is electrically connected to the first node.

[0008] Optionally, in an embodiment of the present application, the writing module further includes a third capacitor, one end of the third capacitor is electrically connected to the first power supply end, and the other end of the third capacitor is electrically connected to the fifth node.

[0009] Optionally, in an embodiment of the present application, the driving circuit also includes a reset module, which is connected to a first reset signal, a second reset signal, a third scan signal and a fourth scan signal, and is electrically connected to the first node and the fourth node. The reset module is used to output the first reset signal to the first node under the control of the third scan signal, and the reset module is also used to output the second reset signal to the fourth node under the control of the fourth scan signal.

[0010] Optionally, in an embodiment of the present application, the reset module includes a fourth transistor and a fifth transistor; the gate of the fourth transistor is connected to the third scanning signal, the first electrode of the fourth transistor is connected to the first reset signal, and the second electrode of the fourth transistor is electrically connected to the first node; the gate of the fifth transistor is connected to the fourth scanning signal, the first electrode of the fifth transistor is connected to the second reset signal, and the second electrode of the fifth transistor is electrically connected to the fourth node.

[0011] Optionally, in an embodiment of the present application, the first light-emitting control module includes a sixth transistor, a gate of the sixth transistor is connected to the first light-emitting control signal, a first electrode of the sixth transistor is electrically connected to the first power supply terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

[0012] Optionally, in an embodiment of the present application, the second light-emitting control module includes a seventh transistor, a gate of the seventh transistor is connected to the second light-emitting control signal, a first electrode of the seventh transistor is electrically connected to the third node, and a second electrode of the seventh transistor is electrically connected to the fourth node.

[0013] In a second aspect, the present application further provides a driving method for driving the driving circuit described above, the driving method comprising: in a data writing stage, the first light-emitting control module controls the disconnection between the first power supply terminal and the second node under the control of the first light-emitting control signal, the second light-emitting control module controls the disconnection between the third node and the fourth node under the control of the second light-emitting control signal, and the writing module outputs the data signal to the first node under the control of the first scanning signal and the second scanning signal;

[0014] In the control stage, the first light-emitting control module controls the disconnection between the first power supply terminal and the second node under the control of the first light-emitting control signal, the second light-emitting control module controls the disconnection between the third node and the fourth node under the control of the second light-emitting control signal, and the writing module disconnects the line between the data signal and the second node under the control of the first scanning signal and the second scanning signal.

[0015] In a third aspect, the present application further provides a display panel, wherein the display panel comprises a plurality of pixels arranged in an array, and each of the pixels comprises the driving circuit described above.

[0016] The present application provides a driving circuit, a driving method and a display panel, wherein the driving circuit includes a driving transistor, a first light-emitting control module, a second light-emitting control module, a light-emitting device and a writing module. The use of the driving circuit can avoid the continuous writing of data signals in a low-frequency state causing the voltage of the first electrode of the driving transistor to change, thereby causing the voltage difference between the first electrode and the gate of the driving transistor to change, causing the threshold voltage of the driving transistor to drift, and thus causing the display panel to flicker. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the structure of a driving circuit provided in an embodiment of the present application;

[0019] Figure 2 A first circuit diagram of a driving circuit provided in an embodiment of the present application;

[0020] Figure 3a A second circuit diagram of a driving circuit provided in an embodiment of the present application;

[0021] Figure 3b A third circuit schematic diagram of the driving circuit provided in the embodiment of the present application;

[0022] Figure 3c A fourth circuit schematic diagram of a driving circuit provided in an embodiment of the present application;

[0023] Figure 4a A fifth circuit diagram of the driving circuit provided in the embodiment of the present application;

[0024] Figure 4bA sixth circuit diagram of the driving circuit provided in an embodiment of the present application;

[0025] Figure 5a A seventh circuit diagram of the driving circuit provided in the embodiment of the present application;

[0026] Figure 5b An eighth circuit diagram of the driving circuit provided in the embodiment of the present application;

[0027] Figure 6 A ninth circuit diagram of a driving circuit provided in an embodiment of the present application;

[0028] Figure 7 for Figure 6 The timing diagram of the driving circuit shown;

[0029] Figure 8 A schematic diagram of voltage simulation of each node in a low-frequency frame provided in an embodiment of the present application;

[0030] Fig. 9 A schematic diagram of a driving method according to an embodiment of the present invention;

[0031] Fig.10 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0033] The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the first electrode and the second electrode of the transistor used here are symmetrical, the first electrode and the second electrode are interchangeable. In the embodiments of the present application, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called the first electrode and the other is called the second electrode.

[0034] In addition, the transistors used in the embodiments of the present application may include P-type transistors and / or N-type transistors, wherein the P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level.

[0035] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of the driving circuit provided in the embodiment of the present application. Figure 1As shown, the driving circuit provided in the embodiment of the present application includes a light-emitting device D, a driving transistor T0, a writing module 101, a first light-emitting control module 102 and a second light-emitting control module 103.

[0036] It should be noted that the light-emitting device D may be a micro light-emitting diode (Micro Light Emitting Diode, Micro-LED), a mini light-emitting diode (Mini Light Emitting Diode, Mini-LED) or an organic light-emitting diode (Organic Light-Emitting Diode, OLED). In some embodiments, the light-emitting device DD may include a Micro-LED, a Mini-LED or an OLED. In other embodiments, the light-emitting device DD may include multiple Micro-LEDs, multiple Mini-LEDs or multiple OLEDs, and multiple Micro-LEDs may be arranged in series or in parallel, and multiple Mini-LEDs and multiple OLEDs may be arranged in series or in parallel.

[0037] The light emitting device D is connected in series to a light emitting circuit formed by a first power supply terminal VDD and a second power supply terminal VSS. Specifically, the first power supply terminal VDD and the second power supply terminal VSS are both DC voltage sources. The gate of the driving transistor T0 is electrically connected to the first node Q, the first electrode of the driving transistor T0 is electrically connected to the second node A, and the second electrode of the driving transistor T0 is electrically connected to the third node B; the writing module 101 is connected to the data signal DATA, the first scanning signal SCAN1 and the second scanning signal SCAN2, and is electrically connected to the first node Q, the second node A and the third node B. The first light emitting control module 102 is connected to the first light emitting control signal EM1, and is electrically connected to the first power supply terminal VDD and the second node A; the second light emitting control module 103 is connected to the second light emitting control signal EM2, and is electrically connected to the third node B and the fourth node C. The first end of the light emitting device D is electrically connected to the fourth node C, and the second end of the light emitting device D is electrically connected to the second power supply terminal VSS.

[0038] Specifically, the driving transistor T0 is used to control the current flowing through the driving circuit. The writing module 101 is used to output the data signal DATA to the first node Q under the control of the first scan signal SCAN1 and the second scan signal SCAN2, and control the output of the data signal DATA under the control of the second scan signal SCAN2. The first light-emitting control module 102 is used to control the connection or disconnection between the first power supply terminal VDD and the second node A under the control of the first light-emitting control signal EM1. The second light-emitting control module 103 is used to control the connection or disconnection between the third node B and the fourth node C under the control of the second light-emitting control signal EM2.

[0039] It should be noted that the first node Q, the second node A, the third node B and the fourth node C are all represented as nodes electrically connected to the corresponding devices, and are only represented as electrical connection relationships. The first node Q, the second node A, the third node B and the fourth node C are not represented as terminals.

[0040] In some embodiments, see Figure 2 , Figure 2 The first circuit diagram of the driving circuit provided in the embodiment of the present application is shown in FIG. Figure 1 , Figure 2 As shown, the writing module 101 includes a first transistor T1, a second transistor T2, a third transistor T3 and a first capacitor C1, the gate of the first transistor T1 is connected to the first scanning signal SCAN1, the first electrode of the first transistor T1 is connected to the data signal DATA, and the second electrode of the first transistor T1 is electrically connected to the fifth node E; the gate of the second transistor T2 is connected to the second scanning signal SCAN2, the first electrode of the second transistor T2 is electrically connected to the fifth node E, and the second electrode of the second transistor T2 is electrically connected to the second node A; the gate of the third transistor T3 is connected to the second scanning signal SCAN2, the first electrode of the third transistor T3 is electrically connected to the third node B, and the second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to the first scanning signal SCAN, and the other end of the first capacitor C1 is electrically connected to the first node Q. Among them, the driving transistor T0 and the first transistor T1 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors. The first capacitor C1 is used to store the potential corresponding to the data signal.

[0041] In some embodiments, see Figure 3a , Figure 3a A second circuit diagram of a driving circuit provided in an embodiment of the present application. Figure 1 , Figure 3aAs shown, the writing module includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1 and a second capacitor C2, the gate of the first transistor T1 is connected to the first scanning signal SCAN1, the first electrode of the first transistor T1 is connected to the data signal DATA, and the second electrode of the first transistor T1 is electrically connected to the fifth node E; the gate of the second transistor T2 is connected to the second scanning signal SCAN2, the first electrode of the second transistor T2 is electrically connected to the fifth node E, and the second electrode of the second transistor T2 is electrically connected to the second node A; the gate of the third transistor T3 is connected to the second scanning signal SCAN2, the first electrode of the third transistor T3 is electrically connected to the third node B, and the second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to the first scanning signal SCAN, and the other end of the first capacitor C1 is electrically connected to the first node Q. Among them, the driving transistor T0 and the first transistor T1 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors; one end of the second capacitor C2 is electrically connected to the first power supply terminal VDD, and the other end of the second capacitor C2 is electrically connected to the first node Q. This design is different from the capacitor design electrically connected to the variable signal in the prior art. One end of the second capacitor C2 is electrically connected to the first power supply end and the other end is electrically connected to the first node Q, so that the second capacitor C2 can not only be used to store the corresponding potential of the data signal DATA, but also achieve a voltage stabilizing effect on the first node Q.

[0042] In some embodiments, see Figure 3b , Figure 3b This is a third circuit diagram of the driving circuit provided in the embodiment of the present application. Figure 1 , Figure 3bAs shown, the writing module 101 includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1 and a third capacitor C3, the gate of the first transistor T1 is connected to the first scan signal SCAN1, the first electrode of the first transistor T1 is connected to the data signal DATA, and the second electrode of the first transistor T1 is electrically connected to the fifth node E; the gate of the second transistor T2 is connected to the second scan signal SCAN2, the first electrode of the second transistor T2 is electrically connected to the fifth node E, and the second electrode of the second transistor T2 is electrically connected to the second node A; the gate of the third transistor T3 is connected to the second scan signal SCAN2, the first electrode of the third transistor T3 is electrically connected to the third node B, and the second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to the first scan signal SCAN, and the other end of the first capacitor C1 is electrically connected to the first node Q. Among them, the driving transistor T0 and the first transistor T1 are P-type transistors, the second transistor T2 and the third transistor T3 are N-type transistors; one end of the third capacitor C3 is electrically connected to the first power supply terminal VDD, and the other end of the third capacitor C3 is electrically connected to the fifth node E. This design is different from the capacitor design electrically connected to the variable signal in the prior art. One end of the third capacitor C3 is electrically connected to the first power supply end and the other end is electrically connected to the fifth node E, so that the third capacitor C3 can not only be used to store the corresponding potential of the data signal DATA, but also achieve the voltage stabilization effect on the fifth node E.

[0043] In some embodiments, see Figure 3c , Figure 3c This is a fourth circuit diagram of a driving circuit provided in an embodiment of the present application. Figure 1 , Figure 3cAs shown, the write module 101 includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a second capacitor C2 and a third capacitor C3, the gate of the first transistor T1 is connected to the first scan signal SCAN1, the first electrode of the first transistor T1 is connected to the data signal DATA, and the second electrode of the first transistor T1 is electrically connected to the fifth node E; the gate of the second transistor T2 is connected to the second scan signal SCAN2, the first electrode of the second transistor T2 is electrically connected to the fifth node E, and the second electrode of the second transistor T2 is electrically connected to the second node A; the gate of the third transistor T3 is connected to the second scan signal SCAN2, the first electrode of the third transistor T3 is electrically connected to the third node B, and the second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to the first scan signal SCAN, and the other end of the first capacitor C1 is electrically connected to the first node Q; one end of the second capacitor C2 is electrically connected to the first power supply terminal VDD, and the other end of the second capacitor C2 is electrically connected to the first node Q; one end of the third capacitor C3 is electrically connected to the first power supply terminal VDD, and the other end of the third capacitor C3 is electrically connected to the fifth node E. The driving transistor T0 and the first transistor T1 are P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors.

[0044] In some embodiments, see Figure 4a , Figure 4a This is a fifth circuit diagram of the driving circuit provided in the embodiment of the present application. Figure 1 , Figure 4a As shown, the driving circuit further includes a reset module 104, the reset module 104 is connected to the first reset signal VINI1, the second reset signal VINI2, the third scan signal SCAN3 and the fourth scan signal SCAN4, and is electrically connected to the first node Q and the fourth node C. The reset module 104 is used to output the first reset signal VINI1 to the first node Q under the control of the third scan signal SCAN3, and the reset module 104 is also used to output the second reset signal VINI2 to the fourth node C under the control of the fourth scan signal SCAN4.

[0045] In some embodiments, see Figure 4b , Figure 4b This is a sixth circuit diagram of the driving circuit provided in the embodiment of the present application. Figure 1 , Figure 4bAs shown, the reset module 104 includes a fourth transistor T4 and a fifth transistor T5; the gate of the fourth transistor T4 is connected to the third scan signal SCAN3, the first electrode of the fourth transistor T4 is connected to the first reset signal VINI1, and the second electrode of the fourth transistor T4 is electrically connected to the first node Q; the gate of the fifth transistor T5 is connected to the fourth scan signal SCAN4, the first electrode of the fifth transistor T5 is connected to the second reset signal VINI2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node C. Preferably, the fourth transistor T4 is an N-type transistor, and the fifth transistor T5 is a P-type transistor.

[0046] In some embodiments, see Figure 5a , Figure 5a This is a seventh circuit diagram of a driving circuit provided in an embodiment of the present application. Figure 1 , Figure 5a As shown, the first light-emitting control module 102 includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the first light-emitting control signal EM1, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the second node A. It should be noted that the specific circuit structure of the first light-emitting control module in the driving circuit provided in the embodiment of the present application is only an example, and it can be understood that the first light-emitting control module can also be formed by connecting multiple transistors in series.

[0047] In some embodiments, see Figure 5b , Figure 5b This is an eighth circuit diagram of the driving circuit provided in the embodiment of the present application. Figure 1 , Figure 5b As shown, the second light emitting control module 103 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the second light emitting control signal EM2, the first electrode of the seventh transistor T7 is electrically connected to the third node B, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node C. It should be noted that the specific circuit structure of the second light emitting control module in the driving circuit provided in the embodiment of the present application is only an example, and it can be understood that the second light emitting control module can also be formed by connecting multiple transistors in series.

[0048] Furthermore, the present application embodiment will describe a complete circuit of the driving circuit. Figure 6 , Figure 6 This is a ninth circuit diagram of a driving circuit provided in an embodiment of the present application. Figure 6 As shown, the driving circuit provided in the embodiment of the present application includes a light-emitting device D, a driving transistor T0, a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a second capacitor C2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.

[0049] It should be noted that the driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be one or more of a low-temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor or an amorphous silicon thin film transistor. Preferably, the driving transistor T0, the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are P-type transistors, and the second transistor T2, the third transistor T3 and the fourth transistor T4 are N-type transistors.

[0050] In some embodiments, the transistors in the driving circuit provided in the embodiments of the present application may be set to be transistors of the same type, thereby avoiding the influence of the differences between different types of transistors on the driving circuit.

[0051] Among them, the gate of the first transistor T1 is connected to the first scan signal SCAN1, the first electrode of the first transistor T1 is connected to the data signal DATA, and the second electrode of the first transistor T1 is electrically connected to the fifth node E; the gate of the second transistor T2 is connected to the second scan signal SCAN2, the first electrode of the second transistor T2 is electrically connected to the fifth node E, and the second electrode of the second transistor T2 is electrically connected to the second node A; the gate of the third transistor T3 is connected to the second scan signal SCAN2, the first electrode of the third transistor T3 is electrically connected to the third node B, and the second electrode of the third transistor T3 is electrically connected to the first node Q; one end of the first capacitor C1 is connected to the first scan signal SCAN, and the other end of the first capacitor C1 is electrically connected to the first node Q; one end of the second capacitor C2 is electrically connected to the first power supply terminal VDD, and the other end of the second capacitor C2 is electrically connected to the first node Q; the gate of the fourth transistor T4 is connected to the third scan signal SCAN2, the first electrode of the third transistor T3 is electrically connected to the third node B, and the second electrode of the third transistor T3 is electrically connected to the first node Q. signal SCAN3, the first electrode of the fourth transistor T4 is connected to the first reset signal VINI1, and the second electrode of the fourth transistor T4 is electrically connected to the first node Q; the gate of the fifth transistor T5 is connected to the fourth scan signal SCAN4, the first electrode of the fifth transistor T5 is connected to the second reset signal VINI2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node C; the gate of the sixth transistor T6 is connected to the first light-emitting control signal EM1, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the second node A; the gate of the seventh transistor T7 is connected to the second light-emitting control signal EM2, the first electrode of the seventh transistor T7 is electrically connected to the third node B, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node C; the first end of the light-emitting device D is electrically connected to the fourth node C, and the second end of the light-emitting device D is electrically connected to the second power supply terminal VSS.

[0052] See also Figure 7 , Figure 7 for Figure 1 The timing diagram of the driving circuit shown in FIG. Figure 1 , Figure 6 , Figure 7 As shown, the driving timing of the driving circuit provided in the embodiment of the present application includes a data writing phase t2, a control phase t3 and a light emitting phase t4.

[0053] In the data writing stage t2, the first light-emitting control module 102 controls the disconnection between the first power supply terminal VDD and the second node A under the control of the first light-emitting control signal EM1, and the second light-emitting control module 103 controls the disconnection between the third node B and the fourth node C under the control of the second light-emitting control signal EM2. The writing module 101 outputs the data signal DATA to the first node Q under the control of the first scanning signal SCAN1 and the second scanning signal SCAN2.

[0054] In the control stage t3, the first light-emitting control module 102 controls the disconnection between the first power supply terminal VDD and the second node A under the control of the first light-emitting control signal EM1, the second light-emitting control module 103 controls the disconnection between the third node B and the fourth node C under the control of the second light-emitting control signal EM2, and the write module 101 disconnects the line between the data signal DATA and the second node A under the control of the first scan signal SCAN1 and the second scan signal SCAN2.

[0055] In the light emitting stage t4, the light emitting device D emits light.

[0056] Optionally, in some embodiments, the driving circuit further includes a reset module 104, and the driving timing of the driving circuit further includes a reset phase t1. In the reset phase t1, the reset module 104 writes the potential of the first reset signal VINI1 into the first node Q under the control of the first reset signal VINI1.

[0057] In the data writing phase t2, under the control of the second reset signal VINI2, the reset module 104 writes the potential of the second reset signal VINI2 into the fourth node C. This configuration is conducive to avoiding the mutual influence between the two reset signals.

[0058] The driving circuit provided in the present application includes a light-emitting device D, a driving transistor T0, a writing module 101, a first light-emitting control module 102 and a second light-emitting control module 103. The use of this driving circuit can avoid the continuous writing of the data signal DATA in a low-frequency state causing the voltage of the first electrode of the driving transistor T0 to change, thereby causing the voltage difference between the first electrode and the gate of the driving transistor T0 to change, causing the threshold voltage of the driving transistor T0 to drift, and then causing the display panel to flicker.

[0059] See also Figure 8 Combined with Figure 1 , Figure 6 as well as Figure 7 , Figure 8 This is a schematic diagram of voltage simulation of each node in a low-frequency frame provided by an embodiment of the present application. Figure 8 As shown, in the low frequency state, the voltage of the first electrode and the gate of the driving transistor T0 tend to be stable, and the voltage difference (V gs ) has no obvious change, that is, the voltages of the first node Q and the second node A are stable.

[0060] The present application sets a second transistor T2 controlled by a second scan signal SCAN2 to shield the voltage of the first electrode of the driving transistor T0 caused by continuous writing of the data signal DATA in a low-frequency state, thereby causing the voltage difference between the first electrode and the gate of the driving transistor T0 to change, causing the threshold voltage of the driving transistor T0 to drift, thereby causing the display panel to flicker, ensuring the stability of the first electrode, the second electrode and the gate voltage of the driving transistor T0 in a low-frequency state, thereby improving the stability of the driving transistor T0.

[0061] See also Fig. 9 , Fig. 9 Schematic diagram of the process of the driving method provided in the embodiment of the present application. Fig. 9 As shown, the driving method provided in the embodiment of the present application is used for the above driving circuit. The driving method comprises the following steps:

[0062] S10, data writing stage, the first light-emitting control module 102 controls the disconnection between the first power supply terminal VDD and the second node A under the control of the first light-emitting control signal EM1, the second light-emitting control module 103 controls the disconnection between the third node B and the fourth node C under the control of the second light-emitting control signal EM2, and the writing module 101 outputs the data signal DATA to the first node Q under the control of the first scanning signal SCAN1 and the second scanning signal SCAN2.

[0063] S20, control stage, the first light-emitting control module 102 controls the disconnection between the first power supply terminal VDD and the second node A under the control of the first light-emitting control signal EM1, the second light-emitting control module 103 controls the disconnection between the third node B and the fourth node C under the control of the second light-emitting control signal EM2, and the writing module 101 disconnects the line between the data signal DATA and the second node A under the control of the first scanning signal SCAN1 and the second scanning signal SCAN2.

[0064] S30, light emitting stage, the light emitting device D emits light.

[0065] Optionally, in some embodiments, the driving method further includes a reset stage, and the reset module 104 writes the potential of the first reset signal VINI1 into the first node Q under the control of the first reset signal VINI1.

[0066] In some embodiments, during the reset phase, the reset module 104 writes the potential of the second reset signal VINI2 into the fourth node C under the control of the second reset signal VINI2.

[0067] Optionally, in some embodiments, during the data writing phase, the reset module 104, under the control of the second reset signal VINI2, writes the potential of the second reset signal VINI2 into the fourth node C. This configuration is conducive to avoiding mutual influence between the two reset signals.

[0068] See also Fig.10 , Fig.10 The present invention also provides a display panel 100, including a plurality of pixels 20 arranged in an array, each pixel 11 including the above driving circuit 10, and the above description of the driving circuit 10 may be referred to, and will not be repeated here.

[0069] The driving circuit in the display panel provided in the present application includes a light-emitting device D, a driving transistor T0, a writing module 101, a first light-emitting control module 102 and a second light-emitting control module 103. The use of this driving circuit can avoid the continuous writing of the data signal DATA in a low-frequency state causing the voltage of the first electrode of the driving transistor T0 to change, thereby causing the voltage difference between the first electrode and the gate of the driving transistor T0 to change, causing the threshold voltage of the driving transistor T0 to drift, and then causing the display panel to flicker.

[0070] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: include: a driving transistor, wherein a gate of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the second node, and a second electrode of the driving transistor is electrically connected to the third node; a first light-emitting control module, the first light-emitting control module receiving a first light-emitting control signal and electrically connected to the second node and the first power supply terminal, the first light-emitting control module being used to control conduction or disconnection between the first power supply terminal and the second node under the control of the first light-emitting control signal; a second light-emitting control module, the second light-emitting control module receiving a second light-emitting control signal and electrically connected to the third node and the fourth node, the second light-emitting control module being used to control conduction or disconnection between the third node and the fourth node under the control of the second light-emitting control signal; a light emitting device, wherein a first terminal of the light emitting device is electrically connected to the fourth node, and a second terminal of the light emitting device is electrically connected to the second power supply terminal; A write module, the write module receives a data signal, a first scan signal and a second scan signal, and is electrically connected to the first node, the second node and the third node, the write module is used to output the data signal to the first node under the control of the first scan signal and the second scan signal; the write module is also used to disconnect the line between the data signal and the second node under the control of the second scan signal.

2. The driving circuit according to claim 1, characterized in that: The writing module includes a first transistor, a second transistor, a third transistor and a first capacitor; The gate of the first transistor is connected to the first scanning signal, the first electrode of the first transistor is connected to the data signal, and the second electrode of the first transistor is electrically connected to the fifth node; The gate of the second transistor is connected to the second scanning signal, the first electrode of the second transistor is electrically connected to the fifth node, and the second electrode of the second transistor is electrically connected to the second node; The gate of the third transistor is connected to the second scanning signal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first node; One end of the first capacitor is connected to the first scanning signal, and the other end of the first capacitor is electrically connected to the first node.

3. The driving circuit according to claim 2, characterized in that: The writing module further includes a second capacitor, one end of the second capacitor is electrically connected to the first power supply end, and the other end of the second capacitor is electrically connected to the first node.

4. The driving circuit according to claim 2, characterized in that: The writing module further includes a third capacitor, one end of the third capacitor is electrically connected to the first power supply end, and the other end of the third capacitor is electrically connected to the fifth node.

5. The driving circuit according to claim 1, characterized in that: The driving circuit also includes a reset module, which is connected to a first reset signal, a second reset signal, a third scan signal and a fourth scan signal, and is electrically connected to the first node and the fourth node. The reset module is used to output the first reset signal to the first node under the control of the third scan signal, and the reset module is also used to output the second reset signal to the fourth node under the control of the fourth scan signal.

6. The driving circuit according to claim 5, characterized in that: The reset module includes a fourth transistor and a fifth transistor; The gate of the fourth transistor is connected to the third scanning signal, the first electrode of the fourth transistor is connected to the first reset signal, and the second electrode of the fourth transistor is electrically connected to the first node; A gate of the fifth transistor is connected to the fourth scan signal, a first electrode of the fifth transistor is connected to the second reset signal, and a second electrode of the fifth transistor is electrically connected to the fourth node.

7. The driving circuit according to claim 1, characterized in that: The first light emitting control module includes a sixth transistor, a gate of the sixth transistor is connected to the first light emitting control signal, a first electrode of the sixth transistor is electrically connected to the first power supply terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

8. The driving circuit according to claim 1, characterized in that: The second light emitting control module includes a seventh transistor, a gate of the seventh transistor is connected to the second light emitting control signal, a first electrode of the seventh transistor is electrically connected to the third node, and a second electrode of the seventh transistor is electrically connected to the fourth node.

9. A driving method, used for driving the driving circuit according to any one of claims 1 to 8, characterized in that: The driving method comprises: In the data writing stage, the first light-emitting control module controls the disconnection between the first power supply terminal and the second node under the control of the first light-emitting control signal, the second light-emitting control module controls the disconnection between the third node and the fourth node under the control of the second light-emitting control signal, and the writing module outputs the data signal to the first node under the control of the first scanning signal and the second scanning signal; In the control stage, the first light-emitting control module controls the disconnection between the first power supply terminal and the second node under the control of the first light-emitting control signal, the second light-emitting control module controls the disconnection between the third node and the fourth node under the control of the second light-emitting control signal, and the writing module disconnects the line between the data signal and the second node under the control of the first scanning signal and the second scanning signal.

10. A display panel, characterized in that: The display panel comprises a plurality of pixels arranged in an array, and each of the pixels comprises the driving circuit according to any one of claims 1 to 8.

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