Display panel and display device

Abstract

The application provides a display panel, which comprises an array substrate, a counter substrate and a liquid crystal layer arranged between the array substrate and the counter substrate. A display area of the array substrate comprises a plurality of pixel units for performing image display, each of the pixel units comprises a liquid crystal capacitor and a storage capacitor, the liquid crystal capacitor is connected with a first common electrode line, and the storage capacitor is connected with a second common electrode line. A switch unit is connected with the first common electrode line and the second common electrode line, and is used for electrically connecting the first common electrode line and the second common electrode line when power is turned off, so that the liquid crystal capacitor and the storage capacitor have the same voltage and discharging speed, thereby avoiding screen flickering and image sticking, and effectively improving display effect. The application further provides a display device comprising the display panel.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to display panels and display devices. Background Technology

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has become the mainstream technology in the display field due to its low power consumption, relatively low manufacturing cost, and lack of radiation.

[0003] In practical use, LCDs are prone to screen flickering and even image retention, especially during power-off. These issues can severely impact the user experience. Therefore, addressing screen flickering and image retention during power-off is a crucial factor to consider in LCD design and manufacturing to maximize the user experience. Summary of the Invention

[0004] This application aims to provide a display panel and a display device including the display panel, for improving the screen flickering phenomenon and possible image retention problem when the display panel is turned off.

[0005] On one hand, this application provides a display panel, including an array substrate, a counter substrate, and a liquid crystal layer sandwiched between the array substrate and the counter substrate. The array substrate includes a display area and a non-display area surrounding the display area. The display area includes a plurality of pixel units for performing image display. Corresponding to each pixel unit, the array substrate includes a pixel electrode and a storage capacitor. The counter substrate includes a first common electrode. The pixel electrode and the first common electrode constitute a liquid crystal capacitor. Corresponding to the non-display area, the array substrate is provided with a first common electrode line connected to the first common electrode. Corresponding to the display area, the array substrate includes a plurality of electrically connected second common electrode lines, which are connected to the storage capacitor. The display panel further includes a switching unit connected to the first common electrode line and any one of the second common electrode lines. The switching unit is used to electrically connect the first common electrode line and the second common electrode line when the display panel is powered off.

[0006] In some embodiments, the array substrate corresponding to the non-display area is further provided with a low-voltage DC signal line and a scan driving unit. The low-voltage DC signal line is used to output a low-voltage signal to the scan driving unit when the display panel is working normally. The scan driving unit is used to output a scan signal to the pixel unit to control the pixel unit to receive the image display signal and perform image display. The switching unit includes a first switching transistor, which includes a first control terminal, a first conductive terminal, and a second conductive terminal. The first control terminal of the first switching transistor is connected to the low-voltage DC signal line, the first conductive terminal is connected to the first common electrode line, and the second conductive terminal is connected to the second common electrode line. When the display panel is powered off, the low-voltage DC signal line outputs a first control signal to the first control terminal to control the switching transistor to turn on. The first common electrode line is electrically connected to the second common electrode line through the first conductive terminal, the second conductive terminal, and the second common electrode line.

[0007] In some embodiments, when the display panel is powered on and operating, the low-voltage DC signal line is used to output a low-voltage signal to the scanning drive unit. When the display panel is powered off, the low-voltage DC signal line outputs a high-voltage signal to the scanning drive unit. The high-voltage signal also serves as a first control signal to control the switching transistor to turn on.

[0008] In some embodiments, when the display panel is powered on, the low-voltage signal output by the low-voltage DC signal line is used as a second control signal and transmitted to the first control terminal to control the first switching transistor to turn off, thereby controlling the first conductive terminal to electrically disconnect from the second conductive terminal.

[0009] In some embodiments, the array substrate corresponding to the non-display area is further provided with a first low-frequency DC signal line, a second low-frequency DC signal line, and a scan driving unit. The first low-frequency DC signal line outputs a first low-frequency DC signal, and the second low-frequency DC signal line outputs a second low-frequency DC signal. The first low-frequency DC signal and the second low-frequency DC signal are signals with opposite polarities and change periodically, and are used to switch the operating state of the scan driving unit. The switching unit includes a second switching transistor and a third switching transistor. The second switching transistor includes a second control terminal, a third conductive terminal, and a fourth conductive terminal. The third switching transistor includes a third control terminal, a fifth conductive terminal, and a sixth conductive terminal. The second control terminal of the second switching transistor is connected to the first low-frequency DC signal line. The third control terminal of the third switch is connected to the second low-frequency DC signal line, the third conductive terminal is connected to the first common electrode line, the fourth conductive terminal is connected to the fifth conductive terminal, and the sixth conductive terminal is connected to the second common electrode line. When the second switch and the third switch are powered off on the display panel, the first low-frequency DC signal line outputs a third control signal to the second control terminal to control the second switch to turn on. At the same time, the second low-frequency DC signal line outputs a fourth control signal to the third control terminal to control the third switch to turn on. The fourth control signal is the same as the third control signal. The first common electrode line is electrically connected to the second common electrode line through the first switch, the second switch, and the first common electrode line.

[0010] In some embodiments, when the display panel is powered on, the first low-frequency DC signal line is used to output a first low-frequency DC signal to the scanning drive unit, and the second low-frequency DC signal line is used to output a second low-frequency DC signal to the scanning drive unit. When the display panel is powered off, both the first low-frequency DC signal line and the second low-frequency DC signal line output high-voltage signals as the third control signal and the fourth control signal.

[0011] In some embodiments, when the display panel is powered on, the first low-frequency DC signal and the second low-frequency DC signal alternately control one of the second switching transistors to be turned off, thereby controlling the first common electrode line and the second common electrode line to be electrically disconnected.

[0012] In some embodiments, the first common electrode receives a first common voltage from the first common electrode line, the pixel electrode receives a data voltage corresponding to the image display signal, and the liquid crystal capacitor drives the liquid crystal molecules in the liquid crystal layer to rotate and perform image display under the drive of the first common voltage and the data voltage; the storage capacitor includes a storage electrode and a second common electrode, the storage electrode receives the data voltage, the second common electrode receives a second common voltage from the second common electrode line, and the first common voltage and the data voltage cooperate to maintain the voltage of the liquid crystal capacitor for a preset time period.

[0013] In some implementations, the voltage value of the second common voltage is greater than the voltage value of the first common voltage.

[0014] On the other hand, this application also provides a display device, including a power module and the aforementioned display panel, wherein the power module is used to provide driving power for the display panel to display images.

[0015] Compared to existing technologies, the display panel provided in this application, by electrically connecting the first common electrode line and the second common electrode line when the power is off, can make the first common electrode and the second common electrode have the same voltage and discharge speed, avoiding the voltage difference between them, thereby avoiding the problem of screen flickering and afterimages when the display panel is powered off, thus improving the display panel image display effect and user experience. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 is a schematic diagram of the structure of a display device;

[0018] Figure 2 is a schematic diagram of the side structure of the display panel in Figure 1;

[0019] Figure 3 is a schematic diagram of an example of the planar layout structure of the display panel in Figure 2;

[0020] Figure 4 is a schematic diagram of the equivalent circuit of the pixel unit in the i-th row and j-th column of the array substrate of the display panel in Figure 3.

[0021] Figure 5 is a schematic diagram of the wiring planar structure of the display panel shown in Figure 3;

[0022] Figure 6 is a schematic diagram of the voltage change of the first common electrode signal line and the second common electrode signal line during the discharge process when the display panel in Figure 5 is powered off.

[0023] Figure 7 is a schematic diagram of the display panel wiring planar structure shown in Figure 3 provided in the first embodiment of this application;

[0024] Figure 8 is a schematic diagram of the specific circuit structure of the switching unit shown in Figure 7;

[0025] Figure 9 is a waveform diagram of the signals transmitted in each signal line when the display panel shown in Figure 7 is powered on and working normally;

[0026] Figure 10 is a waveform diagram of the signals transmitted by each signal line when the display panel shown in Figure 7 is powered off.

[0027] Figure 11 is a schematic diagram of the circuit structure of the switching unit shown in Figure 7 provided in the second embodiment of this application.

[0028] Explanation of reference numerals in the attached drawings: Display device-100, Display panel-10, 10', Power module-20, Support frame-30, Display area-10a, Non-display area-10b, Array substrate-10c, Opposing substrate-10d, Display dielectric layer-10e, Backlight module-17, First direction-F1, Second direction-F2, Data driving circuit-12, Scan driving circuit-13, Pixel unit-P, Scan lines-G1~Gn, Data lines-S1~Sm, Gate output control signal-Cg, Source output... Output control signal - Cs, Thin Film Transistor - T0, Storage Capacitor - Cst, Liquid Crystal Capacitor - Clc, Pixel Electrode - 161, First Common Electrode - 162, First Plate of Storage Capacitor - 151, Second Common Electrode - 152, First Common Electrode Line - CFcom, Second Common Electrode Line - Acom, Frame Start Signal Line - STV, Clock Signal Line - CK1 / CK2, Low Voltage DC Signal Line - VSS1 / VSS2, Low Frequency DC Signal Line - LC1 / LC2, Power-Off Time - t off Switching unit-K, control terminal-180, first switching transistor-T1, first control terminal-181, first conductive terminal-182, second conductive terminal-183, second switching transistor-T2, second control terminal-184, third conductive terminal-185, fourth conductive terminal-186, third switching transistor-T3, third control terminal-187, fifth conductive terminal-188, sixth conductive terminal-189. Detailed Implementation

[0029] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0030] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.

[0032] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0034] Please refer to Figure 1, which is a schematic diagram of the structure of a display device. The display device 100 includes a display panel 10, a power module 20, and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is disposed on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide power voltage for the display panel 10 to display images, and the support frame 30 provides fixation and protection for the display panel 10 and the power module 20.

[0035] In other embodiments of this application, the display device 100 may not require the support frame 30, for example, it may be a portable electronic device, such as a mobile phone or tablet computer.

[0036] Please refer to Figure 2, which is a schematic diagram of the side structure of the display panel in Figure 1.

[0037] As shown in Figure 2, the display panel 10 includes an array substrate 10c and a counter substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the counter substrate 10d. The array substrate 10c can be a thin-film transistor (TFT) substrate with a TFT array disposed thereon. The counter substrate 10d can be a color filter (CF) substrate, and a color filter layer (not shown) can be formed by depositing RGB or RGBW color group layers on the CF substrate. Driving elements are disposed on the array substrate 10c and the counter substrate 10d to generate corresponding electric fields according to data signals, thereby driving the display medium in the display medium layer 10e to emit light of corresponding brightness to perform image display. The display medium can be liquid crystal molecules.

[0038] Taking a liquid crystal display panel as an example, the display medium in the display medium layer 10e is a liquid crystal layer. The display panel 10 also includes a backlight module 17 (BM), wherein the backlight module 17 is used to provide light for display to the display medium layer 10e. The liquid crystal molecules in the display medium layer 10e deflect relative angles according to the data signal so as to emit the light transmitted by the backlight module 17 to the opposing substrate to perform image display.

[0039] Please refer to Figure 3, which is a schematic diagram of an example of the planar layout structure of the display panel in Figure 2.

[0040] As shown in Figure 3, the display panel 10 also includes a timing control circuit 11, a data driving circuit 12, and a scan driving circuit 13. The timing control circuit 11, the data driving circuit 12, and the scan driving circuit 13 are disposed in the non-display area 10b of the display panel 10.

[0041] The display area 10a of the display panel 10 has m data lines S1 to Sm and n scan lines G1 to Gn arranged in a grid pattern. The m data lines S1 to Sm extend along a first direction F1, and the n scan lines G1 to Gn extend along a second direction F2. The first direction F1 and the second direction F2 are perpendicular to each other. Pixel units P are disposed at the intersections of the n scan lines G1 to Gn and the data lines S1 to Sm.

[0042] The timing control circuit 11 receives an image signal representing image information from an external signal source, obtains a clock signal CLK, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn for synchronization, and outputs a gate output control signal Cg for controlling the scan drive circuit 13, a source output control signal Cs for controlling the data drive circuit 12, and a data signal representing image information. In this embodiment, the timing control circuit 11 performs data adjustment processing on the original data signal to obtain a data signal, and then transmits the data signal to the data drive circuit 12.

[0043] m data lines S1 to Sm are connected to the data driving circuit 11 and are used to receive data signals provided by the data driving circuit 12, which are stored and transmitted in the form of grayscale values. n scan lines G1 to Gn are connected to the scan driving circuit 13 and are used by the self-scanning driving circuit 13 to receive scan signals.

[0044] Under the control of n scan lines G1 to Gn, the pixel unit P receives the grayscale data voltage of the corresponding data signal provided by the data lines S1 to Sm within a predetermined time period, and drives the display medium layer 10e to deflect by a corresponding angle, thereby emitting light of corresponding brightness according to the corresponding deflection angle, so as to achieve image display by emitting light of corresponding brightness according to the image signal.

[0045] The scan drive circuit 13 receives the gate output control signal Cg from the timing control circuit 11 and outputs scan signals to each scan line G1 to Gn. The data drive circuit 12 receives the source output control signal Cs from the timing control circuit 11 and outputs data signals to each data line S1 to Sm for driving the elements in each pixel unit P in the display area 10a to perform image display. The data signals provided to the display panel 10 are analog grayscale voltages. The scan drive circuit 13 outputs scan signals to control the pixel unit P to receive the data signals output by the data drive circuit 12, thereby controlling the pixel unit P to display the corresponding image.

[0046] Please refer to Figure 4, which is a schematic diagram of the equivalent circuit structure of the pixel unit P in the i-th row and j-th column of the array substrate of the display panel in Figure 3. i and j are positive integers, and 1≤i≤n, 1≤j≤m.

[0047] The pixel unit 14 on the array substrate 10c includes a driving switch T0, a storage capacitor Cst, and a liquid crystal capacitor Clc. The driving switch T0 is connected to the scan line Gi, the data line Sj, and the storage capacitors Cst and Clc, respectively, so that under the control of the scan signal output from the scan line Gi, it selectively transmits the data signal from the data line Sj to the storage capacitors Cst and Clc. In this embodiment, the driving switch T0 is a P-type thin-film transistor, with its gate as the control terminal electrically connected to the scan line Gi, its source as the conductive terminal connected to the data line Sj, and its drain as another conductive terminal connected to the storage capacitor Cst and the liquid crystal capacitor Clc.

[0048] The liquid crystal capacitor Clc includes a pixel electrode 161 and a first common electrode 162, and the storage capacitor Cst includes a storage electrode 151 and a second common electrode 152. Both the pixel electrode 161 and the storage electrode 151 are connected to the drain of the driving switch T0. The first common electrode 162 is connected to the first common electrode signal line CFcom, and the second common electrode 152 is connected to the second common electrode signal line Acom. In this embodiment, it should be noted that the first common electrode 162 is disposed on the opposing substrate 10d.

[0049] The first common electrode 162 receives a first common voltage from the first common electrode line CFcom. The pixel electrode 161 can receive the data voltage corresponding to the image display signal. Under the drive of the first common voltage and the data voltage, the liquid crystal capacitor Clc drives the liquid crystal molecules in the liquid crystal layer to deflect and perform image display. At the same time, the storage electrode 151 also receives the data voltage along with the pixel electrode 161. The second common electrode 152 receives a second common voltage from the second common electrode line Acom. The first common voltage can cooperate with the data voltage to maintain the voltage of the liquid crystal capacitor Clc for a preset time period, thereby enabling the liquid crystal capacitor Clc to maintain a normal voltage during image display and accurately display the image.

[0050] In this embodiment, the first common voltage and the second common voltage are independent and different from each other. The voltage range of the first common voltage is 5-7V, and the voltage range of the second common voltage is 5-10V. As a result, the storage capacitor Cst can better maintain the voltage of the liquid crystal capacitor Clc and prevent the image in the pixel unit P from flickering due to voltage instability.

[0051] Please refer to Figure 5, which is a schematic diagram of the wiring planar structure of the display panel shown in Figure 3.

[0052] The array substrate 10c, corresponding to the non-display area, has multiple bonding areas, routing areas (not shown), and a scan drive circuit 13. The bonding areas include multiple signal line connection terminals, and the signal output lines of the timing control circuit 11 or the data drive circuit 12 can be connected to one end of the signal line connection terminal. The routing areas include multiple signal lines, and the other end of the signal line connection terminal is connected to these multiple signal lines, such as the enable signal line STV, the clock signal lines CK1-CK2, the low-voltage DC signal lines VS1-VS2, the low-frequency DC signal lines LC1-LC2, the first common electrode signal line CFcom, and the second common electrode signal line Acom. At the same time, the enable signal STV, the clock signal lines CK1-CK2, the low-voltage DC signal lines VS1-VS2, and the low-frequency DC signal lines LC1-LC2 are also connected to the scan drive circuit 13 to cooperate in driving the scan drive circuit 13 to work normally and output scan signals.

[0053] Research revealed that the first common electrode signal line CFcom transmits the first common voltage to the liquid crystal capacitor Clc, and the second common electrode signal line Acom transmits the second common voltage to the storage capacitor Cst. Furthermore, the first common electrode signal line CFcom and the second common electrode signal line Acom are independent of each other. Therefore, at the moment t is powered off from the display panel 10... off As shown in Figure 6, this diagram illustrates the voltage changes during the discharge process of the first common electrode signal line CFcom and the second common electrode signal line Acom when the display panel in Figure 5 is powered off. The first common electrode signal line CFcom and the second common electrode signal line Acom discharge independently. Because the voltage in the first common electrode line CFcom is less than the voltage provided by the second common electrode line Acom, their discharge speeds differ, resulting in a voltage difference ΔV between them during the discharge process. This voltage difference ΔV causes screen flickering and afterimages at the moment the display is powered off, thus identifying the cause of screen flickering and afterimages when the display panel is powered off.

[0054] Please refer to Figure 7, which is a schematic diagram of the display panel wiring planar structure shown in Figure 3 provided in the first embodiment of this application.

[0055] In this embodiment, the wiring structure of the display panel 10' shown in FIG7 is basically the same as that of the display panel 10 shown in FIG5. The difference is that the display panel 10' shown in FIG7 also includes a switch unit K. The switch unit K is connected to the first common electrode line CFcom and any one of the second common electrode lines Acom. The switch unit K is used to electrically disconnect the first common electrode line CFcom and the second common electrode line Acom when the display panel 10 is powered on and off, and to electrically connect the first common electrode line CFcom and the second common electrode line Acom when the display panel 10 is powered off and off.

[0056] In this embodiment, the control terminal 180 of the switching unit K is also connected to one of the multiple signal lines. For example, the switching unit K can be connected to the low-voltage DC signal line VSS1 or VSS2, and is turned on or off under the control of the low-voltage DC signal lines VSS1 / VSS2. When the switching unit K is turned on, the first common electrode line CFcom and the second common electrode line Acom are electrically connected. When the switching unit K is turned off, the first common electrode line CFcom and the second common electrode line Acom are electrically disconnected.

[0057] Please refer to Figure 8, which is a schematic diagram of the specific circuit structure of the switch unit K shown in Figure 7.

[0058] The switching unit K includes or may be a first switching transistor T1. The first switching transistor T1 may include a first control terminal 181, a first conductive terminal 182, and a second conductive terminal 183. The first control terminal 181 of the first switching transistor can be connected to low-voltage DC signal lines VSS1 / VSS2, the first conductive terminal 182 is connected to the first common electrode line CFcom, and the second conductive terminal 183 is connected to the second common electrode line Acom. In this embodiment, the first control terminal 181 is connected to the control terminal 180. In other words, the control terminal 180 is simultaneously connected to the low-voltage DC signal lines VSS1 / VSS2 and the first control terminal 181, or the first control terminal 181 directly serves as the control terminal 180.

[0059] When the display panel 10' is powered off, the low-voltage DC signal lines VSS1 / VSS2 output a first control signal to the first control terminal 181 to control the first switch transistor T1 to turn on. The first common electrode line CFcom is electrically connected to the second common electrode line Acom through the first conductive terminal 182 and the second conductive terminal 183. When the display panel 10' is powered on, the low-voltage DC signal lines output a second control signal to the first control terminal 181 to control the first switch transistor T1 to turn off. The first conductive terminal 182, the second conductive terminal 183, and the second common electrode line Acom are electrically disconnected. Thus, the first common electrode line CFcom and the second common electrode line Acom are electrically disconnected, allowing the liquid crystal capacitor Clc and the storage capacitor Cst to receive different common voltages and operate normally.

[0060] In this embodiment, the first switching transistor T1 is an N-type thin-film transistor. In other embodiments, the first switching transistor T1 can also be other types of transistors. Specifically, when the first switching transistor T1 is a thin-film transistor, the first control terminal 181 is the gate of the first switching transistor T1, the first conductive terminal 182 is the source of the first switching transistor T1, and the second conductive terminal 183 is the drain of the first switching transistor T1. Alternatively, the first conductive terminal 182 can also be the drain of the first switching transistor T1, and the second conductive terminal 183 can be the source of the first switching transistor T1.

[0061] In this embodiment, the signals output from the low-voltage DC signal lines VSS1 / VSS2 serve as either a first control signal or a second control signal. Specifically, when the display panel 10 is powered on, the low-voltage signal output from the low-voltage DC signal lines VSS1 / VSS2 serves as the second control signal and is transmitted to the first control terminal 181 to control the first switch transistor T1 to turn off, and the first conductive terminal 182 is electrically disconnected from the second conductive terminal 183. Thus, the liquid crystal capacitor Clc and the storage capacitor Cst can respectively receive the corresponding voltages from the first common electrode line CFcom and the second common electrode line Acom to achieve the required functions of the liquid crystal display panel 10'. When the display panel 10' is powered off, the high-voltage signal output from the low-voltage DC signal lines VSS1 / VSS2 serves as the first control signal and is transmitted to the first control terminal 181 to control the first switch transistor T1 to turn on, and the first conductive terminal 182 is electrically connected to the second conductive terminal 183. Therefore, the first common electrode line CFcom and the second common electrode line Acom, which are connected to the liquid crystal capacitor Clc and the storage capacitor Cst respectively, are both turned on and discharge at the same speed and voltage, thereby eliminating the voltage difference between the first common electrode line CFcom and the second common electrode line Acom, so that the display panel 10' accurately stops displaying the image. Furthermore, this embodiment directly uses the existing signal lines in the existing signal wiring to control the switching unit K, that is, it reuses the signal lines connected to the scan drive circuit 13, without adding other control signal lines, which further reduces the wiring complexity in the non-display area and is beneficial to the realization of narrow bezels.

[0062] Please refer to Figures 7 through 10. Figure 9 is a waveform diagram of the signals transmitted in each signal line when the display panel 10' shown in Figure 7 is powered on and operating normally. Figure 10 is a waveform diagram of the signals transmitted in each signal line when the display panel 10' shown in Figure 7 is powered off. For convenience, the signals transmitted in the corresponding signal lines are represented by the same symbols as the signal lines.

[0063] The specific working process of the switching unit K when the display panel 10' is powered on and working normally, and when it is powered off, will now be explained in detail with reference to Figures 7 to 10.

[0064] When the display panel 10' is powered on and working normally, as shown in Figure 9, the frame start signal line STV outputs an enable signal to the scan drive circuit 13 to start the scan drive circuit 13 to output a scan signal; at the same time, the scan drive circuit 13 also receives periodic square wave signals provided by clock signal lines CK1~CK2, and low-frequency DC signal lines LC1~LC2 provide signals with opposite high and low voltage states; low-voltage DC signal lines VSS1~VSS2 output low-voltage DC signals.

[0065] Simultaneously, low-voltage DC signal lines VSS1 to VSS2 output low-voltage DC signals as the second control signal to the switching unit K. The first switch T1 in the switching unit K is turned off, thereby allowing the first common electrode line CFcom and the second common electrode line Acom to independently provide voltages—the first common voltage and the second common voltage—to the scan drive circuit 13. Combined with the aforementioned other signals, this enables the scan drive circuit 13 to operate normally and output scan signals sequentially. It can be understood that when the display panel 10' is powered on and operating normally, both the first common voltage and the second common voltage are positive voltages, and the positive voltage corresponding to the first common voltage is greater than the positive voltage corresponding to the second common voltage.

[0066] Please refer to Figure 10. When the display panel 10' is powered off at time t... off The frame start signal line STV, clock signal lines CK1~CK2, low voltage DC signal lines VS1~VS2, and low frequency DC signal lines LC1~LC2 all jump to a high voltage of the same value to control the scan drive circuit 13 to stop outputting the scan signal and stop displaying the image.

[0067] Simultaneously, low-voltage DC signal lines VSS1 to VSS2 output high-voltage DC signals as the first control signal to the switching unit K. The first switch T1 in the switching unit K is turned on, thereby making the first common electrode line CFcom and the second common electrode line Acom electrically connected, resulting in the voltages of CFcom and Acom being the same and eliminating the voltage difference ΔV. This solves the flickering and afterimage problems when the display panel 10' is powered off, significantly improving the user experience.

[0068] Please refer to Figure 11, which is a schematic diagram of the circuit structure of the switching unit shown in Figure 7 provided in the second embodiment of this application.

[0069] As shown in Figure 11, the switching unit K includes a second switching transistor T2 and a third switching transistor T3. The second switching transistor T2 includes a second control terminal 184, a third conductive terminal 185, and a fourth conductive terminal 186. The third switching transistor T3 includes a third control terminal 187, a fifth conductive terminal 188, and a sixth conductive terminal 189. The second control terminal 184 of the second switching transistor T2 is connected to the first low-frequency DC signal line LC1. The third control terminal 187 of the third switching transistor T3 is connected to the second low-frequency DC signal line LC2. The third conductive terminal 185 is connected to the first common electrode line CFcom. The fourth conductive terminal 186 is connected to the fifth conductive terminal 188. The sixth conductive terminal 189 is connected to the second common electrode line Acom.

[0070] In this embodiment, the second switch T2 and the third switch T3 are N-type thin-film transistors. Of course, other types of switch transistors can also be used according to actual needs. When the second switch T2 and the third switch T3 are N-type thin-film transistors, the second control terminal 184 is the gate of the second switch T2, the third control terminal 187 is the gate of the third switch T3, the third conductive terminal 185 is the source of the second switch T2, the fourth conductive terminal 186 is the drain of the second switch T2, the fifth conductive terminal 188 is the source of the third switch T3, and the sixth conductive terminal 189 is the drain of the third switch T3.

[0071] In this embodiment, the second control terminal 184 and the third control terminal 187 can both be connected to the control terminal 180. The control terminal 180 can include two independent and insulated ports, which can be connected to the first low-frequency DC signal line LC1 and the second low-frequency DC signal line LC2, respectively. This allows the second control terminal 184 and the third control terminal 187 to be connected to the first low-frequency DC signal line LC1 and the second low-frequency DC signal line LC2, respectively, through the control terminal 180. In other words, the control terminal 180 can be simultaneously connected to the first low-frequency DC signal line LC1, the second low-frequency DC signal line LC2, and the second control terminal 184 and the third control terminal 187, or the second control terminal 184 and the third control terminal 187 can be directly used as the control terminal 180.

[0072] When the display panel 10' is powered off, the first low-frequency DC signal line LC1 outputs a third control signal to the second switch T2, and the second low-frequency DC signal line LC2 outputs a fourth control signal to the third switch T3. In this embodiment, both the third and fourth control signals are at a high level to control the second switch T2 and the third switch T3 to conduct, thereby making the first common electrode line CFcom electrically connected to the second common electrode line Acom through the second switch T2 and the third switch T3.

[0073] Correspondingly, when the display panel 10' is powered on and operating, the first low-frequency DC signal line LC1 is used to output the first low-frequency DC signal to the scan drive circuit 13, and the second low-frequency DC signal line LC2 is used to output the second low-frequency DC signal to the scan drive circuit 13. At this time, the first low-frequency DC signal and the second low-frequency DC signal are signals with opposite levels, so they can control one of the second switch T2 and the third switch T3 to be turned off, thereby making the first common electrode line CFcom and the second common electrode line Acom electrically disconnected from each other, thereby correspondingly transmitting the corresponding common voltage to the liquid crystal capacitor Clc and the storage capacitor Cst, so that the display panel 10' can display images normally and accurately.

[0074] Therefore, in this embodiment, when the display panel 10' is working normally, the two switching transistors T2 and T3 in the switching unit K can be turned on differently, thereby effectively extending the lifespan of the switching transistors in the switching unit K. Simultaneously, when the display panel 10' is powered off, the switching unit K controls the first common electrode line CFcom and the second common electrode line Acom to be electrically connected, making the voltages of the first common electrode line CFcom and the second common electrode line Acom the same, thus eliminating the voltage difference. This solves the screen flickering and afterimage problems when the display panel 10' is powered off, significantly improving the user experience.

[0075] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A display panel, characterized in that, The system includes an array substrate, a counter substrate, and a liquid crystal layer sandwiched between the array substrate and the counter substrate. The array substrate includes a display area and a non-display area surrounding the display area. The display area includes multiple pixel units for image display. For each pixel unit, the array substrate includes a pixel electrode and a storage capacitor. The counter substrate includes a first common electrode. The pixel electrode and the first common electrode constitute a liquid crystal capacitor. For the non-display area, the array substrate is provided with a first common electrode line, a low-voltage DC signal line, and a scan driving unit. The first common electrode line is connected to the first common electrode. For the display area, the array substrate includes multiple electrically connected second common electrode lines, which are connected to the storage capacitor. The low-voltage DC signal line outputs a low-voltage signal to the scan driving unit when the display panel is operating normally. The scan driving unit outputs a scan signal to the pixel. The display panel includes a unit for controlling pixel units to receive image display signals and perform image display; the display panel also includes a switch unit connected to the first common electrode line and any one of the second common electrode lines, the switch unit being used to electrically connect the first common electrode line and the second common electrode line when the display panel is powered off; the switch unit includes a first switch transistor, the first switch transistor including a first control terminal, a first conductive terminal and a second conductive terminal, the first control terminal of the first switch transistor being connected to the low-voltage DC signal line, the first conductive terminal being connected to the first common electrode line, the second conductive terminal being connected to the second common electrode line, the first switch transistor being used to output a first control signal to the first control terminal when the display panel is powered off, to control the first switch transistor to conduct, and the first common electrode line being electrically connected to the second common electrode line through the first conductive terminal and the second conductive terminal.

2. The display panel according to claim 1, characterized in that, When the display panel is powered on, the low-voltage DC signal line is used to output a low-voltage signal to the scanning drive unit. When the display panel is powered off, the low-voltage DC signal line outputs a high-voltage signal to the scanning drive unit. The high-voltage signal also serves as a first control signal to control the first switching transistor to turn on.

3. The display panel according to claim 2, characterized in that, When the display panel is powered on, the low-voltage signal output by the low-voltage DC signal line is used as a second control signal and transmitted to the first control terminal to control the first switching transistor to turn off, thereby controlling the first conductive terminal to electrically disconnect from the second conductive terminal.

4. The display panel according to claim 1, characterized in that, Corresponding to the non-display area, the array substrate is further provided with a first low-frequency DC signal line, a second low-frequency DC signal line, and a scan driving unit. The first low-frequency DC signal line outputs a first low-frequency DC signal, and the second low-frequency DC signal line outputs a second low-frequency DC signal. The first low-frequency DC signal and the second low-frequency DC signal are signals with opposite polarities and change periodically, and are used to switch the working state of the scan driving unit. The switching unit includes a second switching transistor and a third switching transistor. The second switching transistor includes a second control terminal, a third conductive terminal, and a fourth conductive terminal. The third switching transistor includes a third control terminal, a fifth conductive terminal, and a sixth conductive terminal. The second control terminal of the second switching transistor is connected to the first low-frequency DC signal line. The third control terminal of the three switching transistors is connected to the second low-frequency DC signal line, the third conductive terminal is connected to the first common electrode line, the fourth conductive terminal is connected to the fifth conductive terminal, and the sixth conductive terminal is connected to the second common electrode line. When the display panel is powered off, the first low-frequency DC signal line outputs a third control signal to the second control terminal to control the second switching transistor to conduct. At the same time, the second low-frequency DC signal line outputs a fourth control signal to the third control terminal to control the third switching transistor to conduct. The fourth control signal is the same as the third control signal. The first common electrode line is electrically connected to the second common electrode line through the first switching transistor, the second switching transistor, and the second common electrode line.

5. The display panel according to claim 4, characterized in that, When the display panel is powered on, the first low-frequency DC signal line is used to output a first low-frequency DC signal to the scanning drive unit, and the second low-frequency DC signal line is used to output a second low-frequency DC signal to the scanning drive unit. When the display panel is powered off, both the first low-frequency DC signal line and the second low-frequency DC signal line output high-voltage signals as the third control signal and the fourth control signal.

6. The display panel according to claim 5, characterized in that, When the display panel is powered on, the first low-frequency DC signal and the second low-frequency DC signal alternately control one of the second switching transistors to be turned off, thereby controlling the first common electrode line and the second common electrode line to be electrically disconnected.

7. The display panel according to any one of claims 1-6, characterized in that, The first common electrode receives a first common voltage from the first common electrode line, the pixel electrode receives a data voltage corresponding to the image display signal, and the liquid crystal capacitor drives the liquid crystal molecules in the liquid crystal layer to rotate and perform image display under the drive of the first common voltage and the data voltage; the storage capacitor includes a storage electrode and a second common electrode, the storage electrode receives the data voltage, the second common electrode receives a second common voltage from the second common electrode line, and the first common voltage and the data voltage cooperate to maintain the voltage of the liquid crystal capacitor for a preset time period.

8. The display panel according to claim 7, characterized in that, The voltage value of the second common voltage is greater than the voltage value of the first common voltage.

9. A display device, characterized in that, It includes a power module and a display panel according to any one of claims 1-8, wherein the power module is used to provide driving power for the display panel to display images.

Images