A foldback ramp compensation system and a compensation method thereof

Abstract

The application discloses a foldback type slope compensation system and a compensation method thereof, which adopts real-time sampling of the change of the conduction time of adjacent periods to correct the effect of slope compensation in real time, dynamically changes the size of the slope compensation voltage, enters a foldback type adjustment stage when the slope compensation is effective, and adopts a foldback method to find the optimal compensation amount, so that the problem of overlarge or too small slope compensation voltage can be effectively avoided, real-time disturbance caused by different input voltages and output voltages can be adjusted in real time, dynamic response is improved, and output voltage fluctuation caused by subharmonic oscillation can be effectively converged when the input voltage is low and the output is full.

Description

Technical Field

[0001] This invention relates to slope compensation in switching power supply systems to suppress subharmonic oscillations, and particularly to a foldback slope compensation system and its compensation method, belonging to the field of integrated circuit technology. Background Technology

[0002] In switching power supplies, such as flyback converter systems, when the duty cycle of the primary side is greater than 50%, subharmonic oscillations will occur. This manifests as fluctuations in the on-time and large and small waves in the current waveform. In severe cases, it can lead to abnormal system operation. This situation is more serious when the input voltage is low because the inductor current rises at a slower slope. Under peak current PWM control mode, the on-time is longer, making it easier for subharmonic oscillations to occur.

[0003] Figure 1 The subharmonic oscillation shown typically occurs in the current waveform at low voltage input in a flyback converter system. The solid line represents the inductor current waveform I. LM0 This represents the inductor current waveform during normal operation. When a current disturbance ΔI is introduced, the inductor current waveform changes to the form shown by the dashed line I. LM1 As can be seen, the error in the inductor current gradually increases in subsequent cycles, leading to system instability. Furthermore, the oscillation period is mostly twice the switching period, resulting in a large duty cycle. A common suppression method is to add... Figure 2 The slope shown can be compensated by built-in slope to make the original current peak arrive earlier when the duty cycle is too large. Figure 2 The dashed line represents I. LM3 This represents the inductor current waveform when the system becomes unstable after the occurrence of subharmonic oscillations, and realizes the representation of I. LM2 The waveform of the inductor current after adding the slope is shown. It can be seen that after introducing the slope, i.e., slope compensation, the amplitude of the current error signal gradually decreases until it stabilizes after each cycle.

[0004] In practical system applications, subharmonic oscillations may occur prematurely at less than 50% duty cycle, such as 45% or even lower. Existing technologies often add internal compensation based on the duty cycle size. The larger the slope of the compensation ramp, the faster the oscillation decays, but this can also lead to overcompensation. Overcompensation reduces the system's load-carrying capacity and affects its transient response. For flyback converters, the slope of the compensation ramp is generally taken as the slope of the inductor current decrease. However, in actual operation, the output voltage of the flyback converter system is not constant. It cannot provide full coverage compensation for different output voltages and the unstable factors caused by different disturbances that may lead to varying degrees of subharmonic oscillations. Therefore, it is very important to implement dynamic ramp compensation for different output voltages, different systems, and different disturbances to eliminate the influence of subharmonic oscillations in real time. Summary of the Invention

[0005] The purpose of this invention is to overcome the defects existing in the prior art and provide a folded-back ramp compensation system and its compensation method. Targeting the characteristics of subharmonic oscillations occurring under heavy load and full load, the load state is determined based on the feedback voltage. The difference in conduction time between two adjacent cycles is detected in real time to determine whether to adjust the internal compensation ramp size. Through folded-back adjustment, the optimal compensation ramp value is found, realizing real-time adjustment of disturbances on the system.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a foldback slope compensation system, characterized in that it includes an error detection unit, an adjustment control logic unit, a compensation register unit, and a foldback compensation current generation unit; the input of the error detection unit is connected to the switching control signal GON generated by the switching power supply, which represents the periodic conduction of the external power transistor; the output error voltage signal VS(k) and control signals KT3 and KT4 of the error detection unit are connected to the three input terminals of the adjustment control logic unit, wherein the error voltage signal VS(k) represents the error voltage signal in the k-th group after grouping the switching control signal GON according to adjacent periods, where k is a positive integer greater than or equal to 1; the output of the adjustment control logic unit is the control signal KT3. 1. K2 and F1_Latch are connected to the three input terminals of the compensation register unit. At the same time, the control signal F1_Latch, the control signal F2 generated by the adjustment control logic unit, and the switch control signal GON are connected to the three input terminals of the foldback compensation current generation unit. The other input terminal of the compensation register unit is also connected to the voltage signal V(k+1) generated by the foldback compensation current generation unit, which represents the slope compensation information. The output signals V(k), V(k-1), and VCLK of the compensation register unit are connected to the other three input terminals of the foldback compensation current generation unit. Finally, the foldback compensation current generation unit uses the voltage signal V(k+1) to generate the slope compensation voltage Vslope(k+1) output.

[0007] The error detection unit, when the switching power supply is in operation, divides adjacent cycles 2k-1 and 2k into a k-th group based on the input switching control signal GON. It detects the difference in conduction time between the external power transistors within cycles 2k-1 and 2k, converts this difference into an error voltage signal VS(k) within the k-th group, and outputs it along with control signals KT3 and KT4 to the adjustment control logic unit. The error detection unit includes a grouping circuit and a sample-and-hold circuit. The grouping circuit includes D flip-flops DFF01 and DFF02, NAND gates Nand01 and Nand02, and NAND gate Na... The D flip-flop DFF01 is connected to the clock input CLK of the D flip-flop DFF01, one input of the NAND gate Nand01, one input of the NAND gate Nand02, and one input of the NOR gate Nor01. The output Q of the D flip-flop DFF01 is connected to the other input of the NOR gate Nor01 and the other input of the NAND gate Nand01. Connect the other input of NAND gate Nand02. The output signals KT1B of NAND gate Nand01 and KT1 after passing through inverter INV01 are connected to the output signal KT1. The output signals KT2B of NAND gate Nand02 and KT2 after passing through inverter INV03 are connected to the output signal KT2. The output of NOR gate Nor01, after passing through inverter INV02, is connected to the clock input CLK of D flip-flop DFF02, one input of NAND gate Nand03, and one input of NAND gate Nand04. The output Q of D flip-flop DFF02 is connected to the other input of NAND gate Nand03. Connect the other input terminal of the NAND gate Nand04. The output signal KT3B of the NAND gate Nand03 and the output signal KT3 after the signal KT3B passes through the inverter INV04. The output signal KT4B of the NAND gate Nand04 and the output signal KT4 after the signal KT4B passes through the inverter INV05. The sample-and-hold circuit includes PMOS transistors PM01, PM02, PM03, PM04, NMOS transistors NM01, NM02, NM03, NM04, NMS1, NMS2, capacitors C01, C02, C03, C04, CS, resistors R01 and R02, and inverters INV11, INV12, INV13, and INV14. The power supply VDD is respectively... Connect the input terminals of current source I0 and current source I3. The output terminal of current source I0 is connected to the source of PMOS transistor PM01. The drain of PMOS transistor PM01 is connected to the source of PMOS transistor PM02. The drain of PMOS transistor PM02 is connected to the drain of NMOS transistor NM01 and one end of capacitor C03 and outputs signal Va1. The source of NMOS transistor NM01 is connected to the drain of NMOS transistor NM02. The source of NMOS transistor NM02 is connected to the input terminal of current source I1. The output terminal of current source I1 is connected to the other end of capacitor C03 and grounded. The gate of PMOS transistor PM01 is connected to the output signal KT1B of the grouping circuit. The gate of PMOS transistor PM02 is connected to the output signal KT3B of the grouping circuit. The gate of NMOS transistor NM01 is connected to the output signal KT2 of the grouping circuit. The gate of NMOS transistor NM02 is connected to the output signal KT3 of the grouping circuit.The output of current source I3 is connected to the source of PMOS transistor PM03. The drain of PMOS transistor PM03 is connected to the source of PMOS transistor PM04. The drain of PMOS transistor PM04 is connected to the drain of NMOS transistor NM03 and one end of capacitor C04, outputting signal Va2. The source of NMOS transistor NM03 is connected to the drain of NMOS transistor NM04. The source of NMOS transistor NM04 is connected to the input of current source I4. The output of current source I4 is connected to the other end of capacitor C04 and grounded. The gate of PMOS transistor PM03 is connected to the output signal KT1B of the grouping circuit. The gate of PMOS transistor PM04 is connected to the output signal KT4B of the grouping circuit. The gate of NMOS transistor NM03 is connected to the output signal KT2 of the grouping circuit. The gate of NMOS transistor NM04 is connected to the output signal KT4 of the grouping circuit. The output signal KT4 of the grouping circuit is also connected to one end of resistor R01. The other end of resistor R01 is connected to capacitor C04. One end of 01 is connected to the input of inverter INV11, the other end of capacitor C01 is grounded, the output of inverter INV11 is connected to the input of inverter INV12, the output of inverter INV12 is connected to the gate of NMOS transistor NMS1, the drain of NMOS transistor NMS1 is connected to the output signal Va1, the source of NMOS transistor NMS1 is connected to the drain of NMOS transistor NMS2 and one end of capacitor CS and serves as the output of the error detection unit to output the voltage error signal VS(k), the other end of capacitor CS is grounded, the source of NMOS transistor NMS2 is connected to the output signal Va2, the gate of NMOS transistor NMS2 is connected to the output of inverter INV14, the input of inverter INV14 is connected to the output of inverter INV13, the input of inverter INV13 is connected to one end of resistor R02 and one end of capacitor C02, the other end of capacitor C02 is grounded, and the other end of resistor R02 is connected to the output signal KT3 of the grouping circuit;

[0008] The adjustment control logic unit, under the action of control signals KT3 and KT4 output by the error detection unit, generates control signals K1 and K2 and an asynchronous clock CLK0. It compares the error voltage signal VS(k) output in the k-th group with the reference voltage Vref in real time. When the error voltage signal VS(k) is greater than the reference voltage Vref, slope compensation adjustment is required; when the error voltage signal VS(k) is less than the reference voltage Vref, slope compensation adjustment is not required or has already been completed. The comparison result of the error voltage signal VS(k) and the reference voltage Vref is sampled by the falling edge of the asynchronous clock CLK0. Based on the sampled comparison result, control signals F1, F1_Latch, and F2 are generated. The unit includes an internal pulse generation circuit and a judgment circuit. The internal pulse generation circuit includes PMOS transistors PMD1~PMD10, NMOS transistors NMD1~NMD4, inverters INVD1~INVD10, NOR gate NorD1, NOR gate NorD2, and capacitor Cd1~ Cd4 and resistors Rd1~Rd4; the gate of PMOS transistor PMD1 is interconnected with the gate of NMOS transistor NMD1 and the gate of PMOS transistor PMD2, and serves as the input terminal of the adjustment control logic unit, connected to the output signal KT3 of the grouping circuit. The sources of PMOS transistors PMD1 and PMD2 are both connected to the power supply VDD. The drain of PMOS transistor PMD1 is connected to the drain of NMOS transistor NMD1, the drain of PMOS transistor PMD3, one end of capacitor Cd1, and the input terminal of inverter INVD1 through resistor Rd1. The output of inverter INVD1 is connected to the gate of PMOS transistor PMD3 and the input terminal of inverter INVD2. The output of inverter INVD2 is connected to the input terminal of inverter INVD3. The output of inverter INVD3 is connected to one input terminal of OR gate OR1. The other end of capacitor Cd1 is connected to the gate of NMOS transistor NMD1. The sources are all grounded; the gate of PMOS transistor PMD4 is interconnected with the gate of NMOS transistor NMD2 and the gate of PMOS transistor PMD5 and serves as the input of the adjustment control logic unit, connected to the output signal KT4 of the grouping circuit. The source of PMOS transistor PMD4 is interconnected with the source of PMOS transistor PMD5 and connected to the power supply VDD. The drain of PMOS transistor PMD4 is connected to the drain of NMOS transistor NMD2, the drain of PMOS transistor PMD6, one end of capacitor Cd2, and the input of inverter INVD4 through resistor Rd2. The output of inverter INVD4 is connected to the gate of PMOS transistor PMD6 and the input of inverter INVD5. The output of inverter INVD5 is connected to the input of inverter INVD6. The output of inverter INVD6 is connected to the other input of OR gate OR1. The other end of capacitor Cd2 and the source of NMOS transistor NMD2 are both grounded.The clock signal CLK0 output by OR gate OR1 is connected to the gates of PMOS transistor PMD7, NMOS transistor NMD3, and the input of inverter INVD7, as well as the gates of PMOS transistors PMD8, NMOS transistor NMD4, and PMOS transistor PMD9, and one input of NOR gate NorD2. The other input of NOR gate NorD2 is connected to the output of inverter INVD10. The output of NOR gate NorD2 serves as the output of the adjustment control logic unit, outputting the control signal K2. The input of inverter INVD10 is connected to the output of inverter INVD9 and... The gate of PMOS transistor PMD10 is connected to the gate of PMOS transistor PMD9. The source of PMOS transistor PMD10 is connected to the drain of PMOS transistor PMD9. The sources of PMOS transistors PMD9 and PMD8 are both connected to the power supply VDD. The drain of PMOS transistor PMD8 is connected to the drain of NMOS transistor NMD4, the drain of PMOS transistor PMD10, the input of inverter INVD9, and one end of capacitor Cd4 through resistor Rd4. The other end of capacitor Cd4 is connected to the source of NMOS transistor NMD4 and grounded. The source of PMOS transistor PMD7 is connected to the power supply VDD. The drain of the inverter is connected to one end of resistor Rd3, one end of capacitor Cd3, and the input of inverter INVD8. The output of inverter INVD8 is connected to one input of NOR gate NorD1. The other input of NOR gate NorD1 is connected to the output of inverter INVD7. The output of NOR gate NorD1 serves as the output of the adjustment control logic unit, outputting the control signal K1. The other end of resistor Rd3 is connected to the drain of NMOS transistor NMD3. The source of NMOS transistor NMD3 and the other end of capacitor Cd3 are both grounded. The judgment circuit includes comparator COMPD1 and D flip-flop DFF21. The circuit consists of a D flip-flop DFF22, an NOR gate Nor21, an NAND gate Nand21, and an inverter INV21. The negative terminal of comparator COMPD1 is connected to the error voltage signal VS(k) output by the error detection unit as the input terminal of the adjustment control logic unit. The positive terminal of comparator COMPD1 is connected to the reference voltage Vref. The output of comparator COMPD1 is connected to the input terminals D of D flip-flop DFF21 and D of D flip-flop DFF22. The clock signal CLK0 output by OR gate OR1 in the internal pulse generation circuit is connected to the input terminal of D flip-flop DFF21. and the input of the D flip-flop DFF22 The output Q of D flip-flop DFF21 outputs signal F1. The output Q of DFF22 serves as the output of the adjustment control logic unit, outputting signal F2. One input of NOR gate Nor21 is connected to power supply VDD. The other input of NOR gate Nor21 is connected to the output of NOR gate Nor22. The output of NOR gate Nor21 is connected to one input of NOR gate Nor22 and one input of NAND gate Nand21. The other input of NOR gate Nor22 is connected to output signal F1 and the other input of NAND gate Nand21. The output of NAND gate Nand21 is connected to the input of inverter INV21. The output of inverter INV21 serves as the output of the adjustment control logic unit, outputting control signal F1_latch.

[0009] The compensation register unit is used to dynamically store the voltage signals V(k) and V(k-1) representing the slope compensation information in the k+1th group, based on the control signals K1, K2, and F1_Latch output by the adjustment control logic unit and the voltage signal V(k+1) representing the slope compensation information in the k-1th group fed back by the folded-back compensation current generator. When the control signal F1_Latch goes high, the compensation register unit latches the voltage V(k-1) representing the slope compensation information in the k-1th group, generating the voltage signal VLCK; including the first The system comprises a voltage register and a second voltage register. The first voltage register includes NMOS transistors NMR1 and NMR2, a NOR gate Nor41, an inverter INV41, and capacitors C33 and C34. The drain of NMOS transistor NMR1 is connected to the input of the first voltage register and is linked to the feedback signal V(k+1) output by the foldback compensation current generation unit. The gate of NMOS transistor NMR1 is connected to the control signal K1 output by the adjustment control logic unit. The source of NMOS transistor NMR1 is connected to the drain of NMOS transistor NMR2 and one end of capacitor C34. The other end of capacitor C34 is grounded. The source of NMR2 is connected to one end of capacitor C33 and serves as the output of the compensation register, outputting the signal VLCK. The other end of capacitor C33 is grounded. The gate of NMR2 is connected to the output of inverter INV41. The input of inverter INV41 is connected to the output of NOR41. The two inputs of NOR41 are connected to the control signals F1_latch and K2 of the adjustment control logic unit, respectively. The second voltage register includes NMR3, NMR4, capacitors C31 and C32. The drain of NMR3 is... The input of the second voltage register is connected to the feedback signal V(k+1) output by the foldback compensation current generation unit. The source of NMOS transistor NMR3 is connected to the drain of NMOS transistor NMR4 and one end of capacitor C31 and outputs signal V(K). The other end of capacitor C31 is grounded. The source of NMOS transistor NMR4 is connected to one end of capacitor C32 and outputs signal V(k-1). The other end of capacitor C32 is grounded. The gate of NMOS transistor NMR3 is connected to the control signal K1 output by the adjustment control logic unit. The gate of NMOS transistor NMR4 is connected to the control signal K2 output by the adjustment control logic unit.

[0010] The foldback compensation current generation unit is used to select the output voltages V(k), V(k-1), and VCLK of the compensation register unit for addition operation based on the control signals F1_Latch and F2 generated by the adjustment control unit, generating a voltage signal V(k+1) representing the slope compensation information in the (K+1)th group. Based on the voltage signal V(k+1), a slope compensation voltage signal Vslope(k+1) is generated. It includes a data selector, an adder, and a slope generation circuit. The output of the data selector is connected to the input of the adder, and the output of the adder is connected to the input of the slope generation circuit. The slope generation circuit outputs a voltage signal V(k+1) representing the compensation value for the next cycle, which is connected to the input of the compensation register unit. Simultaneously, the output signal of the slope generation circuit is the final slope compensation signal V_SLOPE output by the foldback compensation current generation unit. The data selector includes an NMOS transistor NM... V1, NMOS transistors NMV2 and NMOS transistors NMV3, NAND gate Nand51, inverters INV51 and INV52; the two inputs of NAND gate Nand51 are connected to the control signals F1_latch and F2 output from the adjustment control logic unit, respectively; the output of NAND gate Nand51 is connected to the gate of NMOS transistor NMV1 and the input of inverter INV51; the output of inverter INV51 is connected to the gate of NMOS transistor NMV2 and the input of inverter INV52; the output of inverter INV52 is connected to the gate of NMOS transistor NMV3; the drain of NMOS transistor NMV1 is connected to the signal V(K) output from the compensation register unit; the drain of NMOS transistor NMV2 is connected to the output signal VLCK of the compensation register unit; the drain of NMOS transistor NMV3 is connected to the output signal V(K-1) of the compensation register unit. The source output signal V1 of transistor NMV1 is connected to the first input terminal of the subsequent adder; the source output signal V2 of NMOS transistor NMV3 is connected to the second input terminal of the subsequent adder; and the source output signal V3 of NMOS transistor NMV2 is connected to the third input terminal of the subsequent adder. The adder includes operational amplifier OPV1, NMOS transistors NMV3 and NMV4, capacitor CV4, and resistors RA1 to RA6.One end of resistor RA1 is connected to the output signal V1 of the data selector, one end of resistor RA2 is connected to the output signal V2 of the data selector, and one end of resistor RA3 is connected to the output signal V3 of the data selector. The other end of resistor RA1 is connected to the other ends of resistors RA2 and RA3 and the negative terminal of operational amplifier OPV1. The positive terminal of operational amplifier OPV1 is grounded through resistor RA4. The other ends of resistors RA1, RA2, and RA3 are also connected to the drain of NMOS transistor NMV3 and one end of resistor RA5. The gate of NMOS transistor NMV3 is connected to the signal F1_latch output by the adjustment control logic unit. The other end of resistor RA5 is connected to the source of NMOS transistor NMV3 and one end of resistor RA6. The other end of resistor RA6 is connected to the output terminal of operational amplifier OPV1 and the drain of NMOS transistor NMV4. The gate of NMOS transistor NMV4 is connected to the switch control signal GON. The source of NMOS transistor NMV4 is connected to one end of capacitor CV4 and outputs a voltage signal V(k+1) indicating the magnitude of the compensation value in the next cycle. The other end of CV4 is grounded; the ramp generation circuit includes PMOS transistors PMV1, PMOS transistors PMV2, PMOS transistors PMV3, PMOS transistors PMV4, NMOS transistor NMV5, capacitor CV5, and resistor RAS; the gate of NMOS transistor NMV5 is connected to the voltage signal V(k+1) output by the adder, the source of NMOS transistor NMV5 is grounded through resistor RAS, and the drain of NMOS transistor NMV5 is connected to the drain and gate of PMOS transistors PMV1 and PMOS transistor PMV2. The sources of MOSFET PMV1 and PMV2 are both connected to VDD. The drain of PMV2 is connected to the source of PMV3. The gate of PMV3 is connected to the enable signal Ctr1. The drain of PMV3 is connected to both the drain and gate of PMV4. The source of PMV4 is connected to one end of capacitor CV5 and serves as the output of the foldback compensation current generation unit, outputting the ramp compensation signal V_SLOPE. The other end of capacitor CV5 is grounded.

[0011] Furthermore, in the adjustment control logic unit, the positive terminal of comparator COMPD1 is connected to the reference voltage 0. <Vref<20mV。

[0012] The compensation method of the above-mentioned fold-back ramp compensation system is characterized by the following steps: Taking into account the characteristic that subharmonic oscillations occur under heavy load and full load conditions, the load state is determined based on the feedback voltage characterizing the real-time feedback quantity of the output voltage of the switching power supply system. The difference in conduction time between two adjacent cycles is detected in real time to determine whether to adjust the internal compensation ramp size. Through fold-back adjustment, the optimal compensation ramp value is found, achieving real-time adjustment of disturbances in the system.

[0013] (1)When the system enters full load and the feedback voltage reaches the maximum value and remains unchanged, the ramp compensation adjustment starts;

[0014] (2)According to the switch control signal, the adjacent 2k - 1th cycle and the 2kth cycle are divided into the kth group, where k ∈ N + , N + represents positive integers;

[0015] (3)Detect the conduction time difference of the external power tubes within the adjacent 2k - 1th cycle and the 2kth cycle in the kth group, and convert this conduction time difference into an error voltage signal VS(k);

[0016] (4)Compare VS(k) with the reference voltage Vref, and adjust the ramp compensation voltage according to the comparison result.

[0017] Step (4) specifically includes the following steps:

[0018] (4.1)Use the compensation register unit to store the voltage V(k) representing the ramp compensation information within the kth group and the voltage V(k - 1) representing the ramp compensation information within the k - 1th group;

[0019] (4.2)Within the kth group, if VS(k) > Vref, then within the next group, that is, within the k + 1th group, the voltage V(k + 1) representing the ramp compensation information is corrected to V(k) + V(k - 1), and repeat this process until VS(k) < Vref appears for the first time, generate the latch signal F1_Latch, enter the flyback compensation adjustment stage, latch the voltage V(k - 1) representing the ramp compensation information within the 2k - 1th cycle onto the capacitor C33, and generate the voltage VLCK;

[0020] (4.3)After entering the flyback compensation adjustment stage, within the ith group, i > k, and i ∈ N + , if VS(i) > Vref, then within the next group, that is, within the i + 1th group, the voltage V(i + 1) representing the ramp compensation information is corrected to [V(i) + V(i - 1)] / 2; if VS(i) < Vref, then within the next group, that is, within the i + 1th group, the voltage V(i + 1) representing the ramp compensation information is corrected to [V(i) + VLCK] / 2;

[0021] (4.4)Repeat step (4.3), and through infinite flybacks, the compensation value will finally stabilize at an optimal value.

[0022] Advantages and significant effects of the present invention: The present invention does not rely on the traditional duty cycle detection method. By dynamically changing the magnitude of the slope compensation voltage and adopting a foldback method to find the optimal compensation amount, it can effectively avoid the problem of the slope compensation voltage being too large or too small. It can adjust in real time for real-time disturbances caused by different input voltages and output voltages, improve dynamic response, and effectively converge the output voltage fluctuations caused by subharmonic oscillations when the input voltage is low and the output is at full load. Attached Figure Description

[0023] Figure 1 This is the current waveform of subharmonic oscillation in a common switching power supply;

[0024] Figure 2 The current waveform after slope compensation for subharmonic oscillations in common switching power supplies;

[0025] Figure 3 This is a block diagram of the reversible slope compensation system of the present invention;

[0026] Figure 3-1 This is an embodiment of the grouping circuit in the present invention;

[0027] Figure 3-2 This is an embodiment of the sample-and-hold circuit in the present invention;

[0028] Figure 3-3 This is the voltage waveform of a key node in the sample-and-hold circuit of this invention;

[0029] Figure 3-4 This is an embodiment of the adjustment control logic unit in the present invention;

[0030] Figure 3-5 The waveforms of F1_latch, F2, and the key input signals in this invention are shown.

[0031] Figure 3-6 This is an embodiment of the compensation register unit in the present invention;

[0032] Figure 3-7 This is the control signal waveform in the compensation register unit of this invention;

[0033] Figure 3-8 This is the waveform of the registered voltage signal in the compensation register unit of this invention;

[0034] Figure 3-9 This is an embodiment of the foldback compensation current generating unit in this invention;

[0035] Figure 3-1 0 represents a change in the compensation voltage V(k) that characterizes the slope compensation amount;

[0036] Figure 3-11 represents another variation process of the compensation voltage V(k) characterizing the slope compensation amount;

[0037] Figure 4 This is a flowchart of the compensation method for a turnaround slope compensation system. Detailed Implementation

[0038] The purpose of this invention is to adjust the slope compensation in real time in actual switching power supply systems to eliminate subharmonic oscillation problems or large and small wave problems caused by excessive duty cycle or other disturbances, and to find the optimal compensation point through foldback compensation adjustment.

[0039] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but the present invention is not limited to these embodiments. The present invention covers any alternatives, equivalent methods, and solutions made within the spirit and scope of the present invention.

[0040] The present invention will be described in more detail in the following paragraphs with reference to the accompanying drawings and examples. It should be noted that the drawings are provided in a simplified and intuitive manner rather than using precise scales or parameters, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0041] like Figure 3 The system block diagram of this invention shows that the foldback slope compensation system includes an error detection unit, an adjustment control logic unit, a compensation register unit, and a foldback compensation current generation unit. The input of the error detection unit is connected to the switch control signal GON, the output of the error detection unit is connected to the input of the adjustment control logic unit, the output of the adjustment control logic unit is connected to the input of the foldback compensation current generation unit, the input of the compensation register unit is connected to the output of the foldback compensation current generation unit, and the output of the compensation register unit is connected to the input of the foldback compensation current generation unit.

[0042] The error detection unit includes a grouping circuit and a sample-and-hold circuit. The grouping circuit groups the (2k-1)th cycle and the 2kth cycle together, where k is a positive integer greater than or equal to 1, and k∈N. + .like Figure 3-1 As shown, a D flip-flop is used to group the switch control signal GON into two groups in the 2k-1 and 2k cycles. The D flip-flop internally connects the traditional output terminal QB to the input terminal D, so the D port is omitted in the figure and is only used as a frequency divider. Figure 3-1 The generated control signals KT1~KT4 and KT1B~KT4B will control the operation of the sample-and-hold circuit. The output signals KT1B, KT2, KT3, KT3B, KT4, and KT4B generated by the grouping circuit are connected to... Figure 3-2The input terminals of the sample-and-hold circuit, specifically, control the on / off states of PM01~PM04 and NM01~NM04 respectively. When KT1 and KT3 are high, KT1B and KT3B are low, while KT2 and KT1 are mutually exclusive. At this time, PM01 and PM02 are on, and current source I0 charges capacitor C03. When KT1 is low and KT2 and KT3 are high, current source I1 discharges capacitor C03. If the current magnitudes of current sources I0 and I1 are set to be equal, then the rising and falling slopes of voltage Va1 on capacitor C03 are equal. When KT4 is high, Va1 is stored on capacitor CS. Similarly, the voltage Va2 on capacitor C04 is also stored on capacitor CS when KT3 is high. Since KT3 and KT4 represent the odd and even groups in groups 1 to K respectively, the difference in the on-time of the external power transistors in the odd groups is converted into voltage Va1, and the difference in the on-time of the external power transistors in the even groups is converted into voltage Va2. Figure 3-2 The sampled and held voltage is stored on capacitor CS to obtain a constantly refreshed voltage VS(k). Figure 3-3 It is given schematically. Figure 3-2 The voltage waveforms of Va1 and Va2 shown in the figure, as well as the final output voltage VS(k), show that when there is a time difference between the on-time (high-level duration) of the external power transistor in two adjacent cycles in the k-th group, VS(k) is not 0; when the on-time (high-level duration) of two adjacent cycles in the k-th group is equal, VS(k) is 0.

[0043] See Figure 3-4This invention provides an implementation of the adjustment control logic unit. The output signals KT3 and KT4 generated by the error detection unit are respectively passed through two falling-edge delay circuits and then ORed to obtain an internal clock signal CLK. CLK then passes through a rising-edge pulse generation circuit to obtain a periodic pulse signal K1, and a falling-edge pulse generation circuit to obtain a periodic pulse signal K2. K1 and K2 are used to control the operation of the compensation register unit and the foldback compensation current generation unit. The error signal VS(k) generated by the error detection unit and the reference voltage Vref are compared by comparator COMPD1 to obtain the comparison result. Vref is a voltage greater than 0 and less than +20mV. The comparison result of comparator COMPD1 is sampled by the falling edge of CLK through D flip-flops DFF21 and DFF22 to obtain control signals F1 and F2. When F1 first changes from low to high, F1_Latch is locked at high level and does not change. The output signals F1_Latch and F2 of the judgment circuit are connected to the input terminals of the compensation register unit and the foldback compensation current generation unit. The locking of F1_Latch signifies that, from this moment on, the foldback compensation current generation unit and the compensation register unit will enter the foldback compensation adjustment phase to seek the optimal compensation effect. See also... Figure 3-5 The waveforms of key signals such as F1_latch, F2, and VS(k) are given. After F1_Latch is locked to a high level, the F2 signal controls the direction of the folding adjustment, whether it folds upward or downward, and finally controls the value of VS(k) to be approximately equal to Vref.

[0044] See Figure 3-6 This paper presents one embodiment of the compensation register unit in this invention. Under the control of the output signals K1 and K2 of the adjustment control logic unit, the output signal V(k+1) from the foldback compensation current generation unit is shifted and stored on capacitors C31 and C32. Since V(k+1) lags behind the voltage on capacitor C31 by one cycle, and the voltage on capacitor C31 lags behind the voltage on capacitor C32 by one cycle, the voltage information on C31 and the voltage information on C32 can be represented by V(k) and V(k-1), respectively. Simultaneously, when F1_Latch is locked to a high level, NMR2 is turned off, and the voltage on VLCK remains unchanged. See the control signal waveforms of switches K1~K2 for reference. Figure 3-7 K1 and K2 have been generated by the aforementioned adjustment control logic unit. The waveforms of the voltages V(k), V(k-1), and VLCK on C31, C32, and C33 are as follows: Figure 3-8 As shown.

[0045] See Figure 3-9, an embodiment of the folding compensation current generation unit in the present invention is given. The data selector selects one or two of V(k), V(k-1), and VLCK according to the control signals F1_Latch and F2 output by the adjustment control logic unit and sends them to the input end of the adder. The resistance values of the resistors in the adder satisfy RA1 = RA2 = RA3 = RA4 = 2RA5 = 2RA6. The output of the adder is also controlled by NMV3. Specifically, the following situations are included:

[0046] 1) When F1_Latch is at a low level and F2 is also at a low level, V(k) and V(k-1) are selected and sent to the input end of the adder. Since F1_Latch is at a low level, V(k+1) = V(k) + V(k-1);

[0047] 2) When F1_Latch is locked at a high level and F2 is at a low level, V(k) and V(k-1) are selected and sent to the input end of the adder. At the same time, RA5 is short-circuited by NMV3. At this time, V(k+1) = [V(k) + V(k-1)] / 2;

[0048] 3) When F1_Latch is locked at a high level and F2 is at a high level, VLCK is selected and sent to the input end of the adder. At the same time, RA5 is short-circuited by NMV3. At this time, V(k+1) = [V(k) + VLCK] / 2.

[0049] Figure 3-1 0 and Figure 3-1 1 schematically shows the change process of the compensation voltage V(k+1) characterizing the ramp compensation amount. It can be seen that in Figure 3-1 0, when three cycle steps are taken, when the compensation amount is 8V0, F1 becomes high for the first time and locks VLCK = 5V0. Then in the next cycle, the compensation amount is (8V0 + 5V0) / 2 = 6.5V0. At this time, the ramp compensation is still insufficient, and VS(k) < Vref in this group, so the F2 signal flips to low, and then in the next cycle, it is adjusted to (6.5V0 + 8V0) / 2 = 7.25V0... and so on in a loop. Figure 3-1 In 1, when three cycle steps are taken, when the compensation amount is 8V0, F1 becomes high for the first time. Then in the next cycle, the compensation amount is (8V0 + 5V0) / 2 = 6.5V0. At this time, the compensation is excessive, so F2 remains high, indicating over-compensation. Then in the next cycle, the compensation amount is corrected to (6.5V0 + 5V0) / 2 = 5.75V0, and F2 remains high, indicating over-compensation. And in the next cycle, the compensation amount is (5.75V0 + 5V0) / 2 = 5.375V0... and so on in an endless loop. V(k+1) takes a folding change form under the action of the control voltage F2 and finally selects the optimal compensation voltage. Figure 3-9The ramp generation circuit is also given. The physical voltage V(k + 1) characterizing the ramp compensation amount controls the current to integrate on the capacitor to form a ramp voltage. The ramp starts to be generated under the control of the Ctrl signal, where Ctrl is the enable signal provided by the switching power supply. Different V(k + 1) generates ramps Vslope(k + 1) with different slopes, achieving dynamic change of the ramp compensation amount within each group.

[0050] Figure 4 The compensation method flowchart of the flyback ramp compensation system is given, including the following steps:

[0051] (1) When the system enters full load and the feedback voltage reaches the maximum value and remains unchanged, the ramp compensation adjustment starts. The feedback voltage mentioned refers to that in the switching power supply, in order to make the system stable, the system needs to work in a closed-loop negative feedback state. The feedback voltage is the real-time feedback of the output voltage of the switching power supply system and indicates the load weight. Taking the flyback converter as an example, the feedback voltage is generated by the optoelectronic coupling device and TL431.

[0052] (2) According to the switch control signal, the adjacent 2k - 1th period and 2kth period are divided into the kth group, where k ∈ N + and N + represents positive integers;

[0053] (3) Detect the conduction time difference of the external power transistor within the adjacent 2k - 1th period and 2kth period in the kth group, and convert this conduction time difference into an error voltage signal VS(k);

[0054] (4) Compare VS(k) with the reference voltage Vref. Vref is a voltage greater than 0 and less than +20 mV. According to the comparison result, adjust the ramp compensation voltage.

[0055] Further, the step (4) specifically includes the following steps:

[0056] (4.1) Use the compensation register unit to store the voltage V(k) characterizing the ramp compensation information within the kth group and the voltage V(k - 1) characterizing the ramp compensation information within the k - 1th group;

[0057] (4.2) Within the kth group, if VS(k) > Vref, then within the next group, that is, within the k + 1th group, the voltage V(k + 1) characterizing the ramp compensation information is corrected to V(k) + V(k - 1), and repeat this process until VS(k) < Vref appears for the first time, generate a latch signal F1_Latch, enter the flyback compensation adjustment stage, latch the voltage V(k - 1) characterizing the ramp compensation information within the 2k - 1th period to a capacitor to generate a voltage VLCK;

[0058] After entering the folding-back compensation adjustment stage, within the i-th group, where i > k and i ∈ N + , if VS(i) > Tref, then the voltage V(i + 1) representing the ramp compensation information in the next group, i.e., the (i + 1)-th group, is corrected to [V(i) + V(i - 1)] / 2; if VS(i) < Tref, then the voltage V(i + 1) representing the ramp compensation information in the next group, i.e., the (i + 1)-th group, is corrected to [V(i) + VLCK] / 2;

[0059] (4.4) Repeat step (4.3). Through infinite folding-back, the compensation value will eventually approximately stabilize at an optimal value.

Claims

1. A reversible slope compensation system, characterized in that, The system includes an error detection unit, an adjustment control logic unit, a compensation register unit, and a foldback compensation current generation unit. The input of the error detection unit is connected to the switching control signal GON generated by the switching power supply, representing the periodic conduction of the external power transistor. The output of the error detection unit, the error voltage signal VS(k), and control signals KT3 and KT4, are connected to the three inputs of the adjustment control logic unit. The error voltage signal VS(k) represents the error voltage signal in the k-th group after grouping the switching control signal GON according to adjacent periods, where k is a positive integer greater than or equal to 1. The output of the adjustment control logic unit, the control signals K1, K2, and F1_Latch, are connected to the compensation register unit. The three input terminals of the compensation register unit are connected to the three input terminals of the foldback compensation current generation unit. The control signal F1_Latch, the control signal F2 generated by the adjustment control logic unit, and the switch control signal GON are also connected to the three input terminals of the foldback compensation current generation unit. The other input terminal of the compensation register unit is also connected to the voltage signal V(k+1) generated by the foldback compensation current generation unit, which represents the slope compensation information. The output signals V(k), V(k-1) and VCLK of the compensation register unit are connected to the other three input terminals of the foldback compensation current generation unit. Finally, the foldback compensation current generation unit uses the voltage signal V(k+1) to generate the slope compensation voltage Vslope(k+1) output. The error detection unit, when the switching power supply is in operation, divides adjacent cycles 2k-1 and 2k into a k-th group based on the input switching control signal GON. It detects the difference in conduction time between the external power transistors within cycles 2k-1 and 2k, converts this difference into an error voltage signal VS(k) within the k-th group, and outputs it along with control signals KT3 and KT4 to the adjustment control logic unit. The error detection unit includes a grouping circuit and a sample-and-hold circuit. The grouping circuit includes D flip-flops DFF01 and DFF02, NAND gates Nand01 and Nand02, and NAND gate Na... The D flip-flop DFF01 is connected to the clock input CLK of the D flip-flop DFF01, one input of the NAND gate Nand01, one input of the NAND gate Nand02, and one input of the NOR gate Nor01. The output Q of the D flip-flop DFF01 is connected to the other input of the NOR gate Nor01 and the other input of the NAND gate Nand01. Connect the other input of NAND gate Nand02. The output signals KT1B of NAND gate Nand01 and KT1 after passing through inverter INV01 are connected to the output signal KT1. The output signals KT2B of NAND gate Nand02 and KT2 after passing through inverter INV03 are connected to the output signal KT2. The output of NOR gate Nor01, after passing through inverter INV02, is connected to the clock input CLK of D flip-flop DFF02, one input of NAND gate Nand03, and one input of NAND gate Nand04. The output Q of D flip-flop DFF02 is connected to the other input of NAND gate Nand03. Connect the other input terminal of the NAND gate Nand04. The output signal KT3B of the NAND gate Nand03 and the output signal KT3 after the signal KT3B passes through the inverter INV04. The output signal KT4B of the NAND gate Nand04 and the output signal KT4 after the signal KT4B passes through the inverter INV05. The sample-and-hold circuit includes PMOS transistors PM01, PM02, PM03, PM04, NMOS transistors NM01, NM02, NM03, NM04, NMS1, NMS2, capacitors C01, C02, C03, C04, CS, resistors R01 and R02, and inverters INV11, INV12, INV13, and INV14. The power supply VDD is respectively... Connect the input terminals of current source I0 and current source I3. The output terminal of current source I0 is connected to the source of PMOS transistor PM01. The drain of PMOS transistor PM01 is connected to the source of PMOS transistor PM02. The drain of PMOS transistor PM02 is connected to the drain of NMOS transistor NM01 and one end of capacitor C03 and outputs signal Va1. The source of NMOS transistor NM01 is connected to the drain of NMOS transistor NM02. The source of NMOS transistor NM02 is connected to the input terminal of current source I1. The output terminal of current source I1 is connected to the other end of capacitor C03 and grounded. The gate of PMOS transistor PM01 is connected to the output signal KT1B of the grouping circuit. The gate of PMOS transistor PM02 is connected to the output signal KT3B of the grouping circuit. The gate of NMOS transistor NM01 is connected to the output signal KT2 of the grouping circuit. The gate of NMOS transistor NM02 is connected to the output signal KT3 of the grouping circuit.The output of current source I3 is connected to the source of PMOS transistor PM03. The drain of PMOS transistor PM03 is connected to the source of PMOS transistor PM04. The drain of PMOS transistor PM04 is connected to the drain of NMOS transistor NM03 and one end of capacitor C04, outputting signal Va2. The source of NMOS transistor NM03 is connected to the drain of NMOS transistor NM04. The source of NMOS transistor NM04 is connected to the input of current source I4. The output of current source I4 is connected to the other end of capacitor C04 and grounded. The gate of PMOS transistor PM03 is connected to the output signal KT1B of the grouping circuit. The gate of PMOS transistor PM04 is connected to the output signal KT4B of the grouping circuit. The gate of NMOS transistor NM03 is connected to the output signal KT2 of the grouping circuit. The gate of NMOS transistor NM04 is connected to the output signal KT4 of the grouping circuit. The output signal KT4 of the grouping circuit is also connected to one end of resistor R01. The other end of resistor R01 is connected to capacitor C04. One end of 01 is connected to the input of inverter INV11, the other end of capacitor C01 is grounded, the output of inverter INV11 is connected to the input of inverter INV12, the output of inverter INV12 is connected to the gate of NMOS transistor NMS1, the drain of NMOS transistor NMS1 is connected to the output signal Va1, the source of NMOS transistor NMS1 is connected to the drain of NMOS transistor NMS2 and one end of capacitor CS and serves as the output of the error detection unit to output the voltage error signal VS(k), the other end of capacitor CS is grounded, the source of NMOS transistor NMS2 is connected to the output signal Va2, the gate of NMOS transistor NMS2 is connected to the output of inverter INV14, the input of inverter INV14 is connected to the output of inverter INV13, the input of inverter INV13 is connected to one end of resistor R02 and one end of capacitor C02, the other end of capacitor C02 is grounded, and the other end of resistor R02 is connected to the output signal KT3 of the grouping circuit; The adjustment control logic unit, under the action of control signals KT3 and KT4 output by the error detection unit, generates control signals K1 and K2 and an asynchronous clock CLK0. It compares the error voltage signal VS(k) output in the k-th group with the reference voltage Vref in real time. When the error voltage signal VS(k) is greater than the reference voltage Vref, slope compensation adjustment is required; when the error voltage signal VS(k) is less than the reference voltage Vref, slope compensation adjustment is not required or has already been completed. The comparison result of the error voltage signal VS(k) and the reference voltage Vref is sampled by the falling edge of the asynchronous clock CLK0. Based on the sampled comparison result, control signals F1, F1_Latch, and F2 are generated. The unit includes an internal pulse generation circuit and a judgment circuit. The internal pulse generation circuit includes PMOS transistors PMD1~PMD10, NMOS transistors NMD1~NMD4, inverters INVD1~INVD10, NOR gate NorD1, NOR gate NorD2, and capacitor Cd1~ Cd4 and resistors Rd1~Rd4; the gate of PMOS transistor PMD1 is interconnected with the gate of NMOS transistor NMD1 and the gate of PMOS transistor PMD2, and serves as the input terminal of the adjustment control logic unit, connected to the output signal KT3 of the grouping circuit. The sources of PMOS transistors PMD1 and PMD2 are both connected to the power supply VDD. The drain of PMOS transistor PMD1 is connected to the drain of NMOS transistor NMD1, the drain of PMOS transistor PMD3, one end of capacitor Cd1, and the input terminal of inverter INVD1 through resistor Rd1. The output of inverter INVD1 is connected to the gate of PMOS transistor PMD3 and the input terminal of inverter INVD2. The output of inverter INVD2 is connected to the input terminal of inverter INVD3. The output of inverter INVD3 is connected to one input terminal of OR gate OR1. The other end of capacitor Cd1 is connected to the gate of NMOS transistor NMD1. The sources are all grounded; the gate of PMOS transistor PMD4 is interconnected with the gate of NMOS transistor NMD2 and the gate of PMOS transistor PMD5 and serves as the input of the adjustment control logic unit, connected to the output signal KT4 of the grouping circuit. The source of PMOS transistor PMD4 is interconnected with the source of PMOS transistor PMD5 and connected to the power supply VDD. The drain of PMOS transistor PMD4 is connected to the drain of NMOS transistor NMD2, the drain of PMOS transistor PMD6, one end of capacitor Cd2, and the input of inverter INVD4 through resistor Rd2. The output of inverter INVD4 is connected to the gate of PMOS transistor PMD6 and the input of inverter INVD5. The output of inverter INVD5 is connected to the input of inverter INVD6. The output of inverter INVD6 is connected to the other input of OR gate OR1. The other end of capacitor Cd2 and the source of NMOS transistor NMD2 are both grounded.The clock signal CLK0 output by OR gate OR1 is connected to the gates of PMOS transistor PMD7, NMOS transistor NMD3, and the input of inverter INVD7, as well as the gates of PMOS transistors PMD8, NMOS transistor NMD4, and PMOS transistor PMD9, and one input of NOR gate NorD2. The other input of NOR gate NorD2 is connected to the output of inverter INVD10. The output of NOR gate NorD2 serves as the output of the adjustment control logic unit, outputting the control signal K2. The input of inverter INVD10 is connected to the output of inverter INVD9 and... The gate of PMOS transistor PMD10 is connected to the gate of PMOS transistor PMD9. The source of PMOS transistor PMD10 is connected to the drain of PMOS transistor PMD9. The sources of PMOS transistors PMD9 and PMD8 are both connected to the power supply VDD. The drain of PMOS transistor PMD8 is connected to the drain of NMOS transistor NMD4, the drain of PMOS transistor PMD10, the input of inverter INVD9, and one end of capacitor Cd4 through resistor Rd4. The other end of capacitor Cd4 is connected to the source of NMOS transistor NMD4 and grounded. The source of PMOS transistor PMD7 is connected to the power supply VDD. The drain of the inverter is connected to one end of resistor Rd3, one end of capacitor Cd3, and the input of inverter INVD8. The output of inverter INVD8 is connected to one input of NOR gate NorD1. The other input of NOR gate NorD1 is connected to the output of inverter INVD7. The output of NOR gate NorD1 serves as the output of the adjustment control logic unit, outputting the control signal K1. The other end of resistor Rd3 is connected to the drain of NMOS transistor NMD3. The source of NMOS transistor NMD3 and the other end of capacitor Cd3 are both grounded. The judgment circuit includes comparator COMPD1 and D flip-flop DFF21. The circuit consists of a D flip-flop DFF22, an NOR gate Nor21, an NAND gate Nand21, and an inverter INV21. The negative terminal of comparator COMPD1 is connected to the error voltage signal VS(k) output by the error detection unit as the input terminal of the adjustment control logic unit. The positive terminal of comparator COMPD1 is connected to the reference voltage Vref. The output of comparator COMPD1 is connected to the input terminals D of D flip-flop DFF21 and D of D flip-flop DFF22. The clock signal CLK0 output by OR gate OR1 in the internal pulse generation circuit is connected to the input terminal of D flip-flop DFF21. and the input of D flip-flop DFF22 The output Q of D flip-flop DFF21 outputs signal F1. The output Q of DFF22 serves as the output of the adjustment control logic unit, outputting signal F2. One input of NOR gate Nor21 is connected to power supply VDD. The other input of NOR gate Nor21 is connected to the output of NOR gate Nor22. The output of NOR gate Nor21 is connected to one input of NOR gate Nor22 and one input of NAND gate Nand21. The other input of NOR gate Nor22 is connected to output signal F1 and the other input of NAND gate Nand21. The output of NAND gate Nand21 is connected to the input of inverter INV21. The output of inverter INV21 serves as the output of the adjustment control logic unit, outputting control signal F1_latch. The compensation register unit is used to dynamically store the voltage signals V(k) and V(k-1) representing the slope compensation information in the k+1th group, based on the control signals K1, K2, and F1_Latch output by the adjustment control logic unit and the voltage signal V(k+1) representing the slope compensation information in the k-1th group fed back by the folded-back compensation current generator. When the control signal F1_Latch goes high, the compensation register unit latches the voltage V(k-1) representing the slope compensation information in the k-1th group, generating the voltage signal VLCK; including the first The system comprises a voltage register and a second voltage register. The first voltage register includes NMOS transistors NMR1 and NMR2, a NOR gate Nor41, an inverter INV41, and capacitors C33 and C34. The drain of NMOS transistor NMR1 is connected to the input of the first voltage register and is linked to the feedback signal V(k+1) output by the foldback compensation current generation unit. The gate of NMOS transistor NMR1 is connected to the control signal K1 output by the adjustment control logic unit. The source of NMOS transistor NMR1 is connected to the drain of NMOS transistor NMR2 and one end of capacitor C34. The other end of capacitor C34 is grounded. The source of NMR2 is connected to one end of capacitor C33 and serves as the output of the compensation register, outputting the signal VLCK. The other end of capacitor C33 is grounded. The gate of NMR2 is connected to the output of inverter INV41. The input of inverter INV41 is connected to the output of NOR41. The two inputs of NOR41 are connected to the control signals F1_latch and K2 of the adjustment control logic unit, respectively. The second voltage register includes NMR3, NMR4, capacitors C31 and C32. The drain of NMR3 is... The input of the second voltage register is connected to the feedback signal V(k+1) output by the foldback compensation current generation unit. The source of NMOS transistor NMR3 is connected to the drain of NMOS transistor NMR4 and one end of capacitor C31 and outputs signal V(k). The other end of capacitor C31 is grounded. The source of NMOS transistor NMR4 is connected to one end of capacitor C32 and outputs signal V(k-1). The other end of capacitor C32 is grounded. The gate of NMOS transistor NMR3 is connected to the control signal K1 output by the adjustment control logic unit. The gate of NMOS transistor NMR4 is connected to the control signal K2 output by the adjustment control logic unit. The foldback compensation current generation unit is used to select the output voltages V(k), V(k-1), and VCLK of the compensation register unit for addition operation based on the control signals F1_Latch and F2 generated by the adjustment control unit, generating a voltage signal V(k+1) representing the slope compensation information in the (K+1)th group. Based on the voltage signal V(k+1), a slope compensation voltage signal Vslope(k+1) is generated. It includes a data selector, an adder, and a slope generation circuit. The output of the data selector is connected to the input of the adder, and the output of the adder is connected to the input of the slope generation circuit. The slope generation circuit outputs a voltage signal V(k+1) indicating the magnitude of the compensation value in the next cycle, which is connected to the input of the compensation register unit. Simultaneously, the output signal of the slope generation circuit is the final slope compensation signal V_SLOPE output by the foldback compensation current generation unit. The data selector includes an NMOS transistor. The system consists of NMV1, NMOS transistors NMV2 and NMOS transistors NMV3, a NAND gate Nand51, inverters INV51 and INV52. The two inputs of the Nand51 are connected to the control signals F1_latch and F2 output from the adjustment control logic unit, respectively. The output of the Nand51 is connected to the gate of NMOS transistor NMV1 and the input of inverter INV51. The output of inverter INV51 is connected to the gate of NMOS transistor NMV2 and the input of inverter INV52. The output of inverter INV52 is connected to the gate of NMOS transistor NMV3. The drain of NMOS transistor NMV1 is connected to the signal V(k) output from the compensation register unit. The drain of NMOS transistor NMV2 is connected to the output signal VLCK of the compensation register unit. The drain of NMOS transistor NMV3 is connected to the output signal V(k-1) of the compensation register unit. The source output signal V1 of NMOS transistor NMV1 is connected to the first input terminal of the subsequent adder; the source output signal V2 of NMOS transistor NMV3 is connected to the second input terminal of the subsequent adder; and the source output signal V3 of NMOS transistor NMV2 is connected to the third input terminal of the subsequent adder. The adder includes operational amplifier OPV1, NMOS transistors NMV3 and NMV4, capacitor CV4, and resistors RA1 to RA6.One end of resistor RA1 is connected to the output signal V1 of the data selector, one end of resistor RA2 is connected to the output signal V2 of the data selector, and one end of resistor RA3 is connected to the output signal V3 of the data selector. The other end of resistor RA1 is connected to the other ends of resistors RA2 and RA3 and the negative terminal of operational amplifier OPV1. The positive terminal of operational amplifier OPV1 is grounded through resistor RA4. The other ends of resistors RA1, RA2, and RA3 are also connected to the drain of NMOS transistor NMV3 and one end of resistor RA5. The gate of NMOS transistor NMV3 is connected to the signal F1_latch output by the adjustment control logic unit. The other end of resistor RA5 is connected to the source of NMOS transistor NMV3 and one end of resistor RA6. The other end of resistor RA6 is connected to the output terminal of operational amplifier OPV1 and the drain of NMOS transistor NMV4. The gate of NMOS transistor NMV4 is connected to the switch control signal GON. The source of NMOS transistor NMV4 is connected to one end of capacitor CV4 and outputs a voltage signal V(k+1) indicating the magnitude of the compensation value in the next cycle. The other end of CV4 is grounded; the ramp generation circuit includes PMOS transistors PMV1, PMOS transistors PMV2, PMOS transistors PMV3, PMOS transistors PMV4, NMOS transistor NMV5, capacitor CV5, and resistor RAS; the gate of NMOS transistor NMV5 is connected to the voltage signal V(k+1) output by the adder, the source of NMOS transistor NMV5 is grounded through resistor RAS, and the drain of NMOS transistor NMV5 is connected to the drain and gate of PMOS transistors PMV1 and PMOS transistor PMV2. The sources of MOSFET PMV1 and PMV2 are both connected to VDD. The drain of PMV2 is connected to the source of PMV3. The gate of PMV3 is connected to the enable signal Ctr1. The drain of PMV3 is connected to both the drain and gate of PMV4. The source of PMV4 is connected to one end of capacitor CV5 and serves as the output of the foldback compensation current generation unit, outputting the ramp compensation signal V_SLOPE. The other end of capacitor CV5 is grounded.

2. The reversible slope compensation system according to claim 1, characterized in that, In the adjustment control logic unit, the positive terminal of comparator COMPD1 is connected to the reference voltage 0. <Vref<20mV。 3. The compensation method for the reversible slope compensation system according to claim 1 or 2, characterized in that, To address the characteristic of subharmonic oscillations occurring under heavy and full load conditions, the load state is determined based on the feedback voltage, which characterizes the real-time output voltage feedback of the switching power supply system. The difference in conduction time between two adjacent cycles is detected in real time to determine whether to adjust the internal compensation ramp size. Through a foldback adjustment, the optimal compensation ramp value is found, achieving real-time adjustment of disturbances in the system. This includes the following steps: (1)When the system enters full load and the feedback voltage reaches the maximum value and remains unchanged, the ramp compensation adjustment starts; (2) Based on the switch control signal, the adjacent 2k-1th cycle and the 2kth cycle are divided into the kth group, where k∈N + N + Represents positive integers; (3)Detect the conduction time difference of the external power transistor in the (2k - 1)-th and 2k-th cycles adjacent within the k-th group, and convert this conduction time difference into an error voltage signal VS(k); (4)Compare VS(k) with the reference voltage Vref, and adjust the ramp compensation voltage according to the comparison result.

4. The compensation method for the reversible slope compensation system according to claim 3, characterized in that, Step (4) specifically includes the following steps: (4.1)Use the compensation register unit to store the voltage V(k) representing the ramp compensation information within the k-th group and the voltage V(k - 1) representing the ramp compensation information within the (k - 1)-th group; (4.2)Within the k-th group, if VS(k) > Vref, then within the next group, that is, the (k + 1)-th group, the voltage V(k + 1) representing the ramp compensation information is corrected to V(k) + V(k - 1), and repeat this process until VS(k) < Vref appears for the first time, generate a latch signal F1_Latch, enter the flyback compensation adjustment stage, latch the voltage V(k - 1) representing the ramp compensation information in the (k - 1)-th cycle onto the capacitor C33, and generate a voltage VLCK; After entering the folding compensation adjustment stage, within the i-th group, where i > k and i ∈ N + , if VS(i) > Vref, then the voltage V(i + 1) representing the ramp compensation information in the next group, i.e., the (i + 1)-th group, is corrected to [V(i) + V(i - 1)] / 2; if VS(i) < Vref, then the voltage V(i + 1) representing the ramp compensation information in the next group, i.e., the (i + 1)-th group, is corrected to [V(i) + VLCK] / 2; (4.4)Repeat step (4.3), and through infinitely many flybacks, the compensation value will eventually stabilize at an optimal value.

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