Clock data recovery circuit and clock data recovery method
By combining a time delay loop and a frequency lock loop with a deserializer, the problem of complex circuit structure in existing clock data recovery circuits is solved, achieving simplification and improved stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SANECHIPS TECH CO LTD
- Filing Date
- 2021-03-01
- Publication Date
- 2026-06-02
AI Technical Summary
The coordinated operation of phase-locked loop and frequency-locked loop in existing clock data recovery circuits leads to complex circuit structure, requiring high-order filters for compensation to ensure system stability.
A scheme combining a time delay loop and a frequency lock loop with a deserializer is adopted. By simplifying the circuit structure through phase alignment and frequency locking, the phase integral factor is avoided, and an absolutely stable system with a single pole is achieved.
The circuit structure was simplified, resulting in an absolutely stable system. The introduction of phase integral factors was avoided, and the system complexity was reduced.
Smart Images
Figure CN115001486B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communications, and more particularly to a clock data recovery circuit and a clock data recovery method. Background Technology
[0002] In related technologies, the phase-locked loop in clock data recovery circuits achieves frequency phase locking through negative feedback between a phase detector, charge pump, loop filter, and voltage-controlled oscillator. In small-signal model analysis, we can find that the small-signal equation K of the voltage-controlled oscillator... VCO / s represents an integration unit that continuously accumulates phase during phase locking. The capacitor in the filter is 1 / sC, accumulating charge during charging and discharging. Therefore, the closed-loop simulation includes two poles. For systems with two poles, stability-related factors such as phase margin and gain margin must be considered during circuit design. Thus, high-order filters must be used in the phase-locked loop of related technologies to ensure system stability. Simultaneously, clock data recovery circuits in related technologies also include frequency-locked loops for frequency locking. These frequency-locked loops and phase-locked loops must work together, leading to a complex circuit structure for clock data recovery. Summary of the Invention
[0003] The purpose of this invention is to at least solve one of the technical problems existing in the prior art, and to provide a clock data recovery circuit and a clock data recovery method that can simplify the circuit structure.
[0004] In a first aspect, embodiments of the present invention provide a clock data recovery circuit, including a time delay loop, a frequency lock loop, and a deserializer. The time delay loop is used to delay input data according to the phase of a clock signal to achieve phase alignment. The frequency lock loop is connected to the time delay loop and is used to adjust the frequency of the clock signal according to the delayed input data so that the frequency of the clock signal is consistent with the frequency of the input data. The deserializer is connected to both the time delay loop and the frequency lock loop and is used to deserialize the input data according to the clock signal.
[0005] Secondly, embodiments of the present invention provide a clock data recovery method applied to a clock data recovery circuit. The clock data recovery circuit includes a time delay loop, a frequency lock loop, and a deserializer. The time delay loop is connected to the frequency lock loop, and the deserializer is connected to both the time delay loop and the frequency lock loop. The method includes:
[0006] The time delay loop delays the input data according to the phase of the clock signal to achieve phase alignment;
[0007] The frequency-locked loop adjusts the frequency of the clock signal according to the delayed input data so that the frequency of the clock signal is consistent with the frequency of the input data.
[0008] The deserializer deserializes the input data according to the clock signal.
[0009] This invention includes a clock data recovery circuit and a clock data recovery method. The clock data recovery circuit includes a time delay loop, a frequency lock loop, and a deserializer. The time delay loop is used to delay the input data according to the phase of the clock signal to achieve phase alignment. The frequency lock loop is connected to the time delay loop and is used to adjust the frequency of the clock signal according to the delayed input data so that the frequency of the clock signal is consistent with the frequency of the input data. The deserializer is connected to both the time delay loop and the frequency lock loop and is used to deserialize the input data according to the clock signal. According to the solution provided in this embodiment, the phase of the clock signal and the phase of the input data are first compared to delay the input data to achieve phase alignment between the input data and the clock signal, thus avoiding the introduction of phase integration factors. After phase alignment, the phase of the clock signal is consistent with the phase of the delayed input data. If the frequencies of the delayed input data and the clock signal do not match, a certain phase difference will be generated after a period of time. The frequency-locked loop adjusts the frequency of the clock signal according to the phase difference generated by the frequency mismatch between the delayed input data and the clock signal to achieve frequency locking. After the frequency and phase of the input data and the clock signal are locked, the clock signal deserializes the input data through a deserializer. The solution provided in this embodiment can avoid introducing phase integration factors into the entire circuit system, obtain an absolutely stable system with only a single pole, and simplify the circuit structure.
[0010] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description
[0011] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.
[0012] The present invention will be further described below with reference to the accompanying drawings and embodiments;
[0013] Figure 1 This is a structural diagram of a clock data recovery circuit provided in one embodiment of the present invention;
[0014] Figure 2 This is a circuit structure diagram of the numerically controlled delay unit of the clock data recovery circuit provided in an embodiment of the present invention;
[0015] Figure 3 This is a circuit diagram of the 1 / 4 frequency downconverter provided in an embodiment of the present invention;
[0016] Figure 4 This is a timing diagram of the operation of the 1 / 4 frequency down converter circuit provided in the embodiment of the present invention;
[0017] Figure 5 This is a timing diagram for determining the phase position zero and frequency provided in an embodiment of the present invention;
[0018] Figure 6 This is a flowchart of the clock data recovery method provided in an embodiment of the present invention;
[0019] Figure 7 This is a flowchart of a clock data recovery method provided in another embodiment of the present invention;
[0020] Figure 8 This is a flowchart of a clock data recovery method provided in another embodiment of the present invention. Detailed Implementation
[0021] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but they should not be construed as limiting the scope of protection of the present invention.
[0022] In the description of this invention, the use of "first" and "second" is for the purpose of distinguishing technical features only, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or the order of the technical features indicated.
[0023] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.
[0024] This invention provides a clock data recovery circuit and a clock data recovery method, which can simplify the circuit structure.
[0025] The embodiments of the present invention will be further described below with reference to the accompanying drawings.
[0026] like Figure 1 As shown, Figure 1 This is a structural diagram of a clock data recovery circuit provided in one embodiment of the present invention.
[0027] like Figure 1 As shown, a first aspect embodiment of the present invention provides a clock data recovery circuit, including a time delay loop 100, a frequency lock loop 200, and a deserializer 300. The time delay loop 100 is used to delay the input data according to the phase of the clock signal to achieve phase alignment. The frequency lock loop 200 is connected to the time delay loop 100 and is used to adjust the frequency of the clock signal according to the delayed input data so that the frequency of the clock signal is consistent with the frequency of the input data. The deserializer 300 is connected to both the time delay loop 100 and the frequency lock loop 200 and is used to deserialize the input data according to the clock signal.
[0028] In the clock data recovery circuit of this embodiment, the phase of the clock signal is first compared with the phase of the input data to delay the input data and achieve phase alignment between the input data and the clock signal, thus avoiding the introduction of phase integration factors. After phase alignment, the phase of the clock signal is consistent with the phase of the delayed input data. If the frequencies of the delayed input data and the clock signal do not match, a certain phase difference will be generated after a period of time. The frequency locking loop 200 adjusts the frequency of the clock signal according to the phase difference generated by the frequency mismatch between the delayed input data and the clock signal to achieve frequency locking. After the frequency and phase of the input data and the clock signal are locked, the clock signal is deserialized by the deserializer 300. The solution provided in this embodiment can avoid introducing phase integration factors into the entire circuit system, obtain an absolutely stable system with only a single pole, and simplify the circuit structure.
[0029] Reference Figure 1 In one embodiment, the time delay loop 100 includes a numerically controlled delay unit 110, a phase detector 120, a first down-converter 130, and a first accumulator 140 connected in sequence. The output of the first accumulator 140 is connected to the numerically controlled delay unit 110. The phase detector 120 is used to compare the phase of the clock signal and the input data. The numerically controlled delay unit 110 is used to delay the input data according to the result of the phase comparison. The output of the numerically controlled delay unit 110 is also connected to the deserializer 300 to output the delayed input data.
[0030] In this embodiment, input data is transmitted from the input terminal of the numerical control delay unit 110 to the time delay loop 100. The time delay loop 100 compares the clock signal and the delayed numerical control delay unit 110 through the phase detector 120, so that the time delay of the numerical control delay unit 110 cancels out the injection lock control logic delay.
[0031] Reference Figure 1In one embodiment, the frequency-locked loop 200 includes a frequency discriminator 210, a second frequency downscaler 220, a second accumulator 230, and a numerically controlled oscillator 240 connected in sequence. The numerically controlled oscillator 240 outputs clock signals to the phase detector 120, the frequency discriminator 210, and the deserializer 300, respectively. The output of the numerically controlled delay unit 110 is also connected to the frequency discriminator 210 to output the delayed input data.
[0032] In this embodiment, the frequency-locked loop 200 begins normal operation after the time-delay loop 100 is locked. When phase locking occurs, the injected clock signal is in phase with the delayed input data. After a period of time, a phase difference arises because the frequency of the clock signal does not match the frequency of the input data. This phase difference can be determined by the frequency discriminator 210, passed through the second down-conversion unit 220, and input to the second accumulator 230, thereby controlling the output frequency of the numerically controlled oscillator 240 to achieve frequency locking. Once both phase and frequency are locked, the clock signal is deserialized by the deserializer, outputting half-rate data.
[0033] Reference Figure 1 In one embodiment, the clock data recovery circuit further includes a pulse generator 400, the output of which is connected to a numerically controlled oscillator 240 to output a phase zero pulse. The numerically controlled oscillator 240 zeros the phase of the output clock signal according to the received phase zero pulse.
[0034] In this embodiment, phase locking is achieved by using a phase zeroing method. By employing certain control logic, a pulse signal is generated to zero the phase of the clock signal output by the numerically controlled oscillator 240. This control method can avoid introducing the phase integration factor in the numerically controlled oscillator 240, thereby obtaining an absolutely stable system with only a single pole, providing an absolutely stable system for simplifying the circuit structure.
[0035] Reference Figure 1 In one embodiment, the pulse generator 400 is provided with an input terminal for receiving input data to generate a phase position zero pulse based on the rising edge of the input data.
[0036] In this embodiment, after receiving input data, the pulse generator 400 generates a phase zero pulse based on the rising edge of the input data to zero the phase of the clock signal output by the numerically controlled oscillator 240. It can be understood that the pulse generator 400 generates a phase zero pulse every certain period of time, such as several tens of cycles.
[0037] Reference Figure 1 In one embodiment, the pulse generator 400 is connected to the phase detector 120 to trigger the phase detector 120 to perform a phase comparison between the clock signal and the input data.
[0038] In this embodiment, in addition to being connected to the numerically controlled oscillator 240, the pulse generator 30 is also connected to the phase detector 120. After the pulse generator 30 outputs a phase zero pulse to the numerically controlled oscillator 240, it also outputs a trigger signal to the phase detector 120 to trigger the phase detector 120 to compare the phase of the clock signal and the input data. After passing through the first down-conversion unit 130 and the first accumulator 140, the numerically controlled delay unit 110 delays the input data according to the phase difference between the clock signal and the input data to achieve phase alignment between the input data and the clock signal.
[0039] Reference Figure 1 In one embodiment, the pulse generator 400 is connected to the frequency discriminator 210 to trigger the frequency discriminator 210 to determine the frequency of the clock signal and the delayed input data.
[0040] In this embodiment, the frequency-locked loop 200 starts operating after the time-delay loop 100 is locked. Therefore, the pulse generator 400 is connected to the frequency discriminator 210 to output a trigger signal to the frequency discriminator 210, enabling the frequency discriminator 210 to determine the frequency of the clock signal and the delayed input data after phase locking. It is understood that the frequency discriminator 210 can also determine the frequency of the clock signal and the input data before phase locking, that is, it can determine the frequency of the clock signal and the input data without delay. However, since the clock signal is not injected with lock, the frequency determination result will be inaccurate.
[0041] In the clock data recovery circuit described above, phase alignment is achieved by setting the phase to zero. By using certain control logic, a pulse signal is generated to set the phase of the output clock of the numerically controlled oscillator to zero. Frequency determination is performed within a certain time after the phase is set to zero, which reduces one phase integration factor and can obtain an absolutely stable system with only a single pole, thus providing an absolutely stable system for simplifying the circuit structure.
[0042] Based on the clock data recovery circuit of the above embodiments, various embodiments of the clock data recovery method are proposed below.
[0043] Reference Figure 6 Embodiments of the present invention also provide a clock data recovery method, applicable to, for example... Figure 1 The clock data recovery circuit shown includes a time delay loop 100, a frequency-locked loop 200, and a deserializer 300. The time delay loop 100 is connected to the frequency-locked loop 200, and the deserializer 300 is connected to both the time delay loop 100 and the frequency-locked loop 200. The clock data recovery method includes the following steps:
[0044] Step S610: The time delay loop 100 delays the input data according to the phase of the clock signal to achieve phase alignment;
[0045] Step S620: The frequency lock loop 200 adjusts the frequency of the clock signal according to the delayed input data so that the frequency of the clock signal is consistent with the frequency of the input data;
[0046] Step S630: The deserializer 300 deserializes the input data according to the clock signal.
[0047] The clock data recovery method provided in this embodiment first compares the phase of the clock signal with the phase of the input data through a time delay loop 100, thereby delaying the input data to achieve phase alignment between the input data and the clock signal, avoiding the introduction of phase integration factors. After phase alignment, the phase of the clock signal is consistent with the phase of the delayed input data. If the frequencies of the delayed input data and the clock signal do not match, a certain phase difference will be generated after a period of time. The frequency locking loop 200 adjusts the frequency of the clock signal according to the phase difference generated by the frequency mismatch between the delayed input data and the clock signal to achieve frequency locking. After the frequency and phase of the input data and the clock signal are locked, the clock signal is deserialized by the deserializer 300. The scheme provided in this embodiment can avoid introducing phase integration factors into the entire circuit system, obtain an absolutely stable system with only a single pole, and simplify the circuit structure.
[0048] Reference Figure 1 In one embodiment, the time delay loop 100 includes a numerically controlled delay unit 110, a phase detector 120, a first frequency down converter 130 and a first accumulator 140 connected in sequence. The output terminal of the first accumulator 140 is connected to the numerically controlled delay unit 110, and the output terminal of the numerically controlled delay unit 110 is connected to the deserializer 300.
[0049] Reference Figure 7 In step S610, the time delay loop 100 delays the input data according to the phase of the clock signal to achieve phase alignment, including the following steps:
[0050] Step S710: Phase detector 120 performs a phase comparison between the clock signal and the input data;
[0051] Step S720: The numerical control delay unit 110 delays the input data according to the phase comparison result to achieve phase alignment.
[0052] In this embodiment, input data is transmitted from the input terminal of the numerical control delay unit 110 to the time delay loop 100. The time delay loop 100 compares the clock signal and the delayed numerical control delay unit 110 through the phase detector 120. The numerical control delay unit 110 delays the input data according to the phase comparison result to achieve phase alignment, so that the time delay of the numerical control delay unit 110 cancels out the injection lock control logic delay.
[0053] Reference Figure 1 In one embodiment, the frequency lock loop 200 includes a frequency discriminator 210, a second frequency downscaler 220, a second accumulator 230 and a digitally controlled oscillator 240 connected in sequence. The digitally controlled oscillator 240 is connected to the phase detector 120, the frequency discriminator 210 and the deserializer 300 respectively. The output of the digitally controlled delay unit 110 is also connected to the frequency discriminator 210.
[0054] Reference Figure 8 In step S620, the frequency-locked loop 200 adjusts the frequency of the clock signal according to the delayed input data to make the frequency of the clock signal consistent with the frequency of the input data, including the following steps:
[0055] Step S810: The numerical control delay unit 110 outputs the delayed input data to the frequency discriminator 210;
[0056] Step S820: Frequency discriminator 210 determines the frequency of the clock signal and the delayed input data;
[0057] Step S830: The numerically controlled oscillator 240 adjusts the frequency of the clock signal according to the phase difference determined by the frequency.
[0058] In this embodiment, the frequency-locked loop 200 begins normal operation after the time delay loop 100 is locked. Therefore, the numerically controlled delay unit 110 outputs the delayed input data to the frequency discriminator 210. When the phase is locked, the injected locked clock signal is in phase with the delayed input data. After a period of time, a certain phase difference will occur because the frequency of the clock signal does not match the frequency of the input data. This phase difference can be determined by the frequency discriminator 210, and then input to the second accumulator 230 after passing through the second down-conversion unit 220, thereby controlling the output frequency of the numerically controlled oscillator 240 to achieve the purpose of frequency locking. When both the phase and frequency are locked, the clock signal is deserialized by the deserializer, and half-rate data is output.
[0059] The following is combined with Figures 1 to 5 The embodiments of the present invention will be further described below.
[0060] The clock data recovery circuit provided in specific embodiments of the present invention, such as... Figure 1As shown. The clock data recovery circuit includes a time delay loop 100, a frequency lock loop 200, a deserializer 300, and a pulse generator 400. The time delay loop 100 includes a digitally controlled delay unit 110, a phase detector 120, a first frequency downsampling unit 130, and a first accumulator 140 connected in sequence. The output of the first accumulator 140 is connected to the digitally controlled delay unit 110. The frequency lock loop 200 includes a frequency detector 210, a second frequency downsampling unit 220, a second accumulator 230, and a digitally controlled oscillator 240 connected in sequence. The digitally controlled oscillator 240 outputs clock signals to the phase detector 120, the frequency detector 210, and the deserializer 300, respectively. The output of the digitally controlled delay unit 110 is also connected to the frequency detector 210 and the deserializer 300. The output of the pulse generator 400 is connected to the digitally controlled oscillator 240 to output a phase zero-position pulse. After the system is locked, the data passed through the digitally controlled delay unit 110 is deserialized and output. Time delay loop 100 compares clock signal P0 with delayed input data D through phase detector 120. DLY A phase comparison is performed to cancel out the time delay of the numerical control delay unit 110 and the injection lock control logic delay. The frequency lock loop 200 begins normal operation after the time delay loop 100 locks the phase. Once the phase is locked, the injected clock signal P0 and the input data D... DLY The phases are consistent. After a period of time, because the frequency of the clock signal P0 is consistent with the input data D... DLY A mismatch will result in a phase difference, which can be determined by the frequency discriminator 210. After passing through a 1 / 16 frequency downsampling circuit, the result is input into the digital accumulator 230, thereby controlling the output frequency of the numerically controlled oscillator 240 to achieve frequency locking. Once both frequency and phase are locked, the clock signal is deserialized by the deserializer 300, outputting half-rate data. Phase locking is achieved by using a phase zeroing method. By employing certain control logic, a pulse signal is generated to zero the phase of the clock signal output by the numerically controlled oscillator 240. This control method avoids introducing the phase integral factor into the numerically controlled oscillator, resulting in an absolutely stable system with only a single pole, providing an absolutely stable system for simplifying the circuit structure. Figure 2 This is a circuit diagram of the numerically controlled delay unit 110. The numerically controlled delay unit 110 uses a 2-bit binary code to select different signals for coarse adjustment and a 31-bit thermometer code for fine adjustment. The control bits of the thermometer code are evenly distributed across the four loads to ensure that the difference in load capacitance is minimized when the thermometer code changes, thus avoiding affecting the duty cycle of the signal. Figure 3This is a circuit diagram of a 1 / 4 downclocker 130. Because the clock data recovery circuit typically operates at a high frequency, the data obtained through the frequency discriminator or phase detector also has a high frequency, making it impossible to directly enter the accumulator for processing. Therefore, it needs to be processed by a downclocker before entering the accumulator. The downclocker works by splitting the individual data and clock information into two data sets, while simultaneously halving the clock frequency. Figure 4 Timing diagram for the operation of a 1 / 4 downconverter circuit. Figure 5 This is a timing diagram illustrating the phase position zeroing and frequency determination in an embodiment of the present invention. After the phase position zeroing pulse is generated, the delayed input data D... DLY The phase of the clock signal P0 is aligned with the rising edge. After a certain period of time, a phase difference will occur due to the inconsistency between the data rate and the clock frequency. The frequency can be determined based on this phase difference. Figure 5 The frequency determination result shown indicates that the clock signal frequency is too high. Therefore, the output determination result will be used to reduce the output frequency of the numerically controlled oscillator 240.
[0061] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.
Claims
1. A clock data recovery circuit, characterized in that, include: A time delay loop is used to delay the input data according to the phase of the clock signal to achieve phase alignment; A frequency-locked loop, connected to the time-delay loop, is used to adjust the frequency of the clock signal according to the delayed input data so that the frequency of the clock signal is consistent with the frequency of the input data. The deserializer is connected to the time delay loop and the frequency lock loop respectively, and is used to deserialize the input data according to the clock signal.
2. The clock data recovery circuit according to claim 1, characterized in that, The time delay loop includes a numerically controlled delay unit, a phase detector, a first frequency down converter, and a first accumulator connected in sequence. The output of the first accumulator is connected to the numerically controlled delay unit. The phase detector is used to compare the phase of the clock signal and the input data. The numerically controlled delay unit is used to delay the input data according to the phase comparison result. The output of the numerically controlled delay unit is also connected to the deserializer to output the delayed input data.
3. The clock data recovery circuit according to claim 2, characterized in that, The frequency-locked loop includes a frequency discriminator, a second frequency downscaler, a second accumulator, and a digitally controlled oscillator connected in sequence. The digitally controlled oscillator outputs clock signals to the phase detector, the frequency discriminator, and the deserializer, respectively. The output of the digitally controlled delay unit is also connected to the frequency discriminator to output delayed input data.
4. A clock data recovery circuit according to claim 3, characterized in that, It also includes a pulse generator, the output of which is connected to the numerically controlled oscillator to output a phase zero pulse. The numerically controlled oscillator zeros the phase of the output clock signal according to the received phase zero pulse.
5. A clock data recovery circuit according to claim 4, characterized in that, The pulse generator is provided with an input terminal for receiving input data, so as to generate a phase position zero pulse according to the rising edge of the input data.
6. A clock data recovery circuit according to claim 4, characterized in that, The pulse generator is connected to the phase detector to trigger the phase detector to perform a phase comparison between the clock signal and the input data.
7. A clock data recovery circuit according to claim 4, characterized in that, The pulse generator is connected to the frequency discriminator to trigger the frequency discriminator to determine the frequency of the clock signal and the delayed input data.
8. A clock data recovery method, applied to a clock data recovery circuit, the clock data recovery circuit comprising a time delay loop, a frequency lock loop, and a deserializer, wherein the time delay loop is connected to the frequency lock loop, and the deserializer is connected to both the time delay loop and the frequency lock loop, characterized in that, The method includes: The time delay loop delays the input data according to the phase of the clock signal to achieve phase alignment; The frequency-locked loop adjusts the frequency of the clock signal according to the delayed input data so that the frequency of the clock signal is consistent with the frequency of the input data. The deserializer deserializes the input data according to the clock signal.
9. A clock data recovery method according to claim 8, characterized in that, The time delay loop includes a digitally controlled delay unit, a phase detector, a first frequency down converter, and a first accumulator connected in sequence. The output of the first accumulator is connected to the digitally controlled delay unit, and the output of the digitally controlled delay unit is connected to the deserializer. The time delay loop delays the input data according to the phase of the clock signal to achieve phase alignment, including: The phase detector compares the clock signal with the input data in phase. The numerical control delay unit delays the input data based on the phase comparison result to achieve phase alignment.
10. A clock data recovery method according to claim 9, characterized in that, The frequency lock loop includes a frequency discriminator, a second frequency down-converter, a second accumulator, and a digitally controlled oscillator connected in sequence. The digitally controlled oscillator is connected to the phase detector, the frequency discriminator, and the deserializer, respectively. The output of the digitally controlled delay unit is also connected to the frequency discriminator. The frequency-locked loop adjusts the frequency of the clock signal based on the delayed input data to make the frequency of the clock signal consistent with the frequency of the input data, including: The numerical control delay unit outputs the delayed input data to the frequency discriminator; The frequency discriminator determines the frequency of the clock signal and the delayed input data. The numerically controlled oscillator adjusts the frequency of the clock signal based on the phase difference determined by the frequency.