Error Reduction through Circuit Specification Selection

Abstract

Systems and methods for quantum error mitigation are provided. The method may include: accessing a quantum system; implementing a plurality of quantum circuits; obtaining a plurality of measurements performed for each of the quantum circuits; determining an estimated average value of an observable of interest for the quantum circuits based at least in part on the plurality of measurements <o> f ; and, using a single-point complete depolarization error model based at least in part on an estimated average value of the observations of interest <o> f To determine the estimated noise-free value of the interest observation value <o> ψ Each of the multiple quantum circuits can be implemented by a different sequence of quantum gates compared to each of the other quantum circuits in the multiple quantum circuits, thereby implementing one or more circuit specifications, and each of the multiple quantum circuits can be an equivalent logical operation of each of the other quantum circuits in the multiple quantum circuits.< / o> < / o> < / o>

Description

[0001] Priority Claim

[0002] This application claims the benefit of U.S. Provisional Patent Application Ser. No. 62 / 936,753, filed Nov. 18, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to quantum computing systems. Background Art

[0004] Quantum computing is a method of computing that exploits the advantages of quantum effects, such as superposition and entanglement of basis states, which are the basis for performing certain computations more efficiently than classical digital computers. In contrast to digital computers that store and manipulate information in the form of bits (e.g., “1” or “0”), quantum computing systems can manipulate information using qubits (quantum bits). A qubit can refer to a quantum device capable of achieving superposition of multiple states (e.g., data in both the “0” and “1” states), and / or to the superposition of the data itself in multiple states. According to traditional terminology, the superposition of the “0” and “1” states in a quantum system can be represented as, for example, a|0>+b|1>. The “0” and “1” states of a digital computer are analogous to the |0> and |1> basis states of a qubit, respectively. Summary of the Invention

[0005] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the following description, or may be learned from the description, or may be learned through practice of the embodiments.

[0006] One example aspect of the present disclosure relates to a quantum computing system. The quantum computing system can include a quantum system that includes one or more quantum system qubits. The quantum system can be configured to implement a plurality of quantum circuits. Each quantum circuit can include a plurality of quantum gates. Each of the plurality of quantum circuits can be an equivalent logical operation to each of the other quantum circuits in the plurality of quantum circuits. Each of the plurality of quantum circuits can be implemented by a different sequence of quantum gates compared to each of the other quantum circuits in the plurality of quantum circuits, thereby implementing one or more circuit gauges. The quantum computing system can also include a quantum measurement circuit implemented by the quantum computing system. The quantum measurement circuit is operable to perform a plurality of measurements on the quantum circuits. The quantum computing system can also include one or more processors operable to perform operations. The operations can include determining an average value of an observable of interest for the quantum circuits based at least in part on the plurality of measurements. <o> f The operation may also include at least partially based on the average value of the interest observations <o> f to implement an error mitigation scheme for a quantum computing system.

[0007] Another example aspect of the present disclosure relates to a method for estimating noiseless observables of a quantum computing system. The method may include: accessing, by a computing system including one or more computing devices, a quantum system including one or more qubits and one or more quantum measurement devices. The method may further include: implementing, by the computing system, a plurality of quantum circuits. Each quantum circuit may include a plurality of quantum gates. Each of the plurality of quantum circuits may be an equivalent logical operation to each of the other quantum circuits of the plurality of quantum circuits. Each of the plurality of quantum circuits may be implemented by a different sequence of quantum gates compared to each of the other quantum circuits of the plurality of quantum circuits, thereby implementing one or more circuit specifications. The method may further include: obtaining, by the computing system via one or more quantum measurement devices, a plurality of measurements performed for each quantum circuit. The method may further include: determining, by the computing system, an estimated average value of an observable of interest for the quantum circuit based at least in part on the plurality of measurements <o> f The method may further include: using, by a computing system, a single-point full depolarizing error model to at least partially based on an estimated average value of the observations of interest <o> f to determine the estimated noise-free value of the interest observation value <o> ψ 。

[0008] Another example aspect of the present disclosure relates to a method for noise error mitigation for a quantum system. The method may include: accessing, by a computing system including one or more computing devices, a quantum system including one or more qubits and one or more quantum measurement devices. The method may further include: implementing, by the quantum system, a plurality of quantum circuits. Each quantum circuit may include a plurality of quantum gates. Each of the plurality of quantum circuits may be an equivalent logical operation to each of the other quantum circuits in the plurality of quantum circuits. Each of the plurality of quantum circuits may be implemented by a different sequence of quantum gates compared to each of the other quantum circuits in the plurality of quantum circuits, thereby implementing one or more circuit specifications. The method may further include: obtaining, by the computing system via one or more quantum measurement devices, a plurality of measurements performed for the one or more quantum circuits. The method may further include: determining, by the computing system, an estimated average value of an observable of interest for the quantum circuit based at least in part on the plurality of measurements <o> f 。The method may further include: at least in part by a computing system based on the average value of the interest observations <o> f to implement an error mitigation scheme for a quantum system.

[0009] Other aspects of the present disclosure relate to various systems, methods, devices, non-transitory computer-readable media, computer-readable instructions, and computing devices.

[0010] These and other features, aspects, and advantages of the various embodiments of the present disclosure will become better understood with reference to the following description and the appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate example embodiments of the present disclosure and, together with the description, serve to explain the relevant principles. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the specification, a detailed discussion of embodiments for those of ordinary skill in the art is set forth, and the detailed discussion refers to the accompanying drawings, in which:

[0012] Figure 1 depicts an example quantum computing system in accordance with an example embodiment of the present disclosure;

[0013] Figure 2 depicts an example circuit specification for incorporating one or more Clifford gates into a quantum circuit in accordance with an example aspect of the present disclosure;

[0014] Figure 3 depicts an example circuit specification for incorporating Clifford gates and non-Clifford gates into a quantum circuit in accordance with an example aspect of the present disclosure;

[0015] Figure 4 depicts an example circuit specification for incorporating Clifford gates and non-Clifford gates into a quantum circuit in accordance with an example aspect of the present disclosure;

[0016] Figure 5 depicts a flowchart of an example method in accordance with an example aspect of the present disclosure; and

[0017] Figure 6 depicts a flowchart of an example method in accordance with an example aspect of the present disclosure. DETAILED DESCRIPTION

[0018] Generally, the present disclosure relates to systems, apparatuses, and methods that allow for implementing improved error mitigation techniques in a quantum computing system to reduce the impact of noise during state measurement. For example, in some implementations, a single-point fully depolarizing error mitigation scheme only requires quantum circuit measurement data obtained when implementing one or more circuit specifications, and the fidelity estimation of the quantum circuit can be used to improve the accuracy of quantum computing, such as noisy-intermediate scale quantum (NISQ) computing.

[0019] More specifically, the quantum system may include one or more quantum system qubits. The quantum system may be configured to implement one or more circuit specifications using multiple quantum circuits. For example, each quantum circuit may include multiple quantum gates, and each of the quantum circuits may be an equivalent logical operation to each of the other quantum circuits. Each of the quantum circuits may be implemented by a different sequence of quantum gates. By selecting logically equivalent quantum circuits implemented using different sequences of quantum gates, the noise observed in the quantum circuits during measurement can be randomized.

[0020] The quantum measurement circuit implemented in the quantum computing system may perform multiple measurements (e.g., state measurements) on the quantum circuits. These measurements may be performed in parallel for each qubit in the quantum system. For example, readout resonators may be configured to obtain measurements for each qubit in the quantum system.

[0021] Estimated average value of the observable of interest for the quantum circuit <o> f It can be determined at least in part based on multiple measurements. Then, an error mitigation scheme for a quantum computing system can be at least in part based on the average value of the observables of interest <o> f be implemented.

[0022] For example, in some embodiments, one or more circuit specifications implemented by a quantum system may include one or more randomized circuit specifications. For example, one or more randomized circuit specifications may be implemented by injecting one or more random Pauli operator pairs or single-qubit gates into the quantum circuit during free space or in combination with gates already present in the quantum circuit (e.g., during idle times when the quantum circuit is not acting on qubits during the times of the gates). The random Pauli operator pairs or other single-qubit gates may be equivalent to the identity (e.g., they are self-inverse) and may be commuted through adjacent gates until the free space is filled. By commuting the random Pauli operator pairs through quantum gates (or gates), logical operations that are equivalent but implemented in different specifications (such as the Pauli specification) may be performed. The Pauli operators may be commuted through a subset or all of the quantum gates in the quantum circuit.

[0023] In some embodiments, one or more random Pauli operator pairs may be injected by incorporating one or more Clifford gates into the quantum circuit. In some embodiments, one or more random Pauli operator pairs may be injected by incorporating one or more non-Clifford gates into the quantum circuit.

[0024] According to an additional aspect of the present disclosure, in some embodiments, a single-point full depolarization error mitigation scheme may be implemented using the raw measurement data and an approximation of the fidelity f of the quantum circuit. In the single-point full depolarization error mitigation scheme, no additional measurements at different error levels are required, such as the measurements used in a multi-point extrapolation error mitigation scheme.

[0025] To implement the single-point full depolarization error mitigation scheme, an approximation of the circuit fidelity f of one or more circuit specifications may be determined. For example, in some embodiments, cross-entropy benchmarking for a similar circuit structure may be used to determine the approximation of the circuit fidelity f. In some embodiments, the approximation of the circuit fidelity f may be estimated at least in part based on only counting the number of single-qubit gates and two-qubit gates.

[0026] Then, at least in part based on the average value of the observables of interest <o> f and the approximate circuit fidelity f to determine the inferred mean of the observations <o> ψ For example, the formula <o> f ＝f <o> ψ + to determine the inferred mean of the observed values <o> ψ where O is the desired observation, and includes a component attributable to noise.

[0027] The single-point full depolarization error mitigation scheme provided herein can offer more advantages than other error mitigation schemes. For example, since no additional sample points are required, the original number of samples needed can be reduced, which helps avoid the difficulty of converging to a similar accuracy at several different points prior to extrapolation like in multi-point extrapolation schemes. Additionally, the complications associated with operating a device near the limits of its capabilities can be avoided, as an increase in error beyond the threshold for obtaining a reasonable signal can cause the extrapolation scheme to become unstable.

[0028] In some embodiments, one or more circuit specifications can be used to implement a multi-point extrapolation scheme. For example, a noise injection method and multiple extrapolation points can be selected. Each extrapolation point can be evaluated with different random circuit specifications. For example, during each of one or more circuit specifications, one or more additional Clifford gates and one or more corresponding inverses of one or more additional Clifford gates can be implemented. Then, extrapolation can be performed to obtain an improved inferred value of the observation O.

[0029] In some embodiments, circuit specifications can be selected to promote a preferred error direction, which can be biased or unbiased based on the optimal operating mechanism of a quantum error correction code and decoder. For example, during at least one of one or more circuit specifications, existing errors can be biased towards a preferred direction, and error correction codes can be used to correct known error types.

[0030] Aspects of the present disclosure can provide several technical effects and benefits and can provide improvements to quantum computing technology. For example, the single-point full depolarization error mitigation scheme according to an example aspect of the present disclosure can be used to perform extrapolation using single-point estimation by leveraging the knowledge that the circuit specifications are randomly selected. Additionally, compared to other extrapolation error mitigation schemes (e.g., multi-point error mitigation schemes), this error mitigation scheme can reduce the amount of sampling required. Furthermore, the single-point full depolarization error mitigation scheme can remove the possibility of instability associated with making measurements at increased noise levels.

[0031] Additional technical effects and benefits of the present disclosure include allowing for dense packing of quantum circuits through Pauli operator injection and commutation, which can be used for both Clifford and non-Clifford gates. This in turn can allow the randomized circuit specifications used to randomize the noise obtained during quantum circuit measurements, thus allowing the observed noise to be closer to a fully depolarized channel.

[0032] The systems and methods of the present disclosure also provide different combinations of circuit specifications (e.g., randomized circuit specifications and / or preferred error direction circuit specifications) for use with other error mitigation schemes such as multi-point extrapolation schemes and error correction codes. This can allow for improved error mitigation performance, such as when using error correction codes in a quantum computing system.

[0033] The systems and methods of the present disclosure can allow for improved noise mitigation in a quantum computing system. For example, by more accurately compensating for noise in observed measurements, measurement accuracy can be improved, making the quantum computing system more accurate.

[0034] Referring now to the drawings, example aspects of the present disclosure will be discussed in further detail. Figure 1 An example quantum computing system 100 is depicted. The example system 100 is an example of a system implemented as a classical or quantum computer program on one or more classical computers or quantum computing devices in one or more locations, where the systems, components, and techniques described below can be implemented. Figure 1 An example quantum computing system 100 that can be used to implement aspects of the present disclosure is depicted. Those of ordinary skill in the art will understand that other quantum computing architectures or systems can be used without departing from the scope of the present disclosure by using the disclosure provided herein.

[0035] System 100 includes quantum hardware 102 that communicates data with one or more classical processors 104. Quantum hardware 102 includes components for performing quantum computing. For example, quantum hardware 102 includes a quantum system 110, one or more control devices 112, and one or more readout resonators 114. Quantum system 110 can include one or more multi-level quantum subsystems, such as a register of qubits. In some embodiments, the multi-level quantum subsystem can include superconducting qubits, such as flux qubits, charge qubits, transmon qubits, etc. In some embodiments, the multi-level quantum subsystem can include one or more qubits (e.g., a unit of quantum information described by a superposition of D states). In some embodiments, the multi-level quantum subsystem can include a fermionic quantum subsystem.

[0036] The type of multi-level quantum subsystem utilized by system 100 can vary. For example, in some cases, it may be convenient to include one or more readout resonators 114 attached to one or more superconducting qubits (e.g., transmon, flux, Gmon, Xmon, or other qubits). In other cases, ion traps, photonic devices, or superconducting cavities (through which states can be prepared without the need for qubits) can be used. Further examples of implementing multi-level quantum subsystems include fluxmon qubits, silicon quantum dots, or phosphorus-doped qubits.

[0037] A quantum circuit can be constructed via multiple control lines coupled to one or more control devices 112 and applied to a register of qubits included in a quantum system 110. Example control devices 112 that operate on the register of qubits include quantum logic gates or circuits of quantum logic gates, e.g., Clifford gates (such as Hadamard gate, controlled NOT (CNOT) gate, phase gate) and non-Clifford gates (such as square root of Z gate, T gate, etc.). One or more control devices 112 can be configured to operate on the quantum system 110 via one or more corresponding control parameters (e.g., one or more physical control parameters). For example, in some embodiments, the multi-level quantum subsystem can be a superconducting qubit, and the control device 112 can include one or more digital-to-analog converters (DACs) with corresponding voltage physical control parameters.

[0038] The quantum hardware 102 can also include a quantum measurement device, e.g., a readout resonator 114. The measurement result 108 obtained via the quantum measurement device can be provided to the classical processor 104 for processing and analysis. In some embodiments. The quantum hardware 102 can include a quantum circuit, and the (multiple) control devices 112 and the (multiple) readout resonators 114 (or other quantum measurement devices) can include one or more quantum logic gates that operate on the quantum system 102 via microwave pulse physical control parameters sent through the wires included in the quantum hardware 102. Further examples of control devices include arbitrary waveform generators, where the DAC creates signals. The control parameters can include qubit frequencies.

[0039] The (multiple) readout resonators 114 (or other quantum measurement devices) can be configured to perform quantum measurements on the quantum system 110 and send the measurement result 108 to the classical processor 104. Additionally, the quantum hardware 102 can be configured to receive data specifying the physical control parameter values 106 from the classical processor 104. The quantum hardware 102 can use the received physical control parameter values 106 to update the actions of the (multiple) control devices 112 and the (multiple) readout resonators 114 on the quantum system 110. For example, the quantum hardware 102 can receive data specifying a new value representing the voltage strength of one or more DACs included in the control device 112 and can update the actions of the DACs on the quantum system 110 accordingly. The (multiple) readout resonators 114 can be included in one or more quantum measurement circuits operable to perform multiple quantum measurements on the quantum system 110.

[0040] The classical processor 104 can be configured to initialize the quantum system 110 in an initial quantum state (e.g., by sending data of an initial set of specified parameters 106 to the quantum hardware 102).

[0041] The readout resonator 114 (or other quantum measurement device) can take advantage of the impedance difference between the |0> and |1> states of elements (such as qubits) of the quantum system to measure the state of elements (such as qubits). For example, due to the non-linearity of the qubit, when the qubit is in the state |0> or the state |1>, the resonant frequency of the readout resonator 114 can take different values. Therefore, the microwave pulse reflected from the readout resonator 114 carries an amplitude and phase shift depending on the qubit state. In some embodiments, a Purcell filter can be used in combination with the readout resonator 114 to impede the propagation of microwaves at the qubit frequency.

[0042] According to an example aspect of the present disclosure, the quantum computing system 100 (more specifically, the quantum system 110) can be configured to implement one or more circuit specifications by implementing a plurality of quantum circuits. For example, each quantum circuit can include a plurality of quantum gates, and each of the plurality of quantum circuits can be an equivalent logical operation to each of the other quantum circuits in the plurality of quantum circuits. However, each of the plurality of quantum circuits can be implemented by a different sequence of quantum gates compared to each of the quantum circuits in the plurality of quantum circuits, thereby implementing one or more circuit specifications.

[0043] In some embodiments, one or more circuit specifications can include one or more randomized circuit specifications. For example, in some embodiments, one or more randomized circuit specifications can be implemented by injecting one or more pairs of random Pauli operators into one or more quantum circuits. Then, the Pauli operators can propagate through the quantum gates of the quantum circuit, and the quantum gates include Clifford gates and non-Clifford gates.

[0044] For example, the fact that U 2 of the Pauli operator = I (since the Pauli operator is self-inverse) can be utilized to add a pair of Pauli operators to the quantum circuit. Then, the pair of Pauli operators can be commuted through the quantum gates to reach an equivalent (but implemented in a different Pauli specification) operation.

[0045] For example, now referring to Figure 2 , an example circuit specification 200 incorporating one or more Clifford gates into a quantum circuit is depicted according to an example aspect of the present disclosure. Figure 2 Depicts an example circuit specification for injecting one or more pairs of random Pauli operators into a quantum circuit by incorporating one or more Clifford gates into the quantum circuit.

[0046] As shown, circuit specification 200 includes three logically equivalent quantum circuits 210, 220, and 230 implemented using different sequences of quantum gates.

[0047] For example, the first quantum circuit 210 includes a controlled-Z operation implemented by a Clifford gate on two qubits. The quantum circuit 210 can be expressed as the equation C(Z) 1,2 .

[0048] The second quantum circuit 220 includes an operation logically equivalent to the first quantum circuit 210, but the second quantum circuit 220 includes a pair of Pauli X operators. The quantum circuit 220 can be expressed as the equation C(Z) 1,2 X 1 X 1 .

[0049] Similarly, the third quantum circuit 230 includes an operation logically equivalent to the first quantum circuit 210 and the second quantum circuit 220. However, as Figure 2 shown, for the third quantum circuit 230, one of the Pauli X operators has been transformed through the quantum circuit. The quantum circuit 230 can be expressed as the equation X 1 Z 2 C(Z) 1,2 X 1 .

[0050] The example randomized circuit specification techniques of the present disclosure can also be applied to non-Clifford gates. For example, referring to Figure 3 , an example circuit specification 300 for incorporating one or more non-Clifford gates into a quantum circuit according to an example aspect of the present disclosure is depicted.

[0051] As shown, circuit specification 300 includes three logically equivalent quantum circuits 310, 320, and 330 implemented using different sequences of quantum gates.

[0052] For example, the first quantum circuit 310 includes a square root of controlled-Z operation (also known as a controlled-phase gate) implemented by a non-Clifford gate on two qubits. The quantum circuit 310 can be expressed as the equation C(Z 1 / 2 ) 1,2 .

[0053] The second quantum circuit 320 includes operations that are logically equivalent to those of the first quantum circuit 310, but the second quantum circuit 320 includes pairs of Pauli X operators. The quantum circuit 320 can be expressed as the equation C(Z 1 / 2 ) 1,2 X 1 X 1 .

[0054] Similarly, the third quantum circuit 330 includes operations that are logically equivalent to those of the first quantum circuit 310 and the second quantum circuit 320. However, as Figure 3 shown, for the third quantum circuit 330, one of the Pauli X operators has been transformed through the quantum circuit. The quantum circuit 330 can be expressed as the equation X 1 Z 1 / 2 2 C(Z -1 / 2 ) 1,2 X 1 .

[0055] Now referring to Figure 4 , another example circuit specification 400 for incorporating one or more non-Clifford gates into a quantum circuit in accordance with example aspects of the present disclosure is depicted. Similar to Figure 3 , the example circuit specification 400 includes non-Clifford gates.

[0056] As shown, the circuit specification 400 includes three logically equivalent quantum circuits 410, 420, and 430 implemented using different sequences of quantum gates.

[0057] For example, the first quantum circuit 410 includes a plurality of logic gates implemented on one or two qubits, including the fourth root of Z gate (also referred to as the T gate), the R X (θ) gate, the inverse fourth root of Z gate (also referred to as the inverse T gate), and the controlled-Z gate. The R X (θ) gate is a single-qubit rotation about the x-axis by an angle θ. The quantum circuit 410 can be expressed as the equation

[0058] The second quantum circuit 420 includes operations that are logically equivalent to those of the first quantum circuit 410, but the second quantum circuit 420 includes Pauli X operators. The quantum circuit 420 can be expressed as the equation

[0059] Similarly, the third quantum circuit 430 includes operations that are logically equivalent to those of the first quantum circuit 410 and the second quantum circuit 420. However, as Figure 4 shown, for the third quantum circuit 430, the Pauli X operator has been transformed through the quantum circuit. The quantum circuit 430 can be expressed as the equation

[0060] Figures 2 to 4 The depicted example circuit specifications 200 to 400 are example circuit specifications depicting equivalent logical operations of quantum circuits including Clifford and non-Clifford gates and are for illustrative purposes only. One of ordinary skill in the art will recognize that other circuit specifications can be similarly implemented using additional and / or other quantum gates. Additionally, the circuit specifications and example specification randomization techniques of the present disclosure can be applied to less conventional quantum gates, such as Fermi-simulated gates (FSIM), but with a slightly reduced degree of specification freedom. For example, in some embodiments, pairs of Pauli operators can be propagated between quantum circuits, while in other embodiments, individual Pauli operators can be propagated between quantum circuits.

[0061] Referring again to Figure 1 , a quantum measurement circuit (such as one or more readout resonators 114 or other quantum measurement devices) can obtain multiple measurements of a quantum circuit implemented (e.g., as part of one or more circuit specifications). The multiple measurements can then be used by one or more processors (such as one or more classical processors 104) to implement an error mitigation scheme for the quantum computing system 100.

[0062] For example, one or more processors can determine an average value of an observable of interest based at least in part on the multiple measurements <o> f In addition, one or more processors may be at least partially based on the average value of the interest observations <o> f to implement an error mitigation scheme.

[0063] For example, according to an example aspect of the present disclosure, in some embodiments, a single-point full depolarization error mitigation scheme can be implemented on the quantum computing system 100. The single-point full depolarization mitigation scheme can be used, for example, to determine an estimated noise-free value of an observable of interest for the quantum computing system 100 using only the raw measurement data and an estimate of the fidelity f of the quantum computing system 100. <o> ψ 。The single-point full depolarization error mitigation scheme can utilize the following knowledge: Quantum circuits with sufficiently random circuit specifications follow a noise model that is very similar to the fully depolarizing channel.

[0064] For example, the randomized circuit specifications can be implemented by a quantum system, and multiple measurements performed for each quantum circuit of the circuit specifications can be obtained by a quantum measurement circuit (e.g., one or more readout resonators 114 and / or other quantum measurement devices). In some embodiments, Pauli operators can be injected into the quantum circuit during free space of the quantum circuit (e.g., during idle time when the circuit is not acting on qubits during the time of the gate), and the Pauli operators can be transformed through adjacent gates until the free space is filled. Then, one or more processors can estimate the average value of the observable of interest at least in part based on the multiple measurements <o> f 。

[0065] According to additional aspects of the present disclosure, one or more processors may also determine an approximation of the circuit fidelity f. An advantage provided by the single-point full depolarization error mitigation scheme is that when a quantum circuit uses a randomly selected circuit specification, one or more simplification methods may be used to estimate the circuit fidelity f with high probability. For example, in one implementation, gate or cycle fidelity measured for a class of gates of the quantum circuit may be used, and the number of single-qubit gates and two-qubit gates may be counted to measure the fidelity f. In some implementations, component cross-entropy benchmarking for similar circuit structures may be used to determine an approximation of the circuit fidelity f.

[0066] Once an approximation of the circuit fidelity f is determined, a set of random specifications (possibly of size 1) of the circuit may be selected, and one or more processors may determine the average expected value of the observables of interest by averaging multiple measurements of the corresponding set of random specifications <o> f .

[0067] Then, one or more processors can be at least partially based on the average of the interest observations <o> f and an approximation of the circuit fidelity f to determine an inferred mean of the observations of interest <o> ψ For example, the formula

[0068]

[0069] can be used to determine the inferred mean of the interest observations <o> ψ , where O is the desired observation, and includes a component attributable to noise. The inferred mean of the observed values of interest <o> ψ can be the estimated noise-free value of the observed value of interest determined using the single-point full depolarization error model <o> ψ 。

[0070] An advantage provided by the single-point full depolarization error mitigation scheme is that no additional sample points (such as in a multi-point extrapolation error mitigation scheme) are required. Thus, compared to an extrapolation scheme that must converge to a similar accuracy at several different points before extrapolation, the original number of samples required can be reduced. Additionally, if the device is operating near the limits of its capabilities, a multi-point extrapolation scheme may require some means of systematically increasing the error. In the case where the error increase exceeds the threshold for obtaining a reasonable signal, the extrapolation scheme may become unstable.

[0071] However, the systems and methods of the present disclosure can also be implemented with a multi-point extrapolation scheme. For example, one or more processors can at least partially based on the average of the observations of interest by implementing a multi-point extrapolation scheme <o> ψ Implement an error mitigation scheme for the quantum computing system 100. For example, a noise injection method can be selected together with multiple extrapolation points. In some embodiments, the noise injection method can include implementing one or more additional Clifford gates and one or more corresponding inverses of one or more additional Clifford gates during each of one or more circuit specifications.

[0072] Then, one or more processors can implement a multi-point extrapolation scheme by analyzing each of the multiple extrapolation points with different random circuit specifications in one or more circuit specifications and extrapolating an inferred value of the observable of interest O based at least in part on the analysis of the multiple extrapolation points.

[0073] In some embodiments, circuit specifications can be used to promote a preferred error direction. For example, it can be understood that a circuit specification induces a particular type of noise in a known direction. Such a circuit specification can be used, for example, to introduce a known type of error that will be corrected using an error correction code.

[0074] For example, one or more processors can, at least in part based on the average value of the observables of interest, by selecting a circuit specification configured to implement a preferred error direction for error mitigation <o> f to implement an error mitigation scheme for a quantum computing system 100. Circuit specifications can be configured to implement known error types. Then, one or more processors can use error correction codes to correct the known error types.

[0075] The systems and methods of the present disclosure can allow for at least partially based on the average of the interest observations <o> f to implement an error mitigation scheme for a quantum computing system 100. Additionally, the systems and methods of the present disclosure may allow for determining a corrected error-of-interest observable O by correcting the noise components of multiple measurements.

[0076] Figure 5 A flowchart depicting an example method 500 in accordance with example aspects of the present disclosure. Method 500 may be implemented using any suitable quantum computing system, such as Figure 1 the depicted quantum computing system 100. For purposes of illustration and discussion, Figure 5 the steps are depicted in a particular order. Those of ordinary skill in the art, using the disclosures provided herein, will understand that the individual steps in any of the methods disclosed herein may be adjusted, modified, performed simultaneously, omitted, not recited, rearranged, and / or extended in various ways without departing from the scope of the present disclosure.

[0077] In 502, method 500 may include: accessing a quantum system (e.g., Figure 1 the quantum system 110 and / or quantum hardware 102). The quantum system may include one or more quantum system qubits and one or more quantum measurement devices. The quantum system may be configured to implement multiple quantum circuits. Each of the multiple quantum circuits may be implemented by a different sequence of quantum gates compared to each of the other quantum circuits in the multiple quantum circuits, thereby implementing one or more circuit specifications.

[0078] In 504, method 500 may include: implementing multiple quantum circuits. Each of the multiple quantum circuits may be implemented by a different sequence of quantum gates compared to each of the other quantum circuits in the multiple quantum circuits, thereby implementing one or more circuit specifications. In some embodiments, one or more of the circuit specifications may be one or more randomized circuit specifications. For example, one or more pairs of Pauli operators may be propagated through the quantum circuits. In some embodiments, one or more of the quantum circuits may include (e.g., incorporate) one or more Clifford gates. In some embodiments, one or more of the quantum circuits may include (e.g., incorporate) one or more non-Clifford gates.

[0079] In 506, method 500 may include: obtaining multiple measurements performed for one or more of the quantum circuits. For example, (multiple) quantum measurement devices (e.g., (multiple) readout resonators) may obtain one or more measurements for each of one or more of the quantum circuits.

[0080] In 508, method 500 may include: determining an estimated average value of an observable of interest for the quantum circuits, at least in part based on the multiple measurements <o> f .

[0081] In 510, method 500 may include: using a single-point complete depolarization error model to at least partially estimate an average value based on the observed values of interest <o> f To determine an estimated noise-free value of an interest observation value <o> ψ .

[0082] For example, in some embodiments, using a single-point full depolarization error model is at least partially based on an estimated average value of an interest observation <o> f To determine the estimated noise-free value of the interest observation value <o> ψ may include: determining an approximation of the circuit fidelity f of one or more circuit specifications. In some embodiments, the approximation of the circuit fidelity f of one or more circuit specifications may include component cross-entropy benchmarking for similar circuit topologies. In some embodiments, the approximation of the circuit fidelity f of one or more circuit specifications may include counting the number of single-qubit gates and two-qubit gates in the circuit and using the circuit fidelity of these types of gates.

[0083] In some embodiments, using a single-point fully depolarizing error model is at least partially based on an estimated average of observables of interest <o> f to determine an estimated noise-free value of the interest observation value <o> ψ It may further include: at least partially based on the average value of the interest observations <o> f and the approximate circuit fidelity f to determine the inferred mean of the observed values <o> ψ .

[0084] For example, in some embodiments, at least in part based on the average value of the interest observations <o> f and an approximation of the circuit fidelity f to determine an inferred mean of the observations of interest <o> ψ may include: determining an inferred mean value of an observed value according to the formula <o> ψ , where O is the desired observation, and includes a component attributable to noise.

[0085] The estimated mean value of the observations of interest is at least partially based on the single-point fully depolarizing error model <o> f to determine an estimated noise-free value of the interest observation value <o> ψ may include: determining a corrected error interest observation value O by correcting noise components of multiple measurements.

[0086] Figure 6 A flowchart depicting an example method 600 according to example aspects of the present disclosure. The method 600 may be implemented using any suitable quantum computing system, such as Figure 1 the depicted quantum computing system 100. For purposes of illustration and discussion, Figure 6 the steps are depicted in a particular order. One of ordinary skill in the art, by using the disclosure provided herein, will understand that the individual steps in any of the methods disclosed herein may be adjusted, modified, executed simultaneously, omitted, not recited, rearranged, and / or extended in various ways without departing from the scope of the present disclosure.

[0087] At 602, the method 600 may include: accessing a quantum system (e.g., Figure 1 the quantum system 110 and / or the quantum hardware 102). The quantum system may include one or more quantum system qubits and one or more quantum measurement devices. The quantum system may be configured to implement multiple quantum circuits. Each of the multiple quantum circuits may be implemented by a different sequence of quantum gates compared to each of the other quantum circuits in the multiple quantum circuits, thereby implementing one or more circuit specifications.

[0088] At 604, the method 600 may include: implementing multiple quantum circuits. Each of the multiple quantum circuits may be implemented by a different sequence of quantum gates compared to each of the other quantum circuits in the multiple quantum circuits, thereby implementing one or more circuit specifications. In some embodiments, one or more of the circuit specifications may be one or more randomized circuit specifications. For example, one or more pairs of Pauli operators may be propagated through the quantum circuit. In some embodiments, one or more of the quantum circuits may include (e.g., incorporate) one or more Clifford gates. In some embodiments, one or more of the quantum circuits may include (e.g., incorporate) one or more non-Clifford gates. In some embodiments, one or more of the quantum circuits may include one or more quantum circuits configured to implement a preferred error direction for error mitigation.

[0089] At 606, the method 600 may include: obtaining multiple measurements performed for one or more of the quantum circuits. For example, (multiple) quantum measurement devices (e.g., (multiple) readout resonators) may obtain one or more measurements for each of the one or more quantum circuits.

[0090] In 608, method 600 may include: determining an estimated average value of an observable of interest for a quantum circuit based at least in part on a plurality of measurements <o> f .

[0091] In 610, method 600 may include: at least partially based on the average value of the interest observations <o> f to implement an error mitigation scheme for a quantum system. In some embodiments, a single-point fully depolarizing error mitigation scheme can be used. In some embodiments, a multi-point extrapolation scheme can be used. In some embodiments, error correction codes can be used.

[0092] The digital and / or quantum subject matter described in this specification, as well as the embodiments of digital functional operations and quantum operations, can be implemented in digital electronic circuits, appropriate quantum circuits, or more generally, quantum computing systems, in tangible-implemented digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware including the structures disclosed in this specification and their structural equivalents, or implemented in a combination of one or more of them. The term "quantum computing system" can include, but is not limited to, quantum computers / computing systems, quantum information processing systems, quantum cryptography systems, or quantum simulators.

[0093] The embodiments of the digital and / or quantum subject matter described in this specification can be implemented as one or more digital and / or quantum computer programs, that is, one or more modules of digital and / or quantum computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, a data processing apparatus. The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubit / qubits structures, or a combination of one or more of them. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) capable of encoding digital and / or quantum information, the propagated signal being generated to encode digital and / or quantum information for transmission to an appropriate receiver device for execution by the data processing apparatus.

[0094] The terms "quantum information and quantum data" refer to information or data carried, held, or stored in a quantum system, where the smallest non-microscopic system is a qubit, that is, a system that defines the unit of quantum information. It can be understood that the term "qubit" includes all quantum systems that can be appropriately approximated as two-level systems in the corresponding context. Such quantum systems can include multi-level systems, e.g., two-level or more. For example, such systems can include atoms, electrons, photons, ions, or superconducting qubits. In many embodiments, the computational basis states are identified as the ground state and the first excited state, however, it can be understood that other settings where the computational states are identified as higher excited states (e.g., qubits) are possible.

[0095] The term "data processing device" refers to digital and / or quantum data processing hardware and includes all kinds of devices, equipment, and machines for processing digital and / or quantum data, such as programmable digital processors, programmable quantum processors, digital computers, quantum computers, or multiple digital and quantum processors or computers, and combinations thereof. The device may also be or further include special-purpose logic circuits, such as, for example, FPGAs (field-programmable gate arrays), or ASICs (application-specific integrated circuits), or quantum simulators, i.e., quantum data processing devices designed to simulate or generate information about a particular quantum system. Specifically, a quantum simulator is a special-purpose quantum computer that does not have the ability to perform general quantum computing. In addition to hardware, the device may optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code that constitutes processor firmware, protocol stacks, database management systems, operating systems, or combinations of one or more of them.

[0096] Digital computer programs (which may also be referred to as or described as programs, software, software applications, modules, software modules, scripts, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and digital computer programs can be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a digital computing environment. Quantum computer programs (which may also be referred to as or described as programs, software, software applications, modules, software modules, scripts, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and quantum computer programs are translated into an appropriate quantum programming language or can be written in a quantum programming language, such as, for example, QCL, Quipper, Cirq, etc.

[0097] Digital and / or quantum computer programs may, but need not, correspond to files in a file system. The program may be stored in a portion of a file that holds other programs or data (such as one or more scripts stored in a markup language document), stored in a single file dedicated to the relevant program, or stored in multiple coordinated files, such as files that store one or more modules, subroutines, or portions of code. Digital and / or quantum computer programs can be deployed to execute on a single digital computer or a single quantum computer, or deployed to execute on multiple digital and / or quantum computers located at one site or distributed across multiple sites and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network that can transmit quantum data using quantum systems (such as qubits). Generally, digital data communication networks cannot transmit quantum data; however, quantum data communication networks can transmit both quantum data and digital data.

[0098] The processes and logical flows described in this specification can be performed by one or more programmable digital and / or quantum computers operated by one or more digital and / or quantum processors that execute, as appropriate, one or more digital and / or quantum computer programs to perform functions by operating on input digital and quantum data and generating output. The processes and logical flows can also be performed by special-purpose logic circuitry (e.g., FPGA or ASIC), or a quantum simulator, or a combination of special-purpose logic circuitry or a quantum simulator and one or more programmed digital and / or quantum computers, and apparatuses can also be implemented as special-purpose logic circuitry, or a quantum simulator, or a combination of special-purpose logic circuitry or a quantum simulator and one or more programmed digital and / or quantum computers.

[0099] For a system of one or more digital and / or quantum computers or processors to be "configured to" or "operable to" perform particular operations or actions means that the system has software, firmware, hardware, or a combination thereof installed on it that in operation causes the system to perform the operations or actions. For one or more digital and / or quantum computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that, when executed by a digital and / or quantum data processing apparatus, cause the apparatus to perform the operations or actions. A quantum computer can receive instructions from a digital computer that, when executed by the quantum computing apparatus, cause the apparatus to perform the operations or actions.

[0100] Digital and / or quantum computers suitable for executing digital and / or quantum computer programs can be based on general or special-purpose digital microprocessors and / or quantum microprocessors or both, or any other kind of central digital and / or quantum processing unit. In general, the central digital and / or quantum processing unit will receive instructions and digital and / or quantum data from a read-only memory or random access memory or a quantum system (e.g., photons) suitable for transmitting quantum data, or a combination thereof.

[0101] Some example elements of a digital and / or quantum computer are a central processing unit for running or executing instructions, and one or more memory devices for storing instructions and digital and / or quantum data. Special-purpose logic circuitry or a quantum simulator can be supplemented to or incorporated into the central processing unit and memory. In general, a digital and / or quantum computer will also include one or more mass storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks, or a quantum system suitable for storing quantum information) for storing digital and / or quantum data, or be operatively coupled to a mass storage device to receive digital and / or quantum data from and / or transmit digital and / or quantum data to the mass storage device, or both. However, a digital and / or quantum computer need not have such devices.

[0102] A digital and / or quantum computer-readable medium suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data includes all forms of non-volatile digital and / or quantum memories, media, and memory devices, such as including: semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM disks and DVD-ROM disks; and quantum systems, such as trapped atoms or electrons. It can be understood that a quantum memory is a device capable of storing quantum data in high fidelity and with high efficiency for a long time, for example, an optical-matter interface where light is used for transmission and matter is used to store and preserve quantum characteristics (such as superposition or quantum coherence) of quantum data.

[0103] The control of various systems described in this specification, or parts thereof, can be implemented in a digital and / or quantum computer program product including instructions stored on one or more non-transitory machine-readable storage media, and the instructions can be executed on one or more digital and / or quantum processing devices. The systems or parts thereof described in this specification can each be implemented as an apparatus, method, or electronic system, which can include one or more digital and / or quantum processing devices and memory to store executable instructions for performing the operations described in this specification.

[0104] Although this specification contains many specific implementation details, these implementation details should not be construed as limitations on the scope that can be claimed, but rather as descriptions of features specific to particular implementations. The specific features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented separately in multiple implementations, or in any suitable sub-combination. Additionally, although the features are described above as acting in a particular combination, and even initially claimed as such, in some cases, one or more features from the combination can be removed from the claimed combination, and the claimed combination can be directed to a sub-combination or variations of the sub-combination.

[0105] Similarly, although the figures depict operations in a particular order, this should not be construed as requiring the operations to be performed in the particular order shown or in sequential order, or requiring all of the operations shown to achieve the desired result. In certain cases, multitasking and parallel processing may be advantageous. Additionally, the separation of the various system modules and components in the above-described implementations should not be construed as required in all implementations. It should be understood that the described program components and systems can generally be integrated together in a single software product, or packaged into multiple software products.

[0106] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the acts recited in the claims can be performed in a different order and still achieve the desired result. As one example, the processes depicted in the figures need not be in the particular order shown or sequential order to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.< / o> < / o> < / o> < / o> < / o> ​< / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o> < / o>

Claims

1. A quantum computing system, comprising: a quantum system including one or more quantum system qubits, the quantum system being configured to implement a plurality of quantum circuits, each quantum circuit including a plurality of quantum gates, each of the plurality of quantum circuits further including an equivalent logical operation with each of the other quantum circuits of the plurality of quantum circuits, each of the plurality of quantum circuits being implemented by a different sequence of quantum gates compared to each of the other quantum circuits of the plurality of quantum circuits, thereby implementing one or more circuit specifications; a quantum measurement circuit implemented by the quantum computing system, the quantum measurement circuit being operable to perform a plurality of measurements on the quantum circuits; and one or more processors operable to perform operations, the operations including: Determine an average value of an observable of interest for the quantum circuit, at least in part based on the plurality of measurements <o> f ; and< / o> at least in part based on an average value of the interest observations <o> f to implement an error mitigation scheme for the quantum computing system< / o> wherein, at least partially based on the average value of the interest observation values <o> f Implementing an error mitigation scheme for the quantum computing system includes implementing a single-point full depolarization error mitigation scheme,< / o> wherein implementing a single-point full depolarization error mitigation scheme includes determining an approximation of the circuit fidelity f for the one or more circuit specifications.

2. The quantum computing system according to claim 1, wherein, the one or more circuit specifications include one or more randomized circuit specifications.

3. The quantum computing system according to claim 2, wherein, the one or more randomized circuit specifications are implemented by injecting one or more pairs of random Pauli operators into the one or more quantum circuits.

4. The quantum computing system according to claim 3, wherein, injecting one or more pairs of random Pauli operators includes incorporating one or more Clifford gates into the quantum circuits.

5. The quantum computing system according to claim 3, wherein, injecting one or more pairs of random Pauli operators includes incorporating one or more non-Clifford gates into the quantum circuits.

6. The quantum computing system according to claim 1, wherein, the one or more circuit specifications include circuit specifications configured to implement known error types and implement preferred error directions for error mitigation.

7. The quantum computing system according to claim 1, wherein, the approximation of the circuit fidelity f for the one or more circuit specifications includes component cross-entropy benchmarking for similar circuit structures.

8. The quantum computing system according to claim 1, wherein, determining an approximation of the circuit fidelity f for one or more circuit specifications includes counting the number of single-qubit gates and two-qubit gates.

9. The quantum computing system according to claim 1, wherein, Implementing a single-point full depolarization error mitigation solution further includes: at least partially based on the average value of the observed values of interest <o> f and an approximation of the circuit fidelity f to determine an inferred mean of the observations <o> ψ 。< / o> < / o> 10. The quantum computing system according to claim 9, wherein, at least partially based on the average value of the interest observations <o> f and an approximation of the circuit fidelity f to determine an inferred mean of the observations <o> ψ including: determining an inferred average value of the observed value according to the formula <o> ψ , where O is the desired observation, and includes a component attributable to noise.< / o> ​< / o> < / o> 11. The quantum computing system according to any one of claims 1-6, wherein, At least partially based on the average value of the interest observations <o> f Implementing an error mitigation scheme for the quantum computing system includes implementing a multi-point extrapolation scheme.< / o> 12. The quantum computing system according to claim 11, wherein, implementing the multi-point extrapolation scheme includes selecting a noise injection method and a plurality of extrapolation points.

13. The quantum computing system according to claim 12, wherein, the noise injection method includes implementing one or more additional Clifford gates and one or more corresponding inverses of the one or more additional Clifford gates during each of the one or more circuit specifications.

14. The quantum computing system according to claim 12, Wherein, Implementing the multi-point extrapolation scheme includes: analyzing each of the plurality of extrapolation points with different random circuit specifications from the one or more circuit specifications, and extrapolating an inferred value of the observed value of interest O based at least in part on the analysis of the plurality of extrapolation points.

15. The quantum computing system according to claim 1, Wherein, at least in part based on an average value of the interest observations <o> f Implementing an error mitigation scheme for the quantum computing system includes: during at least one of the one or more circuit specifications, implementing known error types, biasing the errors towards a preferred direction, and using error correction codes to correct the errors.< / o> 16. The quantum computing system according to claim 1, Wherein, at least partially based on the average value of the interest observations <o> f Implementing an error mitigation scheme for the quantum computing system includes determining a corrected error interest observation value O by correcting the noise components of the multiple measurements.< / o> 17. A method for estimating a noise-free observed value of a quantum computing system, Comprising: A computing system including one or more computing devices accessing a quantum system including one or more qubits and one or more quantum measurement devices; The computing system implementing a plurality of quantum circuits, each quantum circuit including a plurality of quantum gates, each of the plurality of quantum circuits further including an equivalent logical operation with each of the other quantum circuits among the plurality of quantum circuits, each of the plurality of quantum circuits being implemented by a different sequence of quantum gates compared to each of the other quantum circuits among the plurality of quantum circuits, thereby implementing one or more circuit specifications; The computing system obtaining a plurality of measurements performed for each of the quantum circuits via the one or more quantum measurement devices; The computing system determines an estimated average value of an observable of interest for the quantum circuit, at least in part, based on the plurality of measurements <o> f ; and< / o> The calculation system uses a single-point full depolarization error model to at least partially estimate an average value based on the observed values of interest <o> f to determine an estimated noise-free value of an interest observation value <o> ψ ，< / o> < / o> wherein the estimated mean value of the interest observations is at least partially based on the single-point full depolarization error model used by the computing system <o> f to determine an estimated noise-free value of the interest observation value <o> ψ Including: determining, by the computing system, an approximation of a circuit fidelity f for the one or more circuit specifications.< / o> < / o> 18. The method according to claim 17, Wherein, The one or more circuit specifications include one or more randomized circuit specifications.

19. The method according to claim 18, Wherein, The one or more randomized circuit specifications are implemented by injecting one or more pairs of random Pauli operators into the quantum circuit.

20. The method according to claim 19, Wherein, Injecting one or more pairs of random Pauli operators into the quantum circuit includes incorporating one or more Clifford gates into the quantum circuit.

21. The method according to claim 19, Wherein, Injecting one or more pairs of random Pauli operators into the quantum circuit includes incorporating one or more non-Clifford gates into the quantum circuit.

22. The method according to claim 17, Wherein, Approximating the circuit fidelity f for the one or more circuit specifications includes component cross-entropy benchmarking for a similar circuit structure.

23. The method according to claim 17, Wherein, Determining an approximation of the circuit fidelity f for the one or more circuit specifications by the computing system includes counting the number of single-qubit gates and two-qubit gates.

24. The method according to claim 17, Wherein, Estimated mean value of the interest observations, at least in part, using a single-point total depolarization error model by the computing system <o> f to determine an estimated noise-free value of the interest observation value <o> ψ Further comprising: at least in part by the computing system based on the average value of the interest observations <o> f and an approximation of the circuit fidelity f to determine an inferred mean of the observations <o> ψ 。< / o> < / o> < / o> < / o> 25. The method according to claim 24, Wherein, by the computing system, at least in part, based on the average of the interest observations <o> f and an approximation of the circuit fidelity f to determine an inferred mean of the observations <o> ψ including: the inference average value of the observed value determined by the computing system according to the formula <o> ψ , where O is the desired observation, and includes a component attributable to noise.< / o> ​< / o> < / o> 26. The method according to any one of claims 17-25, Wherein, Estimated mean value of the interest observations, at least in part, based on the single-point full depolarization error model used by the computing system <o> f to determine the estimated noise-free value of the interest observation value <o> ψ Including: determining an interest observation value O with corrected errors by correcting noise components of the plurality of measurements.< / o> < / o> 27. A method for noise error mitigation of a quantum system, Comprising: A computing system including one or more computing devices accessing a quantum system including one or more qubits and one or more quantum measurement devices; Multiple quantum circuits are implemented by the quantum system, each quantum circuit includes multiple quantum gates, and each of the multiple quantum circuits further includes an equivalent logical operation with each of the other quantum circuits in the multiple quantum circuits. Each of the multiple quantum circuits is implemented by a different sequence of quantum gates compared to each of the other quantum circuits in the multiple quantum circuits, thereby implementing one or more circuit specifications; The computing system obtains, via the one or more quantum measurement devices, multiple measurements performed for the one or more quantum circuits; The computing system determines an estimated average value of an observable of interest for the quantum circuit, at least in part, based on the plurality of measurements <o> f ; and< / o> by the computing system based at least in part on the average of the interest observations <o> f to implement an error mitigation scheme for the quantum system< / o> wherein at least in part based on the average value of the interest observations <o> f Implementing an error mitigation scheme for the quantum system includes implementing a single-point full depolarization error mitigation scheme.< / o> Wherein, implementing the single-point full depolarization error mitigation scheme includes determining an approximation of the circuit fidelity f for the one or more circuit specifications.

28. An apparatus configured to perform the method according to any one of claims 17-27.

29. Computer-readable instructions which, when executed by a computing device, cause the method according to any one of claims 17-27 to be performed.

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