Memory device and control method thereof

Abstract

A memory device includes a memory cell array, the memory cell array including one or more memory cells connected between word lines and bit lines. The one or more memory cells include a selected memory cell connected between a selected bit line and a corresponding word line and an unselected memory cell connected between an unselected bit line and a corresponding word line. The memory device also includes a charge control circuit, the charge control circuit being configured to control precharging the selected bit line or the unselected bit line to a first voltage, allowing the unselected bit line to share charge with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

Description

Technical Field

[0001] The present disclosure relates to memory devices and methods of operating the same. Background Art

[0002] During a read operation of a memory cell, several steps may be required before a read voltage is applied to the memory cell. The switching between these steps may be cumbersome and redundant, and may generate undesirable glitches during operation. Summary of the invention

[0003] In one aspect, a memory device includes a memory cell array, the memory cell array including one or more memory cells connected between word lines and bit lines. The one or more memory cells include a selected memory cell connected between a selected bit line and a corresponding word line, and an unselected memory cell connected between an unselected bit line and a corresponding word line. The memory device also includes a charge control circuit coupled to the memory cell array and configured to control precharging the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharge the selected bit line to a second voltage.

[0004] In another aspect, a system includes a memory device, the memory device including a memory cell array. The memory cell array includes one or more memory cells connected between word lines and bit lines. The one or more memory cells include selected memory cells connected between selected bit lines and corresponding word lines and unselected memory cells connected between unselected bit lines and corresponding word lines. The memory device also includes a charge control circuit coupled to the memory cell array and configured to control precharging of the selected bit line or the unselected bit line to a first voltage, charge sharing of the unselected bit line with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharge of the selected bit line to a second voltage.

[0005] In yet another aspect, a method for operating a memory device, the memory device comprising a selected memory cell connected between a selected bit line and a corresponding word line, an unselected memory cell connected between an unselected bit line and a corresponding word line, a first local control gate coupled to the selected bit line or the unselected bit line, a second local control gate coupled between the unselected bit line and the selected bit line, and a third local control gate coupled to the selected bit line. The method comprises setting the selected bit line and the unselected bit line to an initial state, setting the first local control gate to an "on" state to precharge the selected bit line or the unselected bit line to a first voltage, setting the first local control gate to an "off" state and simultaneously setting the second local control gate to an "on" state so that the selected bit line and the unselected bit line reach the same voltage level, setting the second local control gate to an "off" state and simultaneously setting the third local control gate to an "on" state to discharge the selected bit line to a second voltage, applying a read voltage via a corresponding word line and obtaining a read result, and resetting the selected bit line and the unselected bit line to an initial state. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure.

[0007] Figure 1 A block diagram of an exemplary system having a memory device according to some aspects of the present disclosure is shown.

[0008] Figure 2 A schematic diagram of an exemplary memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0009] Figure 3 A schematic diagram of an exemplary memory device including a phase-change memory (PCM) cell according to some aspects of the present disclosure is shown.

[0010] Figure 4 A block diagram of an exemplary memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure is shown.

[0011] Figure 5 A block diagram of an example memory device including a charging control circuit according to some aspects of the present disclosure is shown.

[0012] Figure 6 A block diagram of an example memory device including a charging control circuit according to some aspects of the present disclosure is shown.

[0013] Figure 7A-7B A time sequence of read operations of an exemplary memory device according to some aspects of the present disclosure is shown.

[0014] Figure 8 The simulation results of the time series of the control signal under the read operation are shown.

[0015] Fig. 9A The simulation results of the time series of the control signal under the read operation are shown.

[0016] Fig. 9B Simulation results of a time series of control signals under a read operation using an exemplary method of operating a memory device according to some aspects of the present disclosure are shown.

[0017] Fig.10 A flowchart illustrating an exemplary method of operating a memory device according to some aspects of the present disclosure is shown.

[0018] The present disclosure will be explained with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] Although specific configurations and arrangements have been discussed, it should be understood that this is done only for illustrative purposes. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. In addition, the present disclosure may also be used for various other applications. Functions and structural features as described in the present disclosure may be combined, adjusted and modified with each other and in a manner not specifically shown in the accompanying drawings, so that these combinations, adjustments and modifications are within the scope of the present disclosure.

[0020] Typically, the term can be understood at least in part from the usage in the context. For example, the term "one or more" as used herein depends at least in part on the context, and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, at least in part depending on the context, terms such as "one", "one" or "the" can also be understood to express singular usage or express plural usage. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but can allow the presence of other factors that are not necessarily clearly described, which also depends at least in part on the context. In addition, the term "coupled", "coupled to" or "coupled between..." can be understood as not necessarily intended to be "physically joined or attached", i.e. directly attached, but can also be explained by the indirect connection of intermediate components.

[0021] A phase change memory (PCM) cell is a non-volatile memory device that uses a phase change material to store data. Based on electrothermal heating and quenching of the phase change material, PCM can exploit the difference between the resistivity of the amorphous phase and the crystalline phase in the phase change material (e.g., a chalcogenide alloy). The phase change material in the PCM cell can be located between two electrodes, and a current can be applied to repeatedly switch the material (or at least a portion of it blocking the current path) between the two phases to store data. The "set" state is a low resistance state of the PCM cell, which can be obtained by generating a crystalline region in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated at a crystallization temperature for a sufficient duration. In contrast, the "reset" state is a high resistance state of the PCM cell, which can be obtained by generating an amorphous region in the chalcogenide material. The amorphous state can be generated when the chalcogenide material is heated above its melting temperature and then rapidly quenched to form an amorphous state. The "set" state can be referred to as an "on" state, while the "reset" state can be referred to as an "off" state.

[0022] A conventional read operation of a memory cell may require multiple steps or operations to precharge, share, or discharge the corresponding bit lines before applying a read voltage via a word line to read out the result. Due to resistive-capacitive delay (RC delay), a time interval should be given between each two steps in the multiple steps to avoid false signals caused by overlapping control signals, thereby increasing the read delay.

[0023] Specifically, in order to obtain a result of determining whether a memory cell is in a "set" state or a "reset" state, a charge sharing process is required to make the selected bit line and the unselected bit line reach the same voltage level as a reference voltage before applying a read voltage to the memory cell via a word line. The charge sharing process may include several precharge sharing, charge sharing and discharge steps, which are controlled by applying several control signals to turn on and off several control gates and applying a specific charge or discharge bias to the bit line. However, due to resistance-capacitance delay (RC delay), a time interval should be given between each of the multiple steps to avoid false signals caused by control signal overlap, thereby increasing the read delay. In addition, in a memory device having a phase change memory (PCM) cell (for example, each PCM cell may include a PCM element connected in series with a selector), the read delay is an essential factor in the overall system performance. A solution to avoid false signals between control signal overlaps during precharge sharing, charge sharing or discharge processes while reducing the total read time is highly desired. In addition, since there are multiple precharge sharing, charge sharing or discharge processes, it may be necessary to apply several control signals to turn on and off the control gates to precharge sharing, charge sharing or discharge the corresponding bit lines; these processes are redundant and cumbersome. A simplified method and corresponding circuit design are also needed to control multiple turn-on and turn-off steps.

[0024] In order to solve one or more of the above problems, the present disclosure provides a solution in which an integrated charge control circuit is introduced to prepare the phase by applying a control signal in advance before switching to the next step of the charging or discharging process, thereby reducing false signals between switches and the time interval given to avoid false signals. In addition, the process is simplified to reduce the read delay. Specifically, before applying a read voltage to the word line to read the result of the memory cell, the selected bit line and the unselected bit line are set to an initial state. In some embodiments, the initial state may be a ground state or at 0V.

[0025] Next, during the precharge sharing process, the first local control gate is set to an "on" state to precharge the unselected bit lines to a first voltage, such as a first negative voltage. In some embodiments, it is also possible to precharge the selected bit lines instead of the unselected bit lines. The precharge sharing process is used to pull one of the bit lines to a certain voltage (e.g., a negative voltage) so that after the subsequent charge sharing process, the two bit lines will reach the same voltage level (e.g., half of the previous negative voltage). Note that "precharge" or "precharge sharing" hereinafter refers to charging the bit lines before the charge sharing process.

[0026] Next, during the charge sharing process, the first local control gate is set to the "off" state to stop precharging the unselected bit line (or the selected bit line), and the second local control gate is set to the "on" state at the same time, so that the selected bit line and the unselected bit line reach the same voltage level, which is the reference voltage. Note that "charge sharing" hereinafter refers to electrically connecting two bit lines to reach the same voltage level.

[0027] Next, the second local control gate is set to the "off" state to interrupt the charge sharing of the selected bit line and the unselected bit lines, and the third local control gate is set to the "on" state to discharge the selected bit line to a second voltage, such as a second negative voltage, and then the third local control gate is set to the "off" state to interrupt the discharge of the selected bit line. Note that "discharging" hereinafter refers to charging the bit line to a negative voltage level, especially to a voltage level lower than the reference voltage.

[0028] Next, after the selected bit line is discharged to the second negative voltage and the unselected bit lines are maintained at the reference voltage, a read voltage is applied via the corresponding word line, and a read result is obtained. If the selected memory cell on the selected bit line is in the "set" state, the voltage on the selected bit line will be pulled up above the reference voltage because the read voltage is higher than the set threshold voltage of the selected memory cell, and the unselected bit lines will remain at the reference voltage. The read data (e.g., read voltage or read current) of the memory cell in the "set" state can be obtained later. If the selected memory cell on the selected bit line is in the "reset" state, the voltage on the selected bit line will not be pulled up above the reference voltage because the read voltage is lower than the reset threshold voltage of the selected memory cell. The read data (e.g., read voltage or read current) of the memory cell in the "reset" state can be obtained later.

[0029] After the read result is sensed, the selected bit line and the unselected bit lines are reset to an initial state during a recovery process, and the read operation is completed.

[0030] As described above, by turning on the first local control gate and turning off the second local control gate, and by turning off the second local control gate and turning on the third local control gate at the same time, the time interval can be minimized. In order to turn on one local control gate and turn off another local control gate at the same time while preventing false signals, an integrated charging control circuit can be provided. Specifically, an exemplary integrated charging control circuit provides a first control signal to the first local control gate, provides a second control signal and an inverted first control signal (for example, inverting the first control signal through a first inverter) to a first AND logic gate, and provides a third control signal and an inverted second control signal (for example, inverting the second control signal through a second inverter) to a second AND logic gate. Thus, before the first control signal turns to 0V, the inverted first control signal is maintained at 0V, so that the second local control gate will not turn to "on" regardless of whether the second control signal turns to "on". Therefore, the second control signal can be applied to the first AND logic gate in advance, and wait until the first control signal turns to 0V. And when the first control signal turns to 0V (i.e., the first local control gate turns to "off"), the second local control gate turns to "on" immediately. Since the second control signal is already turned on when the first control signal is turned off, no or very few false signals will be generated. Similarly, before the second control signal turns to 0V, the inverted second control signal is maintained at 0V, so that the third local control gate cannot turn to "on" regardless of whether the third control signal turns to "on". Therefore, the third control signal can be applied to the second AND logic gate in advance, and wait until the second control signal turns to 0V. And when the second control signal turns to 0V (i.e., the second local control gate turns to "off"), the third local control gate turns to "on" immediately. Since the third control signal is already turned on when the second control signal is turned off, no or very few false signals will be generated. It should be noted that the integrated charging control circuit according to some embodiments of the present disclosure is only an example of realizing the desired function or mechanism, and any other control gate combination that realizes the same or similar function is possible according to the above teachings.

[0031] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). In some embodiments, host 108 may be configured to send data to or receive data from memory device 104. In some embodiments, the host may be a user logic unit or user interface, so that a user can give instructions to the host and transmit the instructions to a memory device or memory array.

[0032] The memory device 104 may be any memory device disclosed in the present disclosure. As disclosed in detail below, according to some embodiments, the memory device 104 (e.g., a phase-change random access memory (PCRAM), a dynamic random access memory (DRAM), or a NAND flash memory device) may include a clock input, a command bus, a data bus, a control logic unit, an address register, a row decoder / word line driver, a memory cell array having memory cells, a voltage generator, a page buffer / sense amplifier, a column decoder / bit line driver, and a data input / output (I / O).

[0033] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), wherein the high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC) is used as a data storage device and enterprise storage array for mobile devices (such as smart phones, tablets, laptops, etc.). The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and write operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) for data read from or written to the memory device 104. Any other suitable function may also be performed by the memory controller 106, for example, formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol.For example, the memory controller 106 can communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc. In addition, the memory controller 106 can also be configured to control the operation of the memory device 104 to perform methods according to some embodiments of the present disclosure. For example, in some embodiments, the memory controller 106 can determine whether the read voltage is higher or lower than the threshold voltage of the selected memory cell. In some embodiments, the memory controller 106 may determine that the state of the selected memory cell is a "set" state in response to the read voltage being higher than the threshold voltage of the selected memory cell, or determine that the state of the selected memory cell is a "reset" state in response to the read voltage being lower than the threshold voltage of the selected memory cell. Note that according to some embodiments of the present disclosure, one or more of these operations of the memory device 104 may also be partially or completely performed by the control logic unit.

[0034] Figure 2 1 is a schematic circuit diagram of an exemplary memory device 200 including peripheral circuits according to some aspects of the present disclosure. The memory device 200 may be Figure 11. An example of a memory device 104 in FIG. Memory device 200 may include a memory cell array 201 and a peripheral circuit 202 coupled to memory cell array 201. Memory cell array 201 may include word lines (e.g., selected word line 214), bit lines (e.g., selected bit line 216 and unselected bit line 218), and memory cells (e.g., selected memory cell 208 and unselected memory cell 210) formed between the word lines and the bit lines. In some embodiments, each memory cell (e.g., selected memory cell 208 and unselected memory cell 210) may include a PCM element (not shown) connected in series with a selector (not shown). In some embodiments, a memory cell (e.g., 208 or 210) may also be a DRAM cell including a pair of transistors and capacitors. To read a selected memory cell (e.g., selected memory cell 208), a selected word line voltage (e.g., selected word line voltage Vwl1) may be applied to a selected word line (e.g., selected word line 214), and a selected bit line voltage (e.g., selected bit line voltage Vbl1) may be applied to a selected bit line (e.g., selected bit line 216). Other unselected word lines will remain at an unselected word line voltage (e.g., Vwl0), and other unselected bit lines will remain at an unselected bit line voltage (e.g., Vbl0). In some embodiments, before applying a selected word line voltage (e.g., selected word line voltage Vwl1) to a selected word line (e.g., selected word line 214), an unselected bit line voltage (e.g., Vbl0) of an unselected bit line (e.g., unselected bit line 218) is configured to be set to a reference voltage by a series of voltages during precharge sharing, charge sharing, and discharge processes. In some implementations, the selected bit line voltage (e.g., Vbl1) of the selected bit line (e.g., selected bit line 216) is configured to be set to a range of voltages during precharge sharing, charge sharing, and discharge processes before the selected word line voltage (e.g., selected word line voltage Vwl1) is applied to the selected word line (e.g., selected word line 214). These precharge sharing, charge sharing, and discharge processes will be discussed later.

[0035] Figure 3 3 shows a side view of a cross section of a memory device 300 having a PCM element connected in series with a selector. The memory device 300 includes one or more parallel bit lines 304 (i.e., corresponding to the bit lines 304) above a substrate 302. Figure 2 216 in the bit line 304) and one or more parallel word lines 316 above the bit line 304 (ie, corresponding to Figure 2 214 in the memory device 300). The memory device 300 also includes one or more PCM cells 301 (i.e., corresponding to Figure 2208 in the memory cell 201), each of the PCM cells 301 is arranged at the intersection of a corresponding pair of bit lines 304 and a word line 316. Adjacent PCM cells 301 are separated by an insulating structure 322. Each PCM cell 301 includes a selector 308 and a PCM element 312 above the selector 308. Each PCM cell 301 also includes three electrodes 306, 310 and 314 vertically between the corresponding bit line 304, the selector 308, the PCM element 312 and the corresponding word line 316, respectively. As described above, the read operation of the memory cell may reduce the life of the memory cell. This phenomenon is particularly observed in a PCM cell (e.g., 301) having a PCM element (e.g., 312) connected in series with a selector (e.g., 308), because the PCM cell is more sensitive to the read voltage and may have a higher probability of being stuck in the "reset" state when the read voltage is too high.

[0036] Note that the PCM element 312 can exploit the difference between the resistivity of the amorphous and crystalline phases in a phase change material based on electrothermal heating and quenching of the phase change material (e.g., a chalcogenide alloy). The phase change element can be located between two electrodes, and a current can be applied to repeatedly switch the material (or at least a portion of it blocking the current path) between the two phases to store data.

[0037] The selector 308 may include an ovonic threshold switch (OTS) selector having an ovonic threshold switch (OTS) material, such as zinc telluride (ZnTe), which exhibits field-dependent volatile resistance switching behavior (referred to as the "OTS phenomenon") when an external bias voltage (Va) higher than a threshold voltage (Vth) is applied. At a lower voltage (|Va|<Vth), the high resistance of the OTS selector in its off state keeps the off-state current (Ioff) low. At a higher voltage (|Va|>Vth), the OTS selector undergoes the OTS phenomenon and switches to an on-state with a low resistance; therefore, the current (Ion) through the OTS selector in the on-state increases. As long as the high voltage is provided, the volatile on-state is maintained.

[0038] Figure 4 4 shows a memory cell array 401 (eg, corresponding to a Figure 2 201) and peripheral circuits of an exemplary memory device 400 (eg, corresponding to Figure 1 In some embodiments, the memory cells of the memory cell array 401 include: Figure 3 The PCM unit 301 in.

[0039] like Figure 4As shown, the page buffer / sense amplifier 404 can be coupled to the memory cell array 401 and configured to read data from and program (write) data to the memory cell array 401 according to a control signal from the control logic unit 412. In one example, the page buffer / sense amplifier 404 can store data to be programmed into the memory cell array 201 (e.g., Figure 2 In another example, the page buffer / sense amplifier 404 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 208 coupled to the selected word line 214. In yet another example, the page buffer / sense amplifier 404 can also sense a low-power signal from the selected bit line 216 representing a data bit stored in the memory cell 208 and amplify the small voltage swing to a recognizable logic level in a read operation.

[0040] The column decoder / bit line driver may be coupled to the memory cell array 401 and the control logic unit 412 and configured to be controlled by the control logic unit 412 and select one or more memory cells (e.g., the selected memory cell 208) and bit lines (e.g., the selected bit line 216). The column decoder / bit line driver 406 may be further configured to drive the selected bit line 216. The column decoder / bit line driver 406 may be further configured to drive the selected bit line 216 using the bit line voltage generated from the voltage generator 410.

[0041] The data I / O 416 may be coupled to the page buffer / sense amplifier 404 and / or the column decoder / bit line driver 406 and configured to direct (route) data input from the data bus 423 to the selected memory cell 208 of the memory cell array 201 and to direct (route) data output from the selected memory cell to the data bus 423.

[0042] The row decoder / word line driver 408 may be coupled to the control logic unit 412 and the memory cell array 401, and is configured to be controlled by the control logic unit 412, and select one or more memory cells (e.g., the selected memory cell 208) and a selected word line (e.g., the selected word line 214) in the memory cell array 201. The row decoder / word line driver 408 may be further configured to drive the selected word line 214. The row decoder / word line driver 408 may be further configured to drive the selected word line 214 using a word line voltage generated from the voltage generator 410.

[0043] The voltage generator 410 can be coupled to the control logic unit 412 and configured to be controlled by the control logic unit 412 according to a control signal from the control logic unit 412, and generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be provided to the memory cell array 401.

[0044] The control logic unit 412 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The control logic unit 412 is configured to receive the data from a host (eg, Figure 1 108 in) receives clock signals, command signals, address signals and data signals. Command signals are received via command bus 421. Data signals are received via data bus 423. In some embodiments, control logic unit 412 can be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (digital signal processor, DSP), an application-specific integrated circuit (application-specific integrated circuit, ASIC), a field-programmable gate array (field-programmable gate array, FPGA), a programmable logic device (programmable logic device, PLD), a state machine, a gating logic unit, a discrete hardware circuit and other suitable hardware, firmware and / or software configured to perform the various functions described. In some embodiments, control logic unit 412 is coupled to word line driver 408 and is configured to guide the read voltage into the selected memory cell via word line driver 408.

[0045] The address register 414 may be coupled to the control logic unit 412 or included in the control logic unit 412. The address register 414 may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0046] Figure 5 A memory device (eg, corresponding to a memory device 500) including a charging control circuit 500 according to some aspects of the present disclosure is shown. Figure 4 400). Figure 4As shown, once the control logic unit 412 determines that the command signal is a read command, it triggers the read operation. Before the read voltage is applied to the selected word line, the read operation includes a series of processes of precharge sharing, charge sharing and discharge. According to some embodiments of the present disclosure, these precharge sharing, charge sharing and discharge processes are performed by the charge control circuit 500. The charge control circuit 500 may include a voltage comparator 501 (e.g., corresponding to the page buffer / sense amplifier 404 or included therein) coupled to a memory cell array (e.g., corresponding to the memory cell array 201 or 401), an unselected bit line 511 (e.g., corresponding to the unselected bit line 218) connected to a first input terminal 503 of the voltage comparator 501, and a selected bit line 513 (e.g., corresponding to the selected bit line 216) connected to a second input terminal 505 of the voltage comparator 501. In some embodiments, the voltage comparator 501 is configured to determine that: if the selected bit line voltage Vbl1 of the selected bit line 513 (e.g., the selected bit line 216) is higher than a reference voltage maintained by the unselected bit line 511 (e.g., corresponding to the unselected bit line 218), the selected memory cell (e.g., the selected memory cell 208) is in a "set" state; and if the selected bit line voltage of the selected bit line is lower than the reference voltage, the selected memory cell is in a "reset" state.

[0047] The first local control gate 521 is coupled to the selected bit line 513 (eg, corresponding to Figure 2 , and is configured to control whether to precharge the selected bit line 513 or the unselected bit line 511 to a first voltage (e.g., a first negative voltage Vn1) during a precharge sharing process. In one example, as Figure 5 As shown in FIG. 5 , the first local control gate 521 is configured to control whether to precharge the unselected bit line 511 to the first negative voltage Vn1. In some embodiments, the first negative voltage Vn1 may be -2V to -4V, for example -3.7V.

[0048] The second local control gate 523 is coupled between the selected bit line 513 and the unselected bit line 511, and is configured to control whether to make the selected bit line 513 and the unselected bit line 511 reach the same voltage level (e.g., one-half of the first negative voltage Vn1) during the charge sharing process. After the charge sharing process, the above-mentioned same voltage level (e.g., one-half of the first negative voltage Vn1) can be a reference voltage, which can be used to determine whether the selected memory cell is in a "set" state or a "reset" state by comparing the selected bit line voltage Vbl1 with the reference voltage maintained by the unselected bit line 511. For example, if the selected memory cell is in the "set" state, then after the read voltage is applied across the selected word line, the selected bit line voltage will be pulled up to be higher than the reference voltage. On the contrary, if the selected memory cell is in the "reset" state, then after the read voltage is applied across the selected word line, the selected bit line voltage will still remain below the reference voltage.

[0049] The third local control gate 525 is coupled to the selected bit line 513 and is configured to control whether the selected bit line 513 is discharged to a second voltage (e.g., a second negative voltage Vn2) during the discharge process. In some embodiments, the second negative voltage Vn2 may be -2V to -4V, such as -3.7V. Note that the charging control circuit 500 according to some embodiments of the present disclosure is only an example of implementing a desired function or mechanism; any other control logic gate combination that implements the same or similar function is possible according to the above teachings.

[0050] Figure 6 A memory device (eg, corresponding to a memory device 600) including a charging control circuit 600 according to some aspects of the present disclosure is shown. Figure 4 As described above, in order to switch between the first local control gate 521 and the second local control gate 523 and between the second local control gate 523 and the third local control gate 525 without causing false signals and to reduce the time interval, an exemplary charging control circuit 600 is introduced.

[0051] First, the first control signal 621 may be transmitted to “turn on” and “turn off” the first local control gate 521 . That is, the first local control gate 521 is configured to be controlled by the first control signal 621 .

[0052] Secondly, the second control signal 623 and the inverted first control signal are provided to the first AND logic gate 611, which is the inverted control signal of the first control signal 621 generated by the first inverter 601. The output result of the first AND logic gate 611 can be transmitted to "turn on" and "turn off" the second local control gate 523. That is, the second local control gate 523 is configured to be controlled by the output result of the first AND logic gate 611. The first inverter 601 is coupled to the first AND logic gate 611 and is configured to invert the first control signal 621 into the inverted first control signal. The first AND logic gate 611 is configured to receive the second control signal 623 and the inverted first control signal.

[0053] Third, the third control signal 625 and the inverted second control signal are provided to the second AND logic gate 613, which is the inverted control signal of the second control signal 623 generated by the second inverter 603. The output result of the second AND logic gate 613 can be transmitted to "turn on" and "turn off" the third local control gate 525. That is, the third local control gate 525 is configured to be controlled by the output result of the second AND logic gate 613. The second inverter 603 is coupled to the second AND logic gate 613 and is configured to invert the second control signal 623 into the inverted second control signal. The second AND logic gate 613 is configured to receive the third control signal 625 and the inverted second control signal.

[0054] As described above, the time interval can be minimized by simultaneously turning on the first local control gate 521 and turning off the second local control gate 523, and by simultaneously turning off the second local control gate 523 and turning on the third local control gate 525. Specifically, the first control signal 621 is provided to the first local control gate 521, the second control signal 623 and the inverted first control signal (e.g., the first control signal 621 is inverted by the first inverter 601) are provided to the first AND logic gate 611, and the third control signal 625 and the inverted second control signal (e.g., the second control signal 623 is inverted by the second inverter 603) are provided to the second AND logic gate 613. Thus, before the first control signal 621 turns to 0V, the inverted first control signal remains at 0V, so that the second local control gate 523 cannot turn to "on" regardless of whether the second control signal 623 turns to "on". Therefore, the second control signal 623 can be turned on and pre-applied to the first AND logic gate 611, and wait until the first control signal 621 turns to 0V. When the first control signal 621 turns to 0V (that is, the first local control gate 521 turns to "off"), the second local control gate 523 immediately turns to "on". Since the second control signal 623 is already turned on and has been waiting when the first control signal 621 is turned off, no or very few false signals will be generated. Similarly, before the second control signal 623 turns to 0V, the inverted second control signal remains at 0V, so that regardless of whether the third control signal 625 turns to "on", the third local control gate 525 cannot turn to "on". Therefore, the third control signal 625 can be turned on and pre-applied to the second AND logic gate 613, and wait until the second control signal 623 turns to 0V. When the second control signal 623 turns to 0V (i.e., the second local control gate 523 turns "off"), the third local control gate 525 immediately turns "on". Since the third control signal 625 is already turned on when the second control signal 623 is turned off, no or very few false signals will be generated. Note that the charging control circuit 600 according to some embodiments of the present disclosure is only an example of implementing a desired function or mechanism; according to the above teachings, any other control logic gate combination that implements the same or similar functions is possible.

[0055] Figure 7A-7B 1 shows a time sequence of read operations of an exemplary memory device according to some aspects of the present disclosure. Specifically, Fig. 7A shows the "set" state read sequence, while Figure 7B The “reset” state readout sequence is shown in FIG. Fig. 7AAs shown in , step 1 is an initial state, in which, when the word line voltage (Vwl) has not yet been provided to the memory cell (e.g., the selected memory cell 208), the current (Icell) on the memory cell is 0 mA, and both the selected bit line voltage (Vbl0) and the unselected bit line voltage (Vbl0) are set to the ground voltage or 0V.

[0056] Step 2 is a precharge sharing process in which a selected bit line (eg, the selected bit line 216 ) or an unselected bit line (eg, the unselected bit line 218 ) is precharged to a first negative voltage Vn1 .

[0057] Step 3 is a charge sharing process, in which the selected bit line and the unselected bit line are electrically connected so that the selected bit line and the unselected bit line reach the same voltage level, which is a reference voltage.

[0058] Step 4 is a discharge process, in which the selected bit line is discharged to a second negative voltage Vn2.

[0059] Step 5 is a read process, in which a read voltage (e.g., a word line voltage (Vwl)) is provided to the memory cell. Since the memory cell is in the "set" state, the current across the memory cell increases and pulls the selected bit line voltage up above the reference voltage maintained by the unselected bit line. The voltage comparator 501 (corresponding to the sense amplifier 404 or included in the sense amplifier 404) can therefore determine that the memory cell is in the "set" state by sensing the flag change from 0 (Vbl0>Vbl1) to 1 (Vbl0<Vbl1).

[0060] On the contrary, if the memory cell is in Figure 7B If the memory cell is in the "reset" state, the current across the memory cell remains the same and the selected bit line voltage is not pulled up above the reference voltage. The voltage comparator 501 (corresponding to the sense amplifier 404 or included in the sense amplifier 404) can therefore determine that the memory cell is in the "reset" state by sensing that the flag has not changed from 0 to 1.

[0061] Step 6 is a recovery process, in which both the selected bit line and the unselected bit line are reset to an initial state, which is a ground voltage or 0V.

[0062] Figure 8 The simulation results of the time series of the control signal under the read operation are shown. Figure 8 As shown, step 2 can be divided into step 2a and step 2b, because the first local control gate (corresponding to Figure 5 521 in step 2a) turns "on" during step 2a and turns "off" during step 2b. Meanwhile, step 3 can be divided into step 3a and step 3b, because the second local control gate (corresponding to Figure 5523 in step 3a) turns "on" during step 3a and turns "off" during step 3b. Moreover, step 4 can be divided into step 4a and step 4b because the third local control gate (corresponding to Figure 5 525 in FIG. 5A ) turns “ON” during step 4a and turns “OFF” during step 4b. By turning “ON” and “OFF” several local control gates, there are more than 9 steps for one read operation, which is cumbersome and redundant for the entire system. In addition, since in some embodiments, these local control gates can be controlled by the memory controller (corresponding to Figure 1 The steps are controlled by a basic control unit (BCU) of the components 106) in FIG. 1 , so several clock cycles may be required to perform these steps.

[0063] For example, Fig. 9A , simulation results without a charging control circuit (e.g., 500 or 600) according to some embodiments of the present disclosure show that at least 2 clock cycles (4ns) are required for each switching phase, and therefore a total of 10ns are required for each read operation, which increases the overall read latency (note that the entire read operation may take 120ns).

[0064] Therefore, after implementing the charging control circuit (eg, 500 or 600) according to some embodiments of the present disclosure, Fig. 9B It is shown that the total time interval is less than 0.5 nanoseconds (ns), for example, 247 picoseconds (ps) + 104ps = 351ps, without any aliasing.

[0065] Fig.10 1000 is a flowchart illustrating an exemplary method of operating a memory device according to some aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein. The method 1000 may be partially or completely performed by Figure 4 The control logic unit 412 in Figure 1 It should be understood that the operations shown in method 1000 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Fig.10 The different orders shown are executed.

[0066] refer to Fig.10 , method 1000 begins at operation 1002, wherein a selected bit line (eg, Figure 2 216) and unselected bit lines (e.g., Figure 2 218 in ) and set it to an initial state. In some embodiments, the initial state can be a ground state or at 0V.

[0067] Method 1000 proceeds to operation 1004, such as Fig.10 As shown, during the precharge sharing process, the first local control gate (eg, Figure 5 521 in the ) is set to the "on" state to precharge the selected bit line or the unselected bit line (for example, as Fig. 7A The precharge sharing process is used to pull one of the bit lines to a certain voltage (e.g., a negative voltage) so that after the subsequent charge sharing process, the two bit lines will reach the same voltage level (e.g., half of the previous negative voltage).

[0068] Method 1000 proceeds to operation 1006, such as Fig.10 As shown, during the charge sharing process, the first local control gate is set to the "off" state to interrupt the precharging of the unselected bit lines, and at the same time the second local control gate (eg, Figure 5 523) in is set to the "on" state, so that the selected bit line and the unselected bit lines reach the same voltage level, which is the reference voltage.

[0069] Method 1000 proceeds to operation 1008, such as Fig.10 As shown, the second local control gate is set to the "off" state to interrupt the charge sharing of the selected bit line and the unselected bit line, and the third local control gate (eg, Figure 5 525 in the figure is set to the "on" state to discharge the selected bit line to the second voltage (e.g., the second negative voltage Vn2), and then the third local control gate is set to the "off" state to interrupt the discharge of the selected bit line.

[0070] Method 1000 proceeds to operation 1010, such as Fig.10 As shown, after the selected bit line is discharged to the second negative voltage and the unselected bit lines are kept at the reference voltage, a read voltage is applied via the corresponding word line and a read result is obtained. Figure 2 A selected memory cell (eg, Figure 2If the selected memory cell 208 in the selected bit line is in the "set" state, the voltage on the selected bit line will be pulled up to above the reference voltage because the read voltage is higher than the set threshold voltage of the selected memory cell, while the unselected bit lines will remain at the reference voltage. Read data (e.g., read voltage or read current) can be obtained for the memory cell in the "set" state. If the selected memory cell on the selected bit line is in the "reset" state, the voltage on the selected bit line will not be pulled up to above the reference voltage because the read voltage is lower than the reset threshold voltage of the selected memory cell. Read data (e.g., read voltage or read current) can be obtained for the memory cell in the "reset" state. In some embodiments, the memory cell may be such as Figure 3 The PCM unit 301 in.

[0071] Method 1000 proceeds to operation 1012, such as Fig.10 As shown, after the read result is read out, during the recovery process, the selected bit line and the unselected bit lines are reset to the initial state and the read operation is completed.

[0072] According to one aspect of the present disclosure, a memory device includes a memory cell array, the memory cell array including one or more memory cells connected between word lines and bit lines. The one or more memory cells include a selected memory cell connected between a selected bit line and a corresponding word line and an unselected memory cell connected between an unselected bit line and a corresponding word line. The memory device also includes a charge control circuit, the charge control circuit being coupled to the memory cell array and configured to control precharging the selected bit line or the unselected bit line to a first voltage, causing the unselected bit line to share charge with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

[0073] In some embodiments, the total time interval between each of the following processes is less than 0.5 nanoseconds (ns): precharging a selected bit line or an unselected bit line to a first voltage, sharing charge between the unselected bit line and the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

[0074] In some implementations, the charging control circuit further includes a voltage comparator coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

[0075] In some embodiments, the charging control circuit also includes: a first local control gate, coupled to the selected bit line or the unselected bit line and configured to control precharging of the selected bit line or the unselected bit line to the first voltage; a second local control gate, coupled between the selected bit line and the unselected bit line and configured to control charge sharing between the unselected bit line and the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level; and a third local control gate, coupled to the selected bit line and configured to control discharging of the selected bit line to the second voltage.

[0076] In some embodiments, the charging control circuit further includes: a first inverter configured to receive the first control signal and generate an inverted first control signal; a second inverter configured to receive the second control signal and generate an inverted second control signal; a first AND logic gate coupled to the first inverter and configured to receive the second control signal and the inverted first control signal; and a second AND logic gate coupled to the second inverter and configured to receive a third control signal and the inverted second control signal. The first local control gate is configured to be controlled by the first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, and the third local control gate is configured to be controlled by a second output result of the second AND logic gate.

[0077] In some implementations, each memory cell comprises a phase change memory (PCM) cell.

[0078] In some embodiments, the PCM unit includes a PCM element and a selector connected in series with the PCM element.

[0079] In some embodiments, the first voltage is a first negative voltage of -2V to -4V.

[0080] In some embodiments, the second voltage is a second negative voltage ranging from -2V to -4V.

[0081] In some implementations, the same voltage level is a reference voltage, and the voltage comparator is configured to compare the reference voltage held by the unselected bit lines with a selected bit line voltage of the selected bit line.

[0082] In some embodiments, the voltage comparator is configured to determine that: if the selected bit line voltage of the selected bit line is higher than a reference voltage, the selected memory cell is in a "set" state; and if the selected bit line voltage of the selected bit line is lower than the reference voltage, the selected memory cell is in a "reset" state.

[0083] In some implementations, the memory device further includes a sense amplifier coupled to the memory cell array, and the charge control circuit is included in the sense amplifier.

[0084] In some implementations, the memory device further includes a word line driver coupled to the memory cell array and configured to drive a read voltage into the selected memory cell via a corresponding word line.

[0085] In some implementations, the memory device further includes a control logic unit coupled to the word line driver and configured to direct the read voltage into the selected memory cell via the word line driver.

[0086] In some implementations, the memory device further includes a data register coupled to the charge control circuit and configured to store the read data and the comparison output signal.

[0087] According to another aspect of the present disclosure, a system includes a memory device, the memory device including a memory cell array. The memory cell array includes one or more memory cells connected between word lines and bit lines. The one or more memory cells include selected memory cells connected between selected bit lines and corresponding word lines and unselected memory cells connected between unselected bit lines and corresponding word lines. The memory device also includes a charge control circuit, the charge control circuit is coupled to the memory cell array and is configured to control the precharging of the selected bit line or the unselected bit line to a first voltage, the unselected bit line and the selected bit line charge sharing so that the unselected bit line and the selected bit line reach the same voltage level, and the selected bit line is discharged to a second voltage.

[0088] In some embodiments, the total time interval between each of the following processes is less than 0.5 nanoseconds (ns): precharging a selected bit line or an unselected bit line to a first voltage, sharing charge between the unselected bit line and the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

[0089] In some embodiments, the charging control circuit of the system further includes a voltage comparator coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

[0090] In some embodiments, the charging control circuit of the system also includes: a first local control gate, coupled to the selected bit line or the unselected bit line and configured to control precharging of the selected bit line or the unselected bit line to the first voltage; a second local control gate, coupled between the selected bit line and the unselected bit line and configured to control charge sharing between the unselected bit line and the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level; and a third local control gate, coupled to the selected bit line and configured to control discharging of the selected bit line to the second voltage.

[0091] In some embodiments, the charging control circuit of the system further includes: a first inverter configured to receive a first control signal and generate an inverted first control signal; a second inverter configured to receive a second control signal and generate an inverted second control signal; a first AND logic gate coupled to the first inverter and configured to receive the second control signal and the inverted first control signal; and a second AND logic gate coupled to the second inverter and configured to receive a third control signal and the inverted second control signal. The first local control gate is configured to be controlled by the first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, and the third local control gate is configured to be controlled by a second output result of the second AND logic gate.

[0092] In some implementations, each memory cell comprises a phase change memory (PCM) cell.

[0093] In some embodiments, the PCM unit includes a PCM element and a selector connected in series with the PCM element.

[0094] In some embodiments, the first voltage is a first negative voltage of -2V to -4V.

[0095] In some embodiments, the second voltage is a second negative voltage ranging from -2V to -4V.

[0096] In some implementations, the same voltage level is a reference voltage, and the voltage comparator is configured to compare the reference voltage held by the unselected bit lines with a selected bit line voltage of the selected bit line.

[0097] In some embodiments, the voltage comparator is configured to determine that the selected memory cell is in a “set” state if the selected bit line voltage of the selected bit line is above a reference voltage, and that the selected memory cell is in a “reset” state if the selected bit line voltage of the selected bit line is below the reference voltage.

[0098] In some implementations, the memory device of the system further includes a sense amplifier coupled to the memory cell array, and the charge control circuit is included in the sense amplifier.

[0099] In some implementations, the memory device of the system further includes a word line driver coupled to the memory cell array and configured to drive a read voltage into the selected memory cell via a corresponding word line.

[0100] In some implementations, the memory device of the system further includes a control logic unit coupled to the word line driver and configured to direct the read voltage into the selected memory cell via the word line driver.

[0101] In some implementations, the memory device of the system further includes a data register coupled to the charge control circuit and configured to store read data and the comparison output signal.

[0102] According to another aspect of the present disclosure, a method for operating a memory device, the memory device includes a selected memory cell connected between a selected bit line and a corresponding word line, an unselected memory cell connected between an unselected bit line and a corresponding word line, a first local control gate coupled to the selected bit line or the unselected bit line, a second local control gate coupled between the unselected bit line and the selected bit line, and a third local control gate coupled to the selected bit line. The method includes setting the selected bit line and the unselected bit line to an initial state, setting the first local control gate to an "on" state to precharge the selected bit line or the unselected bit line to a first voltage, setting the first local control gate to an "off" state and simultaneously setting the second local control gate to an "on" state so that the selected bit line and the unselected bit line reach the same voltage level, setting the second local control gate to an "off" state and simultaneously setting the third local control gate to an "on" state to discharge the selected bit line to a second voltage, applying a read voltage via a corresponding word line and obtaining a read result, and resetting the selected bit line and the unselected bit line to an initial state.

[0103] In some embodiments, the initial state is a ground state or 0V.

[0104] In some embodiments, the same voltage level is a reference voltage, and obtaining the read result includes determining that if the selected bit line voltage is higher than the reference voltage, the selected memory cell is in a "set" state; and if the selected bit line voltage is lower than the reference voltage, the selected memory cell is in a "reset" state.

[0105] The foregoing description of specific embodiments can be easily modified and / or adapted to various applications. Therefore, based on the teaching and guidance presented herein, such adaptations and modifications are intended to be within the meaning and range of equivalent changes of the disclosed embodiments.

[0106] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device, comprising: A memory cell array, the memory cell array comprising one or more memory cells connected between a word line and a bit line, wherein the one or more memory cells comprise: a selected memory cell connected between a selected bit line and a corresponding word line; and an unselected memory cell connected between an unselected bit line and the corresponding word line; and a charge control circuit, the charge control circuit being coupled to the memory cell array and configured to control precharging the selected bit line or the unselected bit line to a first voltage, allowing the unselected bit line to share charge with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage, wherein the charge control circuit further comprises: a first local control gate coupled to the selected bit line or the unselected bit line and configured to control precharging of the selected bit line or the unselected bit line to the first voltage; a second local control gate coupled between the selected bit line and the unselected bit line and configured to control the unselected bit line to share charges with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level; and a third local control gate coupled to the selected bit line and configured to control discharging of the selected bit line to the second voltage, Among them, the "turning off" of the first local control gate and the "turning on" of the second local control gate are performed simultaneously, and the "turning off" of the second local control gate and the "turning on" of the third local control gate are performed simultaneously.

2. The memory device according to claim 1, wherein: The total time interval between each of the following processes is less than 0.5 nanoseconds (ns): precharging the selected bit line or the unselected bit line to the first voltage, sharing the charge of the unselected bit line with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to the second voltage.

3. The memory device according to claim 1 or 2, wherein: The charging control circuit further includes: A voltage comparator is coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

4. The memory device according to claim 1, wherein: The charging control circuit further includes: a first inverter configured to receive the first control signal and generate an inverted first control signal; a second inverter configured to receive the second control signal and generate an inverted second control signal; a first AND logic gate coupled to the first inverter and configured to receive the second control signal and the inverted first control signal; and a second AND logic gate coupled to the second inverter and configured to receive a third control signal and the inverted second control signal, wherein the first local control gate is configured to be controlled by the first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, and the third local control gate is configured to be controlled by a second output result of the second AND logic gate.

5. The memory device according to claim 1 or 2, wherein: Each memory cell comprises a phase change memory (PCM) cell.

6. The memory device according to claim 5, wherein: The phase change memory cell includes a phase change memory element and a selector connected in series with the phase change memory element.

7. The memory device according to claim 1 or 2, wherein: The first voltage is a first negative voltage of -2V to -4V.

8. The memory device according to claim 1 or 2, wherein: The second voltage is a second negative voltage of -2V to -4V.

9. The memory device according to claim 3, wherein: The same voltage level is a reference voltage, and the voltage comparator is configured to compare the reference voltage held by the unselected bit lines with the selected bit line voltage of the selected bit line.

10. The memory device according to claim 9, wherein: The voltage comparator is configured to determine that: if the selected bit line voltage of the selected bit line is higher than the reference voltage, the selected memory cell is in a "set" state; and if the selected bit line voltage of the selected bit line is lower than the reference voltage, the selected memory cell is in a "reset" state.

11. The memory device according to claim 1 or 2, further comprising: A sense amplifier is coupled to the memory cell array, wherein the charge control circuit is included in the sense amplifier.

12. The memory device according to claim 1 or 2, further comprising: A word line driver is coupled to the memory cell array and configured to drive a read voltage into the selected memory cell via the corresponding word line.

13. The memory device of claim 12, further comprising: A control logic unit is coupled to the word line driver and is configured to direct the read voltage into the selected memory cell via the word line driver.

14. The memory device of claim 3, further comprising: A data register is coupled to the charge control circuit and is configured to store read data and the comparison output signal.

15. A system comprising: A memory device comprising: A memory cell array, the memory cell array comprising one or more memory cells connected between a word line and a bit line, wherein the one or more memory cells comprise: a selected memory cell connected between a selected bit line and a corresponding word line; and unselected memory cells connected between unselected bit lines and the corresponding word lines; and A charging control circuit is coupled to the memory cell array and is configured to control: precharging the selected bit line or the unselected bit line to a first voltage, allowing the unselected bit line to share charge with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage, wherein the charging control circuit further includes: a first local control gate coupled to the selected bit line or the unselected bit line and configured to control precharging of the selected bit line or the unselected bit line to the first voltage; a second local control gate coupled between the selected bit line and the unselected bit line and configured to control the unselected bit line to share charges with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level; and a third local control gate coupled to the selected bit line and configured to control discharging of the selected bit line to the second voltage, wherein the “turning off” of the first local control gate and the “turning on” of the second local control gate are performed simultaneously, and the “turning off” of the second local control gate and the “turning on” of the third local control gate are performed simultaneously; and A memory controller is coupled to the memory device and is configured to control the memory device.

16. The system of claim 15, wherein: The total time interval between each of the following processes is less than 0.5 nanoseconds (ns): precharging the selected bit line or the unselected bit line to the first voltage, sharing the charge of the unselected bit line with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to the second voltage.

17. The system according to claim 15 or 16, wherein: The charging control circuit further includes: A voltage comparator is coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

18. The system of claim 15, wherein: The charging control circuit further includes: a first inverter configured to receive the first control signal and generate an inverted first control signal; a second inverter configured to receive the second control signal and generate an inverted second control signal; a first AND logic gate coupled to the first inverter and configured to receive the second control signal and the inverted first control signal; and a second AND logic gate coupled to the second inverter and configured to receive a third control signal and the inverted second control signal, wherein the first local control gate is configured to be controlled by the first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, and the third local control gate is configured to be controlled by a second output result of the second AND logic gate.

19. The system according to claim 15 or 16, wherein: Each memory cell comprises a phase change memory (PCM) cell.

20. The system of claim 19, wherein: The phase change memory cell includes a phase change memory element and a selector connected in series with the phase change memory element.

21. The system according to claim 15 or 16, wherein: The first voltage is a first negative voltage of -2V to -4V.

22. The system according to claim 15 or 16, wherein: The second voltage is a second negative voltage of -2V to -4V.

23. The system of claim 17, wherein: The same voltage level is a reference voltage, and the voltage comparator is configured to compare the reference voltage held by the unselected bit lines with the selected bit line voltage of the selected bit line.

24. The system of claim 23, wherein: The voltage comparator is configured to determine that: if the selected bit line voltage of the selected bit line is higher than the reference voltage, the selected memory cell is in a "set" state; and if the selected bit line voltage of the selected bit line is lower than the reference voltage, the selected memory cell is in a "reset" state.

25. The system according to claim 15 or 16, further comprising: A sense amplifier is coupled to the memory cell array, and the charge control circuit is included in the sense amplifier.

26. The system according to claim 15 or 16, further comprising: A word line driver is coupled to the memory cell array and configured to drive a read voltage into the selected memory cell via the corresponding word line.

27. The system of claim 26, further comprising: A control logic unit is coupled to the word line driver and is configured to direct the read voltage into the selected memory cell via the word line driver.

28. The system of claim 17, further comprising: A data register is coupled to the charge control circuit and is configured to store read data and the comparison output signal.

29. A method for operating a memory device, the memory device comprising: a selected memory cell connected between a selected bit line and a corresponding word line, an unselected memory cell connected between an unselected bit line and the corresponding word line, a first local control gate coupled to the selected bit line or the unselected bit line, a second local control gate coupled between the unselected bit line and the selected bit line, and a third local control gate coupled to the selected bit line; and the method comprises: Setting the selected bit line and the unselected bit line to an initial state; Setting the first local control gate to an “on” state to precharge the selected bit line or the unselected bit line to a first voltage; Setting the first local control gate to an “off” state and simultaneously setting the second local control gate to an “on” state so that the selected bit line and the unselected bit line reach the same voltage level; setting the second local control gate to an “off” state and simultaneously setting the third local control gate to an “on” state to discharge the selected bit line to a second voltage; applying a read voltage via a corresponding word line and obtaining a read result; and The selected bit line and the unselected bit lines are reset to the initial state.

30. The method of claim 29, wherein: The initial state is a ground state or 0V.

31. The method according to claim 29 or 30, wherein: The same voltage level is a reference voltage, and obtaining the read result includes determining that: if the selected bit line voltage is higher than the reference voltage, the selected memory cell is in a "set" state; and if the selected bit line voltage is lower than the reference voltage, the selected memory cell is in a "reset" state.

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