Light receiving device, method for manufacturing a light receiving device, and distance measuring module

Abstract

The present technology relates to an optical receiving device, a manufacturing method for an optical receiving device, and a distance measuring module, whereby sensitivity can be improved. An optical receiving device is provided that includes a first tap that detects a charge photoelectrically converted by a photoelectric conversion unit, a pixel array unit in which pixels having a second tap that detects a charge photoelectrically converted by the photoelectric conversion unit are two-dimensionally arranged in a matrix form, an on-chip lens provided on a light incident surface side of a substrate for each pixel, and a lens partition unit formed in the same layer as the on-chip lens and partitioning the on-chip lens. For example, the present technology can be applied to a distance measuring system that performs distance measurement by an indirect ToF method.

Description

Technical Field

[0001] This technology relates to an optical receiving device, a method for manufacturing an optical receiving device, and a distance measurement module, and more specifically to an optical receiving device capable of improving sensitivity, a method for manufacturing an optical receiving device, and a distance measurement module. Background Technology

[0002] Distance measurement sensors using the indirect time-of-flight (ToF) method are known. In indirect ToF range sensors, signal charges obtained by receiving reflected light from the object being measured are distributed to two charge accumulation regions, and the distance is calculated based on the distribution ratio between the signal charges. Among such range sensors, a range sensor with improved light receiving characteristics by being formed as a back-illuminated sensor has been proposed (see, for example, Patent Document 1).

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: PCT International Application Publication No. 2018 / 135320 Summary of the Invention

[0006] The problem to be solved by the present invention

[0007] In this distance measurement sensor using the indirect ToF method, further improvements in sensitivity are desired.

[0008] Given this situation, this technique has been implemented, and it makes it possible to improve sensitivity.

[0009] Solution to the problem

[0010] A light receiving device according to a first aspect of the present technology includes: a pixel array unit, wherein pixels, each including a first tap for detecting charge photoelectrically converted by a photoelectric conversion unit and a second tap for detecting charge photoelectrically converted by a photoelectric conversion unit, are arranged in a matrix in two dimensions; an on-chip lens, each pixel being disposed on the light incident surface side of a substrate; and a lens separator, formed in the same layer as the on-chip lens and separating the on-chip lenses from each other.

[0011] A method for manufacturing a light receiving device according to a second aspect of the present technology includes: for each pixel of a pixel array unit, forming a first tap for detecting charge photoelectrically converted by a photoelectric conversion unit and a second tap for detecting charge photoelectrically converted by a photoelectric conversion unit; forming an on-chip lens for each pixel on the light incident surface side of a substrate; and forming lens partitions that separate the on-chip lenses from each other in the same layer as the on-chip lenses.

[0012] According to a third aspect of the present technology, a distance measurement module includes a light receiving device comprising: a pixel array unit in which pixels, each including a first tap for detecting charge photoelectric conversion by a photoelectric conversion unit and a second tap for detecting charge photoelectric conversion by a photoelectric conversion unit, are arranged in a two-dimensional matrix; an on-chip lens, each pixel being disposed on the light incident surface side of a substrate; and a lens separator formed in the same layer as the on-chip lens and separating the on-chip lenses from each other.

[0013] According to the first and third aspects of the present technology, a light receiving device includes: a pixel array unit, wherein pixels, each including a first tap for detecting charge photoelectrically converted by a photoelectric conversion unit and a second tap for detecting charge photoelectrically converted by a photoelectric conversion unit, are arranged in a matrix in two dimensions; an on-chip lens, each pixel being disposed on the light incident surface side of a substrate; and a lens separator, formed in the same layer as the on-chip lens and separating the on-chip lenses from each other.

[0014] According to a second aspect of the present invention, for each pixel of the pixel array unit, a first tap for detecting charge converted by photoelectric conversion unit and a second tap for detecting charge converted by photoelectric conversion unit are formed; an on-chip lens is formed for each pixel on the light incident surface side of the substrate; and a lens separation portion is formed in the same layer as the on-chip lens to separate the on-chip lenses from each other.

[0015] Both the optical receiving device and the distance measurement module can be independent devices, or they can be modules integrated into another device. Attached Figure Description

[0016] Figure 1 This is a block diagram illustrating an example configuration of an optical receiving device.

[0017] Figure 2 This is a cross-sectional view showing an example of pixel configuration.

[0018] Figure 3 It is a planar diagram of the first and second taps of a pixel.

[0019] Figure 4 It is a cross-sectional view of pixels with a segmented structure.

[0020] Figure 5 It is a cross-sectional view of multiple pixels.

[0021] Figure 6 It is a cross-sectional view of multiple pixels.

[0022] Figure 7 This is a plan view showing a first variant example of a pixel tap.

[0023] Figure 8This is a plan view showing a second variation of the pixel tap.

[0024] Figure 9 This is a plan view showing a third variation of the pixel tap.

[0025] Figure 10 This is a plan view showing the fourth variation of the pixel tap.

[0026] Figure 11 This is a plan view showing the fifth variation of the pixel tap.

[0027] Figure 12 This is a diagram showing the equivalent circuit of a pixel.

[0028] Figure 13 This is a diagram showing another equivalent circuit of a pixel.

[0029] Figure 14 This is a diagram showing a first example of wiring for a vertical signal line.

[0030] Figure 15 This is a diagram showing a second wiring example of a vertical signal line.

[0031] Figure 16 This is a diagram showing a third example of vertical signal line wiring.

[0032] Figure 17 This is a diagram showing a fourth example of vertical signal line wiring.

[0033] Figure 18 It is a plan view of the gate formation surface between the multilayer wiring layer and the substrate.

[0034] Figure 19 This is a diagram showing an example of the planar arrangement of a metal film M1 as the first layer of a multilayer wiring layer.

[0035] Figure 20 This is a diagram showing an example of the planar arrangement of a metal film M2, which serves as the second layer of a multilayer wiring layer.

[0036] Figure 21 This is a diagram showing an example of the planar arrangement of a metal film M3, which serves as the third layer of a multilayer wiring layer.

[0037] Figure 22 This is a diagram showing an example of the planar arrangement of the metal film M4, which serves as the fourth layer of a multilayer wiring layer.

[0038] Figure 23 This is a diagram showing an example of the planar arrangement of the metal film M5, which is the fifth layer of a multilayer wiring layer.

[0039] Figure 24This is a schematic diagram of the first pixel separation structure of a pixel.

[0040] Figure 25 This is a schematic diagram of the second pixel separation structure for a pixel.

[0041] Figure 26 This is a diagram showing the third pixel separation structure of the pixels.

[0042] Figure 27 This is a schematic diagram of the fourth pixel separation structure for a pixel.

[0043] Figure 28 This is a schematic diagram of the fifth pixel separator structure.

[0044] Figure 29 This is a diagram showing the sixth pixel separation structure of the pixels.

[0045] Figure 30 This is a diagram showing the first pixel separation structure with an uneven structure.

[0046] Figure 31 This is a schematic diagram of the seventh pixel segmentation structure.

[0047] Figure 32 A diagram showing the seventh pixel separator structure with an uneven structure is shown.

[0048] Figure 33 This is a schematic diagram of the eighth pixel segmentation structure.

[0049] Figure 34 This is a pixel cross-sectional view showing a modified example of the eighth pixel separation structure.

[0050] Figure 35 This is a diagram used to describe pupil correction in the eighth pixel segmentation structure.

[0051] Figure 36 This is a schematic diagram of the ninth pixel segmentation structure.

[0052] Figure 37 This is a pixel cross-sectional view showing a modified example of the ninth pixel separation structure.

[0053] Figure 38 This is a schematic diagram of the tenth pixel segmentation structure.

[0054] Figure 39 It is used to describe Figure 38 A plan view along the cross-sectional direction.

[0055] Figure 40 This is a pixel cross-sectional view showing a modified example of the tenth pixel separation structure.

[0056] Figure 41This is a plan view showing the planar arrangement of contacts in the tenth pixel separator structure.

[0057] Figure 42 This is a schematic diagram of the eleventh pixel segmentation structure.

[0058] Figure 43 This is a diagram showing the twelfth pixel separation structure of the pixels.

[0059] Figure 44 This is a diagram showing the thirteenth pixel separation structure.

[0060] Figure 45 This is a plan view showing the planar arrangement of the inter-pixel grooves in the thirteenth pixel separation structure.

[0061] Figure 46 This is a diagram showing the fourteenth pixel separation structure of the pixels.

[0062] Figure 47 This is a diagram illustrating a first method for manufacturing an on-chip lens and a lens separator.

[0063] Figure 48 This is a diagram illustrating a first method for manufacturing an on-chip lens and a lens separator.

[0064] Figure 49 This is a diagram illustrating a variation of the first manufacturing method.

[0065] Figure 50 This is a diagram illustrating a variation of the first manufacturing method.

[0066] Figure 51 This is a diagram illustrating a second method for manufacturing on-chip lenses and lens separators.

[0067] Figure 52 This is a diagram used to describe the substrate configuration of an optical receiving device.

[0068] Figure 53 This is a block diagram showing an example configuration of the distance measurement module.

[0069] Figure 54 This is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0070] Figure 55 This is an explanatory diagram showing an example of the installation location of the vehicle external information detection unit and the imaging unit. Detailed Implementation

[0071] The following will describe the modes of implementing this technology (hereinafter referred to as implementation methods). Note that they will be described in the following order.

[0072] 1. Block diagram of the optical receiving device

[0073] 2. Example of pixel structure

[0074] 3. Example of cross-section configuration with multiple pixels

[0075] 4. Examples of other planar shapes for tap T

[0076] 5. Equivalent circuit of a pixel

[0077] 6. Wiring example for Vertical Signal Line (VSL)

[0078] 7. Example of planar arrangement of five-layer metal films M1 to M5

[0079] 8. Example of pixel separator configuration

[0080] 9. A method for manufacturing on-plate lenses and lens separators.

[0081] 10. Example of substrate structure for a light receiving device

[0082] 11. Configuration example of the distance measurement module

[0083] 12. Examples of applications of moving objects

[0084] 1. Block diagram of an optical receiving device

[0085] Figure 1 This is a block diagram illustrating an example configuration of an optical receiving device applying this technology.

[0086] Figure 1 The light receiving device 1 is a back-illuminated current-assisted photon demodulator (CAPD) sensor, and is used, for example, as part of a distance measurement system that performs distance measurement via an indirect ToF method. The distance measurement system can be applied, for example, to in-vehicle systems that are installed on vehicles and measure distances to objects outside the vehicle, and gesture recognition systems that measure distances to objects such as a user's hand and recognize the user's gestures based on the measurement results.

[0087] The light receiving device 1 includes a pixel array unit 20 formed on a semiconductor substrate (not shown) and peripheral circuit units disposed, for example, around the pixel array unit 20. The peripheral circuit units include, for example, a tap driving unit 21, a vertical driving unit 22, a column processing unit 23, a horizontal driving unit 24, and a system control unit 25.

[0088] The light receiving device 1 further includes a signal processing unit 31 and a data storage unit 32. It should be noted that the signal processing unit 31 and the data storage unit 32 may be mounted on the same substrate as the substrate on which the light receiving device 1 is mounted, or they may be disposed on a different substrate in the imaging device than the substrate on which the light receiving device 1 is mounted.

[0089] The pixel array unit 20 has a configuration in which pixels 51, which generate charges according to the amount of received light and output signals according to the charges, are arranged in a two-dimensional matrix in the row and column directions. That is, the pixel array unit 20 includes a plurality of pixels 51 that photoelectrically convert incident light and output detection signals according to the charges obtained as a result. Here, the row direction refers to the arrangement direction of the pixels 51 in the horizontal direction, and the column direction refers to the arrangement direction of the pixels 51 in the vertical direction. The row direction is the horizontal direction in the figure, and the column direction is the vertical direction in the figure.

[0090] Pixel 51 receives and photoelectrically converts light incident from the outside, particularly infrared light, and outputs a signal corresponding to the charge obtained as a result. Pixel 51 includes a first tap TA that applies a predetermined voltage MIX_A (first voltage) and detects the charge converted by photoelectric conversion, and a second tap TB that applies a predetermined voltage MIX_B (second voltage) and detects the charge converted by photoelectric conversion.

[0091] The tap driving unit 21 supplies a predetermined voltage MIX_A to the first tap TA of each pixel 51 of the pixel array unit 20 via a predetermined voltage supply line tdrv, and supplies a predetermined voltage MIX_B to the second tap TB via the predetermined voltage supply line tdrv. Therefore, two of the voltage supply lines tdrv for transmitting voltage MIX_A and voltage supply lines tdrv for transmitting voltage MIX_B are routed in a pixel column of the pixel array unit 20.

[0092] In pixel array unit 20, pixel drive lines (PDRVs) are routed relative to the matrix pixel array in the row direction of each pixel row. The pixel drive lines (PDRVs) send drive signals for performing drive operations when reading detection signals from pixels. Note that in... Figure 1 In this diagram, the pixel driving line (PDRV) is shown as a single line, but is not limited to a single line, and is actually composed of multiple lines. One end of the pixel driving line (PDRV) is connected to the output terminal corresponding to each row of the vertical driving unit 22.

[0093] Furthermore, for each pixel column in the matrix of pixels arranged in pixel array unit 20, four vertical signal lines VSL are routed in the column direction. (This will be referenced later.) Figures 14 to 17The details of the four vertical signal lines (VSL) are described, but by routing four vertical signal lines (VSL) for each pixel column, multiple rows can be read simultaneously, improving the signal-to-noise ratio and reducing the reading time.

[0094] The vertical drive unit 22 includes a shift register, an address decoder, etc., and simultaneously drives all pixels of the pixel array unit 20 row by row. That is, the vertical drive unit 22, together with the system control unit 25 that controls the vertical drive unit 22, constitutes a drive unit that controls the operation of each pixel of the pixel array unit 20.

[0095] The detection signal output from each pixel 51 in the pixel row controlled by the vertical drive unit 22 is input to the column processing unit 23 via the vertical signal line VSL. The column processing unit 23 performs predetermined signal processing on the detection signal output from each pixel 51 via the vertical signal line VSL, and temporarily holds the detection signal after the signal processing.

[0096] Specifically, the column processing unit 23 performs noise removal processing, analog-to-digital (AD) conversion processing, and other signal processing.

[0097] The horizontal driving unit 24 includes a shift register, an address decoder, etc., and sequentially selects the unit circuits corresponding to the pixel columns of the column processing unit 23. Through the selective scanning of the horizontal driving unit 24, the detection signals that have undergone signal processing by the unit circuits of the column processing unit 23 are sequentially output to the signal processing unit 31.

[0098] The system control unit 25 includes a timing generator that generates various timing signals, and performs drive control on the tap drive unit 21, vertical drive unit 22, column processing unit 23, horizontal drive unit 24, etc. based on the various timing signals generated by the timing generator.

[0099] The signal processing unit 31 has at least arithmetic processing capabilities and performs various types of signal processing, such as arithmetic processing, based on the detection signal output from the signal processing unit 23. The data storage unit 32 temporarily stores the data required for signal processing in the signal processing unit 31.

[0100] The optical receiving device 1 is configured as described above.

[0101] Example of pixel structure (2.)

[0102] Next, the structure of the pixels 51 arranged in the pixel array unit 20 will be described.

[0103] Figure 2 A cross-sectional view of a pixel 51 arranged in pixel array unit 20 is shown.

[0104] Pixel 51 receives and photoelectrically converts light incident from the outside, especially infrared light, and outputs a signal corresponding to the charge obtained as a result.

[0105] Pixel 51 includes, for example, a substrate 61 including a P-type semiconductor layer such as a silicon substrate and an on-chip lens 62 formed on the substrate 61. The substrate 61 corresponds to a photoelectric conversion unit that converts light incident on the pixel 51 from the outside.

[0106] The substrate 61 is made of a high-resistivity P-Epi substrate, for example, having a substrate concentration of 1E+13 or less, and is formed to have a resistance (resistivity) of, for example, 500 [Ωcm] or more. Here, the relationship between the substrate concentration and the resistance of the substrate 61 is set such that, for example, the resistance is 2000 [Ωcm] when the substrate concentration is 6.48E+12 [cm3], the resistance is 1000 [Ωcm] when the substrate concentration is 1.30E+13 [cm3], the resistance is 500 [Ωcm] when the substrate concentration is 2.59E+13 [cm3], and the resistance is 100 [Ωcm] when the substrate concentration is 1.30E+14 [cm3].

[0107] exist Figure 2 In this design, the upper surface of substrate 61 is the back surface of substrate 61 and serves as the light-incident surface on which external light is incident. Simultaneously, the lower surface of substrate 61 is the front surface of substrate 61, and a multilayer wiring layer (not shown) is formed thereon. A fixed-charge film 66, including a single-layer film or a stacked film with a positive fixed charge, is formed on the light-incident surface of substrate 61. An on-chip lens 62, which concentrates externally incident light and directs it onto substrate 61, is formed on the upper surface of the fixed-charge film 66. The fixed-charge film 66 enables the light-incident surface side of substrate 61 to accumulate apertures and suppresses the generation of dark current.

[0108] Inter-pixel light-shielding films 63-1 and 63-2, used to prevent crosstalk between adjacent pixels, are formed at the pixel boundary portions on the fixed charge film 66. In the following text, unless it is particularly necessary to distinguish between inter-pixel light-shielding films 63-1 and 63-2, they are also simply referred to as inter-pixel light-shielding film 63.

[0109] In this example, light from the outside is incident on the substrate 61 via the on-chip lens 62, and an inter-pixel light-shielding film 63 is formed to prevent the incident light from the outside from incident on the area of ​​the adjacent pixel 51. That is, light that is incident on the on-chip lens 62 from the outside and travels to another pixel adjacent to pixel 51 is blocked by the inter-pixel light-shielding film 63-1 or the inter-pixel light-shielding film 63-2 and is prevented from incident on the other adjacent pixel.

[0110] Since the light receiving device 1 is a back-illuminated CAPD sensor, the light incident surface of the substrate 61 is the so-called back surface, and no wiring layer including wiring is formed on the back surface. In addition, a multilayer wiring layer is formed in a portion of the surface of the substrate 61 opposite to the light incident surface, wherein wiring for driving transistors formed in the pixel 51, wiring for reading detection signals from the pixel 51, etc., are formed.

[0111] An oxide film 64, a first tap TA, and a second tap TB are formed on the surface side of the substrate 61 opposite to the light incident surface, i.e., inside the lower surface shown in the figure.

[0112] In this example, an oxide film 64 is formed in the central portion of a pixel 51 near the surface of a substrate 61 opposite to the light incident surface, and a first tap TA and a second tap TB are formed at both ends of the oxide film 64.

[0113] Here, the first tap TA includes an N+ semiconductor region 71-1 and an N- semiconductor region 72-1 (N-type semiconductor region) with a lower donor impurity concentration than the N+ semiconductor region 71-1, as well as a P+ semiconductor region 73-1 and a P- semiconductor region 74-1 (P-type semiconductor region) with a lower acceptor impurity concentration than the P+ semiconductor region 73-1. Examples of donor impurities include elements belonging to Group 5 of the periodic table, such as phosphorus (P) or arsenic (As) relative to Si, and examples of acceptor impurities include elements belonging to Group 3 of the periodic table, such as boron (B) relative to Si. Elements that will become donor impurities are called donor elements, and elements that will become acceptor impurities are called acceptor elements.

[0114] exist Figure 2 In the figure, the N+ semiconductor region 71-1 is formed on the right side of the oxide film 64 inside the front surface of the substrate 61, adjacent to the light incident surface. In addition, the N- semiconductor region 72-1 is formed on the upper side of the N+ semiconductor region 71-1 to cover (surround) the N+ semiconductor region 71-1.

[0115] Furthermore, a P+ semiconductor region 73-1 is formed to the right of the N+ semiconductor region 71-1. Additionally, a P- semiconductor region 74-1 is formed above the P+ semiconductor region 73-1 in the attached figure to cover (encircle) the P+ semiconductor region 73-1.

[0116] Furthermore, an N+ semiconductor region 71-1 is formed to the right of the P+ semiconductor region 73-1. Additionally, an N- semiconductor region 72-1 is formed above the N+ semiconductor region 71-1 in the attached figure to cover (encircle) the N+ semiconductor region 71-1.

[0117] Similarly, the second tap TB includes an N+ semiconductor region 71-2 and an N- semiconductor region 72-2 (N-type semiconductor region) with a lower donor impurity concentration than the N+ semiconductor region 71-2, as well as a P+ semiconductor region 73-2 and a P- semiconductor region 74-2 (P-type semiconductor region) with a lower acceptor impurity concentration than the P+ semiconductor region 73-2.

[0118] exist Figure 2 In the substrate 61, an N+ semiconductor region 71-2 is formed in the inner portion of the front surface of the surface opposite to the light incident surface, adjacent to the left side of the oxide film 64. Furthermore, an N- semiconductor region 72-2 is formed on the upper side of the N+ semiconductor region 71-2 to cover (enclose) the N+ semiconductor region 71-2.

[0119] Furthermore, a P+ semiconductor region 73-2 is formed to the left of the N+ semiconductor region 71-2. Additionally, a P- semiconductor region 74-2 is formed above the P+ semiconductor region 73-2 in the figure, to cover (surround) the P+ semiconductor region 73-2.

[0120] Furthermore, an N+ semiconductor region 71-2 is formed to the left of the P+ semiconductor region 73-2. Additionally, an N- semiconductor region 72-2 is formed on the upper side of the N+ semiconductor region 71-2 to cover (encircle) the N+ semiconductor region 71-2.

[0121] An oxide film 64, similar to the central portion of pixel 51, is formed at the end of pixel 51 inside the front surface of the surface of substrate 61 opposite to the light incident surface.

[0122] In the following text, unless there is a specific distinction between the first tap TA and the second tap TB, the first tap TA and the second tap TB will be referred to as tap T.

[0123] Furthermore, in the following text, unless there is a specific need to distinguish between N+ semiconductor region 71-1 and N+ semiconductor region 71-2, N+ semiconductor region 71-1 and N+ semiconductor region 71-2 will be referred to as N+ semiconductor region 71. And unless there is a specific need to distinguish between N- semiconductor region 72-1 and N- semiconductor region 72-2, N- semiconductor region 72-1 and N- semiconductor region 72-2 will be referred to as N- semiconductor region 72.

[0124] Furthermore, in the following text, unless there is a specific need to distinguish between P+ semiconductor region 73-1 and P+ semiconductor region 73-2, P+ semiconductor region 73-1 and P+ semiconductor region 73-2 will be referred to as P+ semiconductor region 73, and unless there is a specific need to distinguish between P- semiconductor region 74-1 and P- semiconductor region 74-2, P- semiconductor region 74-1 and P- semiconductor region 74-2 will be referred to as P- semiconductor region 74.

[0125] Furthermore, in the substrate 61, the separating portion 75-1, which separates the N+ semiconductor region 71-1 from the P+ semiconductor region 73-1, is made of an oxide film or the like. Similarly, the separating portion 75-2, which separates the N+ semiconductor region 71-2 from the P+ semiconductor region 73-2, is also made of an oxide film or the like. Hereinafter, unless there is a specific need to distinguish between the separating portions 75-1 and 75-2, the separating portions 75-1 and 75-2 will be simply referred to as separating portion 75.

[0126] The N+ semiconductor region 71 disposed in the substrate 61 serves as a charge detection unit for detecting the amount of light incident on the pixel 51 from the outside (i.e., the amount of signal carriers generated by photoelectric conversion of the substrate 61). Note that, in addition to the N+ semiconductor region 71, the N- semiconductor region 72 with a low donor impurity concentration can also be considered as a charge detection unit. The N- semiconductor region 72 with a low donor impurity concentration can be omitted. Furthermore, the P+ semiconductor region 73 serves as a voltage application unit for injecting a large amount of carrier current into the substrate 61, i.e., for directly applying a voltage to the substrate 61 to generate an electric field in the substrate 61. Note that, in addition to the P+ semiconductor region 73, the P- semiconductor region 74 with a low acceptor impurity concentration can also be considered as a voltage application unit. The P- semiconductor region 74 with a low acceptor impurity concentration can be omitted.

[0127] Although details will be described later, the floating diffusion (FD) portion (hereinafter also specifically referred to as FD portion A) as a floating diffusion region (not shown) is directly connected to the N+ semiconductor region 71-1, and FD portion A is further connected to the vertical signal line VSL via an amplifying transistor (not shown) and the like.

[0128] Similarly, another FD portion (hereinafter specifically referred to as FD portion B), unlike FD portion A, is directly connected to the N+ semiconductor region 71-2, and FD portion B is further connected to the vertical signal line VSL via an amplifying transistor (not shown) or the like. Here, the vertical signal line VSL connected to FD portion A and the vertical signal line VSL connected to FD portion B are different vertical signal lines VSL.

[0129] For example, when the distance to an object is measured using an indirect Time-of-Flight (ToF) method, infrared light is emitted from an imaging device including a light receiving device 1 toward the object. Then, when the infrared light is reflected by the object and returns to the imaging device as reflected light, the substrate 61 of the light receiving device 1 receives and photoelectrically converts the incident reflected light (infrared light). The tap driving unit 21 drives the first tap TA and the second tap TB of the pixel 51 and distributes the signal corresponding to the charge DET obtained through photoelectric conversion to the FD portion A and the FD portion B.

[0130] For example, at a certain moment, the tap driving unit 21 applies a voltage to two P+ semiconductor regions 73 via a contact or the like. Specifically, for example, the tap driving unit 21 applies a voltage of MIX_A = 1.5V to the P+ semiconductor region 73-1 of the first tap TA, and applies a voltage of MIX_B = 0V to the P+ semiconductor region 73-2 of the second tap TB.

[0131] Then, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and current flows from P+ semiconductor region 73-1 to P+ semiconductor region 73-2. In this case, holes in the substrate 61 move toward P+ semiconductor region 73-2, and electrons move toward P+ semiconductor region 73-1.

[0132] Therefore, when infrared light (reflected light) from the outside is incident on the substrate 61 via the on-chip lens 62 in this state, and the infrared light is photoelectrically converted in the substrate 61 and converted into a pair of electrons and holes, the obtained electrons are guided by the electric field between the P+ semiconductor regions 73 toward the P+ semiconductor region 73-1 and move into the N+ semiconductor region 71-1.

[0133] In this case, the electrons generated by photoelectric conversion are used as signal carriers (signal charges) for detecting a signal corresponding to the amount of infrared light incident on pixel 51 (i.e., the amount of infrared light received).

[0134] Therefore, in the N+ semiconductor region 71-1, the charge corresponding to the electrons that move into the N+ semiconductor region 71-1 is accumulated, and the charge is detected by the column processing unit 23 via the FD section A, the amplifying transistor, the vertical signal line VSL, etc.

[0135] That is, the accumulated charge DET_A in the N+ semiconductor region 71-1 is transferred to the FD portion A directly connected to the N+ semiconductor region 71-1, and the signal corresponding to the charge DET_A transferred to the FD portion A is read by the column processing unit 23 via an amplifying transistor or the vertical signal line VSL. Then, the read signal is processed in the column processing unit 23, such as AD conversion processing, and the obtained detection signal is provided as a result to the signal processing unit 31.

[0136] The detection signal is an indication of the amount of charge of electrons detected by the N+ semiconductor region 71-1, that is, the amount of charge DET_A accumulated in the FD portion A. In other words, the detection signal is a signal representing the amount of infrared light received by pixel 51.

[0137] Note that, similar to the case of N+ semiconductor region 71-1, the detection signal corresponding to the electron detected in N+ semiconductor region 71-2 can also be appropriately used for distance measurement.

[0138] Furthermore, at the next timing, a voltage is applied to the two P+ semiconductor regions 73 via a contact or the like through the tap driving unit 21, thereby generating an electric field in the opposite direction to the electric field generated in the substrate 61 so far. Specifically, for example, a voltage of MIX_A = 0V is applied to the P+ semiconductor region 73-1 of the first tap TA, and a voltage of MIX_B = 1.5V is applied to the P+ semiconductor region 73-2 of the second tap TB.

[0139] Therefore, an electric field is generated between the two P+ semiconductor regions 73 in the substrate 61, and current flows from P+ semiconductor region 73-2 to P+ semiconductor region 73-1.

[0140] When infrared light (reflected light) from the outside is incident on the substrate 61 via the on-chip lens 62 in this state, and the infrared light is photoelectrically converted in the substrate 61 and converted into a pair of electrons and holes, the obtained electrons are guided by the electric field between the P+ semiconductor regions 73 toward the P+ semiconductor region 73-2 and move into the N+ semiconductor region 71-2.

[0141] Therefore, in the N+ semiconductor region 71-2, the charge corresponding to the electrons that move into the N+ semiconductor region 71-2 is accumulated, and the charge is detected by the column processing unit 23 via the FD section B, the amplifying transistor, the vertical signal line VSL, etc.

[0142] That is, the accumulated charge DET_B in the N+ semiconductor region 71-2 is transferred to the FD portion B directly connected to the N+ semiconductor region 71-2, and the signal corresponding to the charge DET_B transferred to the FD portion B is read by the column processing unit 23 via an amplifying transistor or the vertical signal line VSL. Then, the read signal is processed in the column processing unit 23, such as AD conversion processing, and the obtained detection signal is provided as a result to the signal processing unit 31.

[0143] Note that, similar to the case of N+ semiconductor region 71-2, the detection signal corresponding to the electron detected in N+ semiconductor region 71-1 can also be appropriately used for distance measurement.

[0144] In this way, when detection signals obtained by photoelectric conversion in different periods are obtained in the same pixel 51, the signal processing unit 31 calculates distance information representing the distance to the object based on these detection signals and outputs the distance information to the subsequent stage.

[0145] The method for allocating signal carriers to different N+ semiconductor regions 71 in this manner and calculating distance information based on the detection signal corresponding to the signal carrier is called the indirect ToF method.

[0146] Example of the planar shape of tap T

[0147] Figure 3 It is a planar view of the first tap TA and the second tap TB of pixel 51.

[0148] exist Figure 3 In, corresponding to Figure 2 The parts in the text are indicated by the same reference numerals, and their descriptions are omitted appropriately.

[0149] like Figure 3 As shown, each tap T has a structure in which the periphery of the P+ semiconductor region 73 is surrounded by the N+ semiconductor region 71. More specifically, a rectangular P+ semiconductor region 73 is formed at the center of the tap T, and the periphery of the P+ semiconductor region 73 is surrounded by a rectangular N+ semiconductor region 71 (more specifically, a rectangular frame-shaped N+ semiconductor region 71 centered on the P+ semiconductor region 73).

[0150] It should be noted that Figure 3 The separation portion 75 between the P+ semiconductor region 73 and the N+ semiconductor region 71 or oxide film 64 is not shown.

[0151] Infrared light incident from the outside is focused by the on-chip lens 62 onto the central portion of pixel 51, specifically the middle portion between the first tap TA and the second tap TB. Therefore, crosstalk caused by infrared light incident on pixels 51 adjacent to pixel 51 can be suppressed. Furthermore, when infrared light is directly incident on tap T, the charge separation efficiency (i.e., the contrast ratio (Cmod) between active and passive taps) and modulation contrast decrease, and thus this decrease can also be suppressed.

[0152] Here, the tap T that reads the signal corresponding to the charge DET obtained through photoelectric conversion, that is, the tap T that should detect the charge DET obtained through photoelectric conversion, is also called an active tap.

[0153] Conversely, taps T that do not essentially read the signal corresponding to the charge DET obtained through photoelectric conversion, i.e., taps T that are not active taps, are also called passive taps.

[0154] In the example above, the tap T of the P+ semiconductor region 73 with a voltage of 1.5V applied is an active tap, and the tap T of the P+ semiconductor region 73 with a voltage of 0V applied is a passive tap.

[0155] Cmod is calculated by the following formula (1), and is an exponent representing the percentage of charge generated by photoelectric conversion of incident infrared light that can be detected in the N+ semiconductor region 71, which is the active tap T (i.e., whether a signal based on the charge can be extracted), and represents the charge separation efficiency. In formula (1), I0 represents the signal detected by one of the two charge detection units (P+ semiconductor region 73), and I1 represents the signal detected by the other.

[0156] Cmod={|I0-I1| / (I0+I1)}×100...(1)

[0157] Therefore, for example, when infrared light incident from the outside is incident on the region of the passive tap and photoelectric conversion is performed in the non-active tap, there is a high probability that electrons, as signal carriers generated by the photoelectric conversion, will move to the N+ semiconductor region 71 in the non-active tap. Then, the charge of some electrons obtained by photoelectric conversion is not detected in the N+ semiconductor region 71 in the active tap, and Cmod (i.e., charge separation efficiency) decreases.

[0158] Therefore, in pixel 51, by focusing infrared light at a position approximately equidistant from the two taps T near the center of pixel 51, the probability of photoelectric conversion of externally incident infrared light in the region of the inactive tap can be reduced, and charge separation efficiency can be improved. Furthermore, modulation contrast can also be improved in pixel 51. In other words, electrons obtained through photoelectric conversion can be easily guided to the N+ semiconductor region 71 in the active tap.

[0159] Example of a structure for arranging DTI for pixel separation

[0160] exist Figure 2 In the structure of pixel 51 shown, a separator structure can be set between pixels 51 to improve the separation characteristics between adjacent pixels and suppress crosstalk.

[0161] Figure 4 It shows the partition structure set in Figure 2 A cross-sectional view of the configuration between adjacent pixels 51 shown.

[0162] exist Figure 4 In, corresponding to Figure 2 The parts in the text are indicated by the same reference numerals, and their descriptions are omitted.

[0163] Figure 4 Pixel 51 and Figure 2 The difference in pixel 51 shown is that it has deep trench dividers (DTI) 65-1 and 65-2 set as pixel dividers, and in other respects it is the same as... Figure 2 The pixels 51 in the image are identical. DTI65-1 and DTI65-2 are formed in the substrate 61 at a predetermined depth from the back side of the substrate 61 at the boundary portion with the adjacent pixel 51. In the following text, unless there is a specific need to distinguish between DTI65-1 and DTI65-2, DTI65-1 and DTI65-2 are simply referred to as DTI65. DTI65 can be made of an oxide film, for example. Furthermore, for example, DTI65 can have a structure in which the outer periphery of a metal film such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), etc., is covered with an insulating film such as silicon oxide (SiO2) or silicon oxynitride (SiON) (surrounded by it).

[0164] By forming an embedded DTI65 in this way, the infrared light separation characteristics between pixels can be improved, and crosstalk can be suppressed.

[0165] 3. Example of cross-section configuration with multiple pixels

[0166] exist Figure 2 and Figure 4In the cross-sectional configuration of pixel 51 shown, the multilayer wiring layer formed on the front surface side of substrate 61 opposite to the light incident surface is not shown.

[0167] therefore, Figure 5 and Figure 6 Cross-sectional views of multiple adjacent pixels without omitting multiple wiring layers are shown.

[0168] Figure 5 It is along Figure 3 The cross-sectional view taken by line B-B', and Figure 6 It is along Figure 3 A cross-sectional view taken from line A-A'.

[0169] It should be noted that Figure 5 and Figure 6 Each of these is arranged within its own context, including... Figure 4 The image shows a cross-sectional view of multiple pixels 51 of the DTI 65. Furthermore, in... Figure 5 and Figure 6 In, and in Figure 3 and Figure 4 The corresponding parts in the text are indicated by the same reference numerals, and their descriptions are omitted.

[0170] For each pixel, a multilayer wiring layer 111 is formed on the side of the substrate 61 opposite to the light-incident surface on which the on-chip lens 62 is formed. In other words, the substrate 61, as a semiconductor layer, is disposed between the on-chip lens 62 and the multilayer wiring layer 111. The multilayer wiring layer 111 includes five metal films M1 to M5 and an interlayer insulating film 112 between the five metal films M1 to M5. Note that in Figure 5 In the diagram, the outermost metal film M5 of the five metal films M1 to M5 of the multilayer wiring layer 111 is not shown because metal film M5 is located in an invisible position, but... Figure 6 As shown in the figure, Figure 6 From and Figure 5 Cross-sectional views viewed from different directions.

[0171] like Figure 6 As shown, the pixel transistor Tr is formed in the pixel boundary region at the interface between the multilayer wiring layer 111 and the substrate 61. The pixel transistor Tr is described later. Figure 12 and Figure 13 Any one of the described transmission transistor 121, reset transistor 123, amplification transistor 124, selection transistor 125, etc.

[0172] In the five metal films M1 to M5 of the multilayer wiring layer 111, the metal film M1 closest to the substrate 61 includes a power line 113 for providing a power supply voltage, a voltage application line 114 for applying a predetermined voltage to the P+ semiconductor region 73-1 or 73-2, and a reflective member 115 for reflecting incident light. Figure 6 In the metal film M1, the wiring other than the power line 113 and the voltage application line 114 is a reflective member 115; however, some reference numerals are omitted to avoid complexity in the drawings. The reflective member 115 is arranged for reflecting incident light. The reflective member 115 is arranged below the N+ semiconductor regions 71-1 and 71-2 so as to overlap with the N+ semiconductor regions 71-1 and 71-2, which serve as charge detection units, in the plan view. Note that a light-shielding member can be provided instead of the reflective member 115.

[0173] For example, in the metal film M2, which is the second layer from the substrate 61 side, a voltage application line 116 connected to the voltage application line 114 of the metal film M1 is formed. (Refer to later for details.) Figure 12 and Figure 13 The control line 117, including the drive signal TRG, drive signal RST, selection signal SEL, and drive signal FDG, and the VSS line having a predetermined VSS potential (such as GND), are described. Furthermore, a reference is formed in the metal film M2. Figure 12 and Figure 13 The FD 122 and the additional capacitor 127 are described.

[0174] For example, vertical signal lines VSL, VSS wiring, etc. are formed in the metal film M3, which is the third layer from the substrate 61 side.

[0175] For example, in the metal films M4 and M5, which are the fourth and fifth layers from the substrate 61 side, voltage supply lines 118 and 119 are formed for applying a predetermined voltage MIX_A or MIX_B to the P+ semiconductor regions 73-1 and 73-2, which are voltage application units of the tap T.

[0176] It should be noted that the following will refer to... Figures 18 to 23 Describes the details of the planar arrangement of the five metal films M1 to M5 of the multilayer wiring layer 111.

[0177] 4. Examples of other planar shapes for tap T

[0178] Reference Figures 7 to 11 Describe other planar shapes of tap T.

[0179] It should be noted that, Figures 7 to 11 In, corresponding to Figure 3 The parts in the text are indicated by the same reference numerals, and their descriptions are omitted appropriately.

[0180] (First modification to tap T)

[0181] Figure 7 This is a plan view showing the first modified first tap TA and second tap TB of pixel 51.

[0182] exist Figure 3 In the diagram, the planar shape of each tap T, the first tap TA and the second tap TB, is rectangular.

[0183] exist Figure 7 In the first variation shown, the planar shape of each tap T, the first tap TA and the second tap TB, is circular. More specifically, a circular P+ semiconductor region 73 is formed at the center of each tap T, and the periphery of the P+ semiconductor region 73 is surrounded by a circular (annular) N+ semiconductor region 71, with the P+ semiconductor region 73 serving as the center.

[0184] (Second modification to tap T)

[0185] Figure 8 This is a plan view showing the second modification of the first tap TA and the second tap TB of pixel 51.

[0186] exist Figure 3 In this configuration, each tap T is formed such that the N+ semiconductor region 71 surrounds the outer periphery of the P+ semiconductor region 73. However, in Figure 8 In the second variation shown, each tap T is formed such that the linear N+ semiconductor region 71 sandwiches the linear P+ semiconductor region 73 in a direction perpendicular to the longitudinal direction. Therefore, the end face of the short side of the linear P+ semiconductor region 73 is not surrounded by the N+ semiconductor region 71.

[0187] The lateral length of each of the linear N+ semiconductor region 71 and the linear P+ semiconductor region 73 can be any length, and these regions do not need to have the same length.

[0188] (Third modification to tap T)

[0189] Figure 9 This is a plan view showing a third variation of the first tap TA and the second tap TB of pixel 51.

[0190] exist Figure 3 In this configuration, each tap T has a configuration in which a P+ semiconductor region 73 is surrounded by an N+ semiconductor region 71. In other words, the P+ semiconductor region 73 is formed inside the tap T, and the N+ semiconductor region 71 is formed outside the tap T.

[0191] The arrangement of N+ semiconductor region 71 and P+ semiconductor region 73 can be reversed.

[0192] By reversing Figure 3 The arrangement of the N+ semiconductor region 71 and P+ semiconductor region 73 of each tap T is configured to... Figure 9 Each tap T in the process.

[0193] Specifically, Figure 9 Each tap T has a configuration in which a rectangular N+ semiconductor region 71 is surrounded by a P+ semiconductor region 73. In other words, an N+ semiconductor region 71 is formed, and a P+ semiconductor region 73 is formed on the outside.

[0194] (Fourth modification to tap T)

[0195] Figure 10 This is a plan view showing a fourth variation of the first tap TA and the second tap TB of pixel 51.

[0196] Figure 10 Each tap T in the process is reversed Figure 8 The arrangement of the N+ semiconductor region 71 and P+ semiconductor region 73 of each tap T is configured.

[0197] Specifically, Figure 10 Each tap T is formed such that the linear P+ semiconductor region 73 sandwiches the linear N+ semiconductor region 71 between them from a direction perpendicular to the longitudinal direction.

[0198] The lateral length of each of the linear N+ semiconductor region 71 and the linear P+ semiconductor region 73 can be any length, and these regions do not need to have the same length.

[0199] (Fifth modification to tap T)

[0200] Figure 11 This is a plan view showing a fifth variation of the first tap TA and the second tap TB of pixel 51.

[0201] exist Figure 11 In the middle, the six pixels 51 arranged in a 2x4 pattern are distinguished from each other as pixels 51A to 51H.

[0202] The first tap TA and the second tap TB of each pixel 51 may have a structure in which the P+ semiconductor region 73, which serves as a voltage application unit, is shared by adjacent pixels 51. In the following text, the structure in which the P+ semiconductor region 73, which serves as a voltage application unit, is shared by two taps T of different pixels 51, is also referred to as a shared tap structure.

[0203] exist Figure 11 The fifth variation shown is a shared tap structure, in which, as Figure 8The P+ semiconductor region 73 of each tap T voltage application unit is shared by two adjacent pixels 51 in the vertical direction (up and down direction).

[0204] Specifically, the P+ semiconductor region 73-1 disposed at the pixel boundary between pixel 51A and pixel 51C serves as the P+ semiconductor region 73 for applying voltage to the first tap TA of pixel 51A and the P+ semiconductor region 73 for applying voltage to the first tap TA of pixel 51C.

[0205] The P+ semiconductor region 73-1 disposed at the pixel boundary between pixel 51B and pixel 51D serves as the P+ semiconductor region 73 as the voltage application unit of the first tap TA of pixel 51B, and also serves as the P+ semiconductor region 73-1 as the voltage application unit of the first tap TA of pixel 51D.

[0206] The P+ semiconductor region 73-2 disposed at the pixel boundary between pixel 51A and pixel 51E serves as the P+ semiconductor region 73 for applying voltage to the second tap TB of pixel 51B and as the P+ semiconductor region 73 for applying voltage to the second tap TB of pixel 51E.

[0207] The P+ semiconductor region 73-2 disposed at the pixel boundary between pixel 51B and pixel 51F serves as a P+ semiconductor region 73 for applying voltage to the second tap TB of pixel 51B, and also serves as a P+ semiconductor region 73 for applying voltage to the second tap TB of pixel 51F.

[0208] Similarly, each of the P+ semiconductor regions 73-2 located at the pixel boundary between pixel 51C and pixel 51G and the P+ semiconductor region 73-2 located at the pixel boundary between pixel 51D and pixel 51H serves as a voltage application unit for the second tap TB of two adjacent pixels 51 in the vertical direction.

[0209] As described above, similarly in a shared tap structure where the P+ semiconductor region 73 of each tap T's voltage application unit is shared by adjacent pixels, the distance can be determined by referring to... Figure 2 The described operation was measured using an indirect ToF method.

[0210] In such Figure 11In the shared tap structure shown, the distance between the paired P+ semiconductor regions used to generate the electric field (i.e., current) is relatively long (e.g., the distance between the P+ semiconductor region 73-1 of the first tap TA and the P+ semiconductor region 73-2 of the second tap TB). In other words, the distance between the P+ semiconductor regions can be maximized by having adjacent pixels share the P+ semiconductor region 73 of the voltage application unit of each tap T. Therefore, since the current hardly flows between the P+ semiconductor regions of the two taps T, the power consumption of pixel 51 can be reduced, which is beneficial for pixel miniaturization.

[0211] It should be noted that Figure 11 It shows that Figure 8 The tap structure is a configuration of shared tap structures. However, for example, in Figure 10 In the case of a shared tap structure, the N+ semiconductor region 71 is shared by adjacent pixels 51.

[0212] 5. Equivalent Circuit of a Pixel

[0213] Figure 12 The equivalent circuit of pixel 51 is shown.

[0214] Pixel 51 includes a transmission transistor 121A, an FD 122A, a reset transistor 123A, an amplification transistor 124A, and a selection transistor 125A for a first tap TA including an N+ semiconductor region 71-1, a P+ semiconductor region 73-1, etc.

[0215] In addition, pixel 51 includes a transmission transistor 121B, an FD 122B, a reset transistor 123B, an amplification transistor 124B, and a selection transistor 125B for a second tap TB including an N+ semiconductor region 71-2, a P+ semiconductor region 73-2, etc.

[0216] Tap driving unit 21 applies a predetermined voltage MIX_A (first voltage) to P+ semiconductor region 73-1 and a predetermined voltage MIX_B (second voltage) to P+ semiconductor region 73-2. In the example above, one of voltages MIX_A and MIX_B is 1.5V, and the other is 0V. P+ semiconductor regions 73-1 and 73-2 are voltage application units to which the first voltage or the second voltage is applied.

[0217] N+ semiconductor regions 71-1 and 71-2 are both charge detection units, which detect and accumulate the charge generated by the photoelectric conversion of light incident on the substrate 61.

[0218] When the drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 121A becomes conductive in response to it, thereby transferring the charge accumulated in the N+ semiconductor region 71-1 to FD122A. When the drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 121B becomes conductive in response to it, thereby transferring the charge accumulated in the N+ semiconductor region 71-2 to FD122B.

[0219] FD 122A temporarily retains the charge DET_A supplied from the N+ semiconductor region 71-1. FD 122B temporarily retains the charge DET_B supplied from the N+ semiconductor region 71-2. FD 122A and reference Figure 2 The description corresponds to FD part A, and FD 122B corresponds to FD part B.

[0220] When the drive signal RST supplied to the gate electrode becomes active, the reset transistor 123A turns on in response, thereby resetting the potential of FD122A to a predetermined level (supply voltage VDD). When the drive signal RST supplied to the gate electrode becomes active, the reset transistor 123B turns on in response, thereby resetting the potential of FD122B to a predetermined level (supply voltage VDD). Note that when the reset transistors 123A and 123B become active, the transfer transistors 121A and 121B also become active simultaneously.

[0221] By connecting the source electrode of the amplifying transistor 124A to the vertical signal line VSLA via the select transistor 125A, the amplifying transistor 124A forms a source follower circuit using the load MOS of the constant current source circuit unit 126A connected to one end of the vertical signal line VSLA. By connecting the source electrode of the amplifying transistor 124B to the vertical signal line VSLB via the select transistor 125B, the amplifying transistor 124B forms a source follower circuit having a load MOS of the constant current source circuit unit 126B connected to one end of the vertical signal line VSLB.

[0222] Selector transistor 125A is connected between the source electrode of amplifier transistor 124A and the vertical signal line VSLA. When the select signal SEL supplied to the gate electrode becomes active, selector transistor 125A turns on in response and outputs the detection signal from amplifier transistor 124A to the vertical signal line VSLA.

[0223] Selector transistor 125B is connected between the source electrode of amplifier transistor 124B and the vertical signal line VSLB. When the select signal SEL supplied to the gate electrode becomes active, selector transistor 125B turns on in response and outputs the detection signal from amplifier transistor 124B to the vertical signal line VSLB.

[0224] The transfer transistors 121A and 121B, reset transistors 123A and 123B, amplification transistors 124A and 124B, and selection transistors 125A and 125B of pixel 51 are controlled, for example, by vertical drive unit 22.

[0225] Examples of other equivalent circuit configurations for pixels

[0226] Figure 13 Another equivalent circuit for pixel 51 is shown.

[0227] exist Figure 13 In, corresponding to Figure 12 The parts in the text are indicated by the same reference numerals, and their descriptions are omitted appropriately.

[0228] exist Figure 13 In the equivalent circuit, an additional capacitor 127 and a switching transistor 128 for controlling its connection are added. Figure 12 The first tap TA and the second tap TB in the equivalent circuit.

[0229] Specifically, the additional capacitor 127A is connected between the transfer transistors 121A and FD122A via the switching transistor 128A, and the additional capacitor 127B is connected between the transfer transistors 121B and FD122B via the switching transistor 128B.

[0230] When the drive signal FDG supplied to the gate electrode becomes active, the switching transistor 128A turns on in response, thereby connecting the auxiliary capacitor 127A to FD122A. When the drive signal FDG supplied to the gate electrode becomes active, the switching transistor 128B turns on in response, thereby connecting the auxiliary capacitor 127B to FD122B.

[0231] For example, under high illumination with a large amount of incident light, the vertical drive unit 22 activates the switching transistors 128A and 128B, connects FD 122A and the additional capacitor 127A to each other, and connects FD 122B and the additional capacitor 127B to each other. Therefore, more charge can be accumulated under high illumination.

[0232] Meanwhile, under low illumination with a small amount of incident light, the vertical drive unit 22 disables the switching transistors 128A and 128B and disconnects the additional capacitors 127A and 127B from FD122A and 122B, respectively.

[0233] As in Figure 12 In the equivalent circuit, the additional capacitor 127 can be omitted. However, by providing the additional capacitor 127 and using it in various ways depending on the amount of incident light, a high dynamic range can be ensured.

[0234] 6. Wiring Example for Vertical Signal Line (VSL)

[0235] In the optical receiving device 1, as referenced Figure 1 The method described above provides four vertical signal lines VSL for each pixel column of pixels 51 arranged in a matrix in pixel array unit 20.

[0236] Figures 14 to 17 An example of the wiring of an optical receiver 1 is shown in which four vertical signal lines (VSLs) are set for a single pixel column.

[0237] (First wiring example for the vertical signal line VSL)

[0238] Figure 14 The first wiring example of the vertical signal line (VSL) is shown.

[0239] Because in Figure 14 The pixel circuit of each pixel 51 shown in the diagram is related to the pixel circuit in the diagram. Figure 12 The circuits shown are identical, so reference numerals are appropriately omitted. Furthermore, in Figure 11 The shared tap structure shown is adopted as Figure 14 The configuration of each tap T for each pixel 51 in the image.

[0240] It should be noted that, although Figure 14 Only one pixel column is shown, but the same applies to other pixel columns. Furthermore, in Figure 14 In the image, four pixels 51 arranged in a pixel column are distinguished from each other as pixels 51A to 51D, and four vertical signal lines VSL arranged in a pixel column are distinguished from each other as vertical signal lines VSL0 to VSL3.

[0241] exist Figure 14 In the first wiring example, two adjacent pixels 51 in the vertical direction form a pair, the first tap TA of the two pixels 51 to be paired is connected to the same vertical signal line VSL, and the second tap TB of the two pixels 51 to be paired is connected to the same vertical signal line VSL.

[0242] Specifically, pixel 51A and the first tap TA of the paired pixel 51B are connected to vertical signal line VSL0, and the second tap TB of pixel 51A and the paired pixel 51B are connected to vertical signal line VSL2. The first tap TA of the paired pixel 51C and pixel 51D are connected to vertical signal line VSL1, and the second tap TB of the paired pixel 51C and pixel 51D are connected to vertical signal line VSL3.

[0243] Therefore, vertical signal line VSL0 outputs the detection signal of the first tap TA of the paired pixels 51A and 51B to column processing unit 23, and vertical signal line VSL1 outputs the detection signal of the first tap TA of the paired pixels 51C and 51D to column processing unit 23. Vertical signal line VSL2 outputs the detection signal of the second tap TB of the paired pixels 51A and 51B to column processing unit 23, and vertical signal line VSL3 outputs the detection signal of the second tap TB of the paired pixels 51C and 51D to column processing unit 23. Therefore, among the four vertical signal lines VSL0 to VSL3, the two vertical signal lines (vertical signal lines VSL0 and VSL1) that both send the detection signal of the first tap TA and the two vertical signal lines (vertical signal lines VSL2 and VSL3) that both send the detection signal of the second tap TB are set to be adjacent to each other (TA, TA, TB, TB).

[0244] By arranging the four vertical signal lines VSL0 to VSL3 in a pixel column, in the first driving mode where the detection signal of each pixel 51 is output in units of one pixel, the light receiving device 1 can output the detection signal to the outside of the pixel array unit 20 (column processing unit 23) in units of two rows of odd or even rows. Therefore, the reading speed can be improved.

[0245] Meanwhile, in the second driving mode where the detection signals of the two taps T are summed and output, the optical receiving device 1 can sum the detection signals of the first tap TA or the second tap TB of the two pixels to be paired and output the detection signals to the outside of the pixel array unit 20 in units of four rows. In order to improve resolution, even when the number of pixels increases and the signal amount per pixel is small, a sufficient S / N ratio can be ensured by summing the detection signals of the two pixels.

[0246] (Second wiring example for vertical signal line VSL)

[0247] Figure 15 The second wiring example for the vertical signal line VSL is shown.

[0248] exist Figure 15 In the text, appropriate omissions and Figure 14 The descriptions of those similar points to the first wiring example shown in the diagram will be included, and the points that differ from the first wiring example will also be described.

[0249] Figure 15 The second wiring example shares the same characteristics as the first wiring example, where the first taps TA of the two pixels 51 to be paired are connected to the same vertical signal line VSL, and the second taps TB of the two pixels 51 to be paired are also connected to the same vertical signal line VSL.

[0250] However, Figure 15 The second wiring example is the same as in Figure 14 The first wiring example shown is similar in that the first tap TA of the pair of pixels 51A and 51B is connected to the vertical signal line VSL0, but in the second wiring example, the second tap TB is connected to the vertical signal line VSL1 instead of VSL2.

[0251] Figure 15 The second wiring example is similar to the first wiring example in that the second tap TB of the paired pixels 51C and 51D is connected to the vertical signal line VSL3, but in the second wiring example, the first tap TA is not connected to the vertical signal line VSL1 but to the vertical signal line VSL2.

[0252] Therefore, in the second wiring example, vertical signal line VSL0 outputs the detection signal of the first tap TA of paired pixels 51A and 51B, and vertical signal line VSL1 outputs the detection signal of the second tap TB of paired pixels 51A and 51B to column processing unit 23. Vertical signal line VSL2 outputs the detection signal of the first tap TA of pixels 51C and 51D to be paired, and vertical signal line VSL3 outputs the detection signal of the second tap TB of pixels 51C and 51D to be paired. Therefore, among the four vertical signal lines VSL0 to VSL3, the vertical signal line VSL that transmits the detection signal of the first tap TA and the vertical signal line VSL that transmits the detection signal of the second tap TB are arranged alternately (TA, TB, TA, TB).

[0253] The drivers in the second wiring example, both in the first and second driving modes, are similar to those in the first wiring example. Therefore, in the first driving mode, read speed can be improved. In the second driving mode, even with a small signal per pixel, a sufficient signal-to-noise ratio can be ensured by adding the detection signals of two pixels.

[0254] exist Figure 14 First wiring example and Figure 15 In the second wiring example, in the second driving mode where the detection signals of two taps T are added and output, the detection signals of the two taps T to be added are closed within the two pixels constituting the pair. Therefore, the operational deviation between the first taps TA of two vertically adjacent pairs or between the second taps TB of two vertically adjacent pairs can be reduced, and the distortion of high-speed operation can be reduced.

[0255] In addition, Figure 15In the second wiring example, the vertical signal line VSL transmitting the detection signal of the first tap TA and the vertical signal line VSL transmitting the detection signal of the second tap TB are arranged alternately (TA, TB, TA, TB), thereby making the coupling capacitance between adjacent vertical signal lines VSL uniform to reduce noise.

[0256] (Third wiring example for vertical signal line VSL)

[0257] Figure 16 This shows a third wiring example for the vertical signal line VSL.

[0258] exist Figure 16 In the text, appropriate omissions and in Figure 14 The descriptions of those similar points to the first wiring example shown in the diagram will be included, and the points that differ from the first wiring example will also be described.

[0259] exist Figure 16 In the third wiring example, in the second driving mode where two detection signals are added and output, in each of the first tap TA and the second tap TB, the detection signals are shared by the two taps T in the P+ semiconductor region 73 of the voltage application unit.

[0260] For example, the two second taps TB located at the pixel boundary between pixel 51A and pixel 51B are both connected to the vertical signal line VSL2. Therefore, the two second taps TB are two taps T that are added together and output as detection signals in the second driving mode, and they share the P+ semiconductor region 73 located at the pixel boundary between pixel 51A and pixel 51B.

[0261] The two first taps TA, located at the pixel boundary between pixel 51B and pixel 51C, are both connected to the vertical signal line VSL1. Therefore, the two first taps TA are two taps T whose detection signals will be added together and output in the second driving mode, and they share the P+ semiconductor region 73 located at the pixel boundary between pixel 51B and pixel 51C.

[0262] The two second taps TB located at the pixel boundary between pixel 51C and pixel 51D are both connected to the vertical signal line VSL3. Therefore, the two second taps TB are two taps T whose detection signals will be added together and output in the second driving mode, and they share the P+ semiconductor region 73 located at the pixel boundary between pixel 51C and pixel 51D.

[0263] On the other hand, Figure 14In the first wiring example shown, in the second driving mode, as in the third wiring example, the two second taps TB share the P+ semiconductor region 73 of the voltage application unit, but for the first tap TA that adds the detection signals of the two taps T, the P+ semiconductor region 73 of the voltage application unit is not shared.

[0264] For example, in Figure 14 In the alignment of pixels 51A and 51B, for the second tap TB, the detection signals of the second tap TB of pixel 51A and the second tap TB of pixel 51B will be added together, sharing the P+ semiconductor region 73 located at the pixel boundary between pixels 51A and 51B. However, for the first tap TA, the first tap TA of pixel 51A and the first tap TA of pixel 51B whose detection signals are to be added do not share the P+ semiconductor region 73. In other words, the P+ semiconductor region 73 of the first tap TA of pixel 51A and the P+ semiconductor region 73 of the first tap TA of pixel 51B are different P+ semiconductor regions 73.

[0265] In addition, Figure 16 In the third wiring example, the two first taps TA, which have a shared tap structure at the pixel boundary between pixel 51A and pixel 51 (not shown), are both connected to the vertical signal line VSL0. The two second taps TB, which have a shared tap structure at the pixel boundary between pixel 51A and pixel 51B, are both connected to the vertical signal line VSL2. The two first taps TA, which have a shared tap structure at the pixel boundary between pixel 51B and pixel 51C, are both connected to the vertical signal line VSL1. The two second taps TB, which have a shared tap structure at the pixel boundary between pixel 51C and pixel 51D, are both connected to the vertical signal line VSL3. Therefore, among the four vertical signal lines VSL0 to VSL3, the two vertical signal lines (vertical signal lines VSL0 and VSL1) that both transmit the detection signal of the first tap TA and the two vertical signal lines (vertical signal lines VSL2 and VSL3) that both transmit the detection signal of the second tap TB are set to be adjacent to each other (TA, TA, TB, TB).

[0266] In the first driving mode, where the detection signal for each pixel 51 is output as a unit of one pixel, the light receiving device 1 outputs the detection signal to the outside of the pixel array unit 20 (column processing unit 23) in units of two odd-numbered rows or even-numbered rows. Therefore, the reading speed can be improved.

[0267] Meanwhile, in the second driving mode where the detection signals of two taps T are summed and output, the light receiving device 1 sums the detection signals of two first taps TA or two second taps TB corresponding to two pixels and outputs the detection signals to the outside of the pixel array unit 20 in four-row units. Even when the signal amount per pixel is small, a sufficient signal-to-noise ratio can be ensured.

[0268] According to the third wiring example, in the second driving mode, since the P+ semiconductor region 73 is shared as the voltage application unit of the two taps T whose detection signals are applied and output, the variation of the applied voltage applied to the two taps T whose detection signals are applied and output can be suppressed.

[0269] (Fourth wiring example for vertical signal line VSL)

[0270] Figure 17 The fourth wiring example for the vertical signal line VSL is shown.

[0271] exist Figure 17 In this document, descriptions of points similar to those in the first to third wiring examples described above will be appropriately omitted, while points different from those in the first to third wiring examples will be described.

[0272] Unlike in Figure 15 The second wiring example shown in the figure, Figure 17 The fourth wiring example has a configuration in which, in a second drive mode where two detection signals are added and output, the detection signals are shared by the two taps T being added as a voltage application unit, specifically the P+ semiconductor region 73.

[0273] In other words, Figure 17 The fourth wiring example and Figure 16 The common feature of the third wiring examples is that, in the second drive mode in which two detection signals are added and output, in each of the first tap TA and the second tap TB, the detection signal is shared by the two taps T as the P+ semiconductor region 73 of the voltage application unit.

[0274] At the same time, Figure 16 In the third wiring example, the two second taps TB located at the pixel boundary between pixel 51A and pixel 51B are connected to the vertical signal line VSL2, but in Figure 17 In the fourth wiring example, two second taps TB are connected to the vertical signal line VSL1. Furthermore, in the third wiring example, two first taps TA located at the pixel boundary between pixel 51B and pixel 51C are connected to the vertical signal line VSL1, but... Figure 17In the fourth wiring example, the two first taps TA are connected to the vertical signal line VSL2. Therefore, in the four vertical signal lines VSL0 to VSL3, as in Figure 15 In the second wiring example shown, the vertical signal line VSL that transmits the detection signal of the first tap TA and the vertical signal line VSL that transmits the detection signal of the second tap TB are arranged alternately (TA, TB, TA, TB).

[0275] In the first driving mode, where the detection signal for each pixel 51 is output as a unit of one pixel, the light receiving device 1 outputs the detection signal to the outside of the pixel array unit 20 (column processing unit 23) in units of two odd-numbered rows or even-numbered rows. Therefore, the reading speed can be improved.

[0276] Meanwhile, in the second driving mode where the detection signals of two taps T are summed and output, the light receiving device 1 sums the detection signals of two first taps TA or two second taps TB corresponding to two pixels and outputs the detection signals to the outside of the pixel array unit 20 in four-row units. Even when the signal amount per pixel is small, a sufficient signal-to-noise ratio can be ensured.

[0277] According to the fourth wiring example, in the second driving mode, because the P+ semiconductor region 73 is shared as the voltage application unit of the two taps T whose detection signals are applied and output, the variation of the applied voltage applied to the two taps T whose detection signals are applied and output can be suppressed.

[0278] Based on the first to fourth wiring examples of setting four vertical signal lines (VSLs) for a pixel column, a driving mode (first driving mode) that improves resolution by utilizing the signal output as a pixel unit and a driving mode (second driving mode) that improves the signal's signal-to-noise ratio (S / N ratio) rather than resolution in various ways depending on the application can be used. In other words, it is possible to suppress the decrease in ranging accuracy caused by the increase in the number of pixels while increasing the number of pixels.

[0279] 7. Example of the planar arrangement of five-layer metal membranes M1 to M5

[0280] Next, we will refer to Figures 18 to 23 The detailed structure of the multilayer wiring layer 111 formed on the side of the substrate 61 opposite to the light incident surface is described.

[0281] It should be noted that Figures 18 to 23 The configuration shown corresponds to the reference. Figure 5 and Figure 6 The configurations described are different from those in the different modes, but will be described using different reference numerals.

[0282] Figure 18It is a plan view of the gate forming surface, where the contact between the gate electrode and the pixel transistor Tr (which is the interface between the substrate 61 and the multilayer wiring layer 111) is formed on the gate forming surface.

[0283] Figure 18 The plan view on the left is a plan view of the area in the pixel array unit 20 that includes multiple pixels arranged in the vertical direction, and the area of ​​a predetermined pixel 51 is represented by a dashed line. Figure 18 The plan view on the right is a magnified view of the area near pixel 51, indicated by dashed lines in the plan view on the left. In the magnified view, the areas of the first tap TA and the second tap TB are indicated by dashed lines.

[0284] The gate forming surface of substrate 61 includes: an active region 181, in which the gate electrode of pixel transistor Tr is formed, a contact with P+ semiconductor region 73 serving as a voltage application unit, and a contact with N+ semiconductor region 71 serving as a charge detection unit; and an oxide film region 182, which is the region other than the active region 181. The oxide film region 182 corresponds, for example, to... Figure 2 The oxide film 64, the separating portion 75, etc. It should be noted that... Figures 19 to 23 In the diagram, the active region 181 is shown as superimposed on the lower layer, where the reference labels for the reference position relationship are omitted.

[0285] In the region of a pixel 51, a first tap TA including an N+ semiconductor region 71-1, a P+ semiconductor region 73-1, etc., and a second tap TB including an N+ semiconductor region 71-2, a P+ semiconductor region 73-2, etc., are arranged at the pixel boundary to be symmetrical in the vertical direction with respect to the pixel center line (not shown) of pixel 51.

[0286] The transfer transistor 121A, reset transistor 123A, amplification transistor 124A, selection transistor 125A, and switching transistor 128A, which control the first tap TA, and the transfer transistor 121B, reset transistor 123B, amplification transistor 124B, selection transistor 125B, and switching transistor 128B, which control the second tap TB, are symmetrically arranged in the vertical direction with respect to the pixel center line of pixel 51.

[0287] By arranging multiple pixel transistors Tr that control the first tap TA or the second tap TB in two columns in the active region 181, the pixel transistors Tr can be configured to have a margin. Specifically, the gate electrode of the amplifying transistor 124 can be formed to have the largest size, and thus the noise characteristics of the amplifying transistor 124 can be suppressed.

[0288] Figure 19An example of the planar arrangement of the metal film M1, which is the first layer closest to the substrate 61 among the five metal films M1 to M5 that serve as multilayer wiring layers 111, is shown.

[0289] Figure 19 The relationship between the left and right plan views and Figure 18 The relationships are similar.

[0290] In the metal film M1, which is the first layer of the multilayer wiring layer 111, a reflective member 115 for reflecting infrared light is formed between the first tap TA and the second tap TB of the pixel 51. Figure 5 Metal films 201A and 201B are shown. Although the boundary between metal films 201A and 201B is not shown, metal films 201A and 201B are formed symmetrically with respect to the vertical direction of pixel 51 in the region of pixel 51. Figure 19 As shown, the areas of metal films 201A and 201B are formed to be the largest in the region of pixel 51. By reflecting the infrared light that passes through the substrate 61 and is incident on the multilayer wiring layer 111 back to the substrate 61, the amount of infrared light photoelectrically converted in the substrate 61 can be further increased to improve sensitivity.

[0291] Note that the potential of each of the metal films 201A and 201B is a predetermined VSS potential, and in this embodiment, it is, for example, GND.

[0292] Metal film 202A is used to bond the gate electrode of amplifying transistor 124A and FD 122A ( Figure 20 The wiring connects them to each other. Metal film 202B is used to connect the gate electrode of amplifying transistor 124B and FD 122B ( Figure 20 The wiring is interconnected. Metal films 202A and 202B are also symmetrically arranged in the vertical direction with respect to the pixel center line of pixel 51.

[0293] Metal films 203A and 203B are wirings connected to selection transistors 125A and 125B. Metal film 204A is a wiring connected to the N+ semiconductor region 71-1 of the charge detection unit, which serves as the first tap TA of pixel 51, and metal film 204B is a wiring connected to the N+ semiconductor region 71-2 of the charge detection unit, which serves as the second tap TB of pixel 51.

[0294] Metal films 205A and 205B are wires connected to transfer transistors 121A and 121B. Metal films 206A and 206B are wires connected to reset transistors 123A and 123B.

[0295] Metal films 203A to 206A associated with the first tap TA and metal films 203B to 206B associated with the second tap TB are symmetrically arranged in the vertical direction with respect to the pixel center line of pixel 51. A power supply voltage VDD is supplied to the contact 207 located in the pixel center portion of pixel 51 in the vertical direction.

[0296] The metal film 201A, serving as a shielding line, is disposed between the gate electrode of the amplifying transistor 124A and the FD122A ( Figure 20 The metal films 202A are connected to each other and are positioned between the contact 207 and the power supply voltage VDD. Therefore, the influence of the potential of FD122A on the potential fluctuation of the power supply voltage VDD is reduced, and noise is suppressed.

[0297] The metal film 201A, serving as a shielding wire, is also disposed between the gate electrode of the amplifying transistor 124A and the FD 122A ( Figure 20 The metal film 202A, which is connected to each other, is connected to the metal film 203A, which is a line connected to the selection transistor 125A. Therefore, the influence of the potential of FD122A on the potential fluctuation of the selection transistor 125A is reduced, and noise is suppressed.

[0298] The metal film 201A, serving as a shielding wire, is also disposed between the gate electrode of the amplifying transistor 124A and the FD 122A ( Figure 20 The metal films 202A connected to each other are connected to the metal film 204A of the charge detection unit, which serves as the first tap TA, and the line connected to the N+ semiconductor region 71-1. Therefore, the influence of the potential of FD 122A on the potential fluctuation of the charge detection unit of the first tap TA is reduced, and noise is suppressed.

[0299] This also applies to the metal films 201B to 206B with respect to the second tap TB, where the pixel center line of pixel 51 is symmetrically set in the vertical direction.

[0300] Because the pixel transistor Tr driving the first tap TA and the pixel transistor Tr driving the second tap TB are symmetrically arranged in the vertical direction, the wiring load is uniformly adjusted between the first tap TA and the second tap TB. This reduces the driving variation between the first tap TA and the second tap TB.

[0301] Figure 20 An example of the planar arrangement of metal film M2, the second layer of the five-layer metal films M1 to M5, which serve as multilayer wiring layer 111, is shown.

[0302] Figure 20 The relationship between the left and right plan views and Figure 18 The relationships are similar.

[0303] In the metal film M2, which serves as the second layer of the multilayer wiring layer 111, the FD 122A of pixel 51 is composed of a comb-shaped metal film 211A. The GND (VSS potential) metal film 212A is formed in a comb shape and inserted into the comb-shaped gaps of the metal film 211A as FD122A. Each of the metal film 212A serving as FD122A and the GND (VSS potential) metal film 212A is formed in a comb shape, ensuring a large relative area. Therefore, the storage capacity of FD122A can be increased and the dynamic range can be widened. Furthermore, the GND metal film 212A is disposed around the metal film 211A as FD122A to surround the metal film 211A, reducing the influence of other potential changes on the potential of FD122A and suppressing noise.

[0304] In the metal film M2, the FD 122B of pixel 51 is formed at a position symmetrical to FD 122A in the vertical direction relative to the pixel center line of pixel 51. FD 122B is also composed of a comb-shaped metal film 211B, and the comb-shaped metal film 212B with GND (VSS potential) is formed facing the comb-shaped metal film 211B. As FD 122B, the metal film 212B with GND (VSS potential) is disposed around the metal film 211B to surround the metal film 211B, thereby suppressing noise.

[0305] In the metal film M2, FD 122A and 122B are set in a position that is not in contact with... Figure 18 and Figure 19 The pixel transistor Tr is formed in an area overlapping with the pixel transistor Tr. Therefore, potential fluctuations received from the metal film (wiring) connected to the pixel transistor Tr are reduced, and noise is suppressed. It should be noted that FD 122A and 122B can be used with… Figure 18 and Figure 19 The pixel transistor Tr in the image overlaps with part of the forming region.

[0306] Metal film 211A, FD122A, is connected to metal film M1 via two or more vias. Metal film 211B, FD122B, is also connected to metal film M1 via two or more vias. Therefore, the impact of resistance variations caused by process variations is reduced, and noise is also reduced.

[0307] The metal film 213, positioned at the center of the vertical direction of pixel 51, is a wiring for providing the power supply voltage VDD. Metal films 214A and 214B, positioned above and below metal film 213, are wiring for transmitting the drive signal TRG provided to transmission transistors 121A and 121B. Metal films 215A and 215B, positioned outside metal films 214A and 214B, are wiring for transmitting the drive signal RST provided to reset transistors 123A and 123B. Metal films 216A and 216B, positioned outside metal films 215A and 215B, are wires for transmitting the selection signal SEL provided to selection transistors 125A and 125B.

[0308] The wiring of the control signals of the multiple pixel transistors Tr that control the first tap TA or the second tap TB is arranged symmetrically in the vertical direction with respect to the pixel center line of pixel 51, thereby reducing the driving variation of the first tap TA and the second tap TB.

[0309] Figure 21 An example of the planar arrangement of the metal film M3, the third layer among the five metal films M1 to M5, which serve as the multilayer wiring layer 111, is shown.

[0310] Figure 21 The relationship between the left and right plan views and Figure 18 The relationships are similar.

[0311] Vertical signal lines VSL0 to VSL3 are arranged in a metal film M3, which serves as the third layer. Any one of wirings 221 to 225 is arranged on both sides of each of the vertical signal lines VSL0 to VSL3, and each of wirings 221 to 225 is connected to GND (VSS potential). By placing any one of wirings 221 to 225 connected to GND between any two of the vertical signal lines VSL0 to VSL3, potential fluctuations from adjacent vertical signal lines VSL are reduced, and noise is suppressed. Note that if the potentials of two adjacent vertical signal lines VSL0 to VSL3 are the same, the GND line (any one of wirings 221 to 225) between them can be omitted.

[0312] The area where vertical signal lines VSL0 to VSL3 are positioned within pixel 51 in the planar direction does not overlap with FD122A and 122B of the metal film M2. Therefore, the potential fluctuations of FD122A and 122B received from vertical signal lines VSL0 to VSL3 are reduced, and noise is suppressed.

[0313] In the region of metal film M3 corresponding to the positions of metal films 211A and 211B, FD122A and 122B, which are metal films M2, are provided with wiring 231 connected to GND (VSS potential). Therefore, by also setting the metal films 211A and 211B, which are metal films M2, and the GND line of metal film M3 to face each other in the stacking direction, the capacitance of FD122 increases, the potential fluctuation decreases, and the noise is suppressed.

[0314] Figure 22 An example of the planar arrangement of the metal film M4, the fourth layer among the five metal films M1 to M5, which serve as the multilayer wiring layer 111, is shown.

[0315] Figure 22 The relationship between the left and right plan views and Figure 18 The relationships are similar.

[0316] In the metal film M4, which serves as the fourth layer of the multilayer wiring layer 111, voltage supply lines 241-1 and 241-2 are formed for applying a predetermined voltage MIX_A or MIX_B to the P+ semiconductor regions 73-1 and 73-2, which serve as voltage application units for taps T of each pixel 51. Figure 22 In the example, voltage supply line 241-1 is connected via a via to the first tap TA of pixel 51, indicated by the dashed line, and voltage supply line 241-2 is connected via a via to the second tap TB of pixel 51, also indicated by the dashed line. Figure 22 In voltage supply lines 241-1 and 241-2, the areas represented by the shaded grid pattern indicate connections to... Figure 23 The through-hole region of the metal film M5 shown.

[0317] The wiring areas of the voltage supply lines 241-1 and 241-2 of the vertically extending metal film M4 are areas that do not overlap with the areas of the vertical signal lines VSL0 to VSL3 of the metal film M3 in the planar direction. Therefore, the influence of the voltage MIX_A or MIX_B of the voltage supply lines 241-1 and 241-2 on the potential of the vertical signal lines VSL0 to VSL3 is suppressed, and noise is suppressed.

[0318] Figure 23 An example of the planar arrangement of the fifth metal film M5, which is the fifth of the five metal films M1 to M5, serving as the multilayer wiring layer 111, is shown.

[0319] Figure 23 The relationship between the left and right plan views and Figure 18 The relationships are similar.

[0320] In the metal film M5, which is the fifth layer of the multilayer wiring layer 111, voltage supply lines 251-1 and 251-2 are formed for applying a predetermined voltage MIX_A or MIX_B to the P+ semiconductor regions 73-1 and 73-2, which are voltage application units serving as taps T of each pixel 51. Figure 23 In the example, similar to the voltage supply line 241-1 of the metal film M4, voltage supply line 251-1 is a wiring connected to the first tap TA, and voltage supply line 251-2 is a wiring connected to the second tap TB.

[0321] However, the voltage supply line 251-1 of the metal film M5 is not directly connected to the first tap TA, and the predetermined voltage MIX_A is applied to the first tap TA via the voltage supply line 241-1 of the metal film M4. Figure 23 In the voltage supply line 251-1 of the metal film M5, the area represented by the shaded grid pattern represents the through-hole area where the voltage supply lines 241-1 and 251-1 are connected to each other in the stacking direction.

[0322] Similarly, the voltage supply line 251-2 of the metal film M5 is not directly connected to the second tap TB, and the predetermined voltage MIX_B is applied to the second tap TB via the voltage supply line 241-2 of the metal film M4. Figure 23 In the voltage supply line 251-2 of the metal film M5, the area represented by the shaded grid pattern represents the through-hole area where the voltage supply lines 241-2 and 251-2 are connected to each other in the stacking direction.

[0323] For reference Figure 22 Metal film M4 and Figure 23 As can be seen from the metal film M5, the positions of the via regions between voltage supply lines 241-1 and 251-1 and between voltage supply lines 241-2 and 251-2 are offset from each other in the vertical direction. Therefore, the conductive regions between voltage supply lines 241-1 and 251-1 in the planar direction can be separated from the conductive regions between voltage supply lines 241-2 and 251-2 as much as possible. This allows for easy formation of vias and stabilizes the manufacturing process.

[0324] Two layers are wired in the vertical direction of the pixel array unit 20: a voltage supply line 241 for the fourth layer metal film M4 and a voltage supply line 251 for the fifth layer metal film M5. A predetermined voltage MIX_A or MIX_B applied to the tap T of each pixel 51 in the vertical direction is transmitted through these two layers. As a result, the wiring resistance in the vertical direction is reduced, and the propagation delay is decreased. Therefore, in-plane characteristic variations of the pixel array unit 20 can be suppressed.

[0325] Example of Pixel Separator Configuration (8.)

[0326] exist Figures 4 to 6 The structure in which DT165 is arranged as a pixel separator has been described, wherein the pixel 51 uses a tap structure that does not share the P+ semiconductor region 73 (a non-shared tap structure) as the voltage application unit of the tap T.

[0327] Next, we will refer to Figures 24 to 46 The description describes the structure in which the pixel separation portion is set in pixel 51 of tap T, which has a shared tap structure.

[0328] (First pixel segmentation structure)

[0329] Figure 24 A is a planar diagram illustrating the first pixel separation structure. It should be noted that in... Figure 24 In A, the boundary lines between pixels 51, represented by solid lines, are used to describe the boundaries between adjacent pixels 51 and do not represent any structure. This also applies to... Figures 25 to 32 .

[0330] Figure 24 B is corresponding to Figure 24 A pixel cross-sectional view of the line segment passing through tap T in the dashed portion of A.

[0331] In the first pixel separation structure, such as Figure 24 As shown in Figure A, DTI301 is arranged at the boundary portion between pixels 51. The planar shape of DTI301 is a lattice shape, and the lattice spacing is equal to the pixel spacing.

[0332] like Figure 24 As shown in Figure B, the DTI 301 is formed by embedding an insulator (e.g., SiO2) into a recess (trench), which is formed by excavating the substrate 61 to a predetermined depth from the back side, which is the light incident surface side of the substrate 61. The material to be embedded in the trench of the DTI 301 may be, for example, only an insulating layer such as SiO2, or may have a dual structure in which the outer side (pixel center side) of a metal layer such as tungsten is covered with an insulator. The DTI 301 is arranged in a planar view to overlap at least a portion of the P+ semiconductor region 73, which is a voltage application unit for a tap T (first tap TA or second tap TB). Furthermore, an inter-pixel light-shielding film 63 is formed on the upper surface of the DTI 301.

[0333] By forming the first pixel separation structure DTI 301, crosstalk caused by infrared light incident on adjacent pixels 51 can be suppressed. Furthermore, since the infrared light separation characteristics between pixels can be improved, sensitivity can be enhanced.

[0334] (Second pixel separation structure)

[0335] Figure 25 A is a planar diagram showing the second pixel separation structure.

[0336] Similarly, in the second pixel separation structure, such as Figure 25 As shown, DTI302 is set in a lattice shape along the pixel boundaries between pixels 51.

[0337] Figure 25 The pixel cross-section of the dashed line portion in the image is... Figure 24 The cross-sectional view of the first pixel separation structure shown in B is the same, and therefore is not shown.

[0338] Figure 24 The first pixel separation structure in Figure 25 The difference in the second pixel separation structure is that DTI301 is also formed at the intersection of the lattices in the first pixel separation structure, while DTI302 is not formed at the intersection of the lattices in the second pixel separation structure. The method for forming DTI302 and the material embedded in the groove are similar to those for DTI301.

[0339] By forming the second pixel separation structure DTI 302, crosstalk caused by infrared light incident on adjacent pixels 51 can be suppressed. Furthermore, since the infrared light separation characteristics between pixels can be improved, sensitivity can be enhanced.

[0340] Furthermore, according to the DTI302 in which no partition structure is formed at the grid-like intersection, it is possible to suppress the occurrence of overcurrent caused by the large width (width in the planar direction) of the slot at the intersection and the excessive depth of the slot when the DTI is formed.

[0341] (Third pixel separator structure)

[0342] Figure 26 A is a planar diagram showing the third pixel separation structure.

[0343] Figure 26 B is corresponding to Figure 26 A pixel cross-sectional view of the line segment passing through tap T in the dashed portion of A.

[0344] like Figure 26 As shown in A, in the third pixel separation structure, with Figure 24 Similar to the first pixel separation structure shown in A, DTI303 is arranged in a lattice shape at intervals equal to the pixel pitch. The difference between the third pixel separation structure DTI303 and the first pixel separation structure DTI301 lies in the position where DTI303 is formed.

[0345] That is, the position of the third pixel separator DTI303 is offset by half the lattice pitch in both the vertical and horizontal directions relative to the position of the first pixel separator DTI301. In other words, the first pixel separator DTI301 is formed such that the intersection of the lattice is located at the boundary portion between pixels 51, but the third pixel separator DTI303 is formed such that the intersection of the lattice is located at the center portion of the planar region of pixel 51.

[0346] Since DTI303 is formed on the line segment connecting the first tap TA and the second tap TB, it is compatible with... Figure 26 The pixel cross-section corresponding to the dashed line portion in A is in Figure 26 As shown in B.

[0347] The on-chip lens 62 is configured such that incident light is focused onto the central portion of the planar region of pixel 51, in other words, at the midpoint between the first tap TA and the second tap TB. Therefore, the convergence point of the incident light is the intersection of the DTI303, and the diffraction of the incident light by the DTI303 is increased. Thus, sensitivity can be improved.

[0348] (Fourth pixel segmentation structure)

[0349] Figure 27 A is a planar diagram showing the fourth pixel separation structure.

[0350] Figure 27 B is corresponding to Figure 27 A pixel cross-sectional view of the line segment passing through tap T in the dashed portion of A.

[0351] In the fourth pixel separation structure, DTI304 is formed. DTI304 has a structure that intersects with DTI303, which does not have the third pixel separation structure. In other words, the fourth pixel separation structure DTI304 and... Figure 26 The common feature of the third pixel separation structure in the image is that the lattice intersections are formed at the center of the planar region of pixel 51, and are consistent with... Figure 25 The common feature of the second pixel separator structure is that the separator structure is not placed at the intersection.

[0352] Based on the fourth pixel separation structure, similar to the third pixel separation structure, since the intersection of DTI304 is the center part of the pixel region, the diffraction of incident light through DTI304 is increased, and the sensitivity can be improved.

[0353] Furthermore, in DTI 304, since no separation structure is formed at the lattice intersection, it is similar to the second pixel separation structure, which can suppress the occurrence of overcurrent caused by the formation of excessively deep grooves.

[0354] (Fifth pixel separator structure)

[0355] Figure 28 A is a planar diagram showing the fifth pixel separation structure.

[0356] Figure 28 B is corresponding to Figure 28 A pixel cross-sectional view of the line segment passing through tap T in the dashed portion of A.

[0357] In the fifth pixel separation structure, DTI311 is formed. The planar shape of DTI311 is a lattice shape, and the lattice spacing is half (1 / 2) of the pixel spacing.

[0358] In other words, the DTI311 with the fifth pixel separation structure is Figure 24 The first pixel separation structure shown in the figure is DTI301 or Figure 26 The lattice spacing of the third pixel separation structure DTI303 shown in the figure becomes half of its separation structure. Therefore, DTI311 is formed at the boundary portion between pixels 51, and is also formed on the line that divides the rectangular pixel region into two in the vertical and horizontal directions.

[0359] and Figure 28 The pixel cross-section corresponding to the dashed line portion in A is in Figure 28 As shown in B, and similar to Figure 26 B.

[0360] Based on the fifth pixel separation structure, similar to the first pixel separation structure, crosstalk caused by infrared light incident on adjacent pixels 51 can be suppressed. Furthermore, similar to the third pixel separation structure, the convergence point of the incident light is the intersection of DTI311, and the diffraction of the incident light by DTI311 is increased. Therefore, sensitivity can be improved.

[0361] (Sixth pixel separator)

[0362] Figure 29 A is a planar diagram showing the sixth pixel separation structure.

[0363] Figure 29 B is corresponding to Figure 29 A pixel cross-sectional view of the line segment passing through tap T in the dashed portion of A.

[0364] In the sixth pixel separation structure, DTI312 is formed. DTI312 has no arrangement. Figure 28 The diagram shows the intersection structure of the fifth pixel separation structure, DTI311. Specifically, the planar shape of DTI312 is a lattice shape, and the lattice spacing is half (1 / 2) of the pixel spacing. Figure 29 As shown in B, the DTI312 is not arranged in the pixel boundary portion and pixel center portion corresponding to the lattice intersection point.

[0365] Based on the sixth pixel separation structure, similar to the first pixel separation structure, crosstalk caused by infrared light incident on adjacent pixels 51 can be suppressed. Furthermore, similar to the third pixel separation structure, the convergence portion of the incident light is the intersection of DTI312, and the diffraction of the incident light by DTI312 is increased. Therefore, sensitivity can be improved. In addition, because DTI312 is not formed at the lattice intersections, similar to the second pixel separation structure, overcurrent caused by forming excessively deep grooves can be suppressed.

[0366] (Pixel structure with added anti-reflective features)

[0367] In having Figures 24 to 29 In any of the first to sixth pixel separation structures shown, a fine uneven structure can be formed on the light incident surface of the substrate 61.

[0368] Figure 30 It is shown that in which there is Figure 24 The plan view and cross-sectional view of the pixel structure forming the concave-convex structure in the pixel 51 of the first pixel separation structure shown.

[0369] therefore, Figure 30 and Figure 24 They differ from each other only in whether the uneven portion 321 is formed on the light incident surface of the substrate 61, and are the same in all other portions.

[0370] like Figure 30 As shown in the plan view of A, the uneven portion 321 is formed in the region including the central portion of the pixel region. Figure 30 As shown in the cross-sectional view of B, for example, the uneven portion 321 has an inverted pyramid structure, wherein multiple square pyramid regions with vertices on the tap T side are regularly arranged. The base shape of each square pyramid is, for example, a square, and each square pyramid region is formed by excavating the substrate 61 to protrude towards the tap T side. It should be noted that the uneven portion 321 may have a regular pyramid structure in which multiple square pyramid regions with vertices on the side of the on-plate lens 62 (i.e., the light incident side) are regularly arranged. It should be noted that the vertices of the inverted pyramid structure or the front pyramid structure may have curvature and circular shapes.

[0371] exist Figure 30 In the example, the uneven part 321 has a structure in which the square pyramid shapes are arranged in a 3×3 configuration, but the size (square pyramid shape) of the repeating units and their number are arbitrary. Figure 30In the example, the uneven portion 321 is formed only near the center of the pixel area, but the uneven portion 321 can be formed in any area of ​​the light incident surface of the substrate 61, as long as the DTI 301 is not formed in that area. The uneven portion 321 can be formed on the entire light incident surface except for the portion of the DTI 301.

[0372] Although not shown, the uneven portion 321 may also be formed on a surface having Figures 25 to 29 On the light incident surface of the substrate 61 in any of the pixels 51 of the second to sixth pixel separation structures shown in the diagram.

[0373] The diffracted light from the incident light increases through the unevenness 321, creating a gradient in refractive index. This reduces reflection. Therefore, the amount of incident light for photoelectric conversion can be increased, thus improving sensitivity.

[0374] (Seventh pixel segmentation structure)

[0375] Figure 31 A is a planar diagram showing the seventh pixel separation structure.

[0376] Figure 31 B is corresponding to Figure 31 A pixel cross-sectional view of the line segment passing through tap T in the dashed portion of A.

[0377] In the seventh pixel separation structure, DTI331 is formed. (And...) Figure 24 Compared to the first pixel separation structure DTI 301, DTI 301 forms a barrier shared by two adjacent pixels 51 at the boundary portion between pixels 51, but Figure 31 The DTI 331 in the image forms a separate barrier for each pixel. As a result, as... Figure 31 As shown in B, DTI331 forms a double barrier between adjacent pixels.

[0378] like Figure 31 As shown in the plan view in A, along the boundary portion between pixels 51, the corners of the DTI331, which is formed into a rectangular shape, are chamfered so that the edges do not intersect each other at right angles and have a shape that does not form an intersection point at 90 degrees. Therefore, it is possible to suppress defects and damage that occur when forming the groove at the intersection and to suppress the generation of noise charge.

[0379] By using DTI 331, crosstalk caused by infrared light incident on adjacent pixels 51 can be suppressed. Furthermore, sensitivity can be improved because the infrared light separation characteristics between pixels can be enhanced.

[0380] (Pixel structure with added anti-reflective features)

[0381] The seventh pixel segmentation structure can also form an uneven structure.

[0382] Figure 32 It is in having Figure 31 The plan view and cross-sectional view show the uneven portion 321 formed in pixel 51 of the seventh pixel separation structure shown. Therefore, Figure 31 and Figure 32 They differ from each other only in whether the uneven portion 321 is formed on the light incident surface of the substrate 61, and are the same in other portions.

[0383] It should be noted that, Figure 30 The uneven portion 321 shown has a structure in which the quadrangular pyramidal shapes, as repeating units, are arranged in a 3×3 configuration, but in Figure 32 The uneven portion 321 shown has a structure in which the quadrangular pyramid shape is arranged in a 4×4 configuration.

[0384] Similarly, in the seventh pixel segmentation structure, by forming the uneven portion 321, the diffracted light of the incident light increases, and a refractive index gradient is formed. Therefore, reflection is reduced. Thus, the amount of incident light for photoelectric conversion can be increased, thereby improving sensitivity.

[0385] Note that DTI301, DTI302, DTI303, DTI304, DTI311, DTI312 and DTI331, shown as the first to seventh pixel separation structures described above, may additionally include a fixed charge film to cover the sidewalls and bottom surface of the DTI.

[0386] When adding a fixed charge film, the fixed charge film only needs to be formed on the sidewalls and bottom surface of the groove (trench) formed by excavating the substrate 61 to a predetermined depth from the back side of the light incident surface of the substrate 61 and then embedding it into an insulator. As the fixed charge film, a material (such as silicon) that can generate a fixed charge by deposition on the substrate 61 is preferably used to enhance pinning, and a high refractive index material film or a high dielectric film with a negative charge can be used. As a specific material, for example, an oxide or nitride containing at least one element selected from hafnium (Hf), aluminum (Al), zirconium (Zr), tantalum (Ta), and titanium (Ti) can be applied. Examples of film formation methods include chemical vapor deposition (hereinafter referred to as CVD), sputtering, and atomic layer deposition (hereinafter referred to as ALD). By using the ALD method, a SiO2 film with reduced interfacial state during film formation can be formed simultaneously to a thickness of about 1 nm. In addition to the materials mentioned above, examples of materials include oxides or nitrides containing at least one element: lanthanum (La), praseodymium (Pr), cerium (Ce), neodymium (Nd), praseodymium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), thulium (Tm), ytterbium (Yb), lutetium (Lu), and yttrium (Y). Furthermore, the fixed charge film can be composed of a hafnium oxynitride film or an aluminum oxynitride film.

[0387] Regarding the materials used in the fixed-charge film, silicon (Si) or nitrogen (N) can be added to the film, as long as it does not impair the insulating properties. The concentration should be appropriately determined within a range that does not compromise the film's insulation. As mentioned above, adding silicon (Si) or nitrogen (N) can improve the film's heat resistance and prevent ion implantation during the process.

[0388] By covering the sidewalls and bottom surface of the DTI with a fixed charge film, an inversion layer is formed on the surface in contact with the fixed charge film. Therefore, the silicon interface is pinned by the inversion layer, and thus the generation of dark current is suppressed. Suppression of dark current generation helps improve the sensitivity of pixel 51. Furthermore, when a recess is formed in the substrate 61, physical damage may occur on the sidewalls and bottom surface of the recess, and pinning deviation may occur in the peripheral portion of the recess. To address this problem, a fixed charge film with a large amount of fixed charge is formed on the sidewalls and bottom surface of the recess, preventing pinning deviation. When the fixed charge film is formed on the sidewalls and bottom surface of the DTI, the fixed charge film can be integrally and simultaneously formed with the fixed charge film 66 formed on the light incident surface side of the substrate 61.

[0389] (Eighth pixel segmentation structure)

[0390] Figure 33 A is a planar diagram showing the eighth pixel separation structure.

[0391] exist Figure 33 In the eighth pixel separation structure, such as in Figure 24 In the first pixel separation structure shown, DTI301 is arranged at the boundary portion between pixels 51. Figure 33 The planar diagram of the eighth pixel segmentation structure in A and Figure 24 The planar diagram of the first pixel separation structure shown in A is the same. It should be noted that in... Figure 33 In A, the omission is in Figure 24 The boundary lines between pixels 51 shown in A are used for description.

[0392] Figure 33 B is corresponding to Figure 33 A pixel cross-sectional view of the line segment passing through tap T in the dashed portion of A.

[0393] remove Figure 24 In addition to the structure of substrate 61 shown in A, Figure 33 B shows a portion of the multilayer wiring layer 111 formed on the front surface side of the substrate 61, an on-chip lens 62 formed on the rear surface side of the substrate 61, etc.

[0394] An inter-pixel light-shielding film 63, used to prevent crosstalk between adjacent pixels, is formed at the pixel boundary portion of the interface on the back side of the substrate 61. Similar to DTI 301, the inter-pixel light-shielding film 63 is also formed in a lattice shape to surround the periphery of the pixel 51. A planarization film 341 is formed on the lower surface of the on-chip lens 62 on the pixel center side of the inter-pixel light-shielding film 63. The planarization film 341 may be made of, for example, an inorganic film, such as an oxide film (SiO2), a nitride film (SiN), an oxynitride film (SiON), or a silicon carbide film (SiC). Alternatively, the planarization film 341 may be made of an organic material such as resin and have a filtering function that transmits only light with a predetermined wavelength.

[0395] Lens separators 342 are formed on the upper surface of the inter-pixel light-shielding film 63 at the pixel boundary portions between pixels 51, separating the on-chip lenses 62 formed for each pixel 51 from each other. The material of the lens separators 342 can be, for example, a metallic material such as tungsten (W), aluminum (Al), copper (Cu), or titanium (Ti). Furthermore, a planarization film 343 is formed on the on-chip lens 62 such that the upper surface of the on-chip lens 62 is flat at the same height as the lens separators 342. The planarization film 343 can also be made of, for example, an inorganic film, such as an oxide film (SiO2), a nitride film (SiN), an oxynitride film (SiON), or silicon carbide (SiC).

[0396] Here, when the refractive index of the planarization film 343 is represented by n0, the refractive index of the on-chip lens 62 is represented by n1, and the refractive index of the lens separator 342 is represented by n2, the refractive indices n0, n1, and n2 have a relationship of n2 < n0 < n1. The planarization film 343 with refractive index n0 is composed of a film having a higher N (nitrogen) or C (carbon) density than the lens separator 342 with refractive index n2. The on-chip lens 62 with refractive index n1 is composed of a film having a higher N (nitrogen) or C (carbon) density than the planarization film 343 with refractive index n0.

[0397] A multilayer wiring layer 111, including metal films M1 to M3, is formed on the front surface side of the substrate 61. The arrangement and reference of the multilayer wiring layer 111 are as follows. Figures 18 to 23 The detailed configurations described are similar, therefore, their descriptions are omitted. It should be noted that in... Figures 33 to 37 In the multilayer wiring layer 111, there are no contacts for applying voltage MIX_A or MIX_B to the P+ semiconductor region 73, which is a voltage application unit, or contacts for connecting the N+ semiconductor region 71, which is a charge detection unit, to the FD portion (FD122).

[0398] and Figure 24 Compared to the first pixel separation structure shown, the eighth pixel separation structure configured as described above has a newly added lens separation portion 342, which is formed in the same layer as the on-chip lens 62 and separates the on-chip lenses 62 formed for each pixel 51 from each other.

[0399] Based on the eighth pixel separation structure, similar to the first pixel separation structure, the DTI301 formed at the pixel boundary can suppress crosstalk caused by infrared light incident on adjacent pixels 51, and can improve sensitivity. Furthermore, the lens separation portion 342 prevents light reflected from the metal film M1 of the multilayer wiring layer 111 from leaking to adjacent pixels, such as... Figure 33 The incident light F1 is shown in B.

[0400] (Modification of the eighth pixel segmentation structure)

[0401] Figure 34 A is a pixel cross-sectional view showing a first variant of the eighth pixel separation structure.

[0402] Figure 34 B is a pixel cross-sectional view showing a second variation of the eighth pixel separation structure.

[0403] exist Figure 34In the first variation of A, a reflection suppression film 351 that suppresses the reflection of incident light is newly added to the upper part of the lens separation portion 342 that separates the on-chip lenses 62 from each other, and the combined height of the lens separation portion 342 and the reflection suppression film 351 is the same as the height of the planarization film 343.

[0404] The reflection suppression film 351 may be composed of an inorganic film such as an oxynitride film (SiON), a carbonitride film (SiCN), a nitride film (SiN), silicon nitride (Si3N4) or silicon carbide (SiC), or a metal film such as tungsten (W).

[0405] Using the reflection suppression film 351, for example, in Figure 33 In the eighth pixel separation structure, light diffraction that has already struck the upper part of the lens separator 342 and leaked to adjacent pixels can be suppressed. Therefore, crosstalk can be suppressed and sensitivity can be improved.

[0406] exist Figure 34 In the second variation, the cross-sectional shape of the lens separator 342 that separates the on-chip lenses 62 is approximately trapezoidal. Specifically, the area of ​​the upper surface of the lens separator 342 on the incident light side is smaller than the area of ​​the lower surface on the substrate 61 side, and the sidewalls of the lens separator 342 are inclined to face the incident light side. Therefore, the area of ​​the upper surface of the planarization film 343 is larger than the area of ​​the lower surface of the on-chip lens 62.

[0407] As described above, by making the side cross-sectional shape of the lens separator 342 such that the area of ​​the upper surface is smaller than the area of ​​the bottom surface, and... Figure 34 Similar to the incident light F2 shown in Figure B, light with a wider angle can also be introduced into the substrate 61. Therefore, the sensitivity of pixel 51 can be improved.

[0408] In the aforementioned eighth pixel separation structure, the on-chip lens 62, the inter-pixel light-shielding film 63, the lens separation portion 342, etc., formed on the incident surface (back side) side of the substrate 61 can be arranged to perform pupil correction.

[0409] That is, because the incident angle of the principal ray of the incident light from the optical lens (not shown) is 0 degrees (vertical) at the center of the pixel array unit 20, pupil correction is not required, and as... Figure 33 As shown in B, the center of the on-chip lens 62 coincides with the center of the pixel area of ​​the substrate 61.

[0410] Simultaneously, in the peripheral portion (outer periphery) of the pixel array unit 20, since the incident angle of the principal ray of the incident light from the optical lens is a predetermined angle according to the lens design, pupil correction is performed. That is, as... Figure 35As shown in A and B, the center of the on-chip lens 62 is offset from the center of the pixel region of the substrate 61 toward the center of the pixel array unit 20. The offset between the center position of the on-chip lens 62 and the center position of the pixel region of the substrate 61 increases as it gets closer to the outer periphery of the pixel array unit 20.

[0411] Then, based on the offset of the on-chip lens 62, as it gets closer to the outer periphery of the pixel array unit 20, the position of the lens separator 342 also shifts towards the center. Furthermore, the offset of the inter-pixel light-shielding film 63 is smaller than the offset of the lens separator 342 because the inter-pixel light-shielding film 63 is closer to the substrate 61 than the lens separator 342.

[0412] As described above, by arranging the on-chip lens 62, the inter-pixel light-shielding film 63, the lens separator 342, etc. on the incident surface side of the substrate 61 to perform pupil correction, the decrease in sensitivity and charge distribution modulation caused by the difference in the incident angle of the main light rays on the outer periphery of the pixel array unit 20 can be suppressed, and in-plane variation can be suppressed.

[0413] (Ninth pixel segmentation structure)

[0414] Figure 36 This is a planar diagram showing the ninth pixel's separation structure.

[0415] exist Figure 36 In the ninth pixel segmentation structure, it is formed in Figure 24 In the first pixel separation structure shown, the DTI 301 at the boundary between pixels 51 is replaced by the inter-pixel groove 371 that penetrates the substrate 61. Figure 33 The lens separator 342 is not formed on the upper surface of the inter-pixel light-shielding film 63, and the on-chip lens 62 is formed in the entire pixel area in the planar direction, so that the on-chip lenses 62 of adjacent pixels are in contact with each other.

[0416] The inter-pixel trench portion 371 is formed by forming a trench from the rear surface side or the front surface side of the substrate 61 to penetrate the substrate 61 and reach the substrate surface on the opposite side, and embedding, for example, a silicon oxide insulating film into the trench. In addition to an insulating film such as silicon oxide, the material to be embedded in the trench as the inter-pixel trench portion 371 can be, for example, a metallic material such as tungsten (W), aluminum (Al), titanium (Ti), or titanium nitride (TiN) or polycrystalline silicon.

[0417] By forming this inter-pixel trench 371, the taps T of adjacent pixels formed in the shared tap structure can be completely electrically separated from each other. Therefore, as Figure 36 The incident light F3 shown in the figure can prevent the incident light from traveling into adjacent pixels 10, suppress crosstalk, and improve sensitivity.

[0418] (A variation of the ninth pixel segmentation structure)

[0419] Figure 37 A is a pixel cross-sectional view showing a first variant of the ninth pixel separation structure.

[0420] exist Figure 37 In the first variation of A, the inter-pixel trench portion 371 is formed so that it does not reach the substrate surface on the surface side of the substrate 61, but contacts the shallow groove portion 381 formed on the front surface side of the substrate 61, and the groove portion 381 and the inter-pixel trench portion 371 are combined to completely electrically separate the pixels of the substrate 61 from each other. The groove portion 381 and its adjacent separating portion 75 are formed by, for example, shallow trench separation (STI).

[0421] When a trench to be a pixel trench 371 is formed from the back side of the substrate 61 to the vicinity of the substrate surface on the front side of the substrate 61 by means of plasma etching or the like, the groove portion 381 serves as a stop. By forming the groove portion 381 as an insulating layer, damage to the multilayer wiring layer 111 can be prevented during trench formation via contacts formed in the nearby P+ semiconductor region 73.

[0422] Figure 37 B is a pixel cross-sectional view showing a second variation of the ninth pixel separation structure.

[0423] Figure 37 The second variation of B shares the same characteristics as the first variation in that the inter-pixel groove portion 371 and the recess portion 381 are formed at the pixel boundary portion of the substrate 61, and the inter-pixel groove portion 371 and the recess portion 381 completely electrically separate the pixels of the substrate 61 from the back side to the front side of the substrate 61.

[0424] on the other hand, Figure 37 Variation of B in Example 2 and Figure 37 The difference between Modification 1 and Modification 2 is that, in Modification 1, the planar dimensions of the inter-pixel trench portion 371 and the recess portion 381 are approximately the same, while in Modification 2, the planar dimension of the recess portion 381 is larger than the planar dimension of the inter-pixel trench portion 371. Therefore, when the trench to be the inter-pixel trench portion 371 is formed from the back side of the substrate 61 to near the substrate surface on the front side of the substrate 61, it is possible to suppress the trench from deviating from the formation position of the recess portion 381 and allow the trench formation position to vary to a certain extent in the planar direction.

[0425] Furthermore, in the first and second modifications, since the inter-pixel trench portion 371 and the recess portion 381 completely electrically separate the pixels of the substrate 61 from the back side to the front side of the substrate 61, it is possible to prevent incident light from traveling into adjacent pixels 10, suppress crosstalk, and improve sensitivity.

[0426] (Tenth pixel separator structure)

[0427] Figure 38 A is a pixel cross-sectional view showing the tenth pixel separation structure, and is corresponding to Figure 39 A cross-sectional view of the dashed section of A-A'.

[0428] Figure 38 B is a pixel cross-sectional view showing the tenth pixel separation structure, and is corresponding to Figure 39 A cross-sectional view of the dashed section of B-B'.

[0429] Figure 39 It shows Figure 38 A planar view of the pixel cross-section in the cross-sectional direction. For example... Figure 39 As shown, DTI301 is formed into a lattice shape at the pixel boundary to surround the periphery of pixel 51. It should be noted that... Figure 36 The planar arrangement of the inter-pixel groove portion 371 in the ninth pixel separation structure shown in the figure is also consistent with... Figure 39 The plan layout is the same as that of DTI 301.

[0430] exist Figure 38 In the tenth pixel separation structure, the arrangement in the substrate 61 and the arrangement on the back side of the substrate 61 on which the on-chip lens 62 is formed are similar to those in the tenth pixel separation structure. Figure 24 The configuration of the first pixel separation structure shown is similar, so its description will be omitted.

[0431] Meanwhile, contacts 391 and 392 are formed in the multilayer wiring layer 111 on the front surface side of the substrate 61. Contact 391 is an electrode for applying voltage MIX_A or MIX_B to the P+ semiconductor region 73, and contact 392 is an electrode for transferring charge accumulated in the N+ semiconductor region 71 to FD122. Contacts 391 and 392 are connected to the metal film M1, which is the first layer of the multilayer wiring layer 111, at different locations.

[0432] As shown in DTI 301, the contact 391, which serves as an electrode for applying voltage MIX_A or MIX_B to the P+ semiconductor region 73, is formed linearly along the pixel boundary line. Figure 38 As shown in B. For the planar arrangement of contact 391, as... Figure 41 As shown in the plan view of A, contact 391 is formed in relation to Figure 39 The dashed lines of B-B' are longer in the same direction.

[0433] As described above, the contact 391, which serves as an electrode for applying voltage MIX_A or MIX_B to the P+ semiconductor region 73, is formed linearly along the pixel boundary line between the back surface interface of the substrate 61 and the metal film M1. Therefore, as... Figure 38 The incident light F4 shown in A forms a light-shielding wall and can prevent light incident on the pixel boundary or light reflected by the metal film M1 from leaking into adjacent pixels.

[0434] (Modification of the 10th pixel segmentation structure)

[0435] Figure 40 A is a pixel cross-sectional view showing a modified example of the tenth pixel separation structure, and is corresponding to Figure 39 A cross-sectional view of the dashed section of A-A'.

[0436] Figure 40 B is a pixel cross-sectional view showing a modified example of the tenth pixel separation structure, and is corresponding to Figure 39 A cross-sectional view of the dashed section of B-B'.

[0437] exist Figure 40 In a modified example, a recess 381 formed by STI or the like is formed in the center of the P+ semiconductor region 73 on the surface side of the substrate 61. Then, in Figure 38 The contact 391 shown for applying voltage MIX_A or MIX_B to the P+ semiconductor region 73 is formed as a wider contact 391' in the direction of the two taps T connecting the shared tap structure (the direction of the dashed line A-A'), so as to... Figure 40 In a modified example, the region other than the recessed portion 381 is connected to the P+ semiconductor region 73.

[0438] like Figure 40 As shown in B, similar to contact 391', groove 381 is also formed in a straight line along pixel boundary line.

[0439] Figure 41 A is shown Figure 38 A plan view of the planar arrangement of contact 391 in the tenth pixel separation structure shown.

[0440] Figure 41 B is shown Figure 40 A plan view of the planar arrangement of contact 391' in a modified example of the tenth pixel separation structure shown.

[0441] exist Figure 41 In A and B, the dashed line boundary represents the boundary line between pixels 51.

[0442] Because contact 391' is formed to be wider in the direction of the two taps T connecting the shared tap structure, contact 391' is set in a cross shape that intersects with the line along the pixel boundary line.

[0443] (Eleventh pixel segmentation structure)

[0444] Figure 42 It shows a pixel cross-sectional view of the eleventh pixel separation structure, and is corresponding to Figure 39 A cross-sectional view of the dashed section of A-A'.

[0445] exist Figure 42 In the eleventh pixel segmentation structure, used to... Figure 38 The contact 391 of the P+ semiconductor region 73 where the voltage MIX_A or MIX_B is applied in the tenth pixel separation structure is changed to a structure similar to the gate electrode (i.e., contact 401, polysilicon 402, and gate insulating film 403) of each of the plurality of pixel transistors Tr that control the first tap TA or the second tap TB.

[0446] By sharing the structure of the contact used to apply voltage MIX_A or MIX_B to the P+ semiconductor region 73 with the gate electrode structure of each of the multiple pixel transistors Tr that control the first tap TA or the second tap TB, the manufacturing process is stable and conduction failures can be reduced.

[0447] Note that along the corresponding Figure 39 In the direction of the pixel boundary line of the dashed portion of B-B', the pixel cross-sectional structure of the contact 401, polysilicon 402, and gate insulating film 403 in the eleventh pixel separation structure can be as follows: Figure 38 It can be formed as a linear shape along the pixel boundary line, like B in the image, or it can be formed as a circular shape similar to normal contact.

[0448] Moreover, in the eleventh pixel segmentation structure, and in Figure 42 Similar to the incident light F5 shown, it can prevent light incident on the pixel boundary or light reflected by the metal film M1 from leaking into adjacent pixels.

[0449] (Twelfth pixel segmentation structure)

[0450] Figure 43 This is a pixel cross-sectional view showing the twelfth pixel separation structure, and it corresponds to... Figure 39 A cross-sectional view of the dashed section of A-A'.

[0451] Figure 43 The twelfth pixel separation structure includes: a lens separator 342 that separates adjacent on-chip lenses 62 from each other, including... Figure 33In the eighth pixel separation structure shown; the inter-pixel trench 371 penetrates the substrate 61 and includes... Figure 36 In the ninth pixel separation structure shown; and contact 391', which is formed to be wider in the direction connecting the two taps T, including Figure 40 In the variant of the tenth pixel separator structure shown.

[0452] also, Figure 43 The twelfth pixel separation structure includes a reflective member 411 that reflects infrared light between its interface on the front surface side of the substrate 61 and the metal film M1, which is the first layer of the multilayer wiring layer 111. The reflective member 411 can be formed from metallic materials such as tungsten (W), aluminum (Al), copper (Cu), or titanium (Ti), or utilizes structures that reflect or shield light, such as polysilicon or oxide films. The reflective member 411 can be formed using the same material (e.g., polysilicon) as the gate electrode of each of the plurality of pixel transistors Tr, which control a first tap TA or a second tap TB at the same substrate depth as the gate electrode.

[0453] According to the twelfth pixel separation structure, by forming a lens separation portion 342 and an inter-pixel groove portion 371 at the pixel boundary, light incident on pixel 51 can be prevented from leaking to adjacent pixels.

[0454] Furthermore, by forming a contact 391' linearly formed along the pixel boundary line at a depth position between the interface on the surface side of the substrate 61 and the metal film M1, light leakage to adjacent pixels in the multilayer wiring layer 111 can be prevented.

[0455] When the incident light is efficiently confined within the substrate 61 by the lens separator 342, the inter-pixel groove 371, and the contact 391', it is like... Figure 43 The incident light F6 shown is enhanced by the reflective member 411 of the multilayer wiring layer 111, thereby further improving the sensitivity.

[0456] In the multilayer wiring layer 111, the wiring layout of the five-layer metal films M1 to M5 can be freely determined by arranging the dedicated reflective member 411 separately from the five-layer metal films M1 to M5.

[0457] It should be noted that the inter-pixel groove portion 371 can be replaced by a combination of the inter-pixel groove portion 371 and the recess portion 381, which is consistent with the... Figure 37 The modification of the ninth pixel separation structure shown in A and B is the same.

[0458] (Thirteenth pixel segmentation structure)

[0459] Figure 44A is a pixel cross-sectional view showing the thirteenth pixel separation structure, and is corresponding to Figure 45 A cross-sectional view of the dashed section of A-A'.

[0460] Figure 44 B is a pixel cross-sectional view showing the thirteenth pixel separation structure, and is related to... Figure 45 The cross-sectional view corresponding to the dashed part of B-B'.

[0461] Figure 44 The thirteenth pixel segmentation structure in the image has the following structure, wherein, in Figure 38 In the tenth pixel separation structure shown, the DTI301 formed at the pixel boundary portion is replaced by a conductive material 421 and an insulating film 422. The conductive material 421 penetrates the substrate 61 from the back side or front surface side to the opposite side of the substrate surface, and the insulating film 422 is formed on its two outer sides. The conductive material 421 and the insulating film 422 are pixel separation portions that completely electrically separate the pixels of the substrate 61 from each other. The conductive material 421 is made of a metallic material such as polycrystalline silicon or tungsten (W). The insulating film 422 includes, for example, SiO2. A contact 423, which connects the metal film M1, which serves as the first layer, and the conductive material 421 to each other, is connected to the conductive material 421.

[0462] The contact 423, conductive material 421, and insulating film 422 configured as described above have the same structure as the gate electrode of the vertical pixel transistor Tr, wherein the gate electrode is embedded in the substrate depth direction, and a voltage MIX_A or MIX_B is applied from the contact 423 directly connected to the conductive material 421. That is, as the tap driving unit 21 applies voltage MIX_A to the P+ semiconductor region 73-1 of the first tap TA and applies voltage MIX_B to the P+ semiconductor region 73-2 of the second tap TB, voltage MIX_A is applied to the conductive material 421 on the first tap TA side and to the conductive material 421 on the second tap TB side. Therefore, an electric field is generated in the substrate 61, and electrons generated by photoelectric conversion move to the P+ semiconductor region 73-1 or P+ semiconductor region 73-2.

[0463] According to the thirteenth pixel separation structure described above, since the conductive material 421 and the insulating film 422 penetrating the substrate 61 completely electrically separate the pixels of the substrate 61 from each other, incident light can be prevented from traveling into adjacent pixels 10, and crosstalk can be suppressed. Furthermore, by applying a predetermined voltage MIX_A or MIX_B from the contact 423 to the conductive material 421, an electric field is applied to the back side of the substrate 61, which increases the modulation level and improves sensitivity.

[0464] Figure 45 It is shown Figure 44A plan view showing the planar arrangement of the inter-pixel groove portion 371 shown in B.

[0465] In the thirteenth pixel separation structure, the inter-pixel trench 371 is not formed near the conductive material 421 and insulating film 422 to which voltages MIX_A or MIX_B are applied. Therefore, as Figure 44 and Figure 45 As shown in B, the inter-pixel groove portion 371 is formed at the pixel boundary portion except for the tap T of each pixel 51.

[0466] (Fourteenth pixel segmentation structure)

[0467] Figure 46 A is a pixel cross-sectional view showing the fourteenth pixel separation structure, and is corresponding to Figure 39 A cross-sectional view of the dashed section of A-A'.

[0468] exist Figure 46 In the fourteenth pixel segmentation structure of A, with Figure 38 Compared to the tenth pixel separation structure shown, the contact 391 where a voltage MIX_A or MIX_B is applied to the P+ semiconductor region 73 is changed to a contact 401, polysilicon 402, and gate insulating film 403 serving as the gate electrode structure of the planar pixel transistor Tr. Furthermore, the DTI 301 formed at the pixel boundary portion in the substrate 61 is changed to an inter-pixel trench 371 penetrating the substrate 61. Other structures are similar to... Figure 38 The tenth pixel separation structure is similar. The planar arrangement of the inter-pixel groove 371 is similar to that in [the text]. Figure 39 The plan layout of DTI 301 is shown.

[0469] According to the fourteenth pixel separation structure, since the inter-pixel trench portion 371 completely electrically separates the pixels of the substrate 61 from each other, it can prevent incident light from traveling into adjacent pixels 10, suppress crosstalk, and improve sensitivity.

[0470] Furthermore, the control terminal for applying voltage MIX_A or MIX_B to the P+ semiconductor region 73 has a gate electrode structure of a planar pixel transistor Tr. Therefore, the current flowing between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2 can be suppressed, and thus current consumption can be reduced.

[0471] (A variation of the fourteenth pixel segmentation structure)

[0472] Figure 46 B is a pixel cross-sectional view showing a modified example of the fourteenth pixel separation structure, and is corresponding to Figure 39 A cross-sectional view of the dashed section of A-A'.

[0473] Figure 46The modified example in B has the following structure: wherein, the metal film M1, which serves as the first layer, is... Figure 44 In Figure A, the contacts 423 connecting the conductive material 421 of the thirteenth pixel separator structure are replaced with contacts 401, polysilicon 402, and gate insulating film 403, which serve as the gate electrode structure of the planar pixel transistor Tr. The polysilicon 402 is connected to the conductive material 421 in the substrate 61 and has a gate electrode structure in which the gate electrode is embedded in the vertical pixel transistor Tr in the depth direction of the substrate. Other structures are similar to... Figure 44 The thirteenth pixel segmentation structure shown is similar.

[0474] It should be noted that, similar to Figure 44 The thirteenth pixel separation structure shown in the figure has inter-pixel grooves 371 formed at the pixel boundary portion of each pixel 51 except near the tap T, and the planar arrangement of the inter-pixel grooves 371 is similar to Figure 45 The floor plan layout.

[0475] According to the variation of the fourteenth pixel separation structure, since the conductive material 421 and the insulating film 422 penetrating the substrate 61 completely electrically separate the pixels of the substrate 61 from each other, it is possible to prevent incident light from traveling into adjacent pixels 10 and suppress the occurrence of crosstalk.

[0476] Furthermore, the control terminal for applying voltage MIX_A or MIX_B to the P+ semiconductor region 73 has a gate electrode structure of a vertical pixel transistor Tr. Therefore, the current flowing between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2 can be suppressed, and thus current consumption can be reduced.

[0477] Furthermore, since a predetermined voltage MIX_A or MIX_B is applied to the back side of the substrate 61 through the conductive material 421 and the insulating film 422 penetrating the substrate 61, the potential can be modulated to the back side of the substrate 61, and the modulation efficiency can be enhanced.

[0478] Reference Figures 33 to 46 Each configuration of the described eighth to fourteenth pixel separation structure can employ any combination of pixel structures.

[0479] 9. Method for manufacturing on-plate lenses and lens separators

[0480] Next, we will refer to Figures 47 to 51 Description in Figure 33 The method used in the eighth pixel separation structure and other components for manufacturing the on-chip lens 62 and lens separation portion 342.

[0481] (First manufacturing method for lens separator)

[0482] First, refer to Figure 47 and Figure 48 A first method for manufacturing an on-chip lens 62 and a lens separator 342 is described.

[0483] like Figure 47 As shown in Figure A, DTI301 is formed from the back side at the pixel boundary portion of substrate 61. N+ semiconductor region 71 and P+ semiconductor region 73 are formed as taps T (first tap TA or second tap TB). Separator 75, oxide film 64, etc. are formed on the front side of substrate 61, and then a multilayer wiring layer 111 (including five metal films M1 to M5, contacts, etc.) is formed. Subsequently, inter-pixel light-shielding film 63 and planarization film 341 are formed on the upper surface of the back side of substrate 61.

[0484] Next, as Figure 47 As shown in B, a film for forming the lens separator 342, a separator material 342A, is formed on the upper side of the inter-pixel light-shielding film 63 and the planarization film 341. Then, a photoresist 441 is formed and patterned according to the formation position of the lens separator 342. As described above, the separator material 342A can be, for example, a metallic material that is advantageous for shielding light with long wavelengths, such as tungsten (W), aluminum (Al), copper (Cu), or titanium (Ti).

[0485] Next, as Figure 47 As shown in C, the spacer material 342A is etched according to the patterned photoresist 441 to form the lens spacer 342.

[0486] Next, as Figure 47 As shown in D, a lens material film 62A for forming the on-chip lens 62 is conformally formed on the upper surface of the lens separation portion 342.

[0487] Next, as Figure 48 As shown in Figure A, the lens material 62A is flattened by chemical mechanical polishing (CMP) and then heat-treated (reflowed) to form a shape as shown in Figure A. Figure 48 The spherical on-plate lens 62 shown in B.

[0488] Next, as Figure 48 As shown in Figure C, material 343A forms the planarization film 343 to cover the on-plate lens 62 and the lens separator 342, and is planarized by CMP. As a result, the planarization is completed. Figure 33 The eighth pixel separation structure shown is as follows: Figure 48 As shown in D.

[0489] (A variation of the first manufacturing method)

[0490] In formation Figure 47 D, Figure 48 A and Figure 48 In the steps of the spherical on-plate lens 62 described in section B, the following method can also be used.

[0491] For example, such as Figure 49 As shown in Figure A, the lens material 62A is planarized to the same thickness as the lens partition 342, and then, as... Figure 49 As shown in Figure B, photoresist 442 is formed on the upper surface of lens material 62A and then heat-treated. As a result, as... Figure 48 As shown in C, photoresist 442 is formed into a spherical shape.

[0492] Then, the photoresist 442, formed into spherical shapes, is selectively etched, as... Figure 49 As shown in D, the spherical shape of photoresist 442 is transferred to lens material 62A to form an on-film lens 62.

[0493] According to the reference Figure 49 The described lens forming method allows the on-chip lens 62 to be formed at a lower temperature because the lens shape of the on-chip lens 62 is formed using photoresist 442.

[0494] Alternatively, the lens 62 on the spherical sheet can be formed as follows.

[0495] like Figure 50 As shown in Figure A, the lens material 62A is formed as a flat surface, and its film thickness is thicker than that of the lens separator 342. Then, on the upper surface of the lens material 62A, a photoresist 451 is patterned at a planar position that does not overlap with the lens separator 342, and the lens material 62A is etched until the lens separator 342 is exposed. Figure 50 As shown in B.

[0496] Subsequently, through heat treatment, the lens material 62A is formed as shown. Figure 50 The on-chip lens 62 is formed as shown in C, and the lens material 62A is selectively etched into a spherical shape. Therefore, the on-chip lens 62 is formed as shown in C. Figure 50 As shown in D.

[0497] According to the reference Figure 50 The described lens forming method, because the on-chip lens 62 is formed by etching lens material 62A, enhances the stability of the lens shape compared to the case where the lens shape of the on-chip lens 62 is formed with photoresist 442. Figure 49 As shown in the image.

[0498] (Second manufacturing method for the lens separator)

[0499] Next, we will refer to Figure 51 A second method for manufacturing an on-chip lens 62 and a lens separator 342 is described.

[0500] First, such as Figure 51 As shown in A, the on-chip lens 62 is formed on the upper side of the inter-pixel light-shielding film 63 and the planarization film 341 formed on the back side of the substrate 61 by forming a film of lens material 62A, patterning according to the lens formation position, and forming a spherical shape by heat treatment.

[0501] Next, as Figure 51 As shown in B, the material 343A forming the planarization film 343 is such that it has the same thickness as the on-chip lens 62, and is planarized by CMP.

[0502] Next, as Figure 51 As shown in C, in material 343A, which forms a flat planarization film 343, the portion therein where the lens separator 342 is formed is removed by etching. As a result, the planarization film 343 is completed.

[0503] Next, as Figure 51 As shown in Figure D, a membrane of a separating portion material 342A, such as tungsten (W) or aluminum (Al), is formed in the opening portion of the planarized membrane 343 using an atomic layer deposition (ALD) method or similar method with good embedding properties. Then, as... Figure 51 As shown in E, the separating material 342A is flattened by CMP, thereby forming the lens separating portion 342. As a result, the lens separating portion 342 is completed. Figure 33 The eighth pixel separation structure shown. When copper (Cu) is used as the material for the lens separator 342, the lens separator 342 can be formed by an electroplating process.

[0504] The on-plate lens 62 and the lens separator 342 can be formed as described above.

[0505] 10. Example of substrate structure for a light receiving device

[0506] Figure 1 The optical receiver 1 can be adopted Figure 52 The substrate is configured with any one of A to C.

[0507] Figure 52 A shows an example of an optical receiving device 1 including a semiconductor substrate 511 and a support substrate 512 located below the semiconductor substrate 511.

[0508] In this case, a pixel array region 551 corresponding to the pixel array unit 20, a control circuit 552 for controlling each pixel of the pixel array region 551, and a logic circuit 553 including a signal processing circuit for detecting signals are formed on the upper semiconductor substrate 511.

[0509] The control circuit 552 includes the vertical drive unit 22 and the horizontal drive unit 24 described above. The logic circuit 553 includes: a column processing unit 23, which performs AD conversion processing of detection signals, etc.; and a signal processing unit 31, which performs distance calculation processing, calibration processing, etc., to calculate the distance from the ratio between detection signals obtained from two or more taps T in the pixel.

[0510] Or, such as Figure 52 As shown in B, the light receiving device 1 may have a configuration in which a first semiconductor substrate 521 on which a pixel array region 551 and a control circuit 552 are formed, and a second semiconductor substrate 522 on which a logic circuit 553 is formed, are stacked. Note that the first semiconductor substrate 521 and the second semiconductor substrate 522 are electrically connected to each other, for example, by through-holes or Cu-Cu metal bonding.

[0511] Alternatively, such as Figure 52 As shown in Figure C, the light receiving device 1 may have a configuration in which a first semiconductor substrate 531, which forms only pixel array regions 551, is stacked with a second semiconductor substrate 532, on which a region control circuit 554 is formed. In the region control circuit 554, a control circuit for controlling each pixel and a signal processing circuit for processing detection signals are arranged in units of one pixel or in units of regions of multiple pixels. The first semiconductor substrate 531 and the second semiconductor substrate 532 are electrically connected to each other, for example, through-holes or Cu-Cu metal bonding.

[0512] According to Figure 52 The configuration of the control circuit and signal processing circuit in the light receiving device 1 of C, arranged on a pixel-by-pixel or region-by-region basis, allows for setting optimal drive timing and gain for each segmented control unit, and enables the acquisition of optimal distance information regardless of distance and reflectivity. Furthermore, since distance information can be calculated by driving only a portion of the pixel array region 551 instead of the entire surface, power consumption can be suppressed according to the operating mode.

[0513] 11. Configuration Example of Distance Measurement Module

[0514] Figure 53 This is a block diagram illustrating a configuration example of a ranging module that uses optical receiver 1 to output ranging information.

[0515] The distance measurement module 600 includes a light-emitting unit 611, a light-emitting control unit 612, and a light-receiving unit 613.

[0516] The light-emitting unit 611 includes a light source that emits light with a predetermined wavelength and emits illumination light with periodically changing brightness to illuminate an object. For example, the light-emitting unit 611 includes a light-emitting diode as a light source that emits infrared light with a wavelength in the range of 780 nm to 1000 nm and generates illumination light synchronously with a rectangular wave light emission control signal CLKp provided from the light-emitting control unit 612.

[0517] Note that the light emission control signal CLKp is not limited to a rectangular wave; it only needs to be a periodic signal. For example, the light emission control signal CLKp can be a sine wave.

[0518] The light-emitting control unit 612 provides a light-emitting control signal CLKp to the light-emitting unit 611 and the light-receiving unit 613, and controls the timing of the illumination light. The light-emitting control signal CLKp has a frequency of, for example, 20 MHz. Note that the frequency of the light-emitting control signal CLKp is not limited to 20 MHz, and can also be 5 MHz, etc.

[0519] The light receiving unit 613 receives reflected light from the object, calculates the distance information of each pixel based on the light receiving results, generates a depth image (where the distance to each pixel is represented by a gray value), and outputs the depth image.

[0520] The aforementioned light receiving device 1 is used as a light receiving unit 613, and the light receiving device 1, as a light receiving unit 613, calculates the distance information of each pixel based on the signal intensity detected by the charge detection unit (N+ semiconductor region 71) of each of the first tap TA and the second tap TB of each pixel 51 of the pixel array unit 20, for example, based on the light emission control signal CLKp.

[0521] As mentioned above, Figure 1 The light receiving device 1 can be integrated as the light receiving unit 613 of the distance measurement module 600, which obtains distance information via an indirect ToF method and outputs the distance information to the object. By employing each of the above-described configuration examples of the light receiving device 1 as the light receiving unit 613 of the distance measurement module 600, such as a light receiving device in which four vertical signal lines (VSLs) are wired for each pixel column, the resolution and readout speed of the distance measurement module 600 can be improved.

[0522] As described above, according to this technology, the distance measurement characteristics of the light receiving device used as a CAPD sensor can be improved.

[0523] Note that in this technology, the aforementioned tap structure and vertical signal lines (VSLs) can be arbitrarily combined. For example, the optical receiving device 1 can employ a shared tap structure or a non-shared tap structure for a configuration in which four vertical signal lines (VSLs) are arranged for each pixel column. Furthermore, pixels with shared tap structures or non-shared tap structures can be arbitrarily combined with the first to seventh pixel separation structures.

[0524] Furthermore, examples of using electrons as signal carriers have already been described above. However, holes generated through photoelectric conversion can be used as signal carriers. In this case, it is only necessary to construct a charge detection unit for detecting signal carriers using a P+ semiconductor region, a voltage application unit for generating an electric field in the substrate using an N+ semiconductor region, and detect holes as signal carriers in the charge detection unit disposed in the tap T.

[0525] 12. Examples of Applications of Moving Objects

[0526] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on any type of mobile body (such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, aircraft, drones, ships, or robots).

[0527] Figure 54 This is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to this disclosure can be applied.

[0528] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 54 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as part of the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0529] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device that generates drive force for a vehicle such as an internal combustion engine or a drive electric motor, a drive force transmission mechanism that transmits drive force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates braking force for the vehicle.

[0530] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn indicators, and fog lights. In this case, radio waves or signals from various switches sent from a portable device that replaces keys can be input to the body system control unit 12020. The body system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0531] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the images. The vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing, such as detecting people, vehicles, obstacles, signs, characters on the road surface, etc., based on the received images.

[0532] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output the electrical signal as an image or as ranging information. In addition, the light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0533] The vehicle interior information detection unit 12040 detects information inside the vehicle. A driver state detection unit 12041, etc., for detecting the driver's state is connected to the vehicle interior information detection unit 12040. The driver state detection unit 12041 may be, for example, a camera that captures images of the driver. The vehicle interior information detection unit 12040 can calculate the driver's fatigue level or concentration level, or it can determine whether the driver is drowsy based on the detection information input from the driver state detection unit 12041.

[0534] The microcomputer 12051 can calculate control target values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, distance-based following, speed maintenance, collision warning, lane departure warning, etc.

[0535] In addition, the microcomputer 12051 controls the drive force generating device, steering mechanism, braking device, etc. based on the information about the vehicle's surroundings obtained by the vehicle external information detection unit 12030 or the vehicle internal information detection unit 12040, thereby enabling coordinated control related to autonomous driving and other functions that are independent of the driver's operation.

[0536] Additionally, the microcomputer 12051 can output control commands to the vehicle system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control for anti-glare, such as switching from high beam to low beam, by controlling the headlights according to the position of the vehicle in front or oncoming vehicles detected by the external information detection unit 12030.

[0537] The audio-visual output unit 12052 sends at least one of an audio output signal or an image output signal to an output device capable of visually or audibly providing notification information to the vehicle's passengers or external entities. Figure 54 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least an on-board display and / or a head-up display.

[0538] Figure 55 This is a diagram showing an example of the mounting location of the imaging unit 12031.

[0539] exist Figure 55 In the vehicle 12100, imaging units 12101, 12102, 12103, 12104, and 12105 are used as imaging units 12031.

[0540] Imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, in the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, or in the upper part of the windshield in the passenger compartment. Imaging unit 12101 in the front nose of the vehicle compartment and imaging unit 12105 in the upper part of the windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 in the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 in the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. The front images acquired by imaging units 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0541] It should be noted that Figure 55An example of the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 indicates the imaging range of imaging unit 12101 located in the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located in the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located in the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104 onto each other, a top-view image of the vehicle 12100 viewed from above is obtained.

[0542] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0543] For example, the microcomputer 12051 determines the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed to the vehicle 12100) based on distance information obtained from imaging units 12101 to 12104. This allows it to specifically identify three-dimensional objects that are closest to the vehicle 12100's travel path and are traveling in approximately the same direction as the vehicle ahead at a predetermined speed (e.g., 0 km / h or more). Furthermore, the microcomputer 12051 can pre-set a safe following distance in front of the vehicle ahead and can perform automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. This enables coordinated control for autonomous driving and other applications that do not rely on driver input.

[0544] For example, based on distance information obtained from imaging units 12101 to 12104, microcomputer 12051 classifies 3D object data related to 3D objects into categories such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, etc., to extract data, and can use the extracted data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as those visible to the driver and those difficult to see. Then, microcomputer 12051 determines the collision risk, indicating the risk of collision with each obstacle. When the collision risk is higher than a set value and there is a possibility of collision, microcomputer 12051 can output an alarm to the driver via audio speaker 12061 or display unit 12062, or execute forced deceleration or avoidance steering via drive system control unit 12010 to perform driving assistance for collision avoidance.

[0545] At least one of the imaging units 12101 to 12104 can be an infrared camera for detecting infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the image captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the image captured by the imaging units 12101 to 12104 (which are infrared cameras) and performing pattern matching processing on a series of feature points representing the contour of an object to determine whether a pedestrian exists. If the microcomputer 12051 determines that a pedestrian exists in the image captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 to overlay and display a rectangular outline for emphasizing the identified pedestrian. Furthermore, the audio-visual output unit 12052 can control the display unit 12062 to display an icon or similar indicating the pedestrian at a desired location.

[0546] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. The technology according to this disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, for example, by... Figure 1 The light receiving device 1 shown is applied to the imaging unit 12031, which can improve the resolution, reading speed and other characteristics.

[0547] Furthermore, the implementation of this technology is not limited to the above-described implementation, and various modifications can be made to the above-described implementation without departing from the scope of this technology.

[0548] Furthermore, the effects described herein are merely examples, and the effects of this technique are not limited to these and may include other effects.

[0549] It should be noted that this technology can have the following configurations. (1)

[0551] An optical receiving device, comprising:

[0552] A pixel array unit, wherein pixels, each including a first tap and a second tap, are arranged in a two-dimensional matrix, wherein the first tap detects the charge converted by the photoelectric conversion unit, and the second tap detects the charge converted by the photoelectric conversion unit.

[0553] On-chip lenses are disposed on the light incident surface side of the substrate for each pixel; and

[0554] The lens separator is formed in the same layer as the on-plate lens and separates the on-plate lenses from each other. (2)

[0556] According to the optical receiving device described in (1), wherein,

[0557] The first tap and the second tap each include a voltage application unit for applying voltage, and

[0558] The voltage application unit is shared by two adjacent pixels. (3)

[0560] According to the optical receiving device described in (2), wherein,

[0561] The pixel array unit includes a recess formed by excavating the substrate to a predetermined depth from the light incident surface side of the substrate, and

[0562] The groove is formed to overlap with at least a portion of the voltage application unit in the plan view. (4)

[0564] The optical receiving device according to any one of (1) to (3), wherein,

[0565] A reflection suppression film that suppresses the reflection of incident light is formed on the upper surface of the lens separator. (5)

[0567] The light receiving device according to any one of (1) to (4), wherein,

[0568] The sidewalls of the lens divider are inclined to face the incident surface. (6)

[0570] According to the optical receiving device described in (3), wherein,

[0571] The groove is formed to penetrate the substrate. (7)

[0573] The optical receiving device according to any one of (1) to (6) further includes a contact configured to apply a predetermined voltage to the first tap or the second tap, wherein,

[0574] Contacts are formed linearly along the pixel boundary lines. (8)

[0576] According to the optical receiving device described in (7), wherein,

[0577] Contact the gate electrode structure containing the transistor. (9)

[0579] The light receiving device according to any one of (1) to (8) further includes a reflective member that reflects light between the back side interface of the substrate and the metal film as the first layer. (10)

[0581] The light receiving device according to any one of (1), (2), (4), (5), and (9) further includes a pixel separation portion, which is disposed at the pixel boundary portion of the substrate and electrically separates the pixels of the substrate from each other, wherein,

[0582] The pixel separator has a gate electrode structure of a vertical transistor. (11)

[0584] The optical receiving device according to any one of (1) to (10) further includes a gate electrode structure of a transistor that applies a predetermined voltage to a first tap or a second tap. (12)

[0586] A method for manufacturing an optical receiving device, the method comprising:

[0587] For each pixel of the pixel array unit, a first tap and a second tap are formed. The first tap detects the charge converted by the photoelectric conversion unit, and the second tap detects the charge converted by the photoelectric conversion unit.

[0588] For each pixel, an on-chip lens is formed on the light incident surface side of the substrate; and

[0589] Lens separators that separate the on-plate lenses from each other are formed in the same layer as the on-plate lenses. (13)

[0591] A distance measurement module including a light receiving device, the light receiving device comprising:

[0592] A pixel array unit, wherein pixels, each including a first tap and a second tap, are arranged in a two-dimensional matrix, wherein the first tap detects the charge converted by the photoelectric conversion unit, and the second tap detects the charge converted by the photoelectric conversion unit.

[0593] On-chip lenses are disposed on the light incident surface side of the substrate for each pixel; and

[0594] The lens separator is formed in the same layer as the on-plate lens and separates the on-plate lenses from each other.

[0595] List of reference numerals

[0596] 1. Optical receiving device

[0597] 20-pixel array unit

[0598] 21 Tap Drive Unit

[0599] 51 pixels

[0600] TA First Draw

[0601] TB Second Tap

[0602] VSL (VSL0 to VSL3) vertical signal lines

[0603] 61 substrate

[0604] 62 on-chip lenses

[0605] 71 N+ Semiconductor Region

[0606] 73 P+ semiconductor region

[0607] 111 Multilayer Wiring

[0608] M1 to M5 metal films

[0609] 121 Transfer Transistor

[0610] 122 FD

[0611] 123 Reset transistor

[0612] 124 Amplifying Transistors

[0613] 125 Select Transistor

[0614] 127 Additional Capacitor

[0615] 128 Switching Transistors

[0616] 301 to 304 DTI

[0617] 311, 312 DTI

[0618] 321: Uneven part

[0619] 331 DTI

[0620] 342 Lens Separator

[0621] 343 Smooth Film

[0622] 351 Reflection suppression film

[0623] 371-pixel groove

[0624] 381 Groove section

[0625] Contact 391, 391', 392, 401

[0626] 402 polycrystalline silicon

[0627] 403 gate insulating film

[0628] 411 Reflective component

[0629] 421 Conductive Materials

[0630] 422 Insulating Film

[0631] 423 Contact

[0632] 600 Distance Measurement Module

[0633] 613 Optical Receiver Unit

Claims

1. A light-receiving device comprising: a pixel array unit in which pixels each including a first tap that detects a charge photoelectrically converted by a photoelectric conversion unit and a second tap that detects a charge photoelectrically converted by the photoelectric conversion unit are two-dimensionally arranged in a matrix form; an on-chip lens provided on a light-incident surface side of a substrate for each pixel; a lens partition portion formed in the same layer as the on-chip lens and partitioning the on-chip lenses from each other; and a gate electrode structure of a transistor that applies a predetermined voltage to the first tap or the second tap.

2. The light-receiving device according to claim 1, wherein the first tap and the second tap each include a voltage application unit that applies a voltage, and the voltage application units are shared by two adjacent pixels.

3. The light-receiving device according to claim 2, wherein the pixel array unit includes a groove portion formed by digging the substrate to a predetermined depth from the light-incident surface side of the substrate, and the groove portion is formed so as to overlap at least a part of the voltage application unit in a plan view.

4. The light-receiving device according to claim 1, wherein a reflection-inhibiting film that inhibits reflection of incident light is formed on an upper surface of the lens partition portion.

5. The light-receiving device according to claim 1, wherein a side wall of the lens partition portion is inclined so as to face the light-incident surface side.

6. The light-receiving device according to claim 3, wherein the groove portion is formed so as to penetrate the substrate.

7. The light-receiving device according to claim 1, further comprising a contact configured to apply a predetermined voltage to the first tap or the second tap, wherein the contact is linearly formed along a pixel boundary line.

8. The light-receiving device according to claim 7, wherein the contact has a gate electrode structure of a transistor.

9. The light-receiving device according to claim 1, further comprising a reflection member that reflects light between a back surface side interface of the substrate and a metal film as a first layer.

10. The light-receiving device according to claim 1, further comprising a pixel partition portion provided at a pixel boundary portion of the substrate and electrically partitioning pixels of the substrate from each other, wherein the pixel partition portion has a longitudinal gate electrode structure of a transistor.

11. A method for manufacturing a light-receiving device, the method comprising: for each pixel of a pixel array unit, forming a first tap that detects a charge photoelectrically converted by a photoelectric conversion unit and a second tap that detects a charge photoelectrically converted by the photoelectric conversion unit; forming an on-chip lens on a light-incident surface side of a substrate for each pixel; forming a lens partition portion that partitions the on-chip lenses from each other in the same layer as the on-chip lens; and applying a predetermined voltage to the first tap or the second tap.

12. A distance measurement module including a light-receiving device, the light-receiving device comprising: ​ a pixel array unit in which pixels each including a first tap that detects a charge photoelectrically converted by a photoelectric conversion unit and a second tap that detects a charge photoelectrically converted by the photoelectric conversion unit are two-dimensionally arranged in a matrix form; an on-chip lens provided on a light incident surface side of a substrate for each pixel; a lens partition portion formed in the same layer as the on-chip lens and partitioning the on-chip lenses from each other; and a gate electrode structure of a transistor that applies a predetermined voltage to the first tap or the second tap.

Images