Display device and method of manufacturing a display device

Abstract

A display device and a method of manufacturing the display device are disclosed. The display device may include: a substrate including a display area and a non-display area surrounding at least one side of the display area, the display area including a plurality of pixel areas, each having an emission area; and pixels disposed in each of the plurality of pixel areas and including a display element portion. The display element portion may include: a first insulating layer disposed on the substrate; at least one light-emitting element disposed on the first insulating layer and each having a first end and a second end in a longitudinal direction; a first layer disposed on the first insulating layer and the light-emitting element and in contact with a first area of ​​each of the first end and the second end of the light-emitting element; a second layer disposed on the light-emitting element and in contact with a second area of ​​each of the first end and the second end of the light-emitting element; and an interlayer insulating layer disposed between the first layer and the second layer. Here, the first layer and the second layer may include semiconductor materials.

Description

Technical Field

[0001] This disclosure relates to a display device and a method for manufacturing a display device. Background Technology

[0002] With increasing interest in information display and growing demand for portable information media, the need for and commercialization of display devices has attracted attention. Summary of the Invention

[0003] Technical issues

[0004] The purpose of this disclosure is to provide a display device with improved light output efficiency.

[0005] Furthermore, the purpose of this disclosure is to provide a method for manufacturing the display device described above.

[0006] Technical solution

[0007] According to embodiments of the present disclosure, a display device may include: a substrate, including a display area and a non-display area surrounding at least one side of the display area, the display area including a plurality of pixel areas, each having an emission area; and a pixel, disposed in each of the plurality of pixel areas and including a display element portion.

[0008] In embodiments of this disclosure, the display element portion may include: a first insulating layer disposed on a substrate; at least one light-emitting element disposed on the first insulating layer and each having a first end and a second end in a longitudinal direction; a first layer disposed on the first insulating layer and the light-emitting element and in contact with a first region of each of the first end and the second end of the light-emitting element; a second layer disposed on the light-emitting element and in contact with a second region of each of the first end and the second end of the light-emitting element; and an interlayer insulating layer disposed between the first layer and the second layer. Here, the first layer and the second layer may include semiconductor materials.

[0009] In embodiments of this disclosure, the light-emitting element may include: a first semiconductor layer doped with a first conductive dopant; a second semiconductor layer doped with a second conductive dopant; and an active layer disposed between the first semiconductor layer and the second semiconductor layer. Here, each of the first semiconductor layer and the second semiconductor layer may include gallium nitride (GaN) semiconductor material.

[0010] In embodiments of this disclosure, the first conductive dopant may include an n-type dopant, and the second conductive dopant may include a p-type dopant.

[0011] In embodiments of this disclosure, the first end of the light-emitting element may include a first semiconductor layer, and the second end of the light-emitting element may include a second semiconductor layer.

[0012] In embodiments of this disclosure, the first layer may include a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material, and the second layer may include a transparent oxide semiconductor material.

[0013] In embodiments of this disclosure, the display device may further include: a first power line disposed between the substrate and the first insulating layer and electrically connected to the first layer; and a second power line disposed between the substrate and the first insulating layer, spaced apart from the first power line, and electrically connected to the second layer.

[0014] In embodiments of this disclosure, the first layer may be a hole injection layer that receives a first power from a first electric line and injects holes into a first region of a second end of a light-emitting element, and the second layer may be an electron injection layer that receives a second power from a second electric line and injects electrons into a second region of a first end of a light-emitting element.

[0015] In embodiments of this disclosure, an interlayer insulating layer may be positioned between a first region and a second region of each of the first and second ends of the light-emitting element.

[0016] In embodiments of this disclosure, the first region of the first end of the light-emitting element that contacts the first layer and the second region of the first end of the light-emitting element that contacts the second layer may have the same width or different widths.

[0017] In embodiments of this disclosure, the second region at the first end of the light-emitting element that contacts the second layer and the second region at the second end of the light-emitting element that contacts the second layer may have the same width or different widths.

[0018] In embodiments of this disclosure, the display element portion may further include: a first conductive line disposed between a substrate and a first insulating layer; a second insulating layer disposed on a second layer; and a second conductive line disposed on the second insulating layer.

[0019] In embodiments of this disclosure, different voltages can be applied to the first conductive line and the second conductive line respectively, and an electric field can be formed in the direction intersecting the longitudinal direction of the light-emitting element.

[0020] In embodiments of this disclosure, the second conductive wire may include a transparent conductive material.

[0021] In embodiments of this disclosure, the display element portion may further include a cover layer disposed on the second conductive line to correspond to the light-emitting element. Here, the cover layer may include an opaque conductive material.

[0022] In embodiments of this disclosure, the capping layer can guide light emitted from the light-emitting element in a predetermined direction to determine the location of the emission region of each of a plurality of pixel regions.

[0023] In embodiments of this disclosure, the pixel may further include a pixel circuit section disposed between the substrate and the display element section.

[0024] According to another embodiment of this disclosure, the display device may include: a stretchable substrate including a plurality of island-shaped members and a bridge-shaped member connecting the plurality of island-shaped members; and a plurality of pixels disposed in each of the plurality of island-shaped members and each including a display element portion. Here, the display element portion may include: a first insulating layer disposed in each of the plurality of island-shaped members; a plurality of light-emitting elements disposed on the first insulating layer and each having a first end and a second end in the longitudinal direction; a first layer disposed on the first insulating layer and the plurality of light-emitting elements and in contact with a first region of each of the first end and the second end of each of the plurality of light-emitting elements; a second layer disposed on the plurality of light-emitting elements and in contact with a second region of each of the first end and the second end of each of the plurality of light-emitting elements; and an interlayer insulating layer disposed between the first layer and the second layer. Here, the first layer and the second layer may include semiconductor materials.

[0025] According to embodiments of this disclosure, the first layer may include a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material, and the second layer may include a transparent oxide semiconductor material.

[0026] According to embodiments of the present disclosure, the first end of each of the plurality of light-emitting elements may include a first semiconductor layer doped with an n-type dopant, and the second end of each of the plurality of light-emitting elements may include a second semiconductor layer doped with a p-type dopant.

[0027] According to embodiments of this disclosure, the stretchable substrate may further include cutouts positioned between a plurality of islands and bridges.

[0028] The display device described above can be manufactured by a method that includes providing pixels prepared in a pixel region on a substrate. Here, providing pixels may include: forming a pixel circuit section on the substrate; and forming a display element section on the pixel circuit section.

[0029] In embodiments of this disclosure, forming a display element portion may include: forming a first insulating layer on a pixel circuit portion; supplying a plurality of light-emitting elements on the first insulating layer, each of the plurality of light-emitting elements having a first end and a second end in a longitudinal direction; forming a first layer on the plurality of light-emitting elements, the first layer comprising a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material; forming an interlayer insulating layer on the first layer; forming a second layer on the interlayer insulating layer, the second layer comprising a transparent oxide semiconductor material; and forming a second insulating layer on the second layer.

[0030] According to embodiments of the present disclosure, a first layer may contact each of a first region of a first end and a first region of a second end of a light-emitting element, a second layer may contact each of a second region of a first end and a second region of a second end of a light-emitting element, and an interlayer insulating layer may contact a third region of each of the first and second ends of a light-emitting element between the first and second regions.

[0031] According to embodiments of the present disclosure, the display element forming section may further include: forming a first conductive line between the pixel circuit section and the first insulating layer; forming a second conductive line on the second insulating layer; and forming a capping layer on the second conductive line.

[0032] Beneficial effects

[0033] According to embodiments of the present disclosure, a display device and a method of manufacturing the display device can be provided, which can omit the configuration (alignment electrode or alignment line) for aligning the light-emitting elements by setting a first layer and a second layer after inputting light-emitting elements on a substrate. The first layer includes a hydrogenated amorphous silicon (a-Si:H) semiconductor material in contact with a first region at both ends of each light-emitting element, and the second layer includes a transparent oxide semiconductor material in contact with a second region at both ends of each light-emitting element.

[0034] In addition, a display device and a method for manufacturing the display device can be provided, which can improve light output efficiency by providing a cover layer on the light-emitting element to reflect or scatter light emitted from the light-emitting element in a desired direction.

[0035] The effects of the embodiments according to this disclosure are not limited to those illustrated above, and many more different effects are included in this specification. Attached Figure Description

[0036] Figure 1a This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0037] Figure 1b yes Figure 1a A cross-sectional view of the light-emitting element.

[0038] Figures 2a to 2c This is a circuit diagram showing the unit emission region of a light-emitting device according to an embodiment of the present disclosure, and in particular, a circuit diagram showing an example of a pixel configured in a light-emitting display panel.

[0039] Figure 3 This is a schematic plan view showing the region of a light-emitting device including a unit emission region according to an embodiment of the present disclosure.

[0040] Figure 4 It is along Figure 3A sectional view taken by line I-I'.

[0041] Figure 5a yes Figure 4 An enlarged sectional view of part of EA1, and Figure 5b yes Figure 4 An enlarged sectional view of part of EA2.

[0042] Figure 6a and Figure 6b It is a schematic diagram showing the energy band diagram of the first layer, the first semiconductor layer, the second semiconductor layer, and the second layer.

[0043] Figure 7 This is a cross-sectional view showing the unit emitting region of a light-emitting device according to an embodiment of the present disclosure, and is along... Figure 3 A sectional view taken by line I-I'.

[0044] Figure 8 This is a schematic plan view showing the unit emission region of a light-emitting device according to an embodiment of the present disclosure.

[0045] Figure 9 Is with Figure 8 The sectional view corresponding to line II-II'.

[0046] Figure 10 This illustrates a display device according to an embodiment of the present disclosure and schematically shows its use. Figure 1a and Figure 1b The diagram shows a plan view of an example display device in which the light-emitting element serves as the light source.

[0047] Figure 11a and Figure 11b yes Figure 10 A magnified plan view of part of EA3.

[0048] Figure 12a and Figure 12b This illustrates an embodiment. Figure 10 The diagram shows the electrical connections between the components included in a single pixel.

[0049] Figure 13 It is shown schematically. Figure 10 A planar view of one pixel in the pixel diagram shown.

[0050] Figure 14 It is along Figure 13 The sectional view taken from line III-III'.

[0051] Figure 15 yes Figure 14 A magnified plan view of part of EA4.

[0052] Figure 16 It is implemented according to another embodiment. Figure 13 A schematic plan view of the capping layer shown.

[0053] Figures 17a to 17k The manufacturing process is shown sequentially. Figure 13 A schematic plan view of a method for one pixel is shown.

[0054] Figures 18a to 18k The manufacturing process is shown sequentially. Figure 14 A schematic cross-sectional view of a method for a single pixel is shown. Detailed Implementation

[0055] Because this disclosure can be modified in various ways and has various forms, specific embodiments will be shown in the accompanying drawings and described in detail in the specification. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed, and this disclosure includes all modifications, equivalents, and substitutions within the technical scope of this disclosure.

[0056] In describing each figure, similar reference numerals are used for similar components. In the figures, for clarity of this disclosure, the size of the structures is shown enlarged from their actual size. The terms "first," "second," etc., may be used to describe various components, but these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0057] It should be understood that in this application, terms such as "comprising" and "having" are used to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. Furthermore, the phrase "on another part" for a portion of a layer, film, region, plate, etc., includes not only the case where the portion is "directly on another part" but also the case where there is another part between the portion and the other part. Additionally, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another part, the formation direction is not limited to the upper direction but includes the portion being formed on a side surface or in the lower direction. Conversely, when a portion of a layer, film, region, plate, etc., is formed "below" another part, this includes not only the case where the portion is "directly below" the other part but also the case where there is another part between the portion and the other part.

[0058] In the following description, preferred embodiments of the present disclosure and other issues that are readily understood by those skilled in the art will address with reference to the accompanying drawings. In the following description, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0059] Figure 1a This is a schematic perspective view of a light-emitting element according to an embodiment of the present disclosure, and Figure 1b yes Figure 1a A cross-sectional view of the light-emitting element.

[0060] exist Figure 1a and Figure 1b The image shows a cylindrical light-emitting element (LD), but the type and / or shape of the light-emitting element (LD) according to this disclosure are not limited thereto.

[0061] First, refer to Figure 1a and Figure 1b The light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be implemented as an emission stack pattern 10 in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are stacked sequentially.

[0062] The light-emitting element (LD) can be configured to extend in one direction. When the direction of extension of the light-emitting element (LD) is referred to as the longitudinal direction, the light-emitting element (LD) may include one side end and another side end along the extension direction. Either the first semiconductor layer 11 or the second semiconductor layer 13 may be disposed at one side end of the light-emitting element (LD), and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the other side end of the light-emitting element (LD).

[0063] The light-emitting element (LD) can be configured in various shapes. For example, the LD can have a rod-like or bar-like shape that is long in the longitudinal direction (i.e., with an aspect ratio greater than 1). In embodiments of this disclosure, the length L of the LD in the longitudinal direction can be greater than the diameter D (or the width of the cross-section) of the LD. The LD can include, for example, light-emitting diodes manufactured to be very small, having a diameter D and / or length L on the order of approximately micrometers or nanometers. In embodiments of this disclosure, the size of the LD can be varied according to the requirements (or design conditions) of the lighting device or the self-emissive display device.

[0064] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as Si, Ge, or Sn. However, the materials used to configure the first semiconductor layer 11 are not limited to these, and various other materials may be used to configure the first semiconductor layer 11. In embodiments of this disclosure, the first semiconductor layer 11 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). For example, the first semiconductor layer 11 may be an n-type GaN semiconductor. The first semiconductor layer 11 may include an upper surface 11b in contact with the active layer 12 and a lower surface 11a exposed to the outside.

[0065] The active layer 12 can be disposed on the first semiconductor layer 11 and can be formed as a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 can vary depending on the type of light-emitting element (LD). The active layer 12 can emit light with wavelengths from 400 nm to 900 nm and can use a dual heterostructure. In embodiments of this disclosure, a cladding layer (not shown) doped with a conductive dopant can be formed on and / or under the active layer 12. For example, the cladding layer can be formed of an AlGaN layer or an InAlGaN layer. According to embodiments, materials such as AlGaN or InAlGaN can be used to form the active layer 12, and various other materials can be used to configure the active layer 12. The active layer 12 may include a first surface 12a in contact with the first semiconductor layer 11 and a second surface 12b in contact with the second semiconductor layer 13.

[0066] When an electric field of a predetermined voltage or higher is applied to both ends of the light-emitting element (LD), the LD emits light when electron-hole pairs recombine in the active layer 12. By controlling the light emission of the LD using this principle, the LD can be used as a light source (or light source) for various light-emitting devices (including pixels of display devices).

[0067] The second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as Mg. However, the materials used to configure the second semiconductor layer 13 are not limited to these, and various other materials may be used to configure the second semiconductor layer 13. In embodiments of this disclosure, the second semiconductor layer 13 may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant). For example, the second semiconductor layer 13 may be a p-type GaN semiconductor. The second semiconductor layer 13 may include a lower surface 13a in contact with the active layer 12 and an upper surface 13b exposed to the outside.

[0068] In embodiments of this disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) than each other along the length L of the light-emitting element LD. For example, the first semiconductor layer 11 may have a width (or a thickness) that is relatively wider than the width of the second semiconductor layer 13 (or a thickness that is thicker than the thickness of the second semiconductor layer 13) along the length L of the light-emitting element LD. Therefore, as Figure 1a and Figure 1b As shown, the active layer 12 of the light-emitting element LD can be positioned closer to the upper surface 13b of the second semiconductor layer 13 rather than the lower surface 11a of the first semiconductor layer 11.

[0069] In embodiments of this disclosure, the light-emitting element (LD) may include a lower surface 11a of a first semiconductor layer 11 and an upper surface 13b of a second semiconductor layer 13 exposed to the outside. The lower surface 11a of the first semiconductor layer 11 and the upper surface 13b of the second semiconductor layer 13 may be surfaces in contact with an external material (e.g., a conductive material or a semiconductor material) electrically connected thereto.

[0070] In embodiments of this disclosure, the light-emitting element LD may further include an insulating film 14. However, according to embodiments, the insulating film 14 may be omitted, or may be configured to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0071] The insulating film 14 prevents electrical short circuits that may occur when the active layer 12 comes into contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. Furthermore, by forming the insulating film 14, the lifetime and efficiency of the light-emitting element (LD) can be improved by minimizing surface defects. Additionally, when multiple LDs are closely arranged, the insulating film 14 prevents unwanted short circuits that may occur between the LDs. The presence or absence of the insulating film 14 is not limited as long as short circuits between the active layer 12 and external conductive materials can be prevented.

[0072] like Figure 1a and Figure 1b As shown, the insulating film 14 can be arranged to completely surround the outer peripheral surface of the emission stack pattern 10, which includes the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For ease of description, Figure 1a A portion of the insulating film 14 is removed, but the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 included in the actual emission stack pattern 10 can be surrounded by the insulating film 14.

[0073] In the above embodiments, the insulating film 14 completely surrounds the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, but this disclosure is not limited thereto. According to embodiments, the insulating film 14 may cover the entire outer peripheral surface of the active layer 12, or it may cover only a portion of the outer peripheral surface of each of the first semiconductor layer 11 and the second semiconductor layer 13.

[0074] According to embodiments of this disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include one or more insulating materials selected from the group consisting of SiO2, Si3N4, Al2O3 and TiO2, but is not limited thereto, and various materials with insulating properties may be used.

[0075] When the insulating film 14 is disposed on the light-emitting element LD, it can prevent short circuits between the active layer 12 and the external conductive material. Furthermore, by forming the insulating film 14, the lifespan and efficiency of the light-emitting element LD can be improved by minimizing surface defects. Additionally, when multiple light-emitting elements LD are closely arranged, the insulating film 14 can prevent unwanted short circuits that may occur between the light-emitting elements LD.

[0076] The light-emitting elements (LDs) described above can be used as light sources for various display devices. LDs can be manufactured using surface treatment processes. For example, when multiple LDs are mixed in a fluid solution (or solvent) and supplied to each emission region (e.g., the emission region of each pixel or the emission region of each sub-pixel), a surface treatment can be performed on each of the LDs so that the LDs can be uniformly ejected without unevenly agglomerating in the solution.

[0077] Light-emitting devices including the light-emitting elements (LDs) described above can be used in various types of devices (including display devices) that require a light source. For example, when multiple light-emitting elements (LDs) are arranged in the emission area of ​​each pixel of a display panel, the light-emitting elements (LDs) can be used as a light source for each pixel. However, the application areas of light-emitting elements (LDs) are not limited to the examples described above. For example, light-emitting elements (LDs) can be used in other types of devices that require a light source (such as lighting devices).

[0078] Figures 2a to 2c This is a circuit diagram showing the unit emission region of a light-emitting device according to an embodiment of the present disclosure, and in particular, a circuit diagram showing an example of a pixel configured in a light-emitting display panel.

[0079] exist Figures 2a to 2c In this context, the unit emitting area can be a pixel area in which one of the multiple pixels included in the light-emitting display panel, pixel PXL, is disposed, and it can be a pixel area in which one of the pixels is disposed. Figure 1a and Figure 1b The area of ​​the light-emitting element (LD) and the signal lines electrically connected to the light-emitting element (LD).

[0080] First, refer to Figures 1a to 2a A pixel PXL may include a light-emitting element LD and a first power line PL1 and a second power line PL2 connected to the light-emitting element LD.

[0081] One end of the light-emitting element LD (e.g., the second semiconductor layer 13) can be connected to the first power line PL1, and the other end of the light-emitting element LD (e.g., the first semiconductor layer 11) can be connected to the second power line PL2. A predetermined signal (or voltage) can be transmitted from the first power line PL1 to one end of the light-emitting element LD, and a predetermined signal (or voltage) can be transmitted from the second power line PL2 to the other end of the light-emitting element LD.

[0082] In embodiments of this disclosure, the predetermined signal applied to the first power line PL1 and the predetermined signal applied to the second power line PL2 may have different levels. For example, when one side of the light-emitting element LD is the second semiconductor layer 13 and the other side is the first semiconductor layer 11, the predetermined signal applied to the first power line PL1 may be set to a high potential and the predetermined signal applied to the second power line PL2 may be set to a low potential.

[0083] When a voltage equal to or greater than a threshold voltage is applied between one end and the other end of the light-emitting element LD described above, the light-emitting element LD can emit light with a brightness corresponding to the magnitude of the applied voltage. That is, the light emission of pixel PXL can be controlled by adjusting a predetermined signal applied from the first electric field line PL1 and / or a predetermined signal applied from the second electric field line PL2.

[0084] Next, refer to Figure 1a , Figure 1b and Figure 2b A pixel PXL can include multiple light-emitting elements (LDs) connected in parallel. In this case, the brightness of the pixel PXL can correspond to the sum of the brightness of the multiple light-emitting elements (LDs). When the pixel PXL includes multiple light-emitting elements (LDs), even if defects occur in some of the light-emitting elements (LDs), defects due to defects in the pixel PXL itself can be prevented.

[0085] refer to Figure 1a , Figure 1b and Figure 2c The connection orientation of the light-emitting element LD included in pixel PXL can be changed. For example, one end of the light-emitting element LD can be connected to the second electric field line PL2, and its other end can be connected to the first electric field line PL1. Figure 2a Implementation methods and Figure 2b In one embodiment, the voltages applied between the first electric field line PL1 and the second electric field line PL2 can be in opposite directions.

[0086] Figure 3 This is a schematic plan view showing the region of a light-emitting device including a unit emitting region according to an embodiment of the present disclosure. Figure 4 It is along Figure 3 A cross-sectional view taken by line I-I'. Figure 5a yes Figure 4 An enlarged sectional view of part of EA1. Figure 5b yes Figure 4 Enlarged sectional view of part of EA2, and Figure 6a and Figure 6b It is a schematic diagram showing the energy band diagram of the first layer, the first semiconductor layer, the second semiconductor layer, and the second layer.

[0087] refer to Figure 1a , Figure 1b as well as Figures 3 to 6b The unit emitting region of a light-emitting device is a pixel region PXA in which a pixel PXL including at least one light-emitting element LD is disposed, and may include an emitting region in which light is emitted. In the following text, for ease of description, the unit emitting region is referred to as the pixel region PXA.

[0088] The display element section DPL, including the light-emitting element LD, can be disposed in the pixel area PXA. The display element section DPL can be connected to the first power line PL1 and the second power line PL2.

[0089] First electric field lines PL1 and second electric field lines PL2 may be disposed and / or formed on a substrate SUB and spaced apart from each other. Each of the first electric field lines PL1 and second electric field lines PL2 may extend in one direction (e.g., in a second direction DR2). However, this disclosure is not limited thereto, and the first electric field lines PL1 and second electric field lines PL2 may extend in various directions. The first electric field lines PL1 and second electric field lines PL2 may be formed of a conductive material (or substance). A predetermined signal (or voltage) of constant level may be applied to each of the first electric field lines PL1 and second electric field lines PL2. For example, an external signal (or voltage) may be applied to each of the first electric field lines PL1 and second electric field lines PL2. As another example, each of the first electric field lines PL1 and second electric field lines PL2 may receive a predetermined signal (or voltage) from a configuration in a light-emitting device via an electrical connection to the configuration in which the predetermined signal (or voltage) is applied.

[0090] A barrier layer BRL may be provided and / or formed on the first electric line PL1 and the second electric line PL2.

[0091] A barrier layer (BRL) prevents impurities from diffusing into the display element portion (DPL). The barrier layer (BRL) may include an inorganic insulating layer comprising inorganic materials. For example, the barrier layer (BRL) may include silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiON) and aluminum oxide (AlO) x At least one of the metal oxides of the substrate SUB. The barrier layer BRL can be a single layer, or it can be a multilayer structure with at least two layers. When the barrier layer BRL is multilayered, each layer can be formed of the same material or can be formed of different materials. The barrier layer BRL can be omitted depending on the material of the substrate SUB, the process conditions, etc.

[0092] According to an embodiment, at least one of the first electric field line PL1 and the second electric field line PL2, or the first electric field line PL1 and the second electric field line PL2, may be disposed and / or formed on the barrier layer BRL. Although not directly shown in the figures, a region of the first electric field line PL1 may be exposed to the outside through a first contact hole CH1 through the barrier layer BRL, and a region of the second electric field line PL2 may be exposed to the outside through a second contact hole CH2 through the barrier layer BRL.

[0093] The display element section DPL can be set and / or formed on the barrier layer BRL.

[0094] The display element portion (DPL) can be formed on the barrier layer (BRL) on the substrate (SUB). In this case, the display element portion (DPL) may include at least one insulating layer. Figure 4 In this embodiment, an insulating layer is formed on each of the upper and lower portions of the light-emitting element (LD), but this disclosure is not limited thereto. (See references) Figure 4 In the display element section DPL, a first insulating layer INS1, a light-emitting element LD disposed on the first insulating layer INS1, a first layer FL and a second layer SL in contact with the two ends EP1 and EP2 of the light-emitting element LD, and a second insulating layer INS2 disposed on the second layer SL may be formed. The display element section DPL may also include a dam pattern (not shown), which is disposed and / or formed in the peripheral region of the pixel region PXA of each pixel PXL to define the pixel region PXA of each pixel PXL. Each of the first electric field line PL1 and the second electric field line PL2 may overlap with the dam pattern on the substrate SUB, or may be disposed outside the dam pattern.

[0095] The first insulating layer INS1 can be disposed on the barrier layer BRL. The first insulating layer INS1 may include silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiON) and aluminum oxide (AlO) x The first insulating layer INS1 can be a single layer, but it can also be a multilayer consisting of two or more layers. In embodiments of this disclosure, the first insulating layer INS1 can be made of silicon oxide (SiO2). x It can be formed and can be set as a single layer.

[0096] At least one light-emitting element (LD) may be disposed on the first insulating layer INS1. For example, multiple light-emitting elements (LD) may be disposed on the first insulating layer INS1.

[0097] Each of the light-emitting elements (LDs) can be a light-emitting element with an ultra-small size (e.g., from nanometer to micrometer scale) using a material with an inorganic crystal structure. For example, each of the light-emitting elements (LDs) can be an ultra-small light-emitting element manufactured by an etching method. In embodiments of this disclosure, such as Figures 1a to 4 As shown, each of the light-emitting elements (LDs) can be a light-emitting element comprising an emission stack pattern 10 in which a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 are sequentially stacked along a length L, and an insulating film 14 surrounding the outer peripheral surface (or surface) of the emission stack pattern 10, and manufactured by an etching method.

[0098] Two to dozens of light-emitting elements (LDs) can be set in the pixel area PXA, but the number of light-emitting elements (LDs) is not limited to this.

[0099] In embodiments of this disclosure, each of the light-emitting elements (LDs) can emit either colored light and / or white light. Each of the light-emitting elements (LDs) can be disposed on the first insulating layer INS1 such that the direction of its length L corresponds to a first direction DR1 intersecting the thickness direction (i.e., the third direction DR3) of the display element portion DPL. For example, each light-emitting element (LD) can be disposed on the first insulating layer INS1 such that the direction of its length L is parallel to the first direction DR1.

[0100] The light-emitting element (LD) can be applied to the pixel region PXA via inkjet printing, slot coating, or various other methods. For example, the LD can be mixed with a volatile solvent and supplied to the pixel region PXA via inkjet printing or slot coating. The LD can be disposed on a first insulating layer INS1 disposed in the pixel region PXA. After supplying the LD, the solvent can be evaporated or removed by other methods to finally provide the LD to the pixel region PXA.

[0101] Each of the light-emitting elements (LDs) may have a first end EP1 and a second end EP2 in the direction of length L. The first end EP1 of each of the light-emitting elements (LDs) may be one of a first semiconductor layer 11 and a second semiconductor layer 13, and the second end EP2 of each of the light-emitting elements (LDs) may be the other of the first semiconductor layer 11 and the second semiconductor layer 13. For example, the first end EP1 of each of the light-emitting elements (LDs) may be a first semiconductor layer 11 including an n-type semiconductor layer, and its second end EP2 may be a second semiconductor layer 13 including a p-type semiconductor layer.

[0102] The first FL layer can be disposed and / or formed on the light-emitting element (LD). In embodiments of this disclosure, the first FL layer may comprise a hydrogenated amorphous silicon (a-Si:H) semiconductor material. For example, the first FL layer may comprise a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material doped with a p-type dopant such as Mg.

[0103] The first layer FL can contact both ends EP1 and EP2 of each of the light-emitting elements LD. For example, the first layer FL can contact each of a region of the first end EP1 of each of the light-emitting elements LD and a region of the second end EP2 of each of the light-emitting elements LD.

[0104] In embodiments of this disclosure, such as Figure 5a As shown, the first layer FL can be in direct contact with the first region A1 of the upper surface 13b of the second semiconductor layer 13 of each light-emitting element LD. Furthermore, as... Figure 5b As shown, the first layer FL can be in direct contact with the first region B1 of the lower surface 11a of the first semiconductor layer 11 of each light-emitting element LD. Here, the upper surface 13b of the second semiconductor layer 13 and the lower surface 11a of the first semiconductor layer 11 can be surfaces that are not surrounded by the insulating film 14 and are at least partially exposed to the outside.

[0105] The first region A1 of the upper surface 13b of the second semiconductor layer 13 that contacts the first layer FL and the first region B1 of the lower surface 11a of the first semiconductor layer 11 that contacts the first layer FL can be smaller than the diameter D of the emission stack pattern 10. The first region A1 of the upper surface 13b of the second semiconductor layer 13 that contacts the first layer FL and the first region B1 of the lower surface 11a of the first semiconductor layer 11 that contacts the first layer FL can have the same thickness (or width). However, this disclosure is not limited thereto, and according to embodiments, the first region A1 of the upper surface 13b of the second semiconductor layer 13 that contacts the first layer FL and the first region B1 of the lower surface 11a of the first semiconductor layer 11 that contacts the first layer FL can have different thicknesses (or widths).

[0106] Furthermore, the first layer FL can be disposed and / or formed on the upper surface of each of the light-emitting elements LD. For example, the first layer FL can be disposed and / or formed on the first insulating layer INS1 on which the light-emitting elements LD are disposed, and can be disposed and / or formed on the upper surface of the light-emitting elements LD and on each of the first insulating layers INS1.

[0107] The first layer FL described above can be electrically connected and / or physically connected to the first power line PL1 via the first contact hole CH1. Specifically, the first layer FL can be electrically connected and / or physically connected to the first power line PL1 via a separate connection tool (not shown) and the first contact hole CH1. Here, the separate connection tool can be a configuration for connecting the first power line PL1 and the first layer FL, and can correspond to what will be described later. Figure 9 The second bridging pattern is BRP2. Therefore, a predetermined signal (or voltage) applied to the first power line PL1 can be transmitted to the first layer FL.

[0108] An interlayer insulating layer (ILD) may be disposed and / or formed on the first layer (FL). The ILD may be disposed and / or formed on each of the light-emitting element (LD) and the first layer (FL). The ILD may be an inorganic insulating layer comprising inorganic materials. For example, the ILD may comprise silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiON) and aluminum oxide (AlO) x The interlayer insulating layer (ILD) can be a single layer, but it can also be a multilayer structure with at least two layers. In embodiments of this disclosure, the interlayer insulating layer (ILD) can be made of silicon oxide (SiO2). x It can be formed and configured as a single layer. However, this disclosure is not limited thereto.

[0109] In embodiments of this disclosure, an interlayer insulating layer (ILD) may be disposed and / or formed on a first layer FL that contacts a first region A1 of the upper surface 13b of the second semiconductor layer 13 of each light-emitting element (LD). Furthermore, the interlayer insulating layer (ILD) may be disposed and / or formed on the first layer FL that contacts a first region B1 of the lower surface 11a of the first semiconductor layer 11 of each light-emitting element (LD). Therefore, the interlayer insulating layer (ILD) may contact another region of the upper surface 13b of the second semiconductor layer 13 of each light-emitting element (LD) and another region of the lower surface 11a of the first semiconductor layer 11. For example, as... Figure 5a As shown, the interlayer insulating layer (ILD) can directly contact the second region A2 of the upper surface 13b of the second semiconductor layer 13 of each light-emitting element (LD). Furthermore, as... Figure 5b As shown, the interlayer insulating layer ILD can contact the second region B2 of the lower surface 11a of the first semiconductor layer 11 of each light-emitting element LD.

[0110] The second region A2 of the upper surface 13b of the second semiconductor layer 13, which contacts the interlayer insulating layer (ILD), and the second region B2 of the lower surface 11a of the first semiconductor layer 11, which contacts the ILD, can be smaller than the diameter D of the emission stack pattern 10. In embodiments of this disclosure, the second region A2 of the upper surface 13b of the second semiconductor layer 13, which contacts the ILD, and the second region B2 of the lower surface 11a of the first semiconductor layer 11, which contacts the ILD, can have the same thickness (or width). However, this disclosure is not limited thereto, and according to embodiments, the second region A2 of the upper surface 13b of the second semiconductor layer 13, which contacts the ILD, and the second region B2 of the lower surface 11a of the first semiconductor layer 11, which contacts the ILD, can have different thicknesses (or widths).

[0111] The second layer SL can be disposed and / or formed on the interlayer insulating layer (ILD). The second layer SL can be disposed and / or formed on each of the light-emitting elements (LDs) and the interlayer insulating layer (ILD). The second layer SL can be formed of a transparent oxide semiconductor material having high electron mobility. In embodiments of this disclosure, the second layer SL can be formed of a transparent oxide semiconductor material such as a-IGZO. The second layer SL can contact both ends EP1 and EP2 of each of the light-emitting elements (LDs). For example, the second layer SL can contact another region of the first end EP1 of each light-emitting element (LD) and another region of the second end EP2 of each light-emitting element (LD).

[0112] In embodiments of this disclosure, such as Figure 5a As shown, the second layer SL can be in direct contact with the third region A3 of the upper surface 13b of the second semiconductor layer 13 of each light-emitting element LD. Furthermore, as... Figure 5b As shown, the second layer SL can be in direct contact with the third region B3 of the lower surface 11a of each light-emitting element LD.

[0113] The third region A3 of the upper surface 13b of the second semiconductor layer 13, which contacts the second layer SL, and the third region B3 of the lower surface 11a of the first semiconductor layer 11, which contacts the second layer SL, can be smaller than the diameter D of the emission stack pattern 10. The third region A3 of the upper surface 13b of the second semiconductor layer 13, which contacts the second layer SL, and the third region B3 of the lower surface 11a of the first semiconductor layer 11, which contacts the second layer SL, can have the same thickness (or width). However, this disclosure is not limited thereto, and according to embodiments, the third region A3 of the upper surface 13b of the second semiconductor layer 13, which contacts the second layer SL, and the third region B3 of the lower surface 11a of the first semiconductor layer 11, which contacts the second layer SL, can have different thicknesses (or widths).

[0114] In addition, the second layer SL can be disposed and / or formed on the interlayer insulating layer ILD disposed on the upper surface of the light-emitting element LD.

[0115] The interlayer insulating layer (ILD) described above can be positioned between the first layer (FL) and the second layer (SL). Due to the ILD, the first layer (FL) and the second layer (SL) can be spaced apart from each other. That is, the first layer (FL) and the second layer (SL) can be electrically and / or physically separated from each other.

[0116] The first region A1 of the upper surface 13b of the second semiconductor layer 13 that contacts the first layer FL, the second region A2 of the upper surface 13b of the second semiconductor layer 13 that contacts the interlayer insulating layer ILD, and the third region A3 of the upper surface 13b of the second semiconductor layer 13 that contacts the second layer SL may have the same thickness (or width). However, this disclosure is not limited thereto, and according to embodiments, the first region A1 of the upper surface 13b of the second semiconductor layer 13 that contacts the first layer FL, the second region A2 of the upper surface 13b of the second semiconductor layer 13 that contacts the interlayer insulating layer ILD, and the third region A3 of the upper surface 13b of the second semiconductor layer 13 that contacts the second layer SL may have different thicknesses (or widths). Furthermore, according to another embodiment, two of the following regions may have the same thickness (or width): the first region A1 of the upper surface 13b of the second semiconductor layer 13 that contacts the first layer FL, the second region A2 of the upper surface 13b of the second semiconductor layer 13 that contacts the interlayer insulating layer ILD, and the third region A3 of the upper surface 13b of the second semiconductor layer 13 that contacts the second layer SL.

[0117] The first region B1 of the lower surface 11a of the first semiconductor layer 11 that contacts the first layer FL, the second region B2 of the lower surface 11a of the first semiconductor layer 11 that contacts the interlayer insulating layer ILD, and the third region B3 of the lower surface 11a of the first semiconductor layer 11 that contacts the second layer SL may have the same thickness (or width). However, this disclosure is not limited thereto, and according to embodiments, the first region B1 of the lower surface 11a of the first semiconductor layer 11 that contacts the first layer FL, the second region B2 of the lower surface 11a of the first semiconductor layer 11 that contacts the interlayer insulating layer ILD, and the third region B3 of the lower surface 11a of the first semiconductor layer 11 that contacts the second layer SL may have different thicknesses (or widths). Furthermore, according to another embodiment, two of the following regions may have the same thickness (or width): the first region B1 of the lower surface 11a of the first semiconductor layer 11 that contacts the first layer FL, the second region B2 of the lower surface 11a of the first semiconductor layer 11 that contacts the interlayer insulating layer ILD, and the third region B3 of the lower surface 11a of the first semiconductor layer 11 that contacts the second layer SL.

[0118] The second layer SL can be electrically connected and / or physically connected to the second power line PL2 via the second contact hole CH2. In this case, the second layer SL can extend to the outside of the positioning embankment pattern of the pixel region PXA (e.g., an area of ​​the second power line PL2 exposed by the second contact hole CH2) and can be connected to the second power line PL2. Therefore, a predetermined signal (or voltage) applied to the second power line PL2 can be transmitted to the second layer SL. Here, the predetermined signal applied to the second power line PL2 can be set to a low potential power, and the predetermined signal (or voltage) applied to the first power line PL1 can be set to a high potential power.

[0119] The first layer FL described above can be formed from p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material and can have a lower bandgap than the second layer SL due to material properties. The Fermi level E of the second semiconductor layer 13, including a p-type GaN semiconductor, is... F It can be slightly higher than the price band E. V The Fermi level E of the first semiconductor layer 11, comprising n-type GaN semiconductor material. F It can be slightly lower than the conduction band E C .

[0120] like Figure 6a As shown, the first region A1 on the upper surface 13b of the second semiconductor layer 13, which includes a first layer FL comprising p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material and a second semiconductor layer 13 comprising a p-type GaN semiconductor material, is in contact with each other. This is possible due to the material properties of the second semiconductor layer 13 in contact with the first layer FL (e.g., Fermi level E). F In contrast, the h+ ions have a low energy barrier.

[0121] In addition, such as Figure 6b As shown, the first region B1 on the lower surface 11a of the first semiconductor layer 11, which includes a first layer FL of p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material and a first semiconductor layer 11 including an n-type GaN semiconductor material, is in contact with each other due to the material properties of the first semiconductor layer 11 in contact with the first layer FL (e.g., Fermi level E). F (And has a high energy barrier relative to electron e-.)

[0122] Since the second SL layer described above is formed of a-IGZO, it can have a higher bandgap than the first FL layer formed of p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material. Typically, when the bandgap of silicon is about 1.2 eV, the bandgap of a-IGZO can be about 3.1 eV. Due to the high bandgap, the second SL layer can exhibit high electron mobility. Figure 6aAs shown, the second semiconductor layer SL formed of a-IGZO and the third region A3 of the second semiconductor layer 13, which is in contact with each other on the upper surface 13b of the second semiconductor layer 13, can have a high energy barrier relative to holes h+ and electrons e- due to the material properties of the second semiconductor layer 13 in contact with the second semiconductor layer SL.

[0123] Furthermore, the second layer SL formed of a-IGZO on the lower surface 11a of the first semiconductor layer 11 and the third region B3 of the first semiconductor layer 11, which includes an n-type GaN semiconductor, are in contact with each other, and may have a low energy barrier relative to electron e- due to the material properties of the first semiconductor layer 11 in contact with the second layer SL.

[0124] In embodiments of this disclosure, due to the Fermi level E of the first semiconductor layer 11 and the second semiconductor layer 13 respectively contacting each of the first layer FL and the second layer SL, F The difference is that electrons e- can be selectively injected into the third region B3 of the lower surface 11a of the first semiconductor layer 11, and holes h+ can be selectively injected into the first region A1 of the upper surface 13b of the second semiconductor layer 13.

[0125] When a predetermined signal (or voltage) is applied to each of the first layer FL and the second layer SL via the first electric field line PL1 and the second electric field line PL2, holes h+ can be injected into the second semiconductor layer 13 through the bonding surface of the first region A1 of the first layer FL and the upper surface 13b of the second semiconductor layer 13, which has a low energy barrier for holes h+. Furthermore, electrons e- can be injected into the first semiconductor layer 11 through the bonding surface of the second layer SL and the third region B3 of the lower surface 11a of the first semiconductor layer 11, which has a low energy barrier for electrons e-. The second semiconductor layer 13 can supply holes h+ to the active layer 12, and the first semiconductor layer 11 can supply electrons e- to the active layer 12. Therefore, electrons e- and holes h+ can recombine in the active layer 12 of each light-emitting element LD to transition to a lower energy level and emit light (or ray) with a corresponding wavelength.

[0126] In embodiments of this disclosure, in the first region B1 of the lower surface 11a of the first semiconductor layer 11 that contacts the first layer FL, electrons e- and holes h+ do not move to the first semiconductor layer 11 due to the material properties of the first semiconductor layer 11. In other words, the flow of electrons e- and holes h+ can be blocked in the first region B1 of the lower surface 11a of the first semiconductor layer 11 that contacts the first layer FL.

[0127] Furthermore, in the third region A3 of the upper surface 13b of the second semiconductor layer 13, which is in contact with the second layer SL, electrons e- and holes h+ do not move to the second semiconductor layer 13 due to the material properties of the second semiconductor layer 13. In other words, the flow of electrons e- and holes h+ can be blocked in the third region A3 of the upper surface 13b of the second semiconductor layer 13, which is in contact with the second layer SL.

[0128] As described above, holes h+ can be injected into the second semiconductor layer 13 through a first region A1 on the upper surface 13b of the second semiconductor layer 13 that contacts the first layer FL, and electrons e- can be injected into the first semiconductor layer 11 through a third region B3 on the lower surface 11a of the first semiconductor layer 11 that contacts the second layer SL. Therefore, each light-emitting element LD can emit light. In embodiments of this disclosure, the first layer FL can be used as a hole injection layer for injecting holes h+ into a region of the second semiconductor layer 13, and the second layer SL can be used as an electron injection layer for injecting electrons e- into a region of the first semiconductor layer 11.

[0129] A second insulating layer INS2 may be disposed and / or formed on the second layer SL. The second insulating layer INS2 may cover the second layer SL to protect it. The second insulating layer INS2 may include silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiON) and aluminum oxide (AlO) x At least one of the metal oxides of ). The first insulating layer INS1 may be a single layer, but may also be a multilayer with two or more layers. In embodiments of this disclosure, the second insulating layer INS2 may comprise the same material as the first insulating layer INS1, but this disclosure is not limited thereto.

[0130] According to the above embodiment, the first layer FL, the interlayer insulating layer ILD, and the second layer SL can be disposed on the light-emitting element LD supplied to the pixel region PXA, and a predetermined signal (or voltage) can be applied to the two ends EP1 and EP2 of each of the light-emitting elements LD through the first layer FL, which is in contact with the first semiconductor layer 11 of each light-emitting element LD, and the second layer SL, which is in contact with the first semiconductor layer 11 of each light-emitting element LD. Therefore, each of the light-emitting elements LD can emit light.

[0131] When using a first layer FL and a second layer SL to drive the light-emitting element LD, the configuration for aligning the light-emitting element LD in the pixel region PXA (e.g., alignment electrodes (or alignment lines)) can be omitted.

[0132] As mentioned above, since the light-emitting element (LD) can be aligned in the pixel area PXA without alignment electrodes (or alignment lines), the manufacturing process of the light-emitting element (LD) can be simplified and the manufacturing cost can be reduced.

[0133] Furthermore, since the configuration for aligning the light-emitting element LD in the pixel region PXA is omitted, the size of the pixel PXL can be reduced by minimizing the process margin of the pixel region PXA. Therefore, achieving high resolution for the light-emitting device becomes easier.

[0134] Figure 7 This is a cross-sectional view showing the unit emitting region of a light-emitting device according to an embodiment of the present disclosure, and is along... Figure 3 A sectional view taken by line I-I'.

[0135] about Figure 7 The embodiments described herein primarily focus on the differences from the embodiments described above to avoid repetition. Parts not specifically described in this disclosure are consistent with the embodiments described above, and the same reference numerals indicate the same components, and similar reference numerals indicate similar components.

[0136] refer to Figures 1a to 7 The display element section DPL, including the light-emitting element LD, can be disposed in a pixel area PXA in which a pixel PXL is disposed (or prepared). The display element section DPL may also include a first conductive line CL1 and a second conductive line CL2.

[0137] Specifically, the display element section DPL may include a first conductive line CL1 disposed on a barrier layer BRL disposed on a substrate SUB, a first insulating layer INS1 disposed on the first conductive line CL1, a light-emitting element LD disposed on the first insulating layer INS1, a first layer FL disposed on the light-emitting element LD, an interlayer insulating layer ILD disposed on the first layer FL, a second layer SL disposed on the interlayer insulating layer ILD, a second insulating layer INS2 disposed on the second layer SL, and a second conductive line CL2 disposed on the second insulating layer INS2.

[0138] A first conductive line CL1 may be disposed and / or formed between the barrier layer BRL and the first insulating layer INS1. The first conductive line CL1 may comprise a metal or metal oxide, and may be used alone or in combination, such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, indium tin oxide (ITO), etc., but is not limited thereto. In embodiments of this disclosure, the first conductive line CL1 may comprise indium tin oxide (ITO). A predetermined signal (or voltage) may be applied to the first conductive line CL1.

[0139] The second conductive line CL2 may be disposed and / or formed on the second insulating layer INS2. The second conductive line CL2 may include the same material as the first conductive line CL1, but this disclosure is not limited thereto. According to embodiments, the second conductive line CL2 may include a material different from the material of the first conductive line CL1. In embodiments of this disclosure, the second conductive line CL2 may include indium tin oxide (ITO). A predetermined signal (or voltage) may be applied to the second conductive line CL2. The predetermined signal (or voltage) applied to the first conductive line CL1 and the predetermined signal (or voltage) applied to the second conductive line CL2 may be different from each other, and for example, the signal applied to each of the first conductive line CL1 and the second conductive line CL2 may be driving power for driving pixel PXL. Specifically, the predetermined signal (or voltage) applied to the first conductive line CL1 may be set to a low potential power, and the predetermined signal (or voltage) applied to the second conductive line CL2 may be set to a high potential power. However, this disclosure is not limited thereto, and according to embodiments, the predetermined signal (or voltage) applied to the first conductive line CL1 may be the same as the predetermined signal (or voltage) applied to the second power line PL2.

[0140] When a predetermined signal (or voltage) is applied to each of the first conductive line CL1 and the second conductive line CL2, between the first conductive line CL1 and the second conductive line CL2, Figure 7 An electric field can be formed in the direction of the arrow shown. For example, an electric field can be formed in the direction from the first conductive line CL1 to the second conductive line CL2. In this case, the HE11 mode of the light emitted from the active layer 12 of the light-emitting element LD can be enhanced. The HE11 mode can include the HE11x mode and the HE11y mode in which the polarization states of the light are perpendicular to each other within the single-mode fiber.

[0141] In embodiments of this disclosure, the HE11x mode can refer to a state in which light emitted from the active layer 12 of each light-emitting element LD is polarized along the direction of the length L of each light-emitting element LD. For example, the HE11x mode can refer to a state in which light emitted from the active layer 12 of each light-emitting element LD is polarized along a first direction DR1. In embodiments of this disclosure, the HE11y mode can refer to a state in which light emitted from the active layer 12 of each light-emitting element LD is polarized along a direction intersecting the direction of the length L of each light-emitting element LD. For example, the HE11y mode can refer to a state in which light emitted from the active layer 12 of each light-emitting element LD is polarized along a third direction DR3.

[0142] When a predetermined signal (or voltage) is applied to each of the first conductive line CL1 and the second conductive line CL2, and an electric field is formed in the direction from the first conductive line CL1 to the second conductive line CL2, the HE11x mode can be enhanced. Therefore, the amount (or intensity) of light emitted from the active layer 12 of each light-emitting element LD and polarized in the first direction DR1 can be increased. For example, the amount (or intensity) of light traveling from the active layer 12 of each light-emitting element LD to each of the first semiconductor layer 11 and the second semiconductor layer 13 in the first direction DR1 can be increased. Therefore, the light output efficiency of each light-emitting element LD can be further improved.

[0143] Figure 8 This is a schematic plan view showing the unit emission region of a light-emitting device according to an embodiment of the present disclosure, and Figure 9 Is with Figure 8 The sectional view corresponding to line II-II'.

[0144] about Figure 8 and Figure 9 The implementation method described herein mainly focuses on the differences from the implementation method described above, in order to avoid repetitive descriptions.

[0145] refer to Figures 1a to 2c , Figure 8 as well as Figure 9 The display element part DPL, including the light-emitting element LD, can be set in the pixel area PXA in which a pixel PXL is set (or prepared)

[0146] The display element section DPL may include a first conductive line CL1, a first insulating layer INS1, a light-emitting element LD, a first layer FL, an interlayer insulating layer ILD, a second layer SL, a second insulating layer INS2, and a second conductive line CL2. Furthermore, the display element section DPL may also include a capping layer CVL disposed on and / or formed on the second conductive line CL2.

[0147] A capping layer CVL can be disposed and / or formed on the second conductive line CL2 to overlap with each of the light-emitting elements LD. The capping layer CVL can serve as a light-guiding member for directing light emitted from each of the light-emitting elements LD to concentrate in a specific direction of the pixel region PXA. In embodiments of this disclosure, the capping layer CVL can be formed of a conductive material (or substance) having a constant reflectivity. The conductive material (or substance) can include an opaque metal that facilitates the guidance of light emitted from the light-emitting element LD in a specific direction (e.g., a desired direction) by reflecting or scattering light. The opaque metal can include metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or alloys thereof. According to embodiments, the capping layer CVL can include a transparent conductive material. The transparent conductive material can include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), conductive polymers such as PEDOT, etc. When the capping CVL comprises a transparent conductive material, it may additionally include a separate conductive layer formed of an opaque metal for guiding light emitted from the light-emitting element LD in a specific direction (e.g., a desired direction). However, the material of the capping CVL is not limited to the materials described above.

[0148] Furthermore, according to the implementation method, a grating may be formed on the inner or outer surface of the capping CVL to generate an optical path more effectively.

[0149] As described above, when the capping layer CVL is disposed in a pixel region PXA in which each pixel PXL is disposed (or prepared), the light emitted from the light-emitting element LD can be concentratedly guided in a specific direction (e.g., a desired direction). In this case, the direction of the light emitted from each pixel PXL can be substantially the same, and thus the light output deviation between each pixel PXL and its adjacent pixels PXL can be reduced. Therefore, the light-emitting device can have a uniform light output distribution throughout the entire region.

[0150] Figure 10 This illustrates a display device according to an embodiment of the present disclosure and schematically shows its use. Figure 1a and Figure 1b The diagram shows a plan view of an example display device in which the light-emitting element serves as the light source.

[0151] exist Figure 10 For simplicity, the structure of the display device is briefly shown based on the display area DA of the displayed image. However, according to embodiments, the display device may also include at least one drive circuit section (e.g., scan driver, data driver, etc.) and / or multiple signal lines, not shown.

[0152] refer to Figure 1a , Figure 1b and Figure 10 The display device according to the embodiments of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB, a driver (not shown) for driving the pixels PXL, and a line (not shown) connecting the pixels PXL and the driver.

[0153] Based on the method of driving the light-emitting element (LD), display devices can be divided into passive matrix display devices and active matrix display devices. For example, when the display device is implemented as an active matrix type, each pixel PXL may include a driving transistor that controls the amount of current supplied to the light-emitting element (LD), a switching transistor that transmits data signals to the driving transistor, etc.

[0154] The substrate SUB can include a transparent insulating material and can transmit light.

[0155] The substrate SUB can be a rigid substrate or a flexible substrate.

[0156] For example, a rigid substrate can be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate.

[0157] The flexible substrate can be a film substrate or a plastic substrate comprising a polymeric organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0158] The material applied to the substrate SUB can preferably have resistance to high processing temperatures (or heat resistance) during the manufacturing process of the display device.

[0159] The substrate SUB may include a display area DA and a non-display area NDA disposed around the display area DA. The display area DA includes at least one pixel region in which each pixel PXL is disposed. According to an embodiment, the display area DA may be disposed in the central region of the display device, and the non-display area NDA may be disposed in the edge region of the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and according to an embodiment, the positions of the display area DA and the non-display area NDA may be changed.

[0160] The display area DA can be the area where the pixel PXL is set to display an image. The non-display area NDA can be a portion of the area where the driver for driving the pixel PXL is set and the line connecting the pixel PXL and the driver is set.

[0161] The display area DA can have various shapes. For example, the display area DA can be set into various shapes, such as a polygon with closed shapes including straight lines, a circle or ellipse with curved lines, a semicircle or semi-ellipse with lines and curves.

[0162] The non-display area NDA can be located at at least one side of the display area DA. In embodiments of this disclosure, the non-display area NDA can surround the display area DA.

[0163] Each of the pixels PXL can be disposed on the substrate SUB in the display area DA. In embodiments of this disclosure, the pixels PXL can be arranged in a strip or penTile array structure in the display area DA, but this disclosure is not limited thereto.

[0164] Each pixel PXL may include at least one light-emitting element (LD) driven by corresponding scan signals and data signals. The LD may have dimensions as small as micrometers or nanometers and may be spaced apart from adjacent LDs at a predetermined distance, but this disclosure is not limited thereto. The LD may be configured as the light source for each pixel PXL.

[0165] Each of the pixels PXL can be driven by predetermined signals (e.g., scan signals and data signals) and / or predetermined power (e.g., first drive power and second drive power). However, the type of light-emitting element LD that can be used as the light source for each pixel PXL is not limited to this.

[0166] In embodiments of this disclosure, the color, type, number, etc. of the pixel PXL are not particularly limited, and for example, the color of the light emitted from each pixel PXL can be changed differently.

[0167] The driver can control the driving of each pixel PXL by providing predetermined signals and predetermined power to each pixel PXL via a line. Figure 10 For ease of description, the lines have been omitted.

[0168] The driver may include a timing controller, a scan driver that provides scan signals to pixel PXL via scan lines, a transmit driver that provides transmit control signals to pixel PXL via transmit control lines, and a data driver that provides data signals to pixel PXL via data lines. The timing controller can control the scan driver, transmit driver, and data driver.

[0169] The display device described above may include multiple stretchable portions to realize a retractable display device. In the following, references... Figure 11a and Figure 11b Describes multiple stretching sections.

[0170] Figure 11aand Figure 11b yes Figure 10 A magnified plan view of part of EA3.

[0171] refer to Figure 1a , Figure 1b , Figure 10 , Figure 11a and Figure 11b The display device may include a substrate SUB provided with pixels PXL.

[0172] In embodiments of this disclosure, the substrate SUB may include a plurality of island-shaped members IS and a bridge member BR for connecting adjacent island-shaped members IS in a first direction DR1 and a second direction DR2. Furthermore, the substrate SUB may include a cutout V formed by removing a region of the substrate SUB. In embodiments of this disclosure, the island-shaped members IS, the bridge member BR, and the cutout V may be configured to accommodate a plurality of stretchable portions STU of the display device. Each stretchable portion STU may correspond to a basic stretchable portion of the stretchable display device.

[0173] Each island IS can be an island-shaped substrate SUB, and can be spaced apart from adjacent (or neighboring) island IS in the first direction DR1 with a cutout V inserted therebetween. Furthermore, each island IS can be spaced apart from adjacent (or neighboring) island IS in the second direction DR2 with a cutout V inserted therebetween. At least one pixel PXL, including an emission region EMA from which red, blue, green, and / or white light is emitted, can be positioned (or disposed) on each island IS.

[0174] A bridge-shaped element BR can be disposed between two island-shaped elements IS spaced apart in a first direction DR1 and between two island-shaped elements IS spaced apart in a second direction DR2. The bridge-shaped element BR can be a region of the substrate SUB connecting two adjacent island-shaped elements IS. Lines for transmitting power and / or signals to pixels PXL disposed in each island-shaped element IS can be disposed on the bridge-shaped element BR. Due to the lines disposed on the bridge-shaped element BR, pixels PXL positioned in each island-shaped element IS can be driven while receiving power and / or signals.

[0175] The shape and area (or size) of the notch V can be changed to accommodate the stretching of the display device. The notch V can be positioned between two adjacent island members IS in the first direction DR1 and the second direction DR2, between an island member IS and a bridge member BR, and between two adjacent bridge members BR in the first direction DR1 and the second direction DR2. The notch V can be formed to pass through the substrate SUB. The notch V can provide a separation area between the island members IS, reducing the weight of the substrate SUB and improving its flexibility. Furthermore, by changing the shape of the notch V when the substrate SUB undergoes bending, curling, stretching, etc., stress generation during substrate SUB deformation can be effectively reduced, thereby preventing abnormal deformation of the substrate SUB and improving durability.

[0176] The notch V can be formed by removing a region of the substrate SUB in an etching process or the like, but this disclosure is not limited thereto. According to an embodiment, when manufacturing the substrate SUB, the substrate SUB can be formed to include the notch V. As another embodiment, the notch V can be formed by patterning the substrate SUB after forming the island-shaped member IS and the bridge-shaped member BR. The method of forming the notch V in the substrate SUB is not limited to the embodiments described above, and the notch V can be formed by various methods.

[0177] The display device can be stretched while the shape and area (or size) of the notches V included in the substrate SUB are changed. When viewed in a plan view, the display device can be stretched in various directions (e.g., first direction DR1, second direction DR2, tilt direction of each of the first direction DR1 and second direction DR2, direction opposite to the first direction DR1 (e.g., left direction), direction opposite to the second direction DR2 (e.g., upward direction), etc.). When the display device is stretched, the shape and / or area (or size) of each island IS can remain almost unchanged, and only its position can change. Therefore, when the display device is stretched, the pixels PXL positioned on each of the island IS can be preserved without damage. However, when the display device is stretched, the shape and / or area (or size) of the bridge BR connecting two adjacent island IS can change.

[0178] exist Figure 11a and Figure 11b In this embodiment, each island-shaped element IS resembles a quadrilateral shape, but this disclosure is not limited to this, and the shape of the island-shaped element IS can be modified in various ways. Furthermore, the shape of each bridge-shaped element BR connecting two adjacent island-shaped elements IS is not limited to... Figure 11a and Figure 11b The shape shown can be modified in various ways.

[0179] Figure 12a and Figure 12b It is shown that, according to the embodiment, it includes Figure 10 The circuit diagram shown illustrates the electrical connections between components within a single pixel.

[0180] For example, Figure 12a and Figure 12b Electrical connections between components included in a pixel PXL, according to different embodiments, can be applied to an active display device. However, the types of components included in a pixel PXL that can be applied to embodiments of this disclosure are not limited thereto.

[0181] exist Figure 12a and Figure 12b In China, not only Figure 10 Each of the pixels shown includes a component, and the area where the component is located is referred to as pixel PXL. According to an embodiment, Figure 12a and Figure 12b Each pixel PXL shown can be Figure 10 The display device includes any one of the pixels PXL, and the pixels PXL may have substantially the same or similar structure.

[0182] First, refer to Figure 1a , Figure 1b , Figure 10 , Figure 12a and Figure 12b A pixel PXL (hereinafter referred to as a "pixel") may include an emission unit EMU for emitting light. In addition, the pixel PXL may optionally include pixel circuitry 144 for driving the emission unit EMU and improving the light output efficiency of the light emitted from the emission unit EMU.

[0183] According to an embodiment, the transmitting unit (EMU) may include a plurality of light-emitting elements (LDs) disposed between a first power line PL1 to which a first driving power VDD is applied and a second power line PL2 to which a second driving power VSS is applied. One end of each of the two ends of the light-emitting element LD (e.g., the second semiconductor layer 13) may be connected to the first driving power VDD via a first layer FL, and the other end of each of the two ends of the light-emitting element LD (e.g., the first semiconductor layer 11) may be connected to the second driving power VSS via a second layer SL.

[0184] The first driving power VDD and the second driving power VSS can have different potentials. For example, the first driving power VDD can be set to a high potential, and the second driving power VSS can be set to a low potential. In this case, the potential difference between the first driving power VDD and the second driving power VSS can be set to the threshold voltage of the light-emitting element LD or a higher voltage during the emission period of pixel PXL.

[0185] As described above, each light-emitting element (LD) disposed between a first electric power line PL1 and a second electric power line PL2, which are respectively supplied with signals (or voltages) at different potentials, can be configured as an effective light source. This effective light source can be focused to form the emission unit (EMU) of pixel PXL.

[0186] The light-emitting element (LD) of the transmitting unit EMU can emit light with a brightness corresponding to the driving current supplied through the corresponding pixel circuit 144. For example, the pixel circuit 144 can supply the transmitting unit EMU with a driving current corresponding to the grayscale value of the corresponding frame data during each frame period. The driving current supplied to the transmitting unit EMU can be shunted and flow to the light-emitting element (LD). Therefore, each of the light-emitting elements (LD) can emit light with a brightness corresponding to the current flowing through the light-emitting element (LD), and thus the transmitting unit EMU can emit light with a brightness corresponding to the driving current.

[0187] Pixel circuit 144 can be connected to the scan line (e.g., the i-th scan line Si) and data line (e.g., the j-th data line Dj) of the corresponding pixel PXL. For example, when pixel PXL is located in the i-th (i is a positive integer) row and j-th (j is a positive integer) column of display area DA, pixel circuit 144 of pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of display area DA. According to the implementation, as Figure 12a As shown, the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. However, the structure of the pixel circuit 144 is not limited to... Figure 12a The implementation shown is as follows.

[0188] refer to Figure 12a The pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0189] The first terminal of the second transistor T2 (switching transistor) can be connected to a data line (e.g., the j-th data line Dj), and its second terminal can be connected to the first node N1. Here, the first and second terminals of the second transistor T2 can be different terminals, and for example, when the first terminal is the source electrode, the second terminal can be the drain electrode. Furthermore, the gate electrode of the second transistor T2 can be connected to a scan line (e.g., the i-th scan line Si).

[0190] When a scan signal is supplied from a scan line (e.g., the i-th scan line Si) at which the second transistor T2 can be turned on (e.g., a low voltage), the second transistor T2 can be turned on to electrically connect the data line (e.g., the j-th data line Dj) and the first node N1 to each other. At this time, the data signal of the corresponding frame is supplied to the data line (e.g., the j-th data line Dj), and thus the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is charged in the storage capacitor Cst.

[0191] The first terminal of the first transistor T1 (driving transistor) can be connected to the first driving power VDD, and its second terminal can be electrically connected to the first electrode of each of the light-emitting elements LD. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 controls the amount of driving current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0192] One electrode of the storage capacitor Cst can be connected to the first drive power VDD, and its other electrode can be connected to the first node N1. The storage capacitor Cst is charged with the voltage corresponding to the data signal supplied to the first node N1 and maintains the charged voltage until the data signal of the next frame is supplied.

[0193] Figure 12a A pixel circuit 144 is shown, comprising a second transistor T2 for transmitting data signals to a pixel PXL, a storage capacitor Cst for storing data signals, and a first transistor T1 for supplying a drive current corresponding to the data signals to a light-emitting element LD.

[0194] However, this disclosure is not limited thereto, and the structure of the pixel circuit 144 can be modified and implemented in different ways. For example, the pixel circuit 144 may also include other circuit elements, such as at least one transistor element (such as a transistor element for compensating the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the light emission time of the light-emitting element LD), or a boost capacitor for boosting the voltage of the first node N1.

[0195] In addition, Figure 12a In the pixel circuit 144, the transistors (e.g., the first transistor T1 and the second transistor T2) are P-type transistors, but this disclosure is not limited thereto. That is, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 can be changed to an N-type transistor.

[0196] like Figure 12bAs shown, pixel circuit 144 can be connected to the scan line (e.g., the i-th scan line Si) and data line (e.g., the j-th data line Dj) of pixel PXL. For example, when pixel PXL is set in the i-th row and j-th column of display area DA, the pixel circuit 144 of the corresponding pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of display area DA.

[0197] Furthermore, according to an embodiment, the pixel circuit 144 may also be connected to at least one other scan line. For example, the pixel PXL disposed in the i-th row of the display area DA may also be connected to the (i-1)-th scan line Si-1 and / or the (i+1)-th scan line Si+1. Furthermore, according to an embodiment, in addition to the first driving power VDD and the second driving power VSS, the pixel circuit 144 may also be connected to a third power. For example, the pixel circuit 144 may also be connected to the initialization power Vint.

[0198] The pixel circuit 144 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0199] One electrode (e.g., the source electrode) of the first transistor T1 (driving transistor) can be connected to the first driving power VDD via the fifth transistor T5, and its other electrode (e.g., the drain electrode) can be connected to one side of the light-emitting element LD via the sixth transistor T6. Furthermore, the gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 controls the driving current flowing through the light-emitting element LD between the first driving power VDD and the second driving power VSS in response to the voltage of the first node N1.

[0200] A second transistor T2 (a switching transistor) can be connected between the j-th data line Dj connected to pixel PXL and the source electrode of the first transistor T1. Furthermore, the gate electrode of the second transistor T2 can be connected to the i-th scan line Si connected to pixel PXL. When a scan signal with a gate turn-on voltage (e.g., a low voltage) is supplied from the i-th scan line Si, the second transistor T2 can be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj is transmitted to the first transistor T1.

[0201] The third transistor T3 can be connected between the drain electrode of the first transistor T1 and the first node N1. Furthermore, the gate electrode of the third transistor T3 can be connected to the i-th scan line Si. When a scan signal with a gate-on voltage is supplied from the i-th scan line Si, the third transistor T3 can be turned on to electrically connect the drain electrode of the first transistor T1 and the first node N1 to each other.

[0202] A fourth transistor T4 can be connected between the first node N1 and the initialization power line to which the initialization power Vint is applied. Furthermore, the gate electrode of the fourth transistor T4 can be connected to the previous scan line (e.g., the (i-1)th scan line Si-1). When a scan signal with a gate-on voltage is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 can be turned on to transmit the initialization power Vint voltage to the first node N1. Here, the initialization power Vint can have a voltage equal to or less than the minimum voltage of the data signal.

[0203] The fifth transistor T5 can be connected between the first drive power VDD and the first transistor T1. Furthermore, the gate electrode of the fifth transistor T5 can be connected to a corresponding emitter control line (e.g., the i-th emitter control line Ei). The fifth transistor T5 can be turned off when an emitter control signal with a gate cutoff voltage is supplied to the i-th emitter control line Ei, and can be turned on under other conditions.

[0204] The sixth transistor T6 can be connected between the first transistor T1 and one end of the light-emitting element LD (which is connected to the second node N2). Furthermore, the gate electrode of the sixth transistor T6 can be connected to the i-th emitter control line Ei. The sixth transistor T6 can be turned off when the emitter control signal with a gate cutoff voltage is supplied to the i-th emitter control line Ei, and can be turned on under other conditions.

[0205] The seventh transistor T7 can be connected between one end of the light-emitting element LD and the initialization power line to which the initialization power Vint is applied. Furthermore, the gate electrode of the seventh transistor T7 can be connected to any of the next scan lines (e.g., the (i+1)th scan line Si+1). The seventh transistor T7 can be turned on when a scan signal with a gate on-state voltage is supplied to the (i+1)th scan line Si+1 to supply the initialization power Vint voltage to one end of the light-emitting element LD.

[0206] The storage capacitor Cst can be connected between the first drive power VDD and the first node N1. The storage capacitor Cst can store the data signal supplied to the first node N1 and the voltage corresponding to the threshold voltage of the first transistor T1 during each frame period.

[0207] The structure of the pixel PXL applicable to this disclosure is not limited to Figure 12a and Figure 12b The embodiments shown are illustrated, and the corresponding pixel PXL can have various structures.

[0208] Figure 13 It is shown schematically. Figure 10 A planar view of one pixel in the pixel diagram shown. Figure 14 It is along Figure 13 The sectional view taken from line III-III'. Figure 15 yes Figure 14 Enlarged plan view of part of EA4, and Figure 16 It is implemented according to another embodiment. Figure 13 A schematic plan view of the capping layer shown.

[0209] Figures 13 to 16 The structure of a pixel PXL is simplified and illustrated, such as showing each electrode as a single electrode layer and each insulating layer as a single insulating layer, but this disclosure is not limited thereto.

[0210] Furthermore, in embodiments of this disclosure, the term "formed and / or disposed on the same layer" may mean formed in the same process, and the term "formed and / or disposed on different layers" may mean formed in different processes.

[0211] Furthermore, in embodiments of this disclosure, the term "connection" may refer to both electrical and physical connections in an inclusive manner between two configurations.

[0212] refer to Figure 1a , Figure 1b , Figure 10 as well as Figures 13 to 16 The display device according to embodiments of the present disclosure may include a substrate SUB, a line portion and a plurality of pixels PXL.

[0213] In embodiments of this disclosure, the substrate SUB can be a stretchable substrate formed of a material that is flexible to bend or fold, and can have a single-layer or multi-layer structure. For example, the substrate SUB can include polymeric materials such as silicone elastomers or polyurethanes, but this disclosure is not limited thereto.

[0214] The substrate SUB may include a display area DA and a non-display area NDA disposed around the display area DA, wherein the display area DA includes at least one pixel area PXA in which a pixel PXL is disposed.

[0215] Each pixel PXL may include an island element IS and at least one bridge element BR connected to the island element IS, the island element IS including at least one light-emitting element LD. The bridge element BR may include first bridge elements BR1 to fourth bridge elements BR4 respectively connected to the four sides of the island element IS of the corresponding pixel PXL. However, the number of bridge elements BR is not limited thereto. In embodiments of this disclosure, the island element IS may include a pixel region PXA in which the pixel PXL is disposed.

[0216] The first bridge element BR1 and the third bridge element BR3 can be regions of the substrate SUB extending in the second direction DR2 or the "vertical direction", and when viewed in a plan view, they can connect two adjacent (or neighboring) pixels PXL in the second direction DR2. The second bridge element BR2 and the fourth bridge element BR4 can be regions of the substrate SUB extending in the first direction DR1 or the "horizontal direction", and when viewed in a plan view, they can connect two adjacent (or neighboring) pixels PXL in the first direction DR1.

[0217] The pixel region PXA, in which each pixel PXL is provided (or prepared), may include an emission region EMA and a peripheral region surrounding the emission region EMA, in which light is emitted. In embodiments of this disclosure, the peripheral region may include a non-emission region in which no light is emitted.

[0218] The line portion may include multiple signal lines that transmit signals (or voltages) to each pixel PXL. These signal lines may include, for example, scan lines (e.g., the i-th scan line Si) that transmit scan signals to each pixel PXL, data lines (e.g., the j-th scan line Dj) that transmit data signals to each pixel PXL, a first power line PL1 that transmits a first driving power VDD to each pixel PXL, a second power line PL2 that transmits a second driving power VSS to each pixel PXL, and so on. However, this disclosure is not limited thereto, and according to embodiments, in addition to the signal lines described above, the line portion may also include signal lines that transmit other signals.

[0219] The substrate SUB, the pixel circuit section PCL, and the display element section DPL can be disposed and / or formed in the pixel area PXA of each pixel PXL.

[0220] For the sake of convenience, the pixel circuit section PCL will be described first, and then the display element section DPL will be described.

[0221] The pixel circuit section PCL may include a buffer layer BFL, a pixel circuit 144, and a protective layer PSV.

[0222] The buffer layer (BFL) can prevent impurities from spreading to the pixel circuitry (reference). Figure 12a and Figure 12b The transistors included in “144”. The buffer layer BFL can be related to the reference. Figure 4 The described barrier layer BRL has the same configuration.

[0223] Pixel circuit 144 may include at least one transistor and a storage capacitor Cst. Here, the transistor may include a driving transistor Tdr that controls the driving current of each of the light-emitting elements LD and a switching transistor (not shown) connected to the driving transistor Tdr. The switching transistor described above may have the same characteristics as referenced. Figure 12a and Figure 12b The second transistor T2 described has the same configuration. However, the configuration included in the pixel circuit 144 is not limited to the above-described embodiments, and in addition to the driving transistor Tdr and the switching transistor, the pixel circuit 144 may also include circuit elements that perform another function. In the following embodiments, when one of the driving transistor Tdr and the switching transistor is mentioned casually or collectively, the driving transistor Tdr and the switching transistor are referred to as one transistor T or multiple transistors T.

[0224] Each of the transistors T may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be either a source electrode or a drain electrode, and the second terminal DE may be the other electrode. For example, when the first terminal SE is the source electrode, the second terminal DE may be the drain electrode.

[0225] A transistor semiconductor pattern SCL can be disposed and / or formed on a buffer layer BFL. The transistor semiconductor pattern SCL may include a first contact region contacting a first terminal SE and a second contact region contacting a second terminal DE. The region between the first and second contact regions may be a channel region. The transistor semiconductor pattern SCL can be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The channel region is an undoped semiconductor pattern and may be an intrinsic semiconductor. The first and second contact regions may be doped semiconductor patterns.

[0226] The gate electrode GE may be disposed and / or formed on the transistor semiconductor pattern SCL, and the first gate insulating layer GI1 is interposed between the gate electrode GE and the transistor semiconductor pattern SCL.

[0227] The first gate insulating layer GI1 may be an inorganic insulating layer comprising an inorganic material. For example, the first gate insulating layer GI1 may comprise silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiON) and aluminum oxide (AlO) x The material of the first gate insulating layer GI1 is at least one of the metal oxides described above. However, the material of the first gate insulating layer GI1 is not limited to the embodiments described above. According to an embodiment, the first gate insulating layer GI1 may be formed of an organic insulating layer including organic materials. The first gate insulating layer GI1 may be a single layer, but may also be a multilayer consisting of at least two layers.

[0228] The first terminal SE and the second terminal DE can each contact the first contact area and the second contact area of ​​the transistor semiconductor pattern SCL through contact holes that pass sequentially through the first gate insulating layer GI1 and the second gate insulating layer GI2.

[0229] The second gate insulating layer GI2 can be an inorganic insulating layer comprising inorganic materials. For example, the second gate insulating layer GI2 may comprise silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiON) and aluminum oxide (AlO) x The second gate insulating layer GI2 may comprise the same material as the first gate insulating layer GI1. The second gate insulating layer GI2 may be a single layer, but may also be a multilayer structure with at least two layers.

[0230] In the above embodiments, the first terminal SE and the second terminal DE of each of the transistors T are described as being electrically connected to separate electrodes of the transistor semiconductor pattern SCL, but this disclosure is not limited thereto. According to an embodiment, the first terminal SE of each of the transistors T may be one of a first contact region and a second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL, and the second terminal DE of each of the transistors T may be the other of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. In this case, the second terminal DE of each of the transistors T can be electrically connected to the light-emitting element LD of the corresponding pixel PXL via a separate connection tool such as a bridging electrode or a contact electrode.

[0231] In embodiments of this disclosure, the transistor T included in the pixel circuit 144 may be configured as an LTPS thin-film transistor, but this disclosure is not limited thereto, and may also be configured as an oxide semiconductor thin-film transistor according to embodiments. Furthermore, the case where the transistor T is a thin-film transistor with a top-gate structure is described as an example, but this disclosure is not limited thereto. According to embodiments, the transistor T may be a thin-film transistor with a bottom-gate structure.

[0232] The first electric field line PL1 and the second electric field line PL2 may be disposed and / or formed on the second gate insulating layer GI2.

[0233] The first electric field line PL1 and the second electric field line PL2 can be spaced apart from each other at a predetermined distance on the second gate insulating layer GI2, and can be electrically isolated from each other. A first driving power VDD can be applied to the first electric field line PL1, and a second driving power VSS can be applied to the second electric field line PL2.

[0234] The protective layer PSV can be disposed and / or formed on the first power line PL1, the second power line PL2, and the transistor T.

[0235] A protective layer PSV can be disposed on the second gate insulating layer GI2. The protective layer PSV can be disposed in the form of an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on an inorganic insulating layer. Here, the inorganic insulating layer can include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiON) and aluminum oxide (AlO) x The organic insulating layer may include at least one of the following metal oxides: acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. In embodiments of this disclosure, the protective PSV layer may be formed from the organic insulating layer.

[0236] The protective layer PSV may include first contact holes CH1 to fourth contact holes CH4. The first contact hole CH1 may expose a portion of the first power line PL1, the second contact hole CH2 may expose a portion of the second power line PL2, the third contact hole CH3 may expose a portion of the drive transistor Tdr (e.g., a portion of the second terminal DE), and the fourth contact hole CH4 may expose another portion of the second power line PL2.

[0237] Next, the display element part DPL of each pixel PXL will be described.

[0238] The display element section DPL may include a first bridging pattern BRP1 and a second bridging pattern BRP2, a dam pattern BNK, a light-emitting element LD, a first layer FL and a second layer SL, an interlayer insulating layer ILD, a first conductive line CL1 and a second conductive line CL2, a first insulating layer INS1 and a second insulating layer INS2, and a capping layer CVL disposed on the pixel circuit section PCL.

[0239] The first bridging pattern BRP1 and the second bridging pattern BRP2 can be set apart from each other in the pixel region PXA of each pixel PXL. In an exemplary embodiment, the first bridging pattern BRP1 and the second bridging pattern BRP2 can be set and / or formed on the protective layer PSV.

[0240] The first bridging pattern BRP1 can be connected to the second terminal DE of the driving transistor Tdr through the third contact hole CH3 passing through the protective layer PSV. The second bridging pattern BRP2 can be connected to the first power line PL1 through the first contact hole CH1 passing through the protective layer PSV. Therefore, the first driving power VDD applied to the first power line PL1 can be transmitted to the second bridging pattern BRP2, and the predetermined signal (or voltage) applied to the driving transistor Tdr can be transmitted to the first bridging pattern BRP1.

[0241] The first conductive line CL1 may be disposed and / or formed on the same layer as the first bridging pattern BRP1 and the second bridging pattern BRP2. For example, the first conductive line CL1 may be disposed on the protective layer PSV and spaced apart from the first bridging pattern BRP1 and the second bridging pattern BRP2.

[0242] The first bridging pattern BRP1, the second bridging pattern BRP2, and the first conductive line CL1 may comprise the same material. The first bridging pattern BRP1, the second bridging pattern BRP2, and the first conductive line CL1 may comprise metals or metal oxides, and for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, ITO, etc., may be used alone or in combination, but this disclosure is not limited thereto. In embodiments of this disclosure, the first bridging pattern BRP1, the second bridging pattern BRP2, and the first conductive line CL1 may comprise indium tin oxide (ITO).

[0243] The first conductive line CL1 can be connected to the second power line PL2 through the second contact hole CH2 and the fourth contact hole CH4 passing through the protective layer PSV. Therefore, the second driving power VSS applied to the second power line PL2 can be transmitted to the first conductive line CL1.

[0244] A first insulating layer INS1 may be disposed and / or formed on the first conductive line CL1. In embodiments of this disclosure, the first insulating layer INS1 corresponds to the reference... Figure 4 The first insulating layer INS1 has the same configuration as described, and therefore its description is omitted.

[0245] The first insulating layer INS1 may cover a portion of the first conductive line CL1, for example, the portion of the first conductive line CL1 other than the portion that contacts the second contact hole CH2 and the fourth contact hole CH4 of the protective layer PSV.

[0246] A dam pattern BNK may be disposed and / or formed in the peripheral region of the pixel region PXA of each pixel PXL. The dam pattern BNK may surround at least one side of the peripheral region included in the pixel region PXA of each pixel PXL. The dam pattern BNK may be a structure defining (or separating) an emission region EMA of each pixel PXL and each of its adjacent pixels PXL, and may be, for example, a pixel defining layer. The dam pattern BNK may be configured to include at least one light-blocking material and / or a reflective material to prevent light leakage defects in which light (or rays) leaks between each pixel PXL and its adjacent pixels PXL. According to an embodiment, a reflective material layer may be formed on the dam pattern BNK to further improve the efficiency of light emitted from each pixel PXL.

[0247] The light-emitting element (LD) can be disposed and / or formed on a first insulating layer INS1 in a region (e.g., the central region of the pixel region PXA in a planar view) surrounded by a dam pattern BNK and located in the pixel region PXA. Each of the light-emitting elements (LDs) can be a light-emitting element comprising an emission stack pattern 10 in which a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 are sequentially stacked along a length L, and an insulating film 14 surrounding the outer peripheral surface (or surface) of the emission stack pattern 10, and manufactured by an etching method.

[0248] Each of the light-emitting elements (LDs) can be disposed on the first insulating layer INS1 such that the direction of the length L is parallel to the first direction DR1.

[0249] The light-emitting element (LD) can be input into the pixel region PXA by inkjet printing, slot coating, or other various methods. Each of the light-emitting elements (LD) may have a first end EP1 and a second end EP2 in the direction of length L. The first end EP1 of each of the light-emitting elements (LD) may be a first semiconductor layer 11, and the second end EP2 of each of the light-emitting elements (LD) may be a second semiconductor layer 13.

[0250] The first FL layer can be disposed and / or formed on the light-emitting element LD. In embodiments of this disclosure, the first FL layer may comprise a p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material doped with a p-type dopant (such as Mg).

[0251] The first layer FL can contact both ends EP1 and EP2 of each of the light-emitting elements LD. For example, the first layer FL can directly contact the first region B1 of the first semiconductor layer 11 of each light-emitting element LD, and can directly contact the first region A1 of the second semiconductor layer 13. Furthermore, the first layer FL can contact the second bridging pattern BRP2 to connect to it. Therefore, the first driving power VDD applied to the second bridging pattern BRP2 can be transmitted to the first layer FL.

[0252] Simultaneously, due to the material properties of each of the first semiconductor layer 11 and the second semiconductor layer 13, which are in direct contact with the first layer FL comprising p-type hydrogenated amorphous silicon (a-Si:H) semiconductor material, holes can be selectively injected into one of the first semiconductor layer 11 and the second semiconductor layer 13. In embodiments of this disclosure, the first semiconductor layer 11 may be made of n-type GaN, and the second semiconductor layer 13 may be made of p-type GaN. Therefore, the material properties (e.g., Fermi levels) of the first semiconductor layer 11 and the second semiconductor layer 13 may be different. Due to the difference in the Fermi levels between the first semiconductor layer 11 and the second semiconductor layer 13, even if each of the first semiconductor layer 11 and the second semiconductor layer 13 is in contact with the first layer FL, holes can still be selectively injected into only one region of the second semiconductor layer 13. For example, when a predetermined signal (e.g., a first drive power VDD) is applied to the first layer FL, holes can be injected into the first region A1 of the second semiconductor layer 13 that is in contact with the first layer FL, and holes may not be injected into the first region B1 of the first semiconductor layer 11.

[0253] The first layer FL described above can be used as a hole injection layer in the second semiconductor layer 13 for selectively injecting holes into each of the light-emitting elements LD.

[0254] An interlayer insulating layer (ILD) may be disposed and / or formed on the first layer (FL). The interlayer insulating layer (ILD) may have the same characteristics as the reference layer. Figure 4 The interlayer insulating layer (ILD) described has the same structure. The ILD can be disposed on the first layer FL and can contact both ends EP1 and EP2 of each of the light-emitting elements (LDs). For example, the ILD can directly contact the second region B2 of the first semiconductor layer 11 of each light-emitting element LD, and can directly contact the second region A2 of the second semiconductor layer 13 of each light-emitting element LD.

[0255] The second layer SL can be disposed and / or formed on the interlayer insulating layer ILD. In embodiments of this disclosure, the second layer SL can be formed of a transparent oxide semiconductor material such as α-IGZO.

[0256] The second layer SL can be disposed and / or formed on the interlayer insulating layer ILD and the light-emitting element LD. Furthermore, the second layer SL can be disposed and / or formed on a region of the embankment pattern BNK and the first bridging pattern BRP1. However, this disclosure is not limited thereto, and according to embodiments, the second layer SL may not be disposed and / or formed on the first bridging pattern BRP1.

[0257] In embodiments of this disclosure, the second layer SL can contact both ends EP1 and EP2 of each of the light-emitting elements LD. For example, the second layer SL can directly contact the third region B3 of the first semiconductor layer 11 of each light-emitting element LD, and can directly contact the third region A3 of the second semiconductor layer 13. Furthermore, the second layer SL can be disposed on the first conductive line CL1 to be connected to the first conductive line CL1. Therefore, the second driving power VSS applied to the first conductive line CL1 can be transmitted to the second layer SL.

[0258] Simultaneously, due to the material properties of each of the first semiconductor layer 11 and the second semiconductor layer 13, which are in direct contact with the second layer SL formed of a transparent oxide semiconductor material such as a-IGZO, electrons can be selectively injected into one of the first semiconductor layer 11 and the second semiconductor layer 13. As described above, due to the difference in the Fermi levels between the first semiconductor layer 11 and the second semiconductor layer 13 in contact with the second layer SL, even if each of the first semiconductor layer 11 and the second semiconductor layer 13 is in contact with the second layer SL, electrons can still be selectively injected into only one region of the first semiconductor layer 11. For example, when a predetermined signal (or voltage) (e.g., a second driving power VSS) is applied to the second layer SL, electrons can be injected only into the third region B3 of the first semiconductor layer 11 that is in contact with the second layer SL, and electrons may not be injected into the third region A3 of the second semiconductor layer 13.

[0259] The second layer SL described above can be used as an electron injection layer in the first semiconductor layer 11 of each of the light-emitting elements LD to selectively inject electrons.

[0260] The first layer FL and the second layer SL can be electrically and / or physically separated by the interlayer insulation layer ILD disposed between them.

[0261] In embodiments of this disclosure, the first region A1 of the second semiconductor layer 13 that contacts the first layer FL, the second region A2 of the second semiconductor layer 13 that contacts the interlayer insulating layer ILD, and the third region A3 of the second semiconductor layer 13 that contacts the second layer SL can be the upper surface 13b of the second semiconductor layer 13. The value obtained by summing the thickness of the first region A1, the second region A2, and the third region A3 of the second semiconductor layer 13 can be the same as the diameter D of each light-emitting element LD.

[0262] Furthermore, the first region B1 of the first semiconductor layer 11 that contacts the first layer FL, the second region B2 of the first semiconductor layer 11 that contacts the interlayer insulating layer ILD, and the third region B3 of the first semiconductor layer 11 that contacts the second layer SL can be the lower surface 11a of the first semiconductor layer 11. The value obtained by summing the thickness of the first region B1, the second region B2, and the third region B3 of the first semiconductor layer 11 can be the same as the diameter D of each of the light-emitting elements LD.

[0263] The second insulating layer INS2 may be disposed and / or formed on the second layer SL. The second insulating layer INS2 may comprise the same material as the first insulating layer INS1. For example, the second insulating layer INS2 may be made of materials such as silicon oxide (SiO2). x An inorganic insulating layer is formed. However, this disclosure is not limited thereto. The second insulating layer INS2 may cover the second layer SL so that the second layer SL is not exposed to the outside.

[0264] The second conductive line CL2 may be disposed and / or formed on the second insulating layer INS2. In embodiments of this disclosure, the second conductive line CL2 may comprise the same material as the first conductive line CL1. For example, the second conductive line CL2 may comprise indium tin oxide (ITO).

[0265] In embodiments of this disclosure, the second conductive line CL2 may be disposed and / or formed on another area of ​​the embankment pattern BNK where the second layer SL is not disposed, and although not shown, the second conductive line CL2 may be connected to the first bridging pattern BRP1. When the second conductive line CL2 is connected to the first bridging pattern BRP1, the second conductive line CL2 can be electrically connected through the first bridging pattern BRP1 to a portion of the pixel circuit section PCL (e.g., the driving transistor Tdr). Therefore, a predetermined signal (or voltage) applied to the driving transistor Tdr can be transmitted to the second conductive line CL2.

[0266] In embodiments of this disclosure, the second conductive line CL2 may be positioned on each light-emitting element LD, and the first conductive line CL1 may be positioned below each light-emitting element LD. For example, the first conductive line CL1 and the second conductive line CL2 may be positioned on and below each light-emitting element LD that is interposed between them, respectively.

[0267] As described above, the second driving power VSS can be applied to the first conductive line CL1 via the second power line PL2, and a predetermined signal (or voltage) applied to the driving transistor Tdr can be applied to the second conductive line CL2 via the first bridging pattern BRP1. Here, the predetermined signal (or voltage) applied to the driving transistor Tdr can be a potential power higher than the potential power of the second driving power VSS. When a signal (or voltage) corresponding to each of the first conductive line CL1 and the second conductive line CL2 is applied, an electric field can be formed between the first conductive line CL1 and the second conductive line CL2. For example, an electric field can be formed in the direction from the first conductive line CL1 to the second conductive line CL2. In this case, the HE11 mode of the light emitted from the active layer 12 of each light-emitting element LD can be enhanced. Therefore, the amount (or intensity) of light traveling from the active layer 12 of each light-emitting element LD to each of the first semiconductor layer 11 and the second semiconductor layer 13 can be increased, and thus the light output efficiency of each light-emitting element LD can be further improved.

[0268] A capping layer CVL can be disposed and / or formed on the second conductive line CL2. The capping layer CVL can be configured in the configuration of each pixel region PXA, located at the top layer, and can cover the light-emitting element LD when viewed in a plan view.

[0269] In embodiments of this disclosure, the capping layer CVL can serve as a light guiding member for directing light emitted from each of the light-emitting elements (LDs) to concentrate in a specific direction within the pixel region PXA. The capping layer CVL can be formed of a conductive material (or substance) having a constant reflectivity. The conductive material (or substance) can include an opaque metal that facilitates guiding light in a specific direction (e.g., a desired direction) by reflecting or scattering light emitted from the light-emitting element LD.

[0270] When viewed in a planar view, the capping layer CVL can not overlap with the embankment pattern BNK in the pixel region PXA, but can overlap with the inner region surrounded by the embankment pattern BNK (e.g., the region where light-emitting elements LDs are located). Light emitted from each of the light-emitting elements LDs positioned beneath the capping layer CVL can be reflected or scattered by the capping layer CVL and can travel in a specific direction. Therefore, light can be concentrated and emitted only from a specific area of ​​the pixel region PXA. For example, as... Figure 13As shown, the area between the embankment pattern BNK and the capping layer CVL in the pixel region PXA can be the emission region EMA from which light is emitted.

[0271] As a result, the location of the emission region EMA from which light is emitted in the pixel region PXA can ultimately be determined by the capping layer CVL.

[0272] As described above, when a capping layer CVL is disposed in a pixel region PXA in which each pixel PXL is disposed, light emitted from the light-emitting element LD can be concentratedly guided in a specific direction (e.g., a desired direction). When the position of the capping layer CVL disposed in the pixel region PXA of each pixel PXL is the same as the position of the capping layer CVL disposed in the pixel PXL adjacent to each pixel PXL, the position of the emission region EMA from which light is emitted in each pixel PXL can be substantially the same. Therefore, the light output deviation between each pixel PXL and its adjacent pixels PXL can be reduced, and the display device according to the embodiments of the present disclosure can have a uniform light output distribution throughout the entire area.

[0273] In the above embodiment, the capping layer CVL does not overlap with the embankment pattern BNK in the pixel region PXA, but this disclosure is not limited thereto. According to the embodiment, such as Figure 16 As shown, the capping layer CVL may overlap with a region of the embankment pattern BNK. In this case, light emitted from each of the light-emitting elements LD can travel to a specific region of the pixel region PXA, for example, another region of the embankment pattern BNK that is spaced apart from the capping layer CVL by a predetermined distance and does not overlap with the capping layer CVL. Therefore, the separation space between said other region of the embankment pattern BNK (e.g., the region spaced apart from the capping layer CVL and not overlapping with the capping layer CVL) and the capping layer CVL can be defined as the emission region EMA from which light is emitted.

[0274] The outer coating OC can be disposed and / or formed on the capping layer CVL. The outer coating OC can be a planarization layer that mitigates step differences caused by the underlying configuration, light-emitting element LD, embankment pattern BNK, first layer FL and second layer SL, first conductive line CL1 and second conductive line CL2, first insulating layer INS1 and second insulating layer INS2, etc. According to an embodiment, the outer coating OC can be an encapsulation layer that prevents oxygen and moisture from penetrating into the light-emitting element LD.

[0275] Figures 17a to 17k The manufacturing process is shown sequentially. Figure 13 A schematic plan view of the method for one pixel is shown, and Figures 18a to 18k The manufacturing process is shown sequentially. Figure 14 A schematic cross-sectional view of a method for a single pixel is shown.

[0276] In the following text, combined with Figures 17a to 17k as well as Figures 18a to 18k Described sequentially according to the manufacturing method. Figure 13 and Figure 14 The pixels shown are those according to embodiments of the present disclosure.

[0277] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17a as well as Figure 18a A portion of the pixel circuit section PCL is formed on the substrate SUB.

[0278] The partial configuration of the pixel circuit section PCL may include a driving transistor Tdr, a first power line PL1 and a second power line PL2, and at least one insulating layer. Here, the at least one insulating layer may include a buffer layer BFL, a first gate insulating layer GI1, and a second gate insulating layer GI2 sequentially formed on a substrate SUB.

[0279] Next, a first insulating material layer (not shown) is applied to the driving transistor Tdr and the first electric field line PL1 and the second electric field line PL2, and then a photolithography process, a curing process, and a descaling process (a process to remove residues generated during the process) are performed sequentially to form a protective layer PSV. In embodiments of this disclosure, the protective layer PSV may include a third contact hole CH3 exposing a portion of the driving transistor Tdr, a first contact hole CH1 exposing a portion of the first electric field line PL1, a second contact hole CH2 exposing a portion of the second electric field line PL2, and a fourth contact hole CH4 exposing another portion of the second electric field line PL2.

[0280] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17b , Figure 17c , Figure 18a as well as Figure 18b A transparent metal oxide, such as indium tin oxide (ITO), can be deposited on the protective PSV layer, and photolithography, etching, and lift-off processes can be performed sequentially to form a first bridging pattern BRP1, a second bridging pattern BRP2, and a first conductive line CL1 spaced apart from each other on the protective PSV layer. Here, the etching process can be a wet etching process, but this disclosure is not limited thereto.

[0281] In embodiments of this disclosure, the first bridging pattern BRP1 can be electrically connected and / or physically connected to the driving transistor Tdr via the third contact hole CH3 passing through the protective layer PSV. The second bridging pattern BRP2 can be electrically connected and / or physically connected to the first power line PL1 via the first contact hole CH1 passing through the protective layer PSV. The first conductive line CL1 can be electrically connected and / or physically connected to the second power line PL2 via the second contact hole CH2 and the fourth contact hole CH4 passing through the protective layer PSV.

[0282] Next, silicon oxide (SiO2) is applied to the first bridging pattern BRP1, the second bridging pattern BRP2, and the first conductive line CL1. x A second insulating material layer (not shown) is formed, and then a photolithography process, an etching process, and a stripping process are sequentially performed to form a first insulating layer INS1. Here, the etching process can be a dry etching process, but this disclosure is not limited thereto.

[0283] In embodiments of this disclosure, the first insulating layer INS1 may be formed on a portion of the first conductive line CL1.

[0284] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17d as well as Figures 18a to 18c A third insulating material layer (not shown) is applied to a protective layer PSV on which a first insulating layer INS1 is formed, and then photolithography, curing and deslag removal processes are performed in sequence to form the embankment pattern BNK.

[0285] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17e as well as Figures 18a to 18d A mixed solution comprising light-emitting elements (LDs) is input into pixel region PXA of each of the pixels PXL using an inkjet printing method or the like. For example, inkjet nozzles can be provided on the first insulating layer INS1, and the solvent mixed with multiple light-emitting elements (LDs) can be input into pixel region PXA of each of the pixels PXL through the inkjet nozzles. Here, the solvent can be any one or more of acetone, water, alcohol, and toluene, but this disclosure is not limited thereto. For example, the solvent can be in the form of ink or paste. The method of inputting the light-emitting elements (LDs) into pixel region PXA of each of the pixels PXL is not limited to the above embodiment, and the method of inputting the light-emitting elements (LDs) can be varied.

[0286] After the light-emitting element LD is input into the pixel region PXA of each of the pixels PXL, the solvent can be removed. The light-emitting element LD can be positioned on a region of the pixel region PXA of each of the pixels PXL, for example, on the first insulating layer INS1 of the inner region surrounded by the dike pattern BNK but not overlapping with the dike pattern BNK.

[0287] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17f as well as Figures 18a to 18e Hydrogenated amorphous silicon (a-Si:H) semiconductor material is applied to the light-emitting element (LD) and the first insulating layer (INS1), and photolithography, etching, lift-off, and p-type dopant implantation are performed sequentially to form the first layer FL. Here, the etching process can be a dry etching process, but this disclosure is not limited thereto.

[0288] The first FL layer can be formed of p-type hydrogenated amorphous silicon semiconductor material and can be formed on the first insulating layer INS1. Furthermore, the first FL layer can be disposed on each light-emitting element LD.

[0289] In embodiments of this disclosure, the first layer FL may contact a region at each of the two ends EP1 and EP2 of each light-emitting element LD. For example, the first layer FL may contact a first region B1 of the lower surface 11a of the first semiconductor layer 11 and a first region A1 of the upper surface 13b of the second semiconductor layer 13 of each light-emitting element LD.

[0290] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17g as well as Figures 18a to 18f Apply silicon oxide (SiO2) to the first FL layer x A fourth insulating material layer (not shown) is formed, and then a photolithography process, an etching process, and a lift-off process are sequentially performed to form an interlayer insulating layer (ILD). Here, the etching process can be a dry etching process, but this disclosure is not limited thereto.

[0291] An interlayer insulating layer (ILD) can be formed on the first layer (FL) and can contact another region at both ends (EP1 and EP2) of each light-emitting element (LD). For example, the ILD can contact the second region B2 of the lower surface 11a of the first semiconductor layer 11 and the second region A2 of the upper surface 13b of the second semiconductor layer 13 of each light-emitting element (LD).

[0292] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17h as well as Figures 18a to 18g A transparent metal oxide formed of a-IGZO is applied to the interlayer insulating layer (ILD), and then photolithography, etching, and lift-off processes are sequentially performed to form the second layer (SL). Here, the etching process can be a wet etching process, but this disclosure is not limited thereto.

[0293] The second layer SL can be formed on the interlayer insulating layer ILD. Furthermore, the second layer SL can be formed on the first conductive line CL1, which is exposed to the outside and not covered by the first insulating layer INS1, where the embankment pattern BNK is formed in one area. Therefore, the second layer SL can be electrically connected and / or physically connected to the second electric field line PL2 through the first conductive line CL1. Additionally, the second layer SL can be formed on the first bridging pattern BRP1.

[0294] In embodiments of this disclosure, the second layer SL may contact another region at both ends EP1 and EP2 of each light-emitting element LD. For example, the second layer SL may contact each of the third region B3 of the lower surface 11a of the first semiconductor layer 11 and the third region A3 of the upper surface 13b of the second semiconductor layer 13 of each light-emitting element LD.

[0295] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17i as well as Figures 18a to 18h Apply silicon oxide (SiO2) to the second layer SL. x A fifth insulating material layer (not shown) is formed, and then a photolithography process, an etching process, and a stripping process are sequentially performed to form a second insulating layer INS2. Here, the etching process can be a dry etching process, but this disclosure is not limited thereto.

[0296] A second insulating layer INS2 can be formed on the second layer SL to protect the second layer SL.

[0297] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17j as well as Figures 18a to 18i A transparent metal oxide, such as indium tin oxide (ITO), is deposited on the second insulating layer INS2, and a photolithography process, an etching process, and a lift-off process are performed sequentially to form the second conductive line CL2. Here, the etching process can be a wet etching process, but this disclosure is not limited thereto.

[0298] The second conductive line CL2 can be formed on the second insulating layer INS2 and can also be formed on the first bridging pattern BRP1. Therefore, the second conductive line CL2 can be electrically connected and / or physically connected to the driving transistor Tdr through the first bridging pattern BRP1.

[0299] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 , Figure 17k as well as Figures 18a to 18j A capping layer CVL is formed on the second conductive line CL2. The capping layer CVL can be formed in a region of the pixel region PXA that is surrounded by the embankment pattern BNK but does not overlap with the embankment pattern BNK, for example, in the center (or middle) of the pixel region PXA. For example, the capping layer CVL can be formed on the second conductive line CL2 to correspond to the region where the light-emitting element LD is positioned. However, this disclosure is not limited to this, and the position of the capping layer CVL can be varied according to different embodiments.

[0300] refer to Figure 1a , Figure 1b , Figure 10 , Figures 13 to 15 as well as Figures 18a to 18k An outer coating OC is formed on the capping CVL.

[0301] Although the above description has been made with reference to preferred embodiments of the present disclosure, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various changes and modifications can be made to the present disclosure without departing from the technical scope of the present disclosure as described in the claims.

[0302] Therefore, the scope of this disclosure should not be limited to what is described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A display device, comprising: A substrate includes a display area and a non-display area surrounding at least one side of the display area, the display area including a plurality of pixel areas, each having an emission area; as well as Pixels are disposed in each of the plurality of pixel regions and include a display element portion. The display element portion includes: A first insulating layer is disposed on the substrate; At least one light-emitting element is disposed on the first insulating layer and each has a first end and a second end in the longitudinal direction; The first layer is disposed on the first insulating layer and the light-emitting element and is in contact with a first region of each of the first end and the second end of the light-emitting element; The second layer is disposed on the light-emitting element and contacts a second region of each of the first end and the second end of the light-emitting element; and An interlayer insulation layer is disposed between the first layer and the second layer, and The first layer and the second layer comprise semiconductor materials.

2. The display device according to claim 1, wherein, The light-emitting element includes: The first semiconductor layer is doped with a first conductive dopant; The second semiconductor layer is doped with a second conductive dopant; and An active layer is disposed between the first semiconductor layer and the second semiconductor layer, and Each of the first semiconductor layer and the second semiconductor layer comprises gallium nitride semiconductor material.

3. The display device according to claim 2, wherein, The first conductive dopant includes an n-type dopant, and the second conductive dopant includes a p-type dopant.

4. The display device according to claim 3, wherein, The first end of the light-emitting element includes the first semiconductor layer, and the second end of the light-emitting element includes the second semiconductor layer.

5. The display device according to claim 4, wherein, The first layer comprises a p-type hydrogenated amorphous silicon semiconductor material, and the second layer comprises a transparent oxide semiconductor material.

6. The display device according to claim 5, further comprising: A first electric field line is disposed between the substrate and the first insulating layer and is electrically connected to the first layer; as well as A second electric field line is disposed between the substrate and the first insulating layer, spaced apart from the first electric field line, and electrically connected to the second layer.

7. The display device according to claim 6, wherein, The first layer is a hole injection layer in the first region of the second end of the light-emitting element, which receives the first power from the first electric line and injects holes into it. The second layer is an electron injection layer that receives second power from the second power line and injects electrons into the second region of the first end of the light-emitting element.

8. The display device according to claim 7, wherein, The interlayer insulating layer is positioned between the first region and the second region of each of the first and second ends of the light-emitting element.

9. The display device according to claim 8, wherein, The first region of the first end of the light-emitting element that contacts the first layer and the second region of the first end of the light-emitting element that contacts the second layer have the same width or different widths.

10. The display device according to claim 8, wherein, The second region of the first end of the light-emitting element that contacts the second layer and the second region of the second end of the light-emitting element that contacts the second layer have the same width or different widths.

11. The display device according to claim 7, wherein, The display element unit further includes: A first conductive line is disposed between the substrate and the first insulating layer; A second insulating layer is disposed on the second layer; and The second conductive wire is disposed on the second insulating layer.

12. The display device according to claim 11, wherein, Different voltages are applied to the first conductive line and the second conductive line respectively, and an electric field is formed in the direction that intersects the longitudinal direction of the light-emitting element.

13. The display device according to claim 12, wherein, The second conductive wire comprises a transparent conductive material.

14. The display device according to claim 11, wherein, The display element portion further includes a cover layer disposed on the second conductive line to correspond to the light-emitting element.

15. The display device according to claim 14, wherein, The capping layer comprises an opaque conductive material.

16. The display device according to claim 14, wherein, The capping layer guides the light emitted from the light-emitting element in a predetermined direction to determine the location of the emission region for each of the plurality of pixel regions.

17. The display device according to claim 1, wherein, The pixel also includes a pixel circuit section disposed between the substrate and the display element section.

18. A display device, comprising: A stretchable substrate includes multiple island-shaped members and bridge-shaped members connecting the multiple island-shaped members; as well as Multiple pixels are disposed in each of the plurality of island-shaped members and each includes a display element portion. The display element portion includes: A first insulating layer is disposed in each of the plurality of island-shaped members; Multiple light-emitting elements are disposed on the first insulating layer and each has a first end and a second end in the longitudinal direction; The first layer is disposed on the first insulating layer and the plurality of light-emitting elements and is in contact with a first region of each of the first end and the second end of each of the plurality of light-emitting elements; The second layer is disposed on the plurality of light-emitting elements and contacts a second region of each of the first and second ends of the plurality of light-emitting elements; and An interlayer insulation layer is disposed between the first layer and the second layer. The first layer and the second layer comprise semiconductor materials.

19. The display device according to claim 18, wherein, The first layer comprises a p-type hydrogenated amorphous silicon semiconductor material, and the second layer comprises a transparent oxide semiconductor material.

20. The display device according to claim 19, wherein, The first end of each of the plurality of light-emitting elements includes a first semiconductor layer doped with an n-type dopant, and the second end of each of the plurality of light-emitting elements includes a second semiconductor layer doped with a p-type dopant.

21. The display device according to claim 18, wherein, The stretchable substrate also includes cutouts positioned between the plurality of islands and the bridge.

22. A method for manufacturing a display device, the method comprising: Provide pixels to be prepared in the pixel region of the substrate. The pixels provided include: A pixel circuit portion is formed on the substrate; and A display element portion is formed on the pixel circuit portion, and The display element portion includes: A first insulating layer is formed on the pixel circuit section; A plurality of light-emitting elements are supplied on the first insulating layer, each of the plurality of light-emitting elements having a first end and a second end in the longitudinal direction; A first layer is formed on the plurality of light-emitting elements, the first layer comprising a p-type hydrogenated amorphous silicon semiconductor material; An interlayer insulating layer is formed on the first layer; A second layer is formed on the interlayer insulating layer, the second layer comprising a transparent oxide semiconductor material; and A second insulating layer is formed on the second layer.

23. The method according to claim 22, wherein, The first layer contacts each of the first region at the first end and the first region at the second end of the light-emitting element. The second layer contacts each of the second region of the first end and the second region of the second end of the light-emitting element, and The interlayer insulating layer contacts a third region between the first and second regions of each of the first and second ends of the light-emitting element.

24. The method according to claim 23, wherein, The display element portion further includes: A first conductive line is formed between the pixel circuit section and the first insulating layer; A second conductive line is formed on the second insulating layer; and A capping layer is formed on the second conductive line.

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