Random number generator

Abstract

The present disclosure relates to random number generators. The present disclosure relates to a circuit for testing a random number generator adapted to deliver a series of random bits and comprising at least one test unit configured to detect defects in the series of random bits, the test circuit being adapted to verify, after a first defect is detected by the test unit, whether the number of random bits generated by the random number generator without a second defect being detected by said unit test is less than a first threshold.

Description

Technical Field

[0001] This disclosure generally relates to random number generation, and more specifically, to random number generators. Random number generators typically include test circuitry for verifying the operation of the random number generator. This disclosure relates to a test circuitry for a random number generator. Background Technology

[0002] A true random number generator (TRNG) is a device that generates a sequence of numbers in which there is no deterministic link between a number and its (or its) predecessors.

[0003] Random number generators are used in various fields, especially in computer security. In data encryption, random numbers are commonly used to generate encryption and / or decryption keys.

[0004] Random numbers can be generated based on, for example, physical phenomena, analog signal processing operations, and / or digital signal processing operations.

[0005] A random number generator is characterized by its entropy. A random number generator may include one or more test circuits capable of detecting and / or estimating the evolution or change (in most cases, a decrease) of its entropy. Summary of the Invention

[0006] A higher-performance random number generator is needed.

[0007] A random number generator with higher entropy is needed.

[0008] A higher-performance random number generator test circuit is needed.

[0009] One embodiment can help address all or part of the shortcomings of known random number generators.

[0010] One embodiment can help address all or part of the shortcomings of known random number generator test circuits.

[0011] One embodiment provides a circuit for testing a random number generator adapted to pass a series of random bits and including at least one test unit configured to detect defects in the series of random bits. The test circuit is adapted to verify, after a first defect is detected by the test unit, whether the number of random bits generated by the random number generator is less than a first threshold if a second defect is not detected by the unit test.

[0012] According to one embodiment, the first threshold is equal to the reciprocal of the probability of the defect occurring.

[0013] According to one embodiment, the defect is a series of N consecutive bits all having the same value.

[0014] According to one embodiment, the drawback is a series of N consecutive bits all equal to "1".

[0015] According to one embodiment, the drawback is a series of N consecutive bits all equal to "0".

[0016] According to one embodiment, N equals 34.

[0017] According to one embodiment, the defect is a series of M consecutive bits having a sum greater than the second threshold.

[0018] According to one embodiment, M equals 1024, and the second threshold equals 628.

[0019] According to one embodiment, the random number generator includes at least two test units arranged in parallel.

[0020] According to one embodiment, the at least two test units look for different defects.

[0021] Another embodiment provides a random number generator, including the test circuit disclosed herein.

[0022] According to an embodiment, the random number generator includes a source capable of generating a series of random bits.

[0023] According to one embodiment, the source includes a noise source and a digitization level.

[0024] According to one embodiment, the random number generator includes a processing unit adapted to apply mathematical processing to a series of random bits.

[0025] In one embodiment, an apparatus includes: an input that receives, in operation, an indication of detecting a first type of defect in a random bit sequence; and a defect testing circuit means coupled to the input, wherein the defect testing circuit means generates, in operation, an indication of whether the first type of defect is repeatedly detected within a threshold number of bits of the random bit sequence.

[0026] In one embodiment, a system includes: a plurality of random sequence error detection circuits that detect errors in a random bit sequence during operation; and a defect test circuit means coupled to the plurality of random sequence error detection circuits, wherein the defect test circuit means generates an indication during operation of whether one of the random sequence error detection circuits has detected two errors in a random bit sequence within a threshold number of bits of the random bit sequence.

[0027] In one embodiment, a method includes: detecting a first type of defect in a random bit sequence; and based on the detection of the first type of defect, generating an indication of whether the first type of defect is repeatedly detected within a threshold number of bits in the random bit sequence.

[0028] In one embodiment, the content of a non-transitory computer-readable medium causes a processing circuit device to perform a method comprising: detecting a first type of defect in a random bit sequence; and, based on the detection of the first type of defect, generating an indication as to whether the first type of defect is repeatedly detected within a threshold number of bits in the random bit sequence. Attached Figure Description

[0029] The foregoing features and advantages, as well as other features and advantages, will be set forth in the following detailed description of embodiments by way of illustration rather than limitation, with reference to the accompanying drawings, in which:

[0030] Figure 1 An embodiment of a random number generator is schematically shown in boxes;

[0031] Figure 2 The test is schematically shown in the form of a box. Figure 1 An embodiment of the circuit for a random number generator;

[0032] Figure 3 The illustration is shown. Figure 1 A performance curve of the random number generator, which represents the probability function of the random number generator's entropy defects; and

[0033] Figure 4 An embodiment of a system including a random number generator and circuitry for testing the random number generator is schematically shown in box form. Detailed Implementation

[0034] Unless the context otherwise requires, the same features are indicated by the same reference numerals in the various figures. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0035] For clarity, only steps and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, the term "digital random bit source," meaning the source of digital random bits, will not be described further below. The described embodiments are compatible with conventional digital random bit sources.

[0036] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0037] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or when referring to relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or when referring to orientation qualifiers, such as "horizontal", "vertical", etc., the orientation shown in the figure is used.

[0038] Furthermore, in the description, when it comes to the entropy of random bits, it involves Shannon entropy.

[0039] Unless otherwise stated, the expressions “about,” “approximately,” “basically,” and “on the order of…” indicate within 10% and within 5%, respectively.

[0040] In the following description, reference is made to the binary value of a bit, which has two possible values: "1" (a) or "0" (zero). In practice, a bit can be represented by a voltage oscillating between two levels, with a high level representing "1" (a) and a low level representing "0" (zero).

[0041] Figure 1 An embodiment of the random number generator 100 is schematically shown in the form of a box.

[0042] As mentioned earlier, a true random number generator (TRNG) is a device suitable for transmitting sequences of numbers (e.g., bits) for which there is no deterministic link between a number and its predecessor. This type of generator is often used even in more sophisticated electronic systems.

[0043] The random number generator 100 includes a random bit source 101 (noise source). Source 101 includes a digital or analog noise source, and a digitized level of the noise from the noise source. Figure 1 (Not shown in the image). Source 101 transmits a series of random bits (RawRandomBit). According to one example, source 101 may include one or more ring oscillators and / or one or more phase-locked loops (PLLs).

[0044] The random number generator 100 includes a branch 102 for processing a series of random bits (RawRandomBits) and a branch 103 for testing the source 101.

[0045] Processing branch 102 enables access to a series of random bits (RawRandomBit) and optionally applies mathematical processing to them. According to one example, branch 102 includes:

[0046] Input register 1021 (raw bits);

[0047] Processing unit 1022 (post-processing); and

[0048] Output register 1023 (output).

[0049] Once generated by source 101, a series of random bits (RawRandomBit) are stored in input register 1021 before processing. Register 1021 then passes the storedRandomBits to processing unit 1022.

[0050] Processing unit 1022 applies mathematical processing to the stored bits `StoredRandomBits` stored in input register 1021. Processing unit 1022 passes the processed bits `ProcessedRandomBits` to output register 1023 at its output. The processing unit can add random characters, thereby increasing the reliability of the series of random bits passed from source 101. In other words, the processing unit accumulates entropy bit by bit in `StoredRandomBits` so that each bit of `ProcessedRandomBits` has an entropy of 1. According to the example, processing unit 1022 implements encryption algorithms such as AES (Advanced Encryption Standard), hash functions, or any other function capable of increasing the entropy of a series of random bits. Processing unit 1022 is optional. In practice, the processing unit is not necessary if source 101 is considered to have sufficient performance, but this is rarely the case.

[0051] Output register 1023 stores the processed bits (ProcessedRandomBits) and enables them to be used by electronic devices that require random bits (e.g., processors, see...). Figure 4 Processor 402) access.

[0052] Test branch 103 includes an embodiment of test system 1031 (test) and error register 1032 (error). Test branch 103 verifies whether the operation of source 101 passes a series of "sufficiently random" bits. More specifically, test branch 103 examines a series of random bits (RawRandomBit) passed by source 101 and determines whether there is a deterministic link between the bits and their preceding bits by using different tests. For this purpose, defects can be looked for in the series of random bits.

[0053] Furthermore, random number generators can be submitted to different methods that allow their reliability to be proven, i.e., the sufficiency of the random characters in the random numbers, for example, the sufficiency of random numbers transmitted by bits. These methods are, for example, the SP800-90B method or the AIS31 method. These standards impose on random number generators the requirement to perform tests on the random bits and to apply mathematical processing, such as that performed by the processing unit 1022, to these bits.

[0054] The test system 1031 receives a series of random bits (RawRandomBits) as input and examines this series of random bits. Combined with... Figure 2 The test system 1031 is described in further detail. The test system 1031 outputs the error bit.

[0055] Error register 1032 stores the error bit ErrorBit and makes it accessible to electronic devices that need to verify the reliability of source 101 and random number generator 100. According to one example, error register 1032 can make the error bit ErrorBit accessible by allowing it to be read or by generating an interrupt whenever the value of the error bit ErrorBit indicates that an error has been detected.

[0056] Figure 2 The combination is schematically shown in the form of a box. Figure 1 An embodiment of a test system 200 of type 1031 described herein.

[0057] Test system 200 is suitable for receiving information about Figure 1 Describes a series of random bits of type RawRandomBits, and is suitable for transmitting information about... Figure 1 The description specifies the Error bit of type ErrorBit. The Random bit sequence is composed of... Figure 1 The source described is of type 101 (source) Figure 2 (Not shown in the image) generated.

[0058] The test system 200 consists of two distinct parts. The first part of the test system 200 is adapted to verify a series of random bits passed from the source, and more specifically, to look for different defects in the series of random bits. The second part of the system 200 is adapted to analyze these defects, and more specifically, to determine whether the detected defects are true defects or "false positives".

[0059] The first part of the test system 200 includes one or more test units or circuits 201 (TEST1, ..., TESTN). Each test unit 201 receives a series of random bits (Random) as input and outputs defect bits (Defect1, ..., DefectN). Each test unit 201 is capable of searching for one or more defects in the series of random bits (Random). If the test unit 201 detects a defect, its defect bits (Defect1, ..., DefectN) can be set to "1" (one) or correspondingly set to "0" (zero). Different types of defects can be considered. At least two examples are described in detail below. Those skilled in the art will understand that other tests, such as, for example, tests specific to the type of source that generates the series of random bits (Random), can be implemented.

[0060] According to one example, an N-bit sequence in a series of random bits (Random) where all bits are equal to "1" (1) or correspondingly equal to "0" (0) is considered a defect in the random bit sequence. According to one example, N can be equal to 34. This test is called a repeated test. Therefore, test unit 201 can verify whether a series of random bits (Random) includes a series of N elements, such as 34 elements, all equal to "1" (1) or correspondingly equal to "0" (0). According to one example, unit 201 can test for the existence of an N-bit sequence equal to "1" (one), and another test unit 201 can test for the existence of an N-bit sequence equal to "0" (zero).

[0061] According to another example, a defect can be identified if the sum of M consecutive bits exceeds the threshold SUM. For example, a defect could be the sum of 1024 consecutive bits exceeding 628. This test is called a "monobit" test. Therefore, test unit 201 can calculate the sum of consecutive bits in a series of bits and verify whether the sum is greater than the threshold SUM.

[0062] The second part of the test system 200 includes a test circuit 202 (defect testing). The test circuit 202 receives defect bits Defect1, ..., DefectN from the test unit 201 as input and outputs error bits Error. The test circuit 202 is adapted to verify the frequency of occurrence of defects detected by the test unit 201. More specifically, each defect has a probability of occurrence (albeit a low one), and the test circuit 202 is adapted to verify that the frequency of occurrence does not exceed its probability. According to one example, if a defect has a 1% probability of occurrence, and occurs five times during the generation of one hundred random bits, then the source of the random bits has failed.

[0063] Furthermore, the test circuit 202 can verify whether the defect detected by the test unit 201 is a real defect or a "false positive". In fact, a defect may be a "false positive", that is, there is a defect for a series of random bits, but this does not mean that the source that generates these bits is faulty.

[0064] The presence of "false positive" defects is normal. For example, if the defect corresponds to a specific bit sequence, such as the bit sequence sought by a test of the repeatability type, then that specific sequence can still be randomly generated. More generally, if a defect has a probability of occurrence, this means that when a sufficiently large number of bits are generated, there is a risk that the defect will occur, and this is not a defect of source 201. This sufficiently large number specifically corresponds to the reciprocal of the probability of the defect occurring. As an illustration, if the probability of the defect occurring is 1%, then there are 100 chances of the defect occurring during the generation of 100 random bits.

[0065] According to an embodiment, the test circuit 202 is adapted to enumerate the number of random bits generated when the test unit 201 does not detect another defect after detecting a defect. If the number of random bits is greater than a threshold TH, the test circuit 202 considers the source to be working correctly. The error bit is then set to a value that does not indicate an error, such as "0" (zero). Otherwise, the test circuit 202 considers the source to be faulty. The error bit is then set to a value that indicates an error, such as "1" (a).

[0066] The threshold TH can be defined as the reciprocal of the probability P of the defect searched by test unit 201.

[0067] like Figure 2 As shown, the test circuit is adapted to receive defect bits from multiple test units 201. The test circuit 202 can then be adapted to process each defect bit Defect1, ..., DefectN separately.

[0068] Figure 3 A graph comparing the performance of two types of random number generators with that of an ideal random number generator is shown.

[0069] Figure 3 The graph consists of two curves, illustrating the change in the probability P of detecting defects in a series of random bits based on the Shannon entropy H of the series of random bits in the test branch of the random number generator. The entropy H of the series of random bits quantifies the "disorderliness" of the bit sequence, that is, the randomness of the bit sequence. The higher the entropy, the more "random" the bit sequence is, and therefore the more satisfactory the bit sequence is for the random number generator.

[0070] Curve C1 shows about Figure 1The ideal case of a random number generator of type Generator 100 is described. Curve C1 has a shape with decreasing step size. For entropy between 0 and H1, the probability P is 1, while for entropy exceeding H1, the probability P is 0. This curve indicates that for a source providing random bits with entropy exceeding H1, the occurrence of defects is impossible.

[0071] For example, the value of entropy H1 can be defined empirically by considering the type of random bit source used in the random number generator, the use of the random number generator, etc.

[0072] Curve C2 shows about Figure 1 The description covers the case of a random number generator of type generator 100, but does not include information about... Figure 2 The described circuit is a test circuit of type 202. The generator of curve C2 indicates that it detects an error whenever a defect is detected by test unit 201. Curve C2 shows that, without test circuit 202, the probability P of defect detection decreases sharply according to entropy. In other words, the higher the entropy, the more difficult it is to detect defects.

[0073] Curve C3 shows about Figure 1 The description includes the case of random number generators of type 100, and therefore includes information about... Figure 2 The described circuit is a test circuit of type 202. Curve C3 fits curve C1 better. Curve C3 shows that the addition of test circuit 202 causes the detection probability P to decrease only from the entropy value H1 which is greater than 0, for example, by 0.7 JK. －1 The magnitude.

[0074] The advantage of using test circuit 202 is that it facilitates the detection of changes in entropy based on the presence of defects in the generated random bits.

[0075] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0076] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0077] Figure 4This is a functional block diagram of an embodiment of an electronic device or system 400 of the type described herein. System 400 includes one or more processing cores or circuits 402. Processing core 402 may include, for example, one or more processors, state machines, microprocessors, MCUs, DSPs, programmable logic circuits, discrete circuits, logic gates, registers, and various combinations thereof. Processing core 402 can control the overall operation of system 400, application programs executed by system 400, security operations performed by system 400, etc.

[0078] System 400 includes one or more memories 404, such as one or more non-volatile memories and one or more volatile memories, which can store all or part of the instructions and data related to, for example, the control of system 400, applications and operations performed by system 400.

[0079] System 400 includes a random number generator or circuit 410. The random number generator 410 includes a noise source circuit 412, a random bit sequence processing circuit device 414, and a random sequence testing circuit device 416. The noise source 412 can, for example, use the reference described above. Figure 1 The noise source 101 described above is used to implement this. The random bit processing circuit device 414 can, for example, use the referenced above. Figure 1 The described processing branch 102 is implemented.

[0080] As shown in the figure, the random sequence test circuit 416 includes multiple random sequence test circuits 1 to N 418 and a defect test circuit device 420. For example, it can use... Figure 2 The test circuit 201 implements the random sequence test circuit 418. The defect test circuit device 420 can, for example, use the reference above. Figure 2 The defect testing circuit device 202 described above is used to implement this.

[0081] System 400 may include one or more other processing circuitry devices 406, which may include antennas, power supplies, sensors (e.g., image sensors, audio sensors, accelerometers, pressure sensors, temperature sensors, encoders, etc.), controllers, security circuitry (e.g., encryption processors, etc.), and a main bus system 470. The main bus system 470 may include one or more data, address, power, and / or control buses coupled to the various components of system 400. System 400 may also include an additional bus system, such as bus system 472, which communicatively couples noise source 412 to random bit sequence processing circuitry device 414 and random sequence test circuitry 416.

[0082] In operation, the random bit processing circuit device 414 can provide a random number sequence to the processing circuit device (e.g., processing core 402 or other processing circuit device 406) generated by the random bit processing circuit device 414, and can provide an indication of the reliability of the random number generator generated by the random sequence test circuit 416 (e.g., signaling the interruption of a fault in the noise source 412).

[0083] Figure 4 Embodiments of system 400 may include more components than shown, may include fewer components than shown, may combine or split the shown components, may couple the components together in various ways, and various combinations thereof. For example, a random number generator or circuit 410 may be integrated into the processing core or into other processing circuitry 406 (e.g., into security circuitry). A random sequence test circuit 416 may receive the output of a random bit sequence processing circuitry 414 instead of receiving bit sequences directly from a noise source circuitry 412, etc. System 400 may include a system-on-a-chip (SoC), coupled discrete chips, etc., or various combinations thereof.

[0084] In one embodiment, a circuit (202) for testing a random number generator (100), the random number generator (100) being adapted to transmit a series of random bits (RawRandomBits; Random) and being generally included including at least one test unit (201) configured to detect defects in the series of random bits (RawRandomBits; Random), the test circuit (202) being adapted to verify, after a first defect is detected by the test unit (201), whether the number of random bits generated by the random number generator (100) without a second defect being detected by the unit test (201) is less than a first threshold (TH). The first threshold (TH) may be equal to the reciprocal of the probability (P) of the defect occurring. A defect may be a series of N consecutive bits all having the same value. A defect may be a series of N consecutive bits all equal to "1" (a). A defect may be a series of N consecutive bits all equal to "0" (zero). N may be equal to 34. A defect may be a series of M consecutive bits having a sum greater than a second threshold (SUM). The consecutive bit series M can be equal to 1024, and the second threshold (SUM) can be equal to 628. The random number generator (100) may include at least two test units (201) arranged in parallel. The at least two test units (201) can look for different defects. The random number generator (100) can be summarized as including test circuitry. The generator may include a source capable of generating a series of random bits (RawRandomBits; Random). The source (101) may include a noise source and a digitization stage. The generator may include a processing unit (1022) adapted to apply mathematical processing to the series of random bits (RawRandomBits; Random).

[0085] In one embodiment, an apparatus includes: an input that receives, in operation, an indication of detecting a first type of defect in a random bit sequence; and a defect testing circuitry coupled to the input, wherein the defect testing circuitry generates, in operation, an indication of whether the first type of defect is repeatedly detected within a threshold number of bits in the random bit sequence. In one embodiment, the threshold number of bits is equal to the reciprocal of the probability of the first type of defect occurring. In one embodiment, the first type of defect is a series of N consecutive bits having the same value. In one embodiment, the same value is 1. In one embodiment, the same value is 0. In one embodiment, N equals 34. In one embodiment, the first type of defect is a series of M consecutive bits having a sum greater than the sum of thresholds. In one embodiment, M equals 1024, and the sum of thresholds equals 628. In one embodiment, the apparatus includes: a second input that receives, in operation, an indication of detecting a second type of defect in the random bit sequence, wherein the defect testing circuitry is coupled to the second input, and the defect testing circuitry generates, in operation, an indication of whether the second type of defect is repeatedly detected within a second threshold number of bits in the random bit sequence.

[0086] In one embodiment, a system includes: a plurality of random sequence error detection circuits that detect errors in a random bit sequence during operation; and a defect testing circuit device coupled to the plurality of random sequence error detection circuits, wherein the defect testing circuit device generates, during operation, an indication of whether one of the random sequence error detection circuits has detected two errors in the random bit sequence within a threshold number of bits. In one embodiment, the plurality of random sequence error detection circuits detect errors of a corresponding type in the random bit sequence during operation. In one embodiment, the system includes: a random number generator coupled to the plurality of random sequence error detection circuits, wherein the random number generator generates the random bit sequence during operation. In one embodiment, the random number generator includes a noise source and digitization circuitry. In one embodiment, the system includes: a bit sequence processing circuit device coupled to the random number generator, wherein the bit sequence processing circuit device applies digital signal processing to the random bit sequence during operation to generate random numbers. In one embodiment, the threshold number of bits is equal to the reciprocal of the probability of occurrence of a defect type detected by one of the random sequence error detection circuits. In one embodiment, the defect type detected by one of the multiple random sequence error detection circuits is a series of N consecutive bits with the same value. In one embodiment, N equals 34. In another embodiment, the defect type detected by one of the multiple random sequence error detection circuits is a series of M consecutive bits with a sum greater than a threshold sum. In one embodiment, M equals 1024, and the threshold sum equals 628. In one embodiment, the multiple random sequence error detection circuits detect different types of errors in the random bit sequence during operation; and a defect testing circuit means generates a corresponding indication of whether the multiple random sequence error detection circuits detected two errors in the random bit sequence within a corresponding threshold number of bits.

[0087] In one embodiment, a method includes: detecting a first type of defect in a random bit sequence; and, based on the detection of the first type of defect, generating an indication as to whether the first type of defect is repeatedly detected within a threshold number of bits in the random bit sequence. In one embodiment, the threshold number of bits is equal to the reciprocal of the probability of the first type of defect occurring. In one embodiment, the first type of defect is a series of M consecutive bits having a sum greater than the sum of thresholds. In one embodiment, M equals 1024, and the sum of thresholds equals 628. In one embodiment, the method includes: detecting a second type of defect in the random bit sequence; and, based on the detection of the second type of defect, generating an indication as to whether the second type of defect is repeatedly detected within a second threshold number of bits in the random bit sequence.

[0088] In one embodiment, the content of a non-transitory computer-readable medium causes a processing circuitry means to perform a method comprising: detecting a first type of defect in a random bit sequence; and, based on the detection of the first type of defect, generating an indication as to whether the first type of defect is repeatedly detected within a threshold number of bits in the random bit sequence. In one embodiment, the threshold number of bits is equal to the reciprocal of the probability of the first type of defect occurring. In another embodiment, the method comprises: detecting a second type of defect in the random bit sequence; and, based on the detection of the second type of defect, generating an indication as to whether the second type of defect is repeatedly detected within a second threshold number of bits in the random bit sequence. In one embodiment, the content comprises instructions executed by the processing circuitry means.

[0089] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer-readable medium is provided that includes a computer program adapted to perform one or more of the methods or functions described above. The medium may be a physical storage medium, such as a read-only memory (ROM) chip, or a disk, such as a digital multifunction disc (DVD-ROM), optical disc (CD-ROM), hard disk, memory, network, or a portable media article readable by a suitable drive or via a suitable connection, including one or more barcodes or other related codes encoded on one or more such computer-readable media and readable by a suitable reader device.

[0090] Furthermore, in some embodiments, some or all of these methods and / or functions may be implemented or provided in other ways, such as at least in part in firmware and / or hardware, including but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, and including microcontrollers and / or embedded controllers), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and devices employing RFID technology and various combinations thereof.

[0091] The various embodiments described above can be combined to provide other embodiments. If desired, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide other embodiments.

[0092] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the authorized equivalents of these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. An apparatus comprising: A random sequence generator that generates a random bit sequence during operation; A data processing circuit device coupled to the random sequence generator, wherein the data processing circuit device performs data processing operations using the random bit sequence in operation; The input, in operation, receives an indication of a first type of defect detected in the random bit sequence; A defect testing circuit device coupled to the input and the data processing circuit device, wherein the defect testing circuit device, in operation: Generate an indication as to whether the first type of defect is repeatedly detected within a first threshold number of bits of the random bit sequence; and Based on an indication of whether the generated first type of defect is repeated within a first threshold number of bits of the random bit sequence, an indication of a fault in the random sequence generator is generated; and A second input, which receives in operation an indication of a second type of defect detected in the random bit sequence, wherein the defect testing circuit device is coupled to the second input, and the defect testing circuit device generates in operation an indication of whether the second type of defect is repeatedly detected within a second threshold number of bits in the random bit sequence.

2. The apparatus of claim 1, wherein the number of the first threshold bits is equal to the reciprocal of the probability of occurrence of the first type of defect.

3. The apparatus of claim 1, wherein the first type of defect is a series of N consecutive bits having the same value.

4. The apparatus of claim 3, wherein the same value is 1.

5. The apparatus of claim 3, wherein the same value is 0.

6. The apparatus of claim 3, wherein N equals 34.

7. The apparatus of claim 1, wherein the first type of defect is a series of M consecutive bits having a sum greater than a threshold sum.

8. The apparatus of claim 7, wherein M equals 1024 and the sum of the thresholds equals 628.

9. The apparatus according to claim 1, wherein: The number of the first threshold bits is different from the number of the second threshold bits.

10. A system comprising: A processing circuit device that performs one or more processing operations using a random bit sequence during operation; Multiple random sequence error detection circuits that detect errors in random bit sequences during operation; as well as A defect testing circuit device coupled to the plurality of random sequence error detection circuits and the processing circuit device, wherein the defect testing circuit device, in operation: The system generates an indication of whether one of the plurality of random sequence error detection circuits has detected two errors in the random bit sequence within a threshold number of bits in the random bit sequence. as well as An interrupt signal is generated based on an indication from one of the plurality of random sequence error detection circuits whether it detects two errors in the random bit sequence within a threshold number of bits in the random bit sequence, wherein; The plurality of random sequence error detection circuits detect corresponding different types of errors in the random bit sequence during operation; and The defect testing circuit device generates, during operation, a corresponding indication as to whether the plurality of random sequence error detection circuits have detected two errors in the random bit sequence within a corresponding threshold number of bits in the random bit sequence.

11. The system of claim 10, comprising: A random number generator is coupled to the plurality of random sequence error detection circuits and the processing circuit device, wherein the random number generator generates the random bit sequence in operation.

12. The system of claim 11, wherein the random number generator comprises a noise source and a digitization circuit device.

13. The system of claim 11, comprising: Bit sequence processing circuitry is coupled to the random number generator, wherein the bit sequence processing circuitry applies digital signal processing to the random bit sequence in operation to generate random numbers.

14. The system of claim 10, wherein the number of threshold bits is equal to the reciprocal of the probability of occurrence of a defect type detected by one of the plurality of random sequence error detection circuits.

15. The system of claim 14, wherein the defect type detected by one of the plurality of random sequence error detection circuits is a series of N consecutive bits having the same value.

16. The system of claim 15, wherein N equals 34.

17. The system of claim 14, wherein the defect type detected by one of the plurality of random sequence error detection circuits is a series of M consecutive bits having a sum greater than a threshold sum.

18. The system of claim 17, wherein M equals 1024 and the sum of the thresholds equals 628.

19. The system according to claim 10, wherein, The number of corresponding threshold bits in the random bit sequence is different from each other.

20. A method comprising: Use a random number generator to generate a random bit sequence; A reliability indicator for the random number generator is generated; as well as One or more processing operations are performed based on the random bit sequence and the reliability indication of the random number generator, wherein generating the reliability indication of the random number generator includes: Detecting a first type of defect in the random bit sequence; and Based on the detection of the first type of defect, an indication is generated as to whether the first type of defect is repeatedly detected within a first threshold number of bits in the random bit sequence, wherein the reliability indication generated by the random number generator further includes: Detecting a second type of defect in the random bit sequence, wherein the second type of defect is different from the first type of defect; and Based on the detection of the second type of defect, an indication is generated as to whether the second type of defect is repeatedly detected within a second threshold number of bits in the random bit sequence.

21. The method of claim 20, wherein the number of the first threshold bits is equal to the reciprocal of the probability of occurrence of the first type of defect.

22. The method of claim 20, wherein the first type of defect is a series of M consecutive bits having a sum greater than a threshold sum.

23. The method of claim 22, wherein M equals 1024 and the sum of the thresholds equals 628.

24. The method of claim 20, wherein: The number of the first threshold bits is different from the number of the second threshold bits.

25. A non-transitory computer-readable medium having content that causes a processing circuit device to perform a method, the method comprising: Use a random number generator to generate a random bit sequence; A reliability indicator for the random number generator is generated; as well as One or more processing operations are performed based on the random bit sequence and the reliability indication of the random number generator, wherein generating the reliability indication of the random number generator includes: Detecting a first type of defect in the random bit sequence; and Based on the detection of the first type of defect, an indication is generated as to whether the first type of defect is repeatedly detected within a first threshold number of bits in the random bit sequence. Detecting a second type of defect in the random bit sequence, wherein the second type of defect is different from the first type of defect; and Based on the detection of the second type of defect, an indication is generated as to whether the second type of defect is repeatedly detected within a second threshold number of bits in the random bit sequence.

26. The non-transitory computer-readable medium of claim 25, wherein the number of threshold bits is equal to the reciprocal of the probability of occurrence of the first type of defect.

27. The non-transitory computer-readable medium of claim 25, wherein the number of the first threshold bits is different from the number of the second threshold bits.

28. The non-transitory computer-readable medium of claim 25, wherein the content includes instructions executed by the processing circuitry means.

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