Hardware Trojan Protection Method Based on Rare Value-Based Logical Encryption of Disabled Circuit Nodes

Abstract

The present invention discloses a hardware Trojan protection method based on rare value-based logic encryption of disabled circuit nodes. The method comprises: selecting a node with the largest fault response value in a circuit and implanting a function-destructive encryption gate; inputting a large number of random stimuli into a circuit input port, statistically analyzing the logic values ​​of each node in the circuit, and calculating the node probability; selecting a node with a flip probability lower than a low activity threshold and implanting a rare value-disabled encryption gate; utilizing a scrambler to disrupt the keys of the function-destructive encryption gate and the rare value-disabled encryption gate; and determining the correct key of the circuit. The present invention has the advantages of improving the hardware Trojan protection effect.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit security, and more particularly to a hardware Trojan protection method based on rare value-type logic encryption of disabled circuit nodes. Background Art

[0002] With the rapid development of the integrated circuit industry, the functions integrated into monolithic digital integrated circuit chips are becoming increasingly complex, and the scale and complexity of circuits are also increasing. These chips are increasingly being used in various fields of modern science and technology, particularly in sensitive areas such as financial equipment, mobile communications, transportation, government, and energy. Integrated circuits are playing an increasingly important role in promoting social progress and economic development, and have become a strategic, fundamental, and leading industry supporting social and economic development.

[0003] In today's globalized business model, the sophistication and complexity of the integrated circuit (IC) industry necessitates integrating design / manufacturing services from multiple countries and regions around the world, along with untrusted third-party intellectual property (3PIP) cores, to complete the four stages of IC design, manufacturing, packaging, and testing before bringing a single chip to market. The separation of design and manufacturing processes brought about by industry chain collaboration poses significant security risks to ICs. Third-party IP cores used in the design phase, masks employed in the manufacturing phase, and redundant packaging during the packaging phase can all pose security risks to ICs. These security threats are collectively referred to as hardware Trojans. Through clever design, attackers can conceal hardware Trojans within underlying circuitry, creating security vulnerabilities. By exploiting these vulnerabilities, attackers can tamper with functionality, degrade circuit performance, leak critical information, create denial of service, and even cause irreversible damage to the chip.

[0004] Hardware Trojans, a prominent security risk in the integrated circuit industry, have become a pressing issue in integrated circuit design and manufacturing. If chips containing hardware Trojans were used in military equipment or in key sectors of the national economy, they would cause severe disasters and incalculable economic losses. Therefore, research on hardware Trojan detection and protection technologies to ensure the security and reliability of integrated circuits is a common concern worldwide.

[0005] Hardware Trojans consist of a payload circuit and a trigger circuit. To ensure the concealment of hardware Trojans and prevent them from being detected during chip testing, attackers typically implant trigger structures in low-activity nodes in the circuit. Low-activity nodes have extremely low flipping probabilities and rarely output logical values, thereby reducing the triggering probability of the hardware Trojan.

[0006] In recent years, in order to resist the implantation of hardware Trojans, researchers have proposed hardware Trojan protection technology based on functional destructive logic encryption. For example, "Zhang Yilun, Yan Yingjian, Li Junwei. Hardware Trojan Protection Method Based on Rarity and Logic Encryption [J]. Computer Applications and Software, 2019, 36(12): 321-328." provides a method for implementing hardware Trojan protection through logic encryption. This technology introduces a key by implanting a functional destructive encryption gate, so that the circuit is in a functional error state when the key is not configured correctly. Therefore, the attacker cannot obtain the specific design of the circuit, and thus cannot obtain the implantation location of the hardware Trojan. However, attack methods for logic encryption are also constantly developing. At present, the logic encryption attack method based on fault sensitization and the attack method based on the satisfiability problem (SAT) have been verified to have good attack effects. They can break the logic encryption key of a circuit with less than 5000 logic gates within 10 minutes, thereby making the hardware Trojan protection strategy of logic encryption ineffective. Therefore, the traditional hardware Trojan protection based on functional destructive logic encryption has a poor protection effect. Summary of the Invention

[0007] The technical problem to be solved by the present invention is that the hardware Trojan protection of the existing technology with function-destructive logic encryption has a poor protection effect.

[0008] The present invention solves the above technical problems through the following technical means: a hardware Trojan protection method based on rare value-based logic encryption of disabled circuit nodes, the method comprising:

[0009] Step a: Select the node with the largest fault response value in the circuit and implant a function-destructive encryption gate;

[0010] Step b: Input a large amount of random excitation to the circuit input port, analyze the logic value of each node of the circuit statistically, and calculate the node probability;

[0011] Step c: Select nodes whose flip probability is lower than the low activity threshold and implant a rare value disabled encryption gate;

[0012] Step d: using a scrambler to scramble the keys of the function-destructive encryption gate and the rare-value-disabled encryption gate;

[0013] Step e: Determine the correct key for the circuit.

[0014] The function-destroying encryption gate implanted in this invention obscures the circuit design, making it impossible for attackers to obtain the specific design and, therefore, the implanted location of the hardware Trojan. Furthermore, the implanted rare value-disabling encryption gate prevents the rare value of nodes whose flip probability is below the low activity threshold from appearing. Therefore, even if the logical encryption is breached and the key of the function-destroying encryption gate is obtained by the attacker, the hardware Trojan implanted in the low-activity node will not meet its rare value-based triggering condition. This solves the problem of the easy breach of function-destroying logic encryption technology and enhances the protection against hardware Trojans. Furthermore, the rare value-disabling encryption gate uses a scrambler to obfuscate the function-destroying encryption gate, making it impossible for attackers to obtain the key. This effectively implements the security of the hardware Trojan defense mode itself, further enhancing the protection against hardware Trojans.

[0015] Furthermore, there are two function-destruction encryption gates, namely an XOR encryption gate and an XOR encryption gate. The XOR encryption gate includes a first XOR gate, whose input ends are the node input and the key input, and the correct key is 0; the XOR encryption gate includes an XOR gate, whose input ends are the node input and the key input, and the correct key is 1; when the correct key is input, the circuit functions normally, and when the wrong key is input, the node output is wrong.

[0016] Furthermore, the step a includes:

[0017] a1: Analyze and select the node with the largest fault response value in the circuit as the node to be implanted with the function-destructive encryption gate. The fault response value is the number of bits that occur at the output when a logic error occurs in the circuit node under a fixed number of random inputs.

[0018] a2: Randomly select one of the two function-destructive encryption gates and implant it into the node to be implanted;

[0019] a3: Simulate and analyze whether the Hamming distance between the incorrect output and the correct output is 50% when an incorrect key is input. If it reaches 50%, the functional destruction encryption gate implantation stage is completed. Otherwise, repeat steps a1 and a2 until the Hamming distance reaches 50%, and the key is used as the functional destruction key.

[0020] Furthermore, the step b includes:

[0021] A large number of random input stimuli are applied to the circuit, and the number of clock cycles in which logic 1 appears at each node in the circuit is N1, the number of clock cycles in which logic 0 appears is N0, and the total number of clock cycles is N. Then the probability that the circuit node is 0 is P0 and The probability of a node being 1 is P1 and The flip probability of a node is P t and Nodes where P0 << P1 have a rare value of 0, and nodes where P1 << P0 have a rare value of 1.

[0022] Furthermore, the rare - value disabling encryption gate includes a disabling logic 1 - type encryption gate and a disabling logic 0 - type encryption gate. The disabling logic 1 - type encryption gate includes a second exclusive - OR gate and an AND gate. The input terminals of the second exclusive - OR gate are the node input and the first - bit input of the key. The output terminal of the second exclusive - OR gate is connected to one input terminal of the AND gate. The other input terminal of the AND gate inputs the second - bit of the key, and the output terminal of the AND gate is the node output. The disabling logic 0 - type encryption gate includes a third exclusive - OR gate and an OR gate. The input terminals of the third exclusive - OR gate are the node input and the first - bit input of the key. The output terminal of the third exclusive - OR gate is connected to one input terminal of the OR gate. The other input terminal of the OR gate inputs the second - bit of the key, and the output terminal of the OR gate is the node output.

[0023] Furthermore, for the disabling logic 1 - type encryption gate, its normal - mode key is 01, and its defense - mode key is 00. In the normal mode, the circuit functions normally. In the defense mode, the rare value logic 1 of the node input is disabled, and the node output remains at logic 0.

[0024] Furthermore, for the disabling logic 0 - type encryption gate, its normal - mode key is 00, and its defense - mode key is 01. In the normal mode, the circuit functions normally. In the defense mode, the rare value logic 0 of the node input is disabled, and the node output remains at logic 1.

[0025] Furthermore, step c includes: setting a low - activity threshold based on the target defense effect, selecting nodes with a flip probability lower than the low - activity threshold and designating them as the list of low - activity nodes to be disabled, determining the rare values of the nodes in the list, and implanting a rare - value disabling encryption gate corresponding to the node rare value, with its key as the disabling key.

[0026] Furthermore, step d includes: implanting a scrambler, using the disabling key and the function - destroying key as the scrambler output, and the actual key as the scrambler input, and using the scrambler to confuse the disabling key and the function - destroying key to hide the rare - value disabling encryption gate.

[0027] Furthermore, step e includes:

[0028] e1: Combining the correct value of the function - destroying key and the normal - mode value of the disabling key as the original normal - mode key, and combining the correct value of the function - destroying key and the defense - mode value of the disabling key as the original defense - mode key;

[0029] e2: Determining the descrambler structure based on the implanted scrambler, and for the original normal - mode

[0030] The normal mode key and the original defense mode key are decoded to obtain the actual normal mode key and defense mode key.

[0031] The advantages of the present invention are as follows: the function-destroying encryption gate implanted in the present invention obscures the circuit design, making it impossible for attackers to obtain the specific design and, therefore, the implanted location of the hardware Trojan. Secondly, the implanted rare value-disabled encryption gate prevents the rare value of nodes whose flip probability is lower than the low activity threshold from appearing. Therefore, even if the logical encryption is breached, the function-destroying encryption gate key is obtained by the attacker, causing the hardware Trojan to be implanted in the low-activity node, and its triggering condition based on the rare value cannot be met. This solves the problem of the function-destroying logic encryption technology being easily breached and improves the protection against hardware Trojans. In addition, the rare value-disabled encryption gate achieves obfuscation from the function-destroying encryption gate through a scrambler, making it impossible for attackers to obtain the key. This effectively implements the security of the hardware Trojan defense mode itself and further improves the protection against hardware Trojans. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Flowchart of a hardware Trojan protection method based on rare value-based logic encryption of disabled circuit nodes provided by an embodiment of the present invention;

[0033] Figure 2 Schematic diagram of the rare value disabled encryption gate structure in the hardware Trojan protection method based on rare value disabled circuit node logic encryption provided by an embodiment of the present invention, wherein: Figure 2 (a) is to disable the logic 1 type encryption gate, Figure 2 (b) is to disable the logic 0 type encryption gate;

[0034] Figure 3 Schematic diagram of two function-destructive encryption gate structures in the hardware Trojan protection method based on rare value-based logic encryption of disabled circuit nodes provided by an embodiment of the present invention, wherein: Figure 3 (a) is an XOR encryption gate, Figure 3 (b) is an XOR type encryption gate;

[0035] Figure 4 A schematic diagram of a practical application circuit of the hardware Trojan protection method based on rare value-based logic encryption of disabled circuit nodes provided by an embodiment of the present invention;

[0036] Figure 5 A schematic diagram of a functional destructive encryption gate implanted in a practical application circuit of a hardware Trojan protection method based on rare value-based logic encryption of disabled circuit nodes provided by an embodiment of the present invention;

[0037] Figure 6A schematic diagram of a practical application circuit for implanting a disabled logic 1 encryption gate in a hardware Trojan protection method based on disabled circuit node rare value type logic encryption provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0039] like Figure 1 As shown, a hardware Trojan protection method based on rare value-based logic encryption of disabled circuit nodes includes:

[0040] Step 1: Design of encryption gate structure, based on the digital standard unit design method and rules under the target process library, design Figure 2 The hidden rare value shown is disabled encryption door and Figure 3 Functionality-destroying encryption gate shown.

[0041] See Figure 2 The rare value disabled encryption gate includes a disabled logic 1 encryption gate and a disabled logic 0 encryption gate, such as Figure 2 As shown in (a), the disabled logic 1 type encryption gate includes an XOR gate and an AND gate, the input end of the XOR gate is the node input and the first bit input of the key, the output end of the XOR gate is connected to one input end of the AND gate, the other input end of the AND gate inputs the second bit of the key, and the output end of the AND gate is the node output; Figure 2 As shown in (b), the disabled logic 0 type encryption gate includes an XOR gate and an OR gate, the input end of the XOR gate is the node input and the first bit input of the key, the output end of the XOR gate is connected to one input end of the OR gate, the other input end of the OR gate inputs the second bit of the key, and the output end of the OR gate is the node output.

[0042] For a disabled logic 1 type encryption gate, its normal mode key is 01 and its defense mode key is 00. In normal mode, the circuit functions normally. In defense mode, the rare value logic 1 of the node input is disabled and the node output remains at logic 0.

[0043] For a disabled logic 0 type encryption gate, the normal mode key is 00 and the defense mode key is 01. In normal mode, the circuit functions normally. In defense mode, the rare value logic 0 at the node input is disabled and the node output remains at logic 1.

[0044] See Figure 3, there are two function - destroying encryption gates, namely the exclusive - OR encryption gate and the equivalence encryption gate. As Figure 3 shown in (a), the exclusive - OR encryption gate includes an exclusive - OR gate, whose input terminals are the node input and the key input, and the correct key is 0. As Figure 3 shown in (b), the equivalence encryption gate includes an equivalence gate, whose input terminals are the node input and the key input, and the correct key is 1. When the correct key is input, the circuit function is normal. When an incorrect key is input, the node output is incorrect.

[0045] Step 2: Select the node with the largest fault response value in the circuit to implant the function - destroying encryption gate; the specific process is as follows: For the circuit gate - level netlist, based on the fault analysis technology, find the node whose fault can cause the most incorrect output logic values. Instantiate the function - destroying encryption gate, modify the connection relationship of the netlist nodes, and complete the implantation of the function - destroying encryption gate. As Figure 4 The fault of node 2 in the circuit can cause the logic values of all output nodes to be incorrect. Therefore, select node 2 to implant the function - destroying encryption gate, and obtain Figure 5 . When simulating the input of an incorrect key, under a large number of random input stimuli, calculate the Hamming distance between the circuit output and the correct output, and iteratively implant the function - destroying encryption gate until the Hamming distance reaches 50%, and its key is used as the function - destroying key.

[0046] Step 3: Input a large number of random stimuli to the input ports of the circuit, count the logical value analysis situation of each node in the circuit, and calculate the node probability; the specific process is as follows: Apply a large number of random input stimuli to the circuit, and count the number of clock cycles N1 when the logic value of each node in the circuit is 1, the number of clock cycles N0 when the logic value is 0, and the total number of clock cycles N. Then the probability P0 of the circuit node being 0 is the probability P1 of the node being 1 is and the flip probability of the node is P t and Nodes with P0 << P1 have a rare value of 0, and nodes with P1 << P0 have a rare value of 1. For Figure 4 the circuit, apply random input stimuli to nodes 1, 2, and 3. The probability that node 4 is logic 1 is the probability that node 5 is logic 1 is the probability that node 6 is logic 1 is

[0047] Step 4: Select the nodes with a flip probability lower than the low - activity threshold and implant the rare - value - disabling encryption gate; the specific process is as follows: Based on the target defense effect, set the low - activity threshold, select the nodes with a flip probability lower than the low - activity threshold and designate them as the list of low - activity nodes to be disabled, determine the rare values of the nodes in the list, and implant the rare - value - disabling encryption gate corresponding to the rare value of the node, and its key is used as the disabling key. In Figure 4In the circuit, node 5 is selected as the low-activity node to be disabled, and a disabled logic 1 type encryption gate is implanted to obtain Figure 6 .

[0048] Step 5: Use a scrambler to scramble the keys of the function-destroying encryption gate and the rare-value disabled encryption gate; the specific process is: implant a scrambler, use the disabled key and the function-destroying key as the scrambler outputs, and the actual key as the scrambler input. Use the scrambler to confuse the disabled key and the function-destroying key, eliminate the bit-by-bit correspondence between the disabled key, the function-destroying key and the actual key, and achieve the hiding of the rare-value disabled encryption gate.

[0049] Step 6: Determine the correct key for the circuit. The specific process is:

[0050] The correct value of the key destroyed by the splicing function and the normal mode value of the disabled key are combined as the original normal mode key, and the correct value of the key destroyed by the splicing function and the defense mode value of the disabled key are combined as the original defense mode key. Figure 6 In the example, the function destruction key, disable key 1, and disable key 2 form a combined key, the original normal mode key is 001, and the original defense mode key is 000.

[0051] The descrambler structure is determined based on the implanted scrambler, and the original normal mode key and the original defense mode key are decoded to obtain the actual normal mode key and defense mode key. Figure 6 The original key, after the mapping relationship of the scrambler-descrambler, the actual normal mode key can be mapped to 101, and the actual defense mode key can be mapped to 010, so that the function-destructive encryption door key and the rare value financial encryption door key have no bit-by-bit correspondence with the actual key.

[0052] Through the above technical solutions, the present invention aims at the problem that the function-destructive logic encryption technology is slightly easy to be cracked, which leads to the failure of hardware Trojan protection, and proposes a hardware Trojan protection method based on the rare value logic encryption of disabled nodes. The method first adopts the fault analysis technology to implant the function-destructive encryption gate, then extracts the low-activity nodes of the circuit, and implants the corresponding rare value disabled encryption gate, and finally uses the scrambler to scramble the two encryption gate keys, and finally determines the corresponding correct key between the normal working mode of the circuit and the hardware Trojan defense mode. First, the implanted function-destructive encryption gate obscures the circuit design, making it impossible for the attacker to obtain the specific design, and thus the implantation location of the hardware Trojan. Secondly, the implanted rare value disabled encryption gate can be configured with a defense mode key. At this time, the rare value of the low-activity node of the circuit ( Figure 4 The logical value 1 of node 5) will not appear, so even if the logical encryption is broken, the functional destruction encryption gate key is obtained by the attacker, allowing the hardware Trojan to be implanted in the low-activity node ( Figure 4At node 5), the trigger condition based on the rare value cannot be met, thus solving the problem of the vulnerability of function-destroying logical encryption technology and improving the protection against hardware Trojans. In addition, the rare value-disabled encryption gate adopts a concealed design and uses a scrambler to achieve obfuscation with the function-destroying encryption gate. Even if the regular working mode key is compromised, the attacker cannot obtain the defense mode key. This effectively ensures the security of the hardware Trojan defense mode itself and improves the protection effect.

[0053] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A hardware Trojan protection method based on rare value logic encryption of disabled circuit nodes, characterized in that: The method comprises: Step a: Select the node with the largest fault response value in the circuit and implant a function-destroying encryption gate; there are two function-destroying encryption gates, namely an XOR encryption gate and an XOR encryption gate. The XOR encryption gate includes a first XOR gate, whose input ends are the node input and the key input, and the correct key is 0; the XOR encryption gate includes an XOR gate, whose input ends are the node input and the key input, and the correct key is 1; when the correct key is input, the circuit functions normally, and when the incorrect key is input, the node output is incorrect; Step b: Input a large amount of random excitation to the circuit input port, analyze the logic value of each node of the circuit, and calculate the node probability; Step c: Select a node whose flip probability is lower than a low activity threshold, and implant a rare value disabled encryption gate; the rare value disabled encryption gate includes a disabled logic 1 encryption gate and a disabled logic 0 encryption gate, the disabled logic 1 encryption gate includes a second XOR gate and an AND gate, the input end of the second XOR gate is the node input and the first bit input of the key, the output end of the second XOR gate is connected to one input end of the AND gate, the other input end of the AND gate inputs the second bit of the key, and the output end of the AND gate is the node output; the disabled logic 0 encryption gate includes a third XOR gate and an OR gate, the input end of the third XOR gate is the node input and the first bit input of the key, the output end of the third XOR gate is connected to one input end of the OR gate, the other input end of the OR gate inputs the second bit of the key, and the output end of the OR gate is the node output; Step d: using a scrambler to scramble the keys of the function-destructive encryption gate and the rare-value-disabled encryption gate; Step e: Determine the correct key for the circuit: e1: The correct value of the key destroyed by the splitting function and the normal mode value of the disabled key are combined as the original normal mode key. The correct value of the key destroyed by the splitting function and the defense mode value of the disabled key are combined as the original defense mode key. e2: Determine the descrambler structure based on the implanted scrambler, and decode the original normal mode key and the original defense mode key to obtain the actual normal mode key and defense mode key.

2. The hardware Trojan protection method based on rare value type logic encryption of disabled circuit nodes according to claim 1 is characterized in that: The step a comprises: a1: Analyze and select the node with the largest fault response value in the circuit as the node to be implanted with the function-destructive encryption gate. The fault response value is the number of bits that are erroneous at the output when a logic error occurs at the circuit node. a2: Randomly select one of the two function-destructive encryption gates and implant it into the node to be implanted; a3: Simulate and analyze whether the Hamming distance between the incorrect output and the correct output is 50% when an incorrect key is input. If it reaches 50%, the functional destruction encryption gate implantation stage is completed. Otherwise, repeat steps a1 and a2 until the Hamming distance reaches 50%. The key is used as the functional destruction key.

3. The hardware Trojan protection method based on rare value type logic encryption of disabled circuit nodes according to claim 2 is characterized in that: The step b comprises: A large number of random input stimuli are applied to the circuit, and the number of clock cycles in which logic 1 appears at each node in the circuit is counted. , the number of clock cycles in which logic 0 appears is , the number of all clock cycles is , then the probability that the circuit node is 0 is and The probability of a node being 1 is and , the flip probability of the node is and , << The node has a rare value of 0. << The node has a rare value of 1.

4. The hardware Trojan protection method based on rare value type logic encryption of disabled circuit nodes according to claim 3 is characterized in that: For a disabled logic 1 type encryption gate, its normal mode key is 01 and its defense mode key is 00. In normal mode, the circuit functions normally. In defense mode, the rare value logic 1 of the node input is disabled and the node output remains at logic 0.

5. The hardware Trojan protection method based on rare value type logic encryption of disabled circuit nodes according to claim 4 is characterized in that: For a disabled logic 0 type encryption gate, its normal mode key is 00 and its defense mode key is 01. In normal mode, the circuit functions normally. In defense mode, the rare value logic 0 of the node input is disabled and the node output remains at logic 1.

6. The hardware Trojan protection method based on rare value type logic encryption of disabled circuit nodes according to claim 5 is characterized in that: The step c includes: setting a low activity threshold based on the target defense effect, selecting nodes with a flip probability lower than the low activity threshold and defining them as a list of low activity nodes to be disabled, and determining the rarity value of the nodes in the list, implanting a rare value disabled encryption gate corresponding to the node rarity value, and using its key as a disabled key.

7. The hardware Trojan protection method based on rare value type logic encryption of disabled circuit nodes according to claim 6 is characterized in that: The step d includes: implanting a scrambler, using the disable key and the function destruction key as the scrambler outputs, the actual key as the scrambler input, and using the scrambler to confuse the disable key and the function destruction key to achieve hiding of the rare value disabled encryption door.

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