Memory and operating method thereof, memory system

Abstract

The embodiments of the present disclosure disclose a memory and an operating method thereof, and a memory system. The operating method comprises: charging a first dummy word line to a first voltage in a first charging phase of a programming operation; wherein the first dummy word line is located between an upper select gate line and a word line, and / or the first dummy word line is located between a lower select gate line and the word line; charging the first dummy word line from the first voltage to a second voltage in a second charging phase of the programming operation; wherein the second charging phase is located after the first charging phase, and a charging rate of the first charging phase is less than or equal to a charging rate of the second charging phase; and charging a selected word line of the word lines to a programming voltage after the second charging phase; wherein the programming voltage is greater than the second voltage.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of integrated circuits, and particularly to a memory and its operation method, and a memory system. Background Technology

[0002] With the development of technology, people are using more and more portable electronic devices in their lives, such as digital cameras, MP3 players, tablets, and smartphones. As a result, the memory market has also grown rapidly, leading to a gradual increase in the integration and bit density of memory.

[0003] However, as the integration and bit density of memory increase, the coupling in the memory is enhanced during the execution of logical operations (e.g., programming operations), affecting the normal operation of the memory. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a method for operating a memory is provided, comprising:

[0005] In the first charging phase of the programming operation, the first dummy word line is charged to a first voltage; wherein the first dummy word line is located between the upper select gate line and the word line, and / or, the first dummy word line is located between the lower select gate line and the word line;

[0006] In the second charging phase of the programming operation, the first dummy word line is charged from the first voltage to the second voltage; wherein the second charging phase is after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase.

[0007] After the second charging phase, selected word lines are charged to the programming voltage, wherein the programming voltage is greater than the second voltage.

[0008] According to a second aspect of the present disclosure, a memory is provided, comprising:

[0009] Storage cell array, including:

[0010] A word line, which is located between the upper selection gate line and the lower selection gate line;

[0011] The first dummy word line is located between the upper select gate line and the word line, and / or the first dummy word line is located between the lower select gate line and the word line;

[0012] Peripheral circuitry is coupled to the memory cell array; wherein,

[0013] The peripheral circuit is configured to charge the first dummy word line to a first voltage during the first charging phase of the programming operation.

[0014] The peripheral circuit is further configured to charge the first dummy word line from the first voltage to the second voltage during the second charging phase of the programming operation; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase.

[0015] The peripheral circuitry is further configured to charge selected word lines to a programming voltage after the second charging phase; wherein the programming voltage is greater than the second voltage.

[0016] According to a third aspect of the present disclosure, a memory system is provided, comprising:

[0017] One or more memories as provided in the second aspect of the embodiments of this disclosure;

[0018] A memory controller, coupled to the memory and configured to control the memory.

[0019] In this embodiment of the present disclosure, the first dummy word line is charged to a first voltage during the first charging stage of the programming operation, and then charged from the first voltage to a second voltage during the second charging stage of the programming operation. Since the second charging stage is located after the first charging stage, the charging process of the first dummy word line is divided into two stages, and the charging rate of the first charging stage is less than or equal to the charging rate of the second charging stage. This allows for better control of the boost rate of the first dummy word line, which is beneficial for reducing the parasitic capacitance between the first dummy word line and the upper select gate line and / or the parasitic capacitance between the first dummy word line and the lower select gate line, thereby reducing the coupling effect of the first dummy word line on the upper select gate line and / or the lower select gate line.

[0020] Furthermore, since the coupling effect of the first dummy word line to the upper select gate line and / or lower select gate line is reduced, it helps to reduce the probability of a significant increase in the voltage of the upper select gate line and / or lower select gate line during programming, thus ensuring the normal operation of memory programming. Attached Figure Description

[0021] Figure 1 This is a partial cross-sectional view of a memory according to an exemplary embodiment;

[0022] Figure 2 This is a partial cross-sectional view of a memory according to a specific example;

[0023] Figure 3 This is a timing diagram illustrating a method of operating a memory according to an exemplary embodiment;

[0024] Figure 4This is a waveform diagram of an enable signal according to an exemplary embodiment;

[0025] Figure 5 This is a flowchart illustrating a method of operating a memory according to an embodiment of the present disclosure;

[0026] Figure 6 This is a timing diagram of a memory operation method according to an embodiment of the present disclosure. Figure 1 ;

[0027] Figure 7 This is a timing diagram of a memory operation method according to an embodiment of the present disclosure. Figure 2 ;

[0028] Figure 8 This is a timing diagram of a memory operation method according to an embodiment of the present disclosure. Figure 3 ;

[0029] Figure 9 This is a timing diagram of a memory operation method according to an embodiment of the present disclosure. Figure 4 ;

[0030] Figure 10 This is a schematic diagram of a memory system according to an embodiment of the present disclosure;

[0031] Figure 11a This is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0032] Figure 11b A schematic diagram of a solid-state drive (SSD) according to an embodiment of this disclosure;

[0033] Figure 12 This is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0034] Figure 13 This is a partial cross-sectional view of a memory cell array including NAND memory strings, according to an embodiment of the present disclosure;

[0035] Figure 14 This is a block diagram of a memory including a memory cell array and peripheral circuitry, according to embodiments of the present disclosure. Detailed Implementation

[0036] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0037] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0038] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0039] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0040] Figure 1 This is a partial cross-sectional view of a memory 10 according to an exemplary embodiment. (Refer to...) Figure 1 As shown, the memory 10 includes a substrate 11, a stacked structure on the substrate 11, and at least one channel structure 16 penetrating the stacked structure; the stacked structure includes at least one bottom select gate (bsg) 12, at least one word line (WL) 14, and at least one top select gate (tsg) 15; a common source 17, penetrating the stacked structure and coupled to the substrate 11, is used to divide the stacked structure into multiple sub-blocks.

[0041] The stack-up structure also includes at least one dummy word line, for example, a dummy (dum) word line 13a (denoted as lower dummy word line 13a) located between lower select gate line 12 and word line 14. Another example is a dummy word line 13b (denoted as upper dummy word line 13b) located between word line 14 and upper select gate line 15.

[0042] The memory string includes a series-connected lower-select transistor, a memory cell, an upper-select transistor, and at least one dummy memory cell, which may be located between the lower-select transistor and the memory cell; and / or, the dummy memory cell may also be located between the memory cell and the upper-select transistor. For example, lower-select gate line 12 is coupled to the lower-select transistor, lower dummy word line 13a is coupled to the lower dummy memory cell, word line 14 is coupled to the memory cell, upper dummy word line 13b is coupled to the upper dummy memory cell, and upper-select gate line 15 is coupled to the upper-select transistor.

[0043] The substrate 11 includes a first well region 11a, a second well region 11b, a third well region 11c, and a fourth well region 11d. Here, the first well region 11a and the third well region 11c have the same doping type, for example, both are P-type wells, and their doping concentrations can be the same or different. The second well region 11b and the fourth well region 11d have the same doping type, for example, both are N-type wells, and their doping concentrations can be the same or different. In one example, the doping concentration of the fourth well region 11d is greater than that of the second well region 11b, and the common source 17 is coupled to the fourth well region 11d.

[0044] In a specific example, refer to Figure 2 As shown, the memory 10 includes 6 lower select gate lines (i.e., bsg0 to bsg5), 4 lower dummy word lines 13a (i.e., dum0 to dum3), 252 word lines (i.e., WL0 to WL251), 4 upper dummy word lines 13b (i.e., dum4 to dum7) and 4 upper select gate lines (i.e., tsg0 to tsg3). That is, the memory string includes 6 lower select transistors, 4 lower dummy memory cells, 252 memory cells, 4 upper dummy memory cells and 4 upper select transistors connected in series. The memory string is led out through an interconnect structure (including a first metal layer M1 and a second metal layer M2).

[0045] Figure 3 This is a timing diagram illustrating an operation method of a memory according to an exemplary embodiment, the operation method being used to... Figure 1 or Figure 2 The memory 10 shown is programmed. Specifically: during the time period t1 to t2, an on-state voltage (greater than the threshold voltage of the on-state transistor) is applied to the selected upper select gate line tsg(sel), an off-state voltage (e.g., ground voltage vss) is applied to the selected lower select gate line bsg(sel), a pass voltage vpass is applied to the unselected word lines WLn-(unsel) (i.e., word lines above the selected word line) and WLn+(unsel) (i.e., word lines below the selected word line), a bias voltage vbias is applied to the upper dummy word line dum-b and the lower dummy word line dum-a, and a programming voltage (vpe) is applied to the selected word line WLn(sel) to program the selected memory cells in the selected memory string. Here, vpe is greater than vbias, and vbias is greater than or equal to vpass.

[0046] During the time period from t1 to t2, a turn-off voltage is applied to the unselected upper selection gate line tsg (unsel) and the unselected lower selection gate line bsg (unsel) to turn off the channel of the unselected memory string, thereby prohibiting programming of the memory cells in the unselected memory string.

[0047] However, during the programming operation of the memory, due to the coupling effect, parasitic capacitances (such as...) exist between different conductive lines. Figure 2 As shown in the dashed box, voltage fluctuations occur in some conductive lines, affecting the normal operation of the memory. Here, the conductive lines include the lower select gate line, dummy word line, word line (including selected word line and unselected word line), upper select gate line, first metal layer, and second metal layer.

[0048] Reference Figure 3 As shown, during the process of charging the upper dummy word line dum-b to vbias, the coupling effect of the upper dummy word line dum-b to the unselected upper select gate line tsg(unsel) causes a significant increase in the voltage of the unselected upper select gate line tsg(unsel), as indicated by arrow ①. This may cause the upper select transistor of the unselected memory string to be turned on, thereby causing the memory cells in the unselected memory string to be programmed, resulting in programming crosstalk.

[0049] Similarly, during the process of charging the upper dummy word line dum-b to the bias voltage vbias, the coupling effect of the upper dummy word line dum-b to the selected upper select gate line tsg(sel) causes a significant increase in the voltage of the selected upper select gate line tsg(sel), as shown by arrow ②. This results in an increase in the potential of the selected upper select gate line, affecting the normal programming of the selected memory cell.

[0050] Reference Figure 3 As shown, during the process of charging the lower dummy word line dum-a to vbias, the coupling effect of the lower dummy word line dum-a to the unselected lower select gate line bsg(unsel) causes a significant increase in the voltage of the unselected lower select gate line bsg(unsel), as shown by arrow ③. This may cause the lower select transistor of the unselected memory string to be turned on, thereby causing the memory cells in the unselected memory string to be programmed, resulting in programming crosstalk.

[0051] Similarly, during the process of charging the lower dummy word line dum-a to the bias voltage vbias, the coupling effect of the lower dummy word line dum-a to the selected lower select gate line bsg(sel) causes a significant increase in the voltage of the selected lower select gate line bsg(sel), as shown by arrow ④. This may cause the lower select transistor of the selected memory string to turn on, affecting the normal programming of the selected memory cell.

[0052] Figure 4This is a waveform diagram of an enable signal according to an exemplary embodiment, which is used to control dummy word lines during programming. Specifically: at time t1, the first enable signal vdd_en is low (L), the second enable signal vss_en drops from high (H) to low, and the third enable signal vbias_en rises from low to high. That is, at time t1, the third enable signal vbias_en rapidly charges dum (e.g., dum-a) from vss to vdd (e.g., ...). Figure 4 (As shown in the dashed box), this leads to enhanced coupling between dum-a and bsg(unsel) and / or bsg(sel), resulting in voltage changes in bsg(unsel) and / or bsg(sel) as shown in the dashed box. Figure 3 The significant increase shown.

[0053] In view of this, embodiments of the present disclosure provide a method for operating a memory.

[0054] Figure 5 This is a flowchart illustrating a method for operating a memory according to an embodiment of the present disclosure. (Refer to...) Figure 5 As shown, the method includes at least the following steps:

[0055] S110: In the first charging phase of the programming operation, the first dummy word line is charged to a first voltage; wherein the first dummy word line is located between the upper select gate line and the word line, and / or, the first dummy word line is located between the lower select gate line and the word line;

[0056] S120: In the second charging phase of the programming operation, the first dummy word line is charged from the first voltage to the second voltage; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase.

[0057] S130: After the second charging stage, the selected word line is charged to the programming voltage; wherein the programming voltage is greater than the second voltage.

[0058] In this embodiment of the present disclosure, the first dummy word line is charged to a first voltage during the first charging stage of the programming operation, and then charged from the first voltage to a second voltage during the second charging stage of the programming operation. Since the second charging stage is located after the first charging stage, the charging process of the first dummy word line is divided into two stages, and the charging rate of the first charging stage is less than or equal to the charging rate of the second charging stage. This allows for better control of the boost rate of the first dummy word line, which is beneficial for reducing the parasitic capacitance between the first dummy word line and the upper select gate line and / or the parasitic capacitance between the first dummy word line and the lower select gate line, thereby reducing the coupling effect of the first dummy word line on the upper select gate line and / or the lower select gate line.

[0059] Furthermore, since the coupling effect of the first dummy word line to the upper select gate line and / or lower select gate line is reduced, it helps to reduce the probability of a significant increase in the voltage of the upper select gate line and / or lower select gate line during programming, thus ensuring the normal operation of memory programming.

[0060] In some embodiments, the method further includes: charging unselected word lines in the word lines to a pass voltage during a first charging phase and a second charging phase; wherein the pass voltage is greater than a first voltage and the pass voltage is less than or equal to a second voltage;

[0061] The above step S110 includes: performing a first floating operation on the first dummy word line; wherein, during the process of charging an unselected word line to the pass voltage, the unselected word line couples the floating first dummy word line to the first voltage.

[0062] For example, refer to Figure 6 As shown, from t1 to t 13 During the time period, the unselected word line WL is charged to the pass voltage vpass. Here, t1 to t 13 The time period includes t1 to t 11 Time period (i.e., the first charging phase) and t 11 To t 13 Time period (i.e., the second charging phase).

[0063] From t1 to t 11 During the time period, the unselected word line WL couples the floating first dummy word line dum1 to the first voltage vdd, at t 11 To t 13 During a given time period, the first dummy word line dum1 is charged from the first voltage vdd to the second voltage vbias. Here, the voltage vpass is greater than the first voltage vdd, and the voltage vpass is less than or equal to the second voltage vbias.

[0064] It should be noted that during the floating of the first dummy word line, the voltage of the first dummy word line changes with the word line voltage. For example, in the first charging stage, as the word line voltage increases, the voltage of the floating first dummy word line increases, and the boost rate of the first dummy word line in the first charging stage is less than or equal to the boost rate of the first dummy word line in the second charging stage.

[0065] In practical applications, during the first and second charging phases, multiple word lines in the memory (including selected and unselected word lines) are typically charged to the pass voltage. Preferably, the word line adjacent to the first dummy word line couples the floating first dummy word line to the first voltage. For example, when the first dummy word line is located between the upper select gate line and the word line, the word line below and adjacent to the first dummy word line couples the floating first dummy word line to the first voltage; and / or, when the first dummy word line is located between the lower select gate line and the word line, the word line above and adjacent to the first dummy word line couples the floating first dummy word line to the first voltage.

[0066] In this embodiment of the present disclosure, by charging the unselected word line to the pass voltage in the first charging stage and the second charging stage, and performing a first floating operation on the first dummy word line in the first charging stage, the floating first dummy word line is coupled to the first voltage using the unselected word line. This can better control the boost rate of the first dummy word line, which is beneficial to reduce the coupling effect of the first dummy word line on the upper select gate line and / or the lower select gate line, thereby reducing the probability of fluctuations in the upper select gate line and / or the lower select gate line during the programming process, and ensuring the normal operation of the memory programming operation.

[0067] Furthermore, by performing a first floating operation on the first dummy word line during the first charging phase, it is beneficial to reduce the power consumption of memory programming operations.

[0068] In some embodiments, the method further includes performing a first floating operation on the first dummy word line before the first charging phase.

[0069] For example, refer to Figure 6 As shown, at t 01 During the time period t1, the first dummy word line dum1 is floated, that is, before charging the word line WL, the first dummy word line dum1 is floated.

[0070] Still refer to Figure 6 As shown, at t 01 At time t, the first enable signal vdd_en is low, the second enable signal vss_en drops from high to low, and the third enable signal vbias_en is low, meaning the first dummy word line dum1 begins to float. 11 At a certain moment, the first enable signal vdd_en is low, the second enable signal vss_en is low, and the third enable signal vbias_en rises from low to high, meaning the first dummy word line ends floating and begins charging.

[0071] It should be noted that at the same time (i.e., time t1), lowering the second enable signal vss_en from high level to low level and raising the third enable signal vbias_en from low level to high level requires a more complex circuit design.

[0072] In this embodiment of the present disclosure, by floating the first dummy word line before the first charging stage, different enable signals can be switched at different times. Without increasing the complexity of the circuit design, this helps to reduce the coupling effect of the first dummy word line on the upper selection gate line and / or the lower selection gate line.

[0073] In some embodiments, the method further includes: performing a second floating operation on the second dummy word line during a first charging phase; wherein, during the charging of an unselected word line to the pass voltage, the unselected word line couples the floating second dummy word line to the first voltage; the second dummy word line is located between the word line and the first dummy word line, and the floating duration of the second floating operation is different from the floating duration of the first floating operation.

[0074] In one example, refer to Figure 7 As shown, from t1' to t 11 During the time period, the unselected word line WL couples the floating second dummy word line dum2 to the first voltage. In another example, refer to... Figure 8 As shown, from t1 to t 11 During the time period, the unselected word line WL couples the floating second dummy word line dum2 to the first voltage. It should be understood that the floating duration of the second dummy word line is less than the floating duration of the first dummy word line, that is, the floating duration of the first floating operation is greater than the floating duration of the second floating operation.

[0075] In one example, the first dummy word line and the second dummy word line are located between the upper select gate line and the word line, with the first dummy word line positioned between the second dummy word line and the upper select gate line. Specifically, the first dummy word line is relatively closer to the upper select gate line, and the second dummy word line is relatively farther away. The coupling effect of the first dummy word line to the upper select gate line is greater than that of the second dummy word line. By floating the first dummy word line, which is relatively closer to the upper select gate line, for a relatively longer time, and floating the second dummy word line, which is relatively farther away from the upper select gate line, for a relatively shorter time, different controls are applied to the different dummy word lines. In this example, the word line adjacent to the second dummy word line couples the floating second dummy word line to the first voltage. For example, a word line located below and adjacent to the second dummy word line couples the floating second dummy word line to the first voltage.

[0076] In one example, the first dummy word line and the second dummy word line are located between the lower select gate line and the word line, with the first dummy word line positioned between the second dummy word line and the lower select gate line. Specifically, the first dummy word line is relatively closer to the lower select gate line, and the second dummy word line is relatively farther away. The coupling effect of the first dummy word line on the lower select gate line is greater than that of the second dummy word line. By floating the first dummy word line, which is relatively closer to the lower select gate line, for a relatively longer time, and floating the second dummy word line, which is relatively farther away from the lower select gate line, for a relatively shorter time, different controls are applied to the different dummy word lines. In this example, the word line adjacent to the second dummy word line couples the floating second dummy word line to the first voltage. For example, a word line located above and adjacent to the second dummy word line couples the floating second dummy word line to the first voltage.

[0077] It should be noted that the first and second dummy word lines are merely examples used to convey this disclosure. In other embodiments, the memory may also include a third dummy word line, a fourth dummy word line, etc., and different dummy word lines in the memory may be floated for different durations. This disclosure does not impose any limitations on this.

[0078] In this embodiment of the present disclosure, by performing a first floating operation on the first dummy word line and a second floating operation on the second dummy word line during the first charging phase, and the floating duration of the second floating operation is different from that of the first floating operation, the first dummy word line and the second dummy word line can be floated for different durations according to the different coupling effects of the first dummy word line and the second dummy word line on the upper selection gate line and / or the lower selection gate line, which is beneficial to achieving better control over the first dummy word line and the second dummy word line.

[0079] In some embodiments, performing the first floating operation on the first dummy word line includes:

[0080] At the first moment, the first floating operation is performed on the first dummy word line;

[0081] At the second moment, the first floating operation on the first dummy word line ends;

[0082] The above-mentioned second floating operation on the second dummy word line during the first charging phase includes:

[0083] After the first moment and before the second moment, the second floating operation is started on the second dummy word line;

[0084] At the second moment, the second floating operation on the second dummy word line ends.

[0085] For example, refer to Figure 7 As shown, at time t1, the first dummy word line dum1 can be floated. 11At time t1', the floating of the first dummy word line dum1 ends. At time t1', the floating of the second dummy word line dum2 can begin. 11 At time t1, the floating second dummy word line dum2 ends. Here, t1 < t1' < t 11 .

[0086] It is understandable that in this example, the first dummy word line and the second dummy word line start floating at different times and end floating at the same time. That is, by controlling the start time of the first dummy word line to perform the floating operation to be different from the start time of the second dummy word line to perform the floating operation, the floating duration of the second floating operation is controlled to be different from that of the first floating operation.

[0087] In some embodiments, performing the first floating operation on the first dummy word line includes:

[0088] At the first moment, the first floating operation is performed on the first dummy word line;

[0089] At the second moment, the first floating operation on the first dummy word line ends;

[0090] The above-mentioned second floating operation on the second dummy word line during the first charging phase includes:

[0091] At the first moment, the second floating operation is started on the second dummy word line;

[0092] Before the second time step, the second floating operation on the second dummy word line is completed.

[0093] For example, refer to Figure 8 As shown, at time t1, the first dummy word line dum1 can be floated. 11 At time t1, the floating of the first dummy word line dum1 ends. At time t2, the floating of the second dummy word line dum2 can begin. 11 At time ', the floating second dummy word line dum2 ends.' Here, t1 < t 11 '<t 11 .

[0094] Understandably, in this example, the first dummy word line and the second dummy word line begin floating at the same time and end floating at different times. That is, by controlling the end time of the floating operation of the first dummy word line to be different from the end time of the floating operation of the second dummy word line, the floating duration of the second floating operation is controlled to be different from that of the first floating operation.

[0095] In some embodiments, step S110 includes: performing a charging operation on the first dummy word line from a first time to a second time to charge the first dummy word line to a first voltage;

[0096] Step S120 includes: charging the first dummy word line from the first voltage to the second voltage during the third to fourth time intervals;

[0097] The above method also includes: maintaining the first dummy word line at the first voltage from the second time point to the third time point.

[0098] For example, refer to Figure 9 As shown, from t1 (i.e., the first time) to t 11 During the second time period (i.e., the second time point), the first dummy word line dum1 is charged from VSS to the first voltage VDD, at time t 11 To t 12 (i.e., the third time point) During the time period, the first dummy word line dum1 is held at the first voltage vdd, at t 12 To t 13 During the fourth time period, the first dummy word line dum1 is charged from the first voltage vdd to the second voltage vbias.

[0099] In some embodiments, the first charging phase includes a first time period to a second time period, and the second charging phase includes a third time period to a fourth time period. The charging rate of the first dummy word line during the first time period to the second time period is less than or equal to the charging rate of the first dummy word line during the third time period to the fourth time period.

[0100] Understandably, in this example, charging the first dummy word line to the second voltage includes at least a first charging stage, a second charging stage, and a holding stage between the first charging stage and the second charging stage. This can better control the boost rate of the first dummy word line, which helps to reduce the coupling effect of the first dummy word line on the upper select gate line and / or the lower select gate line, thereby reducing the probability of fluctuations in the upper select gate line and / or the lower select gate line during programming and ensuring the normal operation of memory programming.

[0101] In some embodiments, during the process of charging the first dummy word line located between the upper select gate line and the word line to a first voltage, the method further includes: applying an on voltage to the upper select gate line coupled to the selected memory string, and applying an off voltage to the lower select gate line coupled to the selected memory string, the upper select gate line of the unselected memory string, and the lower select gate line of the unselected memory string.

[0102] And / or,

[0103] In the process of charging the first dummy word line located between the lower select gate line and the word line to a first voltage, the method further includes: applying an on voltage to the upper select gate line coupled to the selected memory string, and applying an off voltage to the lower select gate line coupled to the selected memory string, the upper select gate line of the unselected memory string, and the lower select gate line of the unselected memory string.

[0104] In the first charging phase and the second charging phase, an on-state voltage is applied to the upper select gate line coupled to the selected memory string, and an off-state voltage is applied to the lower select gate line coupled to the selected memory string to program the selected memory cell in the selected memory string; an off-state voltage is applied to the upper select gate line coupled to the lower select gate line of the unselected memory string to turn off the channel of the unselected memory string, that is, to prevent the programming of the memory cell in the unselected memory string.

[0105] In one example, the first dummy word line is located between the upper selection gate line (including the upper selection gate line of the selected memory string and the upper selection gate line of the unselected memory string) and the word line. By dividing the charging process of the first dummy word line into two stages, and the charging rate of the first charging stage is less than or equal to the charging rate of the second charging stage, the coupling effect of the first dummy word line on the upper selection gate line can be reduced. This is beneficial to reducing the impact on the programming of the selected memory cell, and at the same time, it is beneficial to reduce the probability of the memory cell in the unselected memory string being programmed, thereby reducing the probability of programming crosstalk.

[0106] In one example, the first dummy word line is located between the lower select gate line (including the lower select gate line of the selected memory string and the lower select gate line of the unselected memory string) and the word line. By dividing the charging process of the first dummy word line into two stages, and the charging rate of the first charging stage is less than or equal to the charging rate of the second charging stage, the coupling effect of the first dummy word line on the lower select gate line can be reduced. This is beneficial to reducing the impact on the programming of the selected memory cell, and at the same time, it is beneficial to reduce the probability of the memory cell in the unselected memory string being programmed, thereby reducing the probability of programming crosstalk.

[0107] In some embodiments, the method further includes maintaining the first dummy word line at a second voltage while charging the selected word line to the programming voltage.

[0108] For example, combined Figure 6 As shown, during the time interval t1 to t2, the selected word line and the unselected word line are first charged to the pass voltage and held for a certain period of time. Then, the selected word line is charged from the pass voltage to the programming voltage, while the unselected word line is held at the pass voltage vpass, and the first dummy word line dum1 is held at the second voltage vbias, thus completing the programming of the selected memory cell. Here, the programming voltage is greater than the second voltage vbias.

[0109] It is understood that in this example, the charging of the selected word line is carried out in two stages: first, it is charged to the pass voltage, held for a certain period of time, and then charged to the programming voltage. In other embodiments, the selected word line can also be directly charged to the programming voltage during the time period t1 to t2 to program the selected memory cell.

[0110] In some embodiments, the programming operation includes multiple programming loops; the method further includes:

[0111] In the first charging phase of each programming cycle, the first dummy word line is charged to the first voltage;

[0112] In the second charging phase of each programming cycle, the first dummy word line is charged from the first voltage to the second voltage.

[0113] In one example, during the first charging phase of each programming cycle, a first floating operation may be performed on the first dummy word line to charge the first dummy word line to a first voltage.

[0114] In another example, during the first charging phase of each programming cycle, a charging operation can be performed on the first dummy word line to charge it to a first voltage.

[0115] In another example, during the first charging phase of a portion of the programming cycle, a first floating operation may be performed on the first dummy word line to charge the first dummy word line to a first voltage; during the first charging phase of another portion of the programming cycle, a charging operation may be performed on the first dummy word line to charge the first dummy word line to a first voltage.

[0116] In programming operations, by executing multiple programming loops, the memory cell to be programmed can be programmed to the target state. By charging the first dummy word line to the first voltage in the first charging phase of each programming loop, and charging the first dummy word line from the first voltage to the second voltage in the second charging phase of each programming loop, the charging of the first dummy word line during each programming loop can be better controlled, which helps to reduce the coupling effect of the first dummy word line on the upper select gate line and / or lower select gate line during each programming loop.

[0117] Figure 10 This is a schematic diagram illustrating a memory system 100 according to an embodiment of the present disclosure. (Refer to...) Figure 10 As shown, the memory system 100 includes:

[0118] One or more memory units 103;

[0119] Memory controller 104 is coupled to memory 103 and configured to control memory 103.

[0120] System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0121] like Figure 10 As shown, system 100 may include a host 101 and a storage subsystem 102, the storage subsystem 102 having one or more memories 103, and the storage subsystem also including a memory controller 104. The host 101 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 101 may be configured to send data to the memory 103. Alternatively, the host 101 may be configured to receive data from the memory 103.

[0122] Memory 103 can be any memory device disclosed in this disclosure. Memory 103 can be a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device) that can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0123] In some embodiments, the memory controller 104 is also coupled to the host 101. The memory controller 104 can manage data stored in the memory 103 and communicate with the host 101.

[0124] In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0125] In some embodiments, the memory controller 104 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0126] The memory controller 104 can be configured to control operations of the memory 103, such as read, erase, and program operations. The memory controller 104 can also be configured to manage various functions relating to data stored or to be stored in the memory 103, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 104 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 103.

[0127] The memory controller 104 can also perform any other suitable functions, such as formatting the memory 103. The memory controller 104 can communicate with external devices (e.g., the host 101) according to a specific communication protocol. For example, the memory controller 104 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0128] The memory controller 104 and one or more memories 103 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 100 can be implemented and packaged into different types of end electronic products.

[0129] In such Figure 11a In one example shown, the memory controller 104 and a single memory 103 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 10 The memory card connector 204 is coupled to the host 101.

[0130] In such Figure 11b In another example shown, the memory controller 104 and multiple memories 103 may be integrated into a solid-state drive (SSD) 206. The solid-state drive 206 may also include a connection between the solid-state drive 206 and a host (e.g., Figure 10 The solid-state drive connector 208 is coupled to the host 101. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0131] It is understood that the memory controller 104 can perform the operating methods provided in any embodiment of this disclosure.

[0132] Figure 12 This is a schematic diagram illustrating a memory 300 according to an embodiment of the present disclosure. (Refer to...) Figure 12As shown, the memory 300 includes:

[0133] Storage cell array 301 includes:

[0134] Word line 318 is located between upper selection gate line 311 and lower selection gate line 315;

[0135] The first dummy word line 322 is located between the upper selection gate line 311 and the word line 318, and / or the first dummy word line 322 is located between the lower selection gate line 315 and the word line 318;

[0136] Peripheral circuit 302 is coupled to memory cell array 301; wherein,

[0137] The peripheral circuit 302 is configured to charge the first dummy word line 322 to a first voltage during the first charging phase of the programming operation;

[0138] The peripheral circuit 302 is also configured to charge the first dummy word line 322 from the first voltage to the second voltage during the second charging phase of the programming operation; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase.

[0139] The peripheral circuit 302 is also configured to charge selected word lines to the programming voltage after the second charging phase; wherein the programming voltage is greater than the second voltage.

[0140] The storage cell array 301 may be a NAND flash memory cell array, wherein the storage cell array 301 is provided in the form of an array of NAND storage strings 308, each NAND storage string 308 extending vertically above a substrate (not shown).

[0141] In some implementations, each NAND memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0142] In some embodiments, each storage cell 306 is a single-level cell having two possible storage states and thus being able to store one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range.

[0143] In some embodiments, each storage cell 306 is a cell capable of storing more than a single bit of data in more than four storage states. For example, two bits per cell (also known as a multi-level cell), three bits per cell (also known as a three-level cell), or four bits per cell (also known as a four-level cell) can be stored. Each multi-level cell can be programmed to take a range of possible nominal storage values. In one example, if each multi-level cell stores two bits of data, the multi-level cell can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0144] like Figure 12 As shown, each NAND memory string 308 may include a lower select gate 310 at its source end and an upper select gate 312 at its drain end. The lower select gate 310 and the upper select gate 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations. Each NAND memory string 308 may also include a first dummy memory cell 321 located between the upper select gate 312 and the memory cell 306.

[0145] It should be noted that, Figure 12 This illustration only shows the case where the first dummy word line 322 is located between the upper select gate line 311 and the word line 318, and the first dummy memory cell 321 is located between the upper select gate 312 and the memory cell 306. However, in other embodiments, the first dummy word line 322 may also be located between the lower select gate line 315 and the word line 318, and the first dummy memory cell 321 may be located between the lower select gate 310 and the memory cell 306.

[0146] In some embodiments, the sources of NAND flash memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., common SL). In other words, according to some implementations, all NAND flash memory strings 308 in the same memory block 304 have an array common source (ACS).

[0147] In some embodiments, the upper select gate 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown).

[0148] In some embodiments, each NAND flash memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the upper selection gate 312) or a deselection voltage (e.g., 0V) to the corresponding upper selection gate 312 via one or more upper selection gate lines 311. And / or, in some embodiments, each NAND flash memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the lower selection gate 310) or a deselection voltage (e.g., 0V) to the corresponding lower selection gate 310 via one or more lower selection gate lines 315.

[0149] like Figure 12 As shown, the NAND storage string 308 can be organized into multiple storage blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each storage block 304 is the basic data unit for an erase operation, i.e., all storage cells 306 on the same storage block 304 are erased simultaneously. To erase storage cells 306 in a selected block storage region, a source line of the selected block storage region and the unselected block storage regions on the same storage plane as the selected block storage region can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)).

[0150] It should be understood that, in some examples, erasure operations can be performed at the half-block level, at the quarter-block level, or at any level with any suitable number of blocks or any suitable fraction of blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0151] In some embodiments, each word line 318 is coupled to a memory page 320 of a memory cell 306, where the memory page 320 is the basic data unit for programming operations. The size of a memory page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320, as well as gate lines coupling the control gates. It is understood that a memory cell row is a plurality of memory cells 306 located in the same memory page 320.

[0152] Figure 13 A side view of a cross-section of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 13As shown, the NAND memory string 308 can extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0153] The memory stack layer 404 may include alternating gate conductive layers 406 and gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate dielectric layers 408 in the memory stack layer 404 determines the number of memory cells 306 in the memory cell array 301.

[0154] The gate conductive layer 406 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306 and may extend laterally at the top of the memory stack 404 as an upper select gate line 311, laterally at the bottom of the memory stack 404 as a lower select gate line 315, or laterally between the upper select gate line 311 and the lower select gate line 315 as a word line 318.

[0155] like Figure 13 As shown, the NAND flash memory string 308 includes a channel structure 412 extending vertically through the memory stack layer 404. In some embodiments, the channel structure 412 includes channel holes filled with one or more semiconductor materials (e.g., as semiconductor channel 420) and one or more dielectric materials (e.g., as storage film 418). In some embodiments, the semiconductor channel 420 includes silicon, for example, polycrystalline silicon. In some embodiments, the storage film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trap / storage layer"), and a barrier layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel 420, tunneling layer 426, storage layer 424, and barrier layer 422 are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0156] In some embodiments, such as Figure 13 As shown, a well 414 (e.g., a P-well and / or an N-well) is formed in a substrate 402, and the source terminal of the NAND memory string 308 is in contact with the well 414. For example, a source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 308) during an erase operation. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain terminal of the NAND memory string 308. It should be understood that, although in Figure 13 Additional components, not shown, but which may form the memory cell array 301, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0157] In some embodiments, the peripheral circuit 302 is further configured to charge an unselected word line 318 in the word lines to a pass voltage during a first charging phase and a second charging phase; wherein the pass voltage is greater than the first voltage and the pass voltage is less than or equal to the second voltage.

[0158] The aforementioned peripheral circuit 302 is configured to charge the first dummy word line 322 to a first voltage during the first charging phase of the programming operation, including:

[0159] The peripheral circuit 302 is configured to perform a first floating operation on the first dummy word line 322; wherein, during the process of the peripheral circuit 302 charging the unselected word line 318 to the pass voltage, the unselected word line couples the floating first dummy word line 318 to the first voltage.

[0160] In some embodiments, the storage cell array further includes:

[0161] The second dummy word line 324, the second dummy storage unit 323 is located between storage unit 306 and the first dummy storage unit 321, and the second dummy word line 324 is located between word line 318 and the first dummy word line 322;

[0162] The peripheral circuit 302 is also configured to perform a second floating operation on the second dummy word line 324 during the first charging phase; wherein, during the process of the peripheral circuit 302 charging the unselected word line 318 to the pass voltage, the unselected word line 318 couples the floating second dummy word line 324 to the first voltage; the floating duration of the second floating operation is different from the floating duration of the first floating operation.

[0163] In some embodiments, the peripheral circuit 302 is specifically configured as follows:

[0164] At the first moment, the first floating operation is started on the first dummy word line 322; at the second moment, the first floating operation on the first dummy word line 322 ends.

[0165] After the first moment and before the second moment, the second floating operation is started on the second dummy word line 324; at the second moment, the second floating operation on the second dummy word line 324 ends.

[0166] In some embodiments, the peripheral circuit 302 is specifically configured as follows:

[0167] At the first moment, the first floating operation is started on the first dummy word line 322; at the second moment, the first floating operation on the first dummy word line 322 ends.

[0168] At the first moment, the second floating operation is started on the second dummy word line 324; before the second moment, the second floating operation on the second dummy word line 324 ends.

[0169] In some embodiments, the peripheral circuit 302 is configured to charge the first dummy word line 322 to a first voltage during the first charging phase of the programming operation, including: from a first moment to a second moment, the peripheral circuit 302 charges the first dummy word line 322 to the first voltage;

[0170] The aforementioned peripheral circuit 302 is also configured to charge the first dummy word line from the first voltage to the second voltage during the second charging phase of the programming operation, including: at the third to the fourth time, the peripheral circuit 302 charges the first dummy word line 322 from the first voltage to the second voltage;

[0171] The peripheral circuit 302 is also configured to maintain the first dummy word line 322 at the first voltage from the second time to the third time.

[0172] In some embodiments, when the peripheral circuit 302 is configured to charge the first dummy word line 322 located between the upper select gate line 311 and the word line 318 to a first voltage, the peripheral circuit 302 is further configured to: apply an on voltage to the upper select gate line 311 coupled to the selected memory string, and apply an off voltage to the lower select gate line 315 coupled to the selected memory string, the upper select gate line 311 of the unselected memory string, and the lower select gate line 315 of the unselected memory string;

[0173] And / or,

[0174] When the peripheral circuit 302 is configured to charge the first dummy word line 322 located between the lower select gate line 315 and the word line 318 to a first voltage, the peripheral circuit 302 is also configured to: apply an on voltage to the upper select gate line 311 coupled to the selected memory string, and apply an off voltage to the lower select gate line 315 coupled to the selected memory string, the upper select gate line 311 of the unselected memory string, and the lower select gate line 315 of the unselected memory string.

[0175] In some embodiments, the peripheral circuitry 302 is further configured to maintain the first dummy word line 322 at the second voltage while charging the selected word line 318 to the programming voltage.

[0176] In some embodiments, the programming operation includes multiple programming cycles; the peripheral circuit 302 is configured to charge the first dummy word line 322 to a first voltage during the first charging phase of each programming cycle.

[0177] The peripheral circuit 302 is also configured to charge the first dummy word line 322 from the first voltage to the second voltage during the second charging phase of each programming cycle.

[0178] refer to Figure 12 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit lines 316, word lines 318, dummy word lines (including the first dummy word line 322 and the second dummy word line 324), source lines 314, and select gate lines (including the lower select gate line 315 and the upper select gate line 311). The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit lines 316, word lines 318, the first dummy word line 322, the second dummy word line 324, source lines 314, the lower select gate line 315, and the upper select gate line 311.

[0179] Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 14 Some exemplary peripheral circuitry 302 is shown, including a page buffer / sensor amplifier 504, a column decoder / bit line (BL) driver 506, a row decoder / word line (WL) driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 14 Additional peripheral circuitry not shown.

[0180] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a memory page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0181] The line decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory cell array 301 and select / deselect word lines 318 of memory blocks 304. The line decoder / word line driver 508 can also be configured to use word line voltages (V) generated from the voltage generator 510. WL The line decoder / word line driver 508 can also select / deselect and drive the lower select gate 315 and the upper select gate 311. As described in detail below, the line decoder / word line driver 508 is configured to perform an erase operation on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0182] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0183] It should be emphasized that the peripheral circuit 302 is configured to perform the control method provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0184] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for operating a memory, characterized in that, include: In the first charging phase of the programming operation, the first dummy word line is charged to a first voltage; wherein the first dummy word line is located between the upper select gate line and the word line, and / or, the first dummy word line is located between the lower select gate line and the word line; In the second charging phase of the programming operation, the first dummy word line is charged from the first voltage to the second voltage; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase. After the second charging phase, selected word lines are charged to the programming voltage, wherein the programming voltage is greater than the second voltage.

2. The method according to claim 1, characterized in that, The method further includes: charging unselected word lines among the word lines to a pass voltage during the first charging phase and the second charging phase; wherein the pass voltage is greater than the first voltage and the pass voltage is less than or equal to the second voltage; The step of charging the first dummy word line to a first voltage during the first charging phase of the programming operation includes: A first floating operation is performed on the first dummy word line; wherein, during the process of charging the unselected word line to the through voltage, the unselected word line couples the floating first dummy word line to the first voltage.

3. The method according to claim 2, characterized in that, The method further includes: During the first charging phase, a second floating operation is performed on the second dummy word line; wherein, during the process of charging the unselected word line to the through voltage, the unselected word line couples the floating second dummy word line to the first voltage; the second dummy word line is located between the word line and the first dummy word line, and the floating duration of the second floating operation is different from the floating duration of the first floating operation.

4. The method according to claim 3, characterized in that, The first floating operation performed on the first dummy word line includes: At the first moment, the first floating operation is executed on the first dummy word line; At the second moment, the first floating operation on the first dummy word line ends; The second floating operation performed on the second dummy word line during the first charging phase includes: After the first moment and before the second moment, the second floating operation is performed on the second dummy word line; At the second moment, the second floating operation on the second dummy word line ends.

5. The method according to claim 3, characterized in that, The first floating operation performed on the first dummy word line includes: At the first moment, the first floating operation is executed on the first dummy word line; At the second moment, the first floating operation on the first dummy word line ends; The second floating operation performed on the second dummy word line during the first charging phase includes: At the first moment, the second floating operation is started on the second dummy word line; Before the second moment, the second floating operation on the second dummy word line is terminated.

6. The method according to claim 1, characterized in that, The step of charging the first dummy word line to a first voltage during the first charging phase of the programming operation includes: From the first moment to the second moment, a charging operation is performed on the first dummy word line to charge the first dummy word line to the first voltage; In the second charging phase of the programming operation, charging the first dummy word line from the first voltage to the second voltage includes: During the third and fourth time points, the first dummy word line is charged from the first voltage to the second voltage; The method further includes maintaining the first dummy word line at the first voltage during the second time period to the third time period.

7. The method according to claim 1, characterized in that, In the process of charging the first dummy word line located between the upper select gate line and the word line to the first voltage, the method further includes: applying an on voltage to the upper select gate line coupled to the selected memory string, and applying an off voltage to the lower select gate line coupled to the selected memory string, the upper select gate line of the unselected memory string, and the lower select gate line of the unselected memory string. And / or, In the process of charging the first dummy word line located between the lower select gate line and the word line to the first voltage, the method further includes: applying an on voltage to the upper select gate line coupled to the selected memory string, and applying an off voltage to the lower select gate line coupled to the selected memory string, the upper select gate line of the unselected memory string, and the lower select gate line of the unselected memory string.

8. The method according to claim 1, characterized in that, The method further includes: During the process of charging the selected word line to the programming voltage, the first dummy word line is held at the second voltage.

9. The method according to claim 1, characterized in that, The programming operation includes multiple programming loops; the method further includes: In the first charging phase of each programming cycle, the first dummy word line is charged to the first voltage; In the second charging phase of each programming cycle, the first dummy word line is charged from the first voltage to the second voltage.

10. A memory, characterized in that, include: Storage cell array, including: A word line, which is located between the upper selection gate line and the lower selection gate line; The first dummy word line is located between the upper select gate line and the word line, and / or the first dummy word line is located between the lower select gate line and the word line; Peripheral circuitry is coupled to the memory cell array; wherein, The peripheral circuit is configured to charge the first dummy word line to a first voltage during the first charging phase of the programming operation. The peripheral circuit is further configured to charge the first dummy word line from the first voltage to the second voltage during the second charging phase of the programming operation; wherein the second charging phase is located after the first charging phase, and the charging rate of the first charging phase is less than or equal to the charging rate of the second charging phase. The peripheral circuitry is further configured to charge selected word lines to a programming voltage after the second charging phase; wherein the programming voltage is greater than the second voltage.

11. The memory according to claim 10, characterized in that, The peripheral circuit is further configured to charge an unselected word line among the word lines to a pass voltage during the first charging phase and the second charging phase; wherein the pass voltage is greater than the first voltage and the pass voltage is less than or equal to the second voltage; The peripheral circuitry is configured to charge the first dummy word line to a first voltage during the first charging phase of the programming operation, including: The peripheral circuit is configured to perform a first floating operation on the first dummy word line; wherein, during the process of the peripheral circuit charging the unselected word line to the through voltage, the unselected word line couples the floating first dummy word line to the first voltage.

12. The memory according to claim 11, characterized in that, The storage cell array also includes: The second dummy character line is located between the character line and the first dummy character line; The peripheral circuit is further configured to perform a second floating operation on the second dummy word line during the first charging phase; wherein, during the process of the peripheral circuit charging the unselected word line to the through voltage, the unselected word line couples the floating second dummy word line to the first voltage; the floating duration of the second floating operation is different from the floating duration of the first floating operation.

13. The memory according to claim 12, characterized in that, The peripheral circuit is specifically configured as follows: At the first moment, the first floating operation is executed on the first dummy word line; At the second moment, the first floating operation on the first dummy word line ends; After the first moment and before the second moment, the second floating operation is performed on the second dummy word line; At the second moment, the second floating operation on the second dummy word line ends.

14. The memory according to claim 12, characterized in that, The peripheral circuit is specifically configured as follows: At the first moment, the first floating operation is executed on the first dummy word line; At the second moment, the first floating operation on the first dummy word line ends; At the first moment, the second floating operation is started on the second dummy word line; Before the second moment, the second floating operation on the second dummy word line is terminated.

15. The memory according to claim 10, characterized in that, The peripheral circuitry is configured to charge the first dummy word line to a first voltage during the first charging phase of the programming operation, including: From the first moment to the second moment, the peripheral circuit charges the first dummy word line to the first voltage; The peripheral circuitry is further configured to charge the first dummy word line from the first voltage to the second voltage during the second charging phase of the programming operation, including: During the third to fourth time points, the peripheral circuit charges the first dummy word line from the first voltage to the second voltage; The peripheral circuit is also configured to maintain the first dummy word line at the first voltage during the second time interval to the third time interval.

16. The memory according to claim 10, characterized in that, When the peripheral circuit is configured to charge the first dummy word line located between the upper select gate line and the word line to the first voltage, the peripheral circuit is further configured to: apply an on voltage to the upper select gate line coupled to the selected memory string, and apply an off voltage to the lower select gate line coupled to the selected memory string, the upper select gate line of the unselected memory string, and the lower select gate line of the unselected memory string. And / or, When the peripheral circuit is configured to charge the first dummy word line located between the lower select gate line and the word line to the first voltage, the peripheral circuit is further configured to: apply an on voltage to the upper select gate line coupled to the selected memory string, and apply an off voltage to the lower select gate line coupled to the selected memory string, the upper select gate line of the unselected memory string, and the lower select gate line of the unselected memory string.

17. The memory according to claim 10, characterized in that, The peripheral circuitry is also configured to maintain the first dummy word line at the second voltage while charging the selected word line to the programming voltage.

18. The memory according to claim 10, characterized in that, The programming operations include multiple programming loops; The peripheral circuitry is configured to charge the first dummy word line to the first voltage during the first charging phase of each programming cycle. The peripheral circuitry is also configured to charge the first dummy word line from the first voltage to the second voltage during the second charging phase of each programming cycle.

19. A memory system, characterized in that, include: One or more memories as described in any one of claims 10 to 18; A memory controller, coupled to the memory and configured to control the memory.

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