Direct current bus voltage control

Abstract

For direct current (DC) bus voltage control, one method generates a q-axis reference current from a DC voltage error that includes a DC voltage input modified by a DC bus voltage in a closed outer loop. The method also generates a d-axis reference current from the DC voltage error, where a second order harmonic in the d-axis reference current is delayed 90 degrees from a second order harmonic in the q-axis reference current. The method generates a q-axis current from the q-axis reference current. The method generates a d-axis current from the d-axis reference current. A second order harmonic in the d-axis current is offset 90 degrees from a second order harmonic in the q-axis current. The method controls a DC bus voltage of a voltage control device to mitigate a second order harmonic in the DC bus voltage with the second order harmonic in the q-axis current and the second order harmonic in the d-axis current.

Description

Technical Field

[0001] The subject matter disclosed herein relates to DC bus voltage control, and more particularly to DC bus voltage control for grid-connected converters. Background Technology

[0002] Voltage imbalances in the mains grid can generate significant second-order harmonic oscillations. These imbalances can be caused by impedance imbalances between the mains voltage and the filter. Filtering out second-order harmonic oscillations typically requires more expensive capacitors in the filter. Furthermore, second-order harmonic oscillations can reduce filter lifespan, thereby decreasing power system reliability and increasing maintenance costs. Summary of the Invention

[0003] A method for DC bus voltage control is disclosed. This method uses a voltage regulator based on the DC voltage error V'. DC To generate q-axis reference current The DC voltage error V' DC Includes DC voltage input modified via DC bus voltage in a closed outer loop. This method also uses a voltage regulator to generate a d-axis reference current from a DC voltage error. Among them, the d-axis reference current The second harmonic in the q-axis reference current The second harmonic delay is 90 degrees. This method utilizes the second inner loop current to control the q-axis reference current. To generate q-axis current i q This method utilizes the first inner loop current to control the d-axis reference current. To generate d-axis current i d d-axis current i d Second harmonics and q-axis current i q The second harmonic is offset by 90 degrees. This method controls the DC bus voltage of the voltage control device to utilize the q-axis current i. q Second-order harmonics and d-axis current i in d The second harmonic in the DC bus voltage is reduced to mitigate the second harmonic in the DC bus voltage.

[0004] A device for DC bus voltage control is disclosed. The device includes a voltage regulator, a second inner loop current control, and a first inner loop current control. The voltage regulator is controlled by a DC voltage error V'. DC Generate q-axis reference current Furthermore, the d-axis reference current is generated from the DC voltage error. DC voltage error V' DC Includes DC voltage input modified via DC bus voltage in a closed outer loop. Among them, the d-axis reference current The second harmonic in the q-axis reference current The second harmonic delay is 90 degrees. The second inner loop current control is based on the q-axis reference current. Generate q-axis current i q The first inner loop current control is based on the d-axis reference current. To generate d-axis current i d d-axis current i d Second harmonics and q-axis current i q The second harmonic is offset by 90 degrees. The first inner loop current and the second inner loop current control the DC bus voltage of the voltage control device to utilize the q-axis current i. q and d-axis current i d The second harmonic in the DC bus voltage is reduced to mitigate the second harmonic in the DC bus voltage.

[0005] A computer program product for DC bus voltage control is also disclosed. This computer program product includes a computer-readable storage medium containing program code that can be read / executed by a processor. The processor is controlled by a DC voltage error V'. DC Generate q-axis reference current The DC voltage error V' DC Includes DC voltage input modified via DC bus voltage in a closed outer loop. The processor generates a d-axis reference current based on the DC voltage error. Among them, the d-axis reference current The second harmonic in the q-axis reference current The second harmonic delay is 90 degrees. The processor is referenced by the q-axis current. To generate q-axis current i q The processor is referenced by the d-axis current. To generate d-axis current i d , where the d-axis current i d Second harmonics and q-axis current i q The second harmonic is offset by 90 degrees. The processor controls the DC bus voltage of the voltage control device to utilize the q-axis current i. q Second-order harmonics and d-axis current i in d The second harmonic is used to reduce the second harmonic in the DC bus voltage. Attached Figure Description

[0006] To facilitate understanding of the advantages of embodiments of the present invention, a more detailed description of the embodiments briefly described above will be presented with reference to the specific embodiments shown in the accompanying drawings. While understanding that these drawings depict only some embodiments and should not be considered as limiting the scope, these embodiments will be described and explained more specifically and in detail using the drawings, in which:

[0007] Figure 1A It is a schematic block diagram of a power system according to the implementation method;

[0008] Figure 1B This is a schematic block diagram of a power supply device according to an embodiment;

[0009] Figure 2A This is a schematic block diagram of a voltage regulator according to an implementation method;

[0010] Figure 2B It is a schematic block diagram of the control system according to the implementation method;

[0011] Figure 3 It is a schematic block diagram of control data according to the implementation method;

[0012] Figure 4 It is a schematic block diagram of a computer according to an implementation method;

[0013] Figure 5A This is a schematic flowchart of the voltage control method according to the implementation method;

[0014] Figure 5B This is a schematic flowchart of the reference current generation method according to the implementation method;

[0015] Figure 6A It is based on the voltage phasor diagram of the implementation method;

[0016] Figure 6B It is the waveform of the prior art DC bus voltage according to the implementation method;

[0017] Figure 6C It is the waveform of the DC bus voltage according to the implementation method;

[0018] Figure 7A It is based on the voltage phasor diagram of the implementation method;

[0019] Figure 7B It is the waveform of the prior art DC bus voltage according to the implementation method; and

[0020] Figure 7C It is the waveform of the DC bus voltage according to the implementation method. Detailed Implementation

[0021] Throughout this specification, references to “one embodiment,” “implementation,” or similar language mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, unless otherwise expressly stated, the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, refer to the same embodiment, but rather mean “one or more, but not all, embodiments.” Unless otherwise expressly stated, the terms “comprising,” “including,” “having,” and variations thereof mean “including, but not limited to,” “including ...

[0022] Furthermore, the features, advantages, and characteristics of the described embodiments can be combined in any suitable manner. Those skilled in the art will recognize that embodiments can be practiced without one or more specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments may be recognized in some embodiments.

[0023] These features and advantages of the embodiments will become more apparent from the following description and the appended claims, or may be learned by practice of the embodiments as set forth below. As will be understood by those skilled in the art, various aspects of the invention can be implemented as systems, methods, and / or computer program products. Therefore, various aspects of the invention can take the form of purely hardware implementations, purely software implementations (including firmware, resident software, microcode, etc.), or implementations combining software and hardware aspects, all of which may be generally referred to herein as “circuit,” “module,” or “system.” Furthermore, various aspects of the invention can take the form of computer program products implemented on one or more computer-readable media having program code thereon.

[0024] Many of the functional units described in this specification have been labeled as modules to more specifically emphasize the implementation independence of many functional units. For example, a module can be implemented as a hardware circuit that includes custom VLSI circuitry or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. Modules can also be implemented as programmable hardware devices such as field-programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0025] Modules can also be implemented in software for execution by various types of processors. The identified program code module may, for example, comprise one or more physical or logical blocks of computer instructions, which may be organized, for example, as objects, procedures, or functions. However, the executable file of the identified module does not need to be physically located together, but may include different instructions stored in different locations that, when logically combined, include the module and achieve its intended purpose.

[0026] In practice, a module of program code can be a single instruction or many instructions, and can even be distributed across several different code segments, across different programs, and across several storage devices. Similarly, operational data can be identified and illustrated within the module herein, and this operational data can be implemented in any suitable form and can be organized within any suitable type of data structure. Operational data can be collected as a single dataset or can be distributed across different locations, including across different storage devices, and can exist at least partially as electronic signals within a system or network. In the case of implementing a module or part of a module in software, the program code can be stored on one or more computer-readable media and / or propagated on one or more computer-readable media.

[0027] A computer-readable medium can be a tangible computer-readable storage medium that stores program code. A computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, holographic, micromechanical, or semiconductor system, device, or apparatus, or any suitable combination of the foregoing.

[0028] More specific examples of computer-readable storage media may include, but are not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), optical storage devices, magnetic storage devices, holographic storage media, micromechanical storage devices, or any suitable combination thereof. In the context of this document, a computer-readable storage medium can be any tangible medium that may include and / or store program code for use by, or in conjunction with, an instruction execution system, device, or apparatus.

[0029] Computer-readable media can also be computer-readable signal media. Computer-readable signal media can include propagated data signals containing program code, such as data signals in baseband or data signals as part of a carrier wave. Such propagated signals can take any of a variety of forms, including but not limited to electrical, electromagnetic, magnetic, optical, or any suitable combination thereof. Computer-readable signal media can be any computer-readable medium that is not a computer-readable storage medium but can transmit, propagate, or deliver program code for use by or in conjunction with an instruction execution system, device, or apparatus. Program code implemented on a computer-readable signal medium can be transmitted using any suitable medium, including but not limited to wireline, optical fiber, radio frequency (RF), or any suitable combination thereof.

[0030] In one implementation, a computer-readable medium may include a combination of one or more computer-readable storage media and one or more computer-readable signal media. For example, program code may be transmitted as an electromagnetic signal via fiber optic cable for processor execution, or it may be stored on a RAM storage device for processor execution.

[0031] The program code used to perform the operations of various aspects of this invention can be written in any combination of one or more programming languages, including: object-oriented programming languages ​​such as Python, Ruby, R, Java, JavaScript, Smalltalk, C++, C sharp, Lisp, Clojure, PHP, etc., and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet provided by an Internet service provider). The computer program product can be shared, thereby serving multiple customers simultaneously in a flexible and automated manner.

[0032] Computer program products can be integrated into client, server, and network environments by configuring the computer program product to coexist with applications, operating systems, and network operating system software, and then installing the computer program product on clients and servers in the environments where it will operate. In one implementation, software is identified on clients and servers that include a network operating system in which the computer program product will be deployed; this software is required by or works with the computer program product. This includes the network operating system, which is software that enhances the basic operating system by adding networking capabilities.

[0033] Furthermore, the features, structures, or characteristics of the described embodiments can be combined in any suitable manner. In the following description, numerous specific details, such as examples of programming, software modules, user selection, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., are provided to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that embodiments can be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the embodiments.

[0034] The implementation can transmit data between electronic devices. The implementation can also convert data from a first format to a second format, including converting data from a non-standard format to a standard format and / or converting data from a standard format to a non-standard format. The implementation can modify, update, and / or process data. The implementation can store received, converted, modified, updated, and / or processed data. The implementation can provide remote access to data, including updated data. The implementation can make data and / or updated data available in real time. The implementation can generate and transmit messages in real time based on data and / or updated data. The implementation can securely transmit encrypted data. The implementation can organize data for efficient verification. Additionally, the implementation can verify data in response to action and / or lack thereof.

[0035] The following description of various aspects of the embodiments is based on schematic flowcharts and / or schematic block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the present invention. It should be understood that each block in the schematic flowcharts and / or schematic block diagrams, as well as combinations of blocks in the schematic flowcharts and / or schematic block diagrams, can be implemented by program code. The program code can be provided to a processor of a general-purpose computer, special-purpose computer, sequencer, or other programmable data processing apparatus to generate machine learning, such that instructions, when executed via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the schematic flowcharts and / or schematic block diagrams.

[0036] The program code may also be stored in a computer-readable medium that can direct a computer, other programmable data processing device or other means to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of art including instructions that implement the functions / actions specified in one or more boxes of a schematic flowchart and / or schematic block diagram.

[0037] Program code may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce computer-implemented processing, such that the program code executing on the computer or other programmable apparatus provides processing for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0038] The schematic flowcharts and / or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the schematic flowcharts and / or block diagrams may represent a code module, code segment, or portion of code comprising one or more executable instructions for implementing a specified logical function.

[0039] It should also be noted that in some alternative implementations, the functions indicated in the boxes may not occur in the order shown in the figures. For example, two boxes shown consecutively may actually be executed substantially simultaneously, or the two boxes may sometimes be executed in reverse order, depending on the functions involved. Other steps and methods that are functionally, logically, or effectively equivalent to one or more boxes or a portion of those boxes shown in the figures can be envisioned.

[0040] While various arrow and line types may be used in flowcharts and / or block diagrams, they should be understood as not limiting the scope of the corresponding implementation. In fact, some arrows or other connectors may be used solely to indicate the logical flow of the depicted implementation. For example, an arrow may indicate a waiting or monitoring period of unspecified duration between the enumerated steps of the depicted implementation. It should also be noted that each box in a block diagram and / or flowchart, and combinations of boxes in block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system performing the specified function or action, or by a combination of dedicated hardware and program code.

[0041] The description of the elements in each figure can be referenced to the elements in the preceding figures. In all figures, similar reference numerals refer to similar elements, including alternative embodiments of similar elements.

[0042] Figure 1A This is a schematic block diagram of a power system 100. In the depicted embodiment, the power supply unit 102 generates a DC bus voltage V from the grid voltage 120. DC 133. DC bus voltage V DC 133 can be filtered by filter 104 to supply power to converter 106, which supplies power to load 108. Due to the unbalanced mains voltage 120, the DC bus voltage V DC 133 may include significant second-order harmonic oscillations. Additionally, impedance imbalance between the mains voltage 120 and filter 104 can generate significant second-order harmonic oscillations. Second-order harmonic oscillations typically require increasing the capacitance in filter 104, thus increasing the cost of filter 104. Furthermore, second-order harmonic oscillations can reduce the lifespan of filter 104, decrease the reliability of power system 100, and increase maintenance costs. Second-order harmonic oscillations can also affect load 108.

[0043] The implementation described herein utilizes the second harmonics in the q-axis and d-axis currents, as will be described below, to mitigate second harmonic oscillations in the DC bus voltage 133. This reduces the cost of filter 104 and filter maintenance. Furthermore, it improves the reliability of the power system 100.

[0044] Figure 1B yes Figure 1A A schematic block diagram of the power supply device 102. The power supply device 102 receives a DC voltage input. 127. DC voltage input 127 passes through the DC bus voltage V in the closed outer loop 117. DC 133 was modified to generate the DC voltage error V' of the drive voltage regulator 101. DC128. Arithmetic function 143 can add values ​​and / or signals and / or subtract values ​​and / or signals. Arithmetic function 143 can be executed by electronic components and / or a computer.

[0045] The following text will be Figure 2A As described, voltage regulator 101 generates q-axis reference current. 130 and d-axis reference current 129. In one embodiment, as will be described below, the voltage regulator 101 can be based on a proportional-integral-resonant (PIR) controller and a d-axis current reference input, and the DC voltage error V' DC 128 generates q-axis reference current 130 and d-axis reference current 129.

[0046] q-axis reference current 130 minus q-axis current i q 135 drives the second inner loop current control 103b to generate the q-axis current i q 135. d-axis reference current 129 minus d-axis current i d 125 drives the first inner loop current control 103a to generate the d-axis current i d 125. In Figure 2B The first inner loop current control 103a and the second inner loop current control 103b are described in more detail.

[0047] d-axis current i d The second harmonics and q-axis current i in 125 q The second harmonic in 135 is offset by 90 degrees. Therefore, the d-axis current i d Second harmonics and q-axis current i in 125 q The second harmonics in 135 cancel each other out. The d-axis current i d 125 and q-axis current i q The voltage control device 105 controls the generation of DC bus voltage 133, thereby reducing the second harmonic in DC bus voltage 133.

[0048] Figure 2A yes Figure 1B A schematic block diagram of a voltage regulator 101. In the depicted embodiment, the proportional controller 201 receives a DC voltage error V'. DC 128 and generates a proportional error 121. The resonant regulator 203 generates a regulating harmonic current 122 from the proportional error 121. In one embodiment, the resonant regulator 203 implements the function G as shown in Equation 1. r(s), where s is the transfer function, k r It is a proportionality constant, Δθ is the compensation angle, and ω e It is the estimated base frequency of the power grid.

[0049] Formula 1

[0050] In an alternative embodiment, the resonant regulator 203 implements a function G with a compensation angle Δθ of 180 degrees as shown in Equation 2. r (s).

[0051] Formula 2

[0052] The q-axis intermediate current 126 is generated based on the proportional error 121. In the described embodiment, the q-axis intermediate current 126 is the sum of the proportional error 121 and the adjustment harmonic current 122.

[0053] The integral controller 205 filters the proportional error 121 to generate the integral current reference 123. This generates the q-axis reference current. 130 is the sum of the q-axis intermediate current 126 and the integral current reference 123.

[0054] The q-axis intermediate current 126 can be filtered using a low-pass filter 207 to generate the d-axis intermediate current 131. In one embodiment, the low-pass filter 207 implements the function G shown in Equation 3. t (s), where s is the transfer function, k is a constant, and ω e It is the estimated base frequency of the power grid.

[0055] Formula 3

[0056] Generate as d-axis reference current 129 is the sum of the d-axis intermediate current 131 and the d-axis current reference input 137. The d-axis current i d The second harmonics and q-axis current i in 125 q The second harmonic in 135 is offset by 90 degrees.

[0057] Figure 2B This is a schematic block diagram of the power supply device 102. The DC voltage error V' is received by the voltage regulator 101. DC 128, the DC voltage error V' DC 128 includes a DC voltage input modified via DC bus voltage 133. 127. Voltage regulator 101 can generate q-axis reference current based on proportional-integral-resonant (PIR) controller and d-axis current reference input 137, and DC voltage error 128. 130 and d-axis reference current 129. For example Figure 2A As shown, voltage regulator 101 can generate q-axis reference current. 130 and d-axis reference current 129.

[0058] In one implementation, the abc-dq reference frame transformation 225 receives the three-phase grid voltage e of the grid voltage 120. abc 259 and three-phase current i abc 261. Transformation from abc to dq reference frame 225 Generates d-axis current i d 125. q-axis current i q 135. d-axis grid voltage e d 241 and q-axis grid voltage e q 242. In one implementation, Equation 4 is used to determine the d-axis current i. d 125 and q-axis current i q 135, where i a i b i c It is the three-phase current i abc The three phase currents of 261, and θ e It is the phase angle θ of the grid voltage. e 251.

[0059] Formula 4

[0060] Phase-locked loop (PLL) 227 based on d-axis grid voltage e d 241 and q-axis grid voltage e q 242 is used to generate the estimated power grid fundamental frequency ω e 253 and grid voltage phase angle θ e 251.

[0061] The first inner loop current control 103a is based on the d-axis reference current. 129 minus d-axis current i d 125, and this difference is modified using the first proportional / integral controller 221a. The q-axis current i is multiplied by the filter inductive reactance 223b. q 135 is subtracted from the output of the first proportional / integral controller 221a to generate the d-axis output 263. The d-axis output 263 is added to the d-axis mains voltage 241 to generate the d-axis voltage output. 161.

[0062] The second inner loop current control 103b obtains the q-axis reference current. 130 minus q-axis current i q135, and this difference is modified using the second proportional / integral controller 221b. The d-axis current i multiplied by the filter inductive reactance 223a... d The inverse value of 125 is subtracted from the output of the second proportional-integral controller 221b to generate the q-axis output 265. The q-axis output 265 is then added to the q-axis mains voltage 242 to generate the q-axis voltage output. 163.

[0063] Because the d-axis current i d The second harmonics and q-axis current i in 125 q The second harmonic offset in 135 is 90 degrees, and the d-axis voltage output is... Second harmonic and q-axis voltage output in 161 The second harmonics in 163 are canceled out by the voltage control device 105, which receives the d-axis voltage output. 161 and q-axis voltage output 163 and generates a DC bus voltage V with reduced second harmonics. DC 133.

[0064] Figure 3 This is a schematic block diagram of control data 300. Control data 300 can be used to control the DC bus voltage 133 of the voltage control device 105. Control data 300 can be organized as a data structure in memory. In the depicted embodiment, control data 300 includes a compensation angle Δθ 301. As described in Equation 1, the resonant regulator 203 can employ a compensation angle Δθ 301. In one embodiment, the resonant regulator 203 can be 180 degrees as in Equation 2.

[0065] Figure 4 This is a schematic block diagram of a computer 400. The computer 400 can perform one or more functions for the power supply device 102, voltage regulator 101, and / or internal loop current control 103a to 103b. In the depicted embodiment, the computer 400 includes a processor 405, a memory 410, and communication hardware 415. The memory 410 can store code and data. The processor 405 can execute code and process data. The communication hardware 415 can communicate with other devices.

[0066] Figure 5AThis is a schematic flowchart of voltage control method 500. Method 500 can control the DC bus voltage 133 of voltage control device 105 to mitigate second harmonics. Method 500 can be performed by power supply device 102 and / or its components. In one embodiment, method 500 is performed by computer 400 that performs the functions of voltage regulator 101, first inner loop current control 103a and second inner loop current control 103b, ABC to DQ reference frame transformation 225 and / or PLL 227.

[0067] Method 500 begins, and in one embodiment, the voltage regulator 101 is controlled by a DC voltage error V'. DC 128 generates 501 q-axis reference current 130. DC voltage error V' DC 128 may include a DC voltage input modified by DC bus voltage 133 in the closed outer loop 117. 127, such as Figure 1B As shown. In Figure 5B The generation of the 501 q-axis reference current is described in more detail. Implementation method of 130.

[0068] Voltage regulator 101 can also generate a 503 d-axis reference current from DC voltage error 128. 129. d-axis reference current The second harmonic ratio q-axis reference current in 129 The second harmonic delay in 130 is 90 degrees. Figure 5B The generation of the 503 d-axis reference current is described in more detail. Implementation method of 129.

[0069] The second inner loop current control 103b can be determined by the q-axis reference current. 130 generates 505 q-axis current 135, such as Figure 2B As shown. Additionally, the first inner loop current control 103a can be controlled by the d-axis reference current. 129 generates 507 d-axis currents 125.

[0070] The first inner loop current control 103a and the second inner loop current control 103b can utilize the q-axis current i q Second harmonics and d-axis current i in 135 dThe second harmonic in 125 reduces the second harmonic in DC bus voltage 133 to control the DC bus voltage 133 of voltage control device 105 509. As a result, the second harmonic in DC bus voltage 133 is reduced. Power supply device 102 also supplies 511 power to load 108, such as Figure 1A As shown.

[0071] Figure 5B This is a schematic flowchart of reference current generation method 550. Method 550 can generate q-axis current i. q 135 and d-axis current i d 125. In one implementation, method 550 is performed. Figure 5A Steps 501 and 503. Method 550 may be performed by the power supply device 102 and / or its components. In one embodiment, method 550 is performed by a computer 400 that performs the functions of the voltage regulator 101.

[0072] Method 550 begins, and in one embodiment, proportional controller 201 modifies 551 the DC voltage error 128 to generate a proportional error 121. Integral controller 205 can filter 553 the proportional error 121 to generate an integral current reference 123.

[0073] Arithmetic function 143 can generate a 555 q-axis intermediate current 126 from proportional error 121. In one embodiment, the q-axis intermediate current 126 is generated as the sum of proportional error 121 and adjusted harmonic current 122, which is generated based on proportional error 121 adjusted by resonant regulator 203. Resonant regulator 203 can implement Equation 1 or Equation 2.

[0074] The low-pass filter 207 can filter the q-axis intermediate current 126 to generate the d-axis intermediate current 131. The low-pass filter 207 can implement Equation 3. The d-axis intermediate current 131 can be generated based on the harmonic current 122 filtered by the low-pass filter 207. In addition, the generated q-axis intermediate current 126 is the sum of the proportional error 121 and the adjusted harmonic current 122, which is generated based on the proportional error 121 adjusted by the resonant modulator 203.

[0075] Arithmetic function 143 can generate a 559 q-axis reference current. 130 is the sum of the q-axis intermediate current 126 and the integral current reference 123. The arithmetic function 143 can also generate the d-axis reference current 561. 129 is the sum of the d-axis intermediate current 131 and the d-axis current reference input 137, and method 550 ends.

[0076] Figure 6A It is shown Figures 6B to 6C The voltage phasor diagram of the voltage phases. The three-phase grid voltages 120A to 120C are shown as having a phase A voltage imbalance of 119A.

[0077] Figure 6B It is controlled using existing technology. Figure 6A The voltage phasor diagram shows the waveforms of the DC bus voltage 133 and the three-phase currents 113a to 113c of the voltage control device 105. The waveforms are for a 30% voltage sag. The second harmonic is shown in the DC bus voltage 133.

[0078] Figure 6C This is the implementation method. Figure 6A The voltage phasor diagram shows the waveforms of the DC bus voltage 133 and the three-phase currents 113a to 113c of the voltage control device 105. The waveforms are for a 30% voltage sag. As shown, this reduces... Figure 6B The second harmonic.

[0079] Figure 7A It is aimed at Figures 7B to 7C Voltage phasor diagram. The three-phase grid voltages 120a to 120c are shown as having phase A voltage imbalance 119a to phase B voltage imbalance 119b.

[0080] Figure 7B It is controlled using existing technology. Figure 7A The voltage phasor diagram shows the waveforms of the DC bus voltage 133 and the three-phase currents 113a to 113c of the voltage control device 105. The waveforms are for a 30% voltage sag. The second harmonic is shown in the DC bus voltage 133.

[0081] Figure 7C This is the implementation method. Figure 7A The voltage phasor diagram shows the waveforms of the DC bus voltage 133 and the three-phase currents 113a to 113c of the voltage control device 105. The waveforms are for a 30% voltage sag. As shown, this reduces... Figure 6B The second harmonic.

[0082] Problem / Solution

[0083] Imbalances in the mains voltage 120 can generate significant second-order harmonic oscillations. This imbalance can be caused by impedance imbalances between the mains voltage 120 and the filter 104. Filtering out second-order harmonic oscillations typically requires more expensive capacitors in the filter 104. Furthermore, second-order harmonic oscillations can reduce the lifespan of the filter 104, thereby reducing the reliability of the power system 100 and increasing maintenance costs.

[0084] The implementation utilizes the second harmonics in the q-axis current 135 and the second harmonics in the d-axis current 125 to mitigate the second harmonic oscillations in the DC bus voltage 133. Therefore, the cost of filter maintenance and filter 104 is reduced, thereby improving the cost-effectiveness and reliability of the power system 100.

[0085] This specification uses examples to disclose the invention and also enables any person skilled in the art to practice the invention, including making and using any apparatus or system and performing any incorporated methods. The patentable scope of the invention is defined by the claims and may include other examples that would occur to a person skilled in the art. Such other examples are intended to fall within the scope of the claims if they have structural elements that are not different from the literal language of the claims, or if they include equivalent structural elements that are not substantially different from the literal language of the claims.

Claims

1. A method for DC bus voltage control, comprising: A voltage regulator is used to generate a q-axis reference current from a DC voltage error, which includes a DC voltage input modified by the DC bus voltage in a closed outer loop. The voltage regulator is used to generate a d-axis reference current from the DC voltage error, wherein the second harmonic in the d-axis reference current is delayed by 90 degrees from the second harmonic in the q-axis reference current. The q-axis current is generated from the q-axis reference current using the second inner loop current control. The d-axis current is generated from the d-axis reference current using the first inner loop current control, wherein the second harmonic in the d-axis current is offset by 90 degrees from the second harmonic in the q-axis current; and The DC bus voltage of the voltage control device is controlled by canceling the second harmonics in the d-axis current and the second harmonics in the q-axis current, so as to reduce the second harmonics in the DC bus voltage by utilizing the second harmonics in the q-axis current and the second harmonics in the d-axis current.

2. The method according to claim 1, wherein, The q-axis reference current and the d-axis reference current are generated from the DC voltage error based on the proportional-integral-resonant PIR controller and the d-axis current reference input.

3. The method according to claim 1, further comprising: The DC voltage error is modified using a proportional controller to generate a proportional error; The proportional error is filtered using an integral controller to generate an integral current reference; The q-axis intermediate current is generated from the aforementioned proportional error; The q-axis intermediate current is filtered using a low-pass filter to generate the d-axis intermediate current; The q-axis reference current is generated as the sum of the q-axis intermediate current and the integral current reference; as well as The d-axis reference current is generated as the sum of the d-axis intermediate current and the d-axis current reference input.

4. The method according to claim 3, wherein, The d-axis intermediate current is generated from the harmonic current filtered by the low-pass filter.

5. The method according to claim 3, wherein, The low-pass filter implementation function Where s is the transfer function, k is a constant, and ω e It is the estimated base frequency of the power grid.

6. The method according to claim 3, wherein, The q-axis intermediate current is generated as the sum of the proportional error and the adjusted harmonic current, which is generated by the proportional error adjusted by the resonant regulator.

7. The method according to claim 6, wherein, The resonant tuner implements the function Where s is the transfer function, k r It is a proportionality constant. It is a compensation angle, and ω e It is the estimated base frequency of the power grid.

8. The method according to claim 6, wherein, The resonant tuner implements the function Where s is the transfer function, k r It is a proportionality constant. It is a compensation angle, and ω e It is the estimated base frequency of the power grid.

9. The method according to claim 8, wherein, The compensation angle is 180 degrees.

10. A device for DC bus voltage control, comprising: A voltage regulator that generates a q-axis reference current from a DC voltage error and a d-axis reference current from the same DC voltage error, the DC voltage error including a DC voltage input modified by a DC bus voltage in a closed outer loop, wherein the second harmonic in the d-axis reference current is delayed by 90 degrees from the second harmonic in the q-axis reference current; The second inner loop current control generates the q-axis current i from the q-axis reference current. q ;as well as The first inner loop current control generates the d-axis current i from the d-axis reference current. d The second harmonic in the d-axis current is offset by 90 degrees from the second harmonic in the q-axis current. The first inner loop current and the second inner loop current control the DC bus voltage of the voltage control device by canceling the second harmonic in the d-axis current and the second harmonic in the q-axis current, so as to reduce the second harmonic in the DC bus voltage by utilizing the second harmonic in the q-axis current and the second harmonic in the d-axis current.

11. The device according to claim 10, wherein, The q-axis reference current and the d-axis reference current are generated based on the proportional-integral-resonant PIR controller and the d-axis current reference input, using the DC voltage error.

12. The device according to claim 10, wherein the voltage regulator further performs the following operations: The DC voltage error is modified using a proportional controller to generate a proportional error; The proportional error is filtered using an integral controller to generate an integral current reference; The q-axis intermediate current is generated based on the aforementioned proportional error; The q-axis intermediate current is filtered using a low-pass filter to generate the d-axis intermediate current; The q-axis reference current is generated as the sum of the q-axis intermediate current and the integral current reference; as well as The d-axis reference current is generated as the sum of the d-axis intermediate current and the d-axis current reference input.

13. The device according to claim 12, wherein, The d-axis intermediate current is generated from the harmonic current filtered by the low-pass filter.

14. The device according to claim 12, wherein, The low-pass filter implementation function Where s is the transfer function, k is a constant, and ω e It is the estimated base frequency of the power grid.

15. The device according to claim 12, wherein, The q-axis intermediate current is generated as the sum of the proportional error and the adjusted harmonic current, which is generated by the proportional error adjusted by the resonant regulator.

16. A computer program product comprising a computer-readable storage medium containing program code executable by a processor to perform the following operations: A q-axis reference current is generated from a DC voltage error, wherein the DC voltage error includes a DC voltage input modified by the DC bus voltage in a closed outer loop; The d-axis reference current is generated from the DC voltage error, wherein, The second harmonic in the d-axis reference current is delayed by 90 degrees from the second harmonic in the q-axis reference current. The q-axis current is generated from the q-axis reference current; The d-axis current is generated from the d-axis reference current, wherein the second harmonic in the d-axis current is offset by 90 degrees from the second harmonic in the q-axis current. as well as The DC bus voltage of the voltage control device is controlled by canceling the second harmonics in the d-axis current and the second harmonics in the q-axis current, so as to reduce the second harmonics in the DC bus voltage by utilizing the second harmonics in the q-axis current and the second harmonics in the d-axis current.

17. The computer program product according to claim 16, wherein, The q-axis reference current and the d-axis reference current are generated based on the proportional-integral-resonant PIR controller and the d-axis current reference input, and the DC voltage error.

18. The computer program product according to claim 16, wherein the processor further performs the following operations: The DC voltage error is modified using a proportional controller to generate a proportional error; The proportional error is filtered using an integral controller to generate an integral current reference; The q-axis intermediate current is generated from the aforementioned proportional error; The q-axis intermediate current is filtered using a low-pass filter to generate the d-axis intermediate current; The q-axis reference current is generated as the sum of the q-axis intermediate current and the integral current reference; as well as The d-axis reference current is generated as the sum of the d-axis intermediate current and the d-axis current reference input.

19. The computer program product according to claim 18, wherein, The d-axis intermediate current is generated from the harmonic current filtered by the low-pass filter.

20. The computer program product according to claim 18, wherein, The low-pass filter implementation function Where s is the transfer function, k is a constant, and ω e It is the estimated base frequency of the power grid.

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