Verification method, electronic device, and storage medium

Abstract

The application provides a method for verifying a logical system design, an electronic device and a storage medium. The method comprises: receiving a verification target of a user; calling a plurality of verification tools respectively via a calling interface of an integration tool according to the verification target; generating a multi-tool verification process based on the verification target and the plurality of verification tools; and calling the plurality of verification tools to achieve the verification target according to the multi-tool verification process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer software, and particularly relates to a method for verifying a logic system design, an electronic device and a storage medium. BACKGROUND

[0002] In the field of integrated circuit verification, simulation generally refers to running a design on a computer after compiling the design to simulate and test various functions of the logic system design. The logic system design can be, for example, a design for an Application Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a specific application. Therefore, the design to be tested or verified in simulation can also be referred to as a Device Under Test (DUT).

[0003] With the expansion of the scale of chip design, the number of verification tools required to verify the logic system design is increasing. However, there is currently a lack of coordination between various verification tools. Users cannot conveniently call multiple verification tools for coordinated verification. SUMMARY

[0004] In view of this, the present application provides a verification method, an electronic device and a storage medium.

[0005] A first aspect of the present application provides a method for verifying a logic system design. The method comprises: receiving a verification target of a user; calling multiple verification tools via a calling interface of an integration tool according to the verification target; generating a multi-tool verification flow based on the verification target and the multiple verification tools; and calling the multiple verification tools according to the multi-tool verification flow to achieve the verification target.

[0006] A second aspect of the present application provides an electronic device. The electronic device comprises: a memory configured to store a set of instructions; and at least one processor configured to execute the set of instructions to perform the method of the first aspect.

[0007] A third aspect of the present application provides a non-transitory computer-readable storage medium storing a set of instructions of an electronic device, the set of instructions being used to cause the electronic device to perform the method of the first aspect.

[0008] The verification method, the electronic device and the storage medium provided by the application integrate and further edit the capabilities of multiple verification tools through the integration tool, so that the user can flexibly design the verification function required by the user, and the efficiency of the user in verifying the logical system design is improved. In addition, in the case that the user temporarily lacks an individual verification tool locally, the integration tool provided by the embodiment of the application can also call the individual verification tool from the cloud to meet the temporary needs of the user. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only a part of the application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0010] Figure 1A A structural schematic diagram of an exemplary electronic device according to an embodiment of the application is shown.

[0011] Figure 1A A set of exemplary verification tools according to an embodiment of the application is shown.

[0012] Figure 2 A schematic diagram of an integration tool according to an embodiment of the application is shown.

[0013] Figure 3 A schematic diagram of a verification tool in the cloud according to an embodiment of the application is shown.

[0014] Figure 4 A schematic diagram of a flow for achieving a verification target according to an embodiment of the application is shown.

[0015] Figure 5 A flowchart of a method for verifying a logical system design according to an embodiment of the application is shown. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the application more clear, the application will be further described in detail below with reference to the specific embodiments and the drawings.

[0017] It should be noted that the technical terms or scientific terms used in the present application should be understood as the general meaning understood by a person with ordinary skills in the art to which the present application belongs, unless otherwise defined. The terms "first", "second" and the like used in the present application do not represent any order, number or importance, but are only used to distinguish different components. The terms "include" or "contain" and the like mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and the like are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect.

[0018] Figure 1A A structural schematic diagram of an electronic device 100 according to an embodiment of the present application is shown. The electronic device 100 may, for example, be a computer host. The electronic device 100 can include a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other for internal communication of the device through the bus 110.

[0019] The processor 102 can be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 can be used to perform functions related to the technology described in the present application. In some embodiments, the processor 102 can also include multiple processors integrated as a single logic component. For example, Figure 1A As shown, the processor 102 can include multiple processors 102a, 102b and 102c.

[0020] The memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as Figure 1AAs shown, the stored data can include program instructions (e.g., program instructions for implementing the technical solutions of the present application) and data to be processed (e.g., the memory 104 can store temporary code generated in a compilation process). The processor 102 can also access the stored program instructions and data, and execute the program instructions to operate on the data to be processed. The memory 104 can include volatile storage or non-volatile storage. In some embodiments, the memory 104 can include random access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard disk, solid state disk (SSD), flash memory, memory stick, etc.

[0021] The network interface 106 can be configured to provide communication with other external devices to the electronic device 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It can be understood that the type of network is not limited to the specific examples described above. In some embodiments, the network interface 106 can include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0022] The peripheral interface 108 can be configured to connect the electronic device 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices can include input devices such as keyboards, mice, touchpads, touchscreens, microphones, various sensors, etc., and output devices such as displays, speakers, vibrators, indicator lights, etc.

[0023] The bus 110 can be configured to transmit information between various components of the electronic device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as internal buses (e.g., processor-memory buses), external buses (USB ports, PCI-E buses), etc.

[0024] It should be noted that although the above device only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the specific implementation process, the device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only contain the components necessary for implementing the embodiments of the present application, and does not necessarily contain all the components shown in the figure.

[0025] Figure 1B A set of example verification tools according to embodiments of the present application is shown.

[0026] As Figure 1BAs shown, in the verification process of a logic system design (e.g., a chip design), a plurality of verification tools can be involved, such as simulation tools, formal verification tools, PSS (Portable Stimulus Standard) tools, waveform tools, debugging tools, equivalence verification tools, etc. In the prior art, these verification tools can only be run individually and cannot be integrated and invoked.

[0027] However, in the actual verification process of a logic system design (e.g., a chip design), a plurality of tools often need to cooperate to achieve efficient verification.

[0028] To solve the above problems, embodiments of the present application provide a verification method, an electronic device and a storage medium to efficiently integrate a plurality of verification tools and facilitate a verification user to implement a custom function as desired.

[0029] Figure 2 A schematic diagram of an integrated tool 200 according to an embodiment of the present application is shown.

[0030] The integrated tool 200 can include a calling interface 202. The integrated tool 200 can be connected to the interfaces of a plurality of verification tools via the calling interface 202. For example, the calling interface 202 of the integrated tool 200 can be communicatively connected to the interfaces 2122, 2142 and 2162 of the verification tools 212, 214 and 216, respectively, for invoking the verification tools 212, 214 and 216. It can be understood that one calling interface 202 in the present application can include a plurality of sub-interfaces. In other words, the calling interface 202 can invoke a plurality of verification tools at a time.

[0031] The verification tools 212, 214 and 216 can be a plurality of verification tools such as software simulation tools, formal verification tools, hardware simulation tools, debugging tools, etc. The core unit of software simulation can be a computer host with CPU as the core, and the core unit of hardware simulation can be an FPGA chip or a special chip and its circuit system. Each verification tool has a corresponding number of software and hardware resources. The integrated tool 200 can be connected to the interfaces 2122, 2142 and 2162 of the verification tools 212, 214 and 216 through the calling interface 202 to collect the current number of relevant software and hardware resources of each verification tool to provide support information for subsequent verification processes and verification task scheduling.

[0032] The interfaces 2122, 2142 and 2162 can be an Application Programming Interface (API) or a command line calling interface for providing the capabilities of the verification tools 212, 214 and 216 to the tool that initiates a calling request via the interface.

[0033] In some embodiments, when the interfaces 2122, 2142, and 2162 are APIs, the integration tool 200 can invoke the APIs via the invocation interface 202, which in turn invokes the corresponding verification tools 212, 214, or 216.

[0034] In some embodiments, when the interfaces 2122, 2142, and 2162 are command line invocation interfaces, the integration tool 200 can use a script to input commands to the interfaces 2122, 2142, and 2162, which in turn invokes the corresponding verification tools 212, 214, or 216.

[0035] Figure 3 A diagram illustrating a verification tool 302 in the cloud according to embodiments of the present application is shown. As Figure 3 shown, the integration tool 200 is communicatively connected to the verification tool 302 in the cloud via the invocation interface 202, which enables the integration tool 200 to remotely invoke the capabilities of the verification tool 302.

[0036] In some embodiments, when a user uses the integration tool 200 to invoke a verification tool, the verification tool can not be installed on the electronic device 100. The verification tool that is not installed can be a tool that is not frequently used by the user. The integration tool 200 can also invoke a tool provided by an EDA tool vendor through a cloud service from the cloud. That is, the integration tool 200 can invoke a tool in the cloud via the invocation interface 202.

[0037] In some embodiments, to invoke multiple verification tools, the integration tool 200 can receive a verification target from a user, and invoke the multiple verification tools according to the verification target.

[0038] Figure 4 A diagram illustrating a flow 400 to achieve a verification target according to embodiments of the present application is shown.

[0039] As Figure 4 shown, the integration tool 200 can receive a verification target 402 from a user (not shown). The verification target 402 can be, for example, to detect whether a chip design can pass all test cases in dynamic verification with a line coverage of 90% or more, and pass static verification.

[0040] According to the verification target 402, the integration tool 200 can invoke a plurality of verification tools (e.g., the verification tools 212, 214, 216, or 302, etc.) via the invocation interface 202, respectively. In some embodiments, the integration tool 200 can analyze the verification target 402 to determine a plurality of verification tasks 404 (e.g., the verification tasks 4041-4043) associated with the verification target 402 and an execution order of the plurality of verification tasks 404 (as shown by the arrows between the verification tasks 4041-4043).

[0041] For example, the verification target 402 described above can be decomposed by the integration tool 200 into a dynamic verification by a software simulation tool (verification task 4041), a static verification by a formal verification tool (verification task 4042), and sending of failed assertions / test cases of the dynamic verification and the static verification to a debugging tool (verification task 4043). The initial execution order can be a sequential execution. It can be appreciated that a verification task can include all inputs (e.g., chip design source code, assertions, test benches (TBs), test cases, etc.) required to perform the task.

[0042] In addition to the plurality of verification tasks and the execution order, the integration tool 200 can further generate commands 406 for operating the corresponding debugging tools.

[0043] In some embodiments, the multi-tool verification flow can include the plurality of verification tasks 404, the execution order, and the commands 406 described above. Thus, the integration tool 200 can generate a multi-tool verification flow based on the verification target and the plurality of verification tools.

[0044] In some embodiments, the verification tools 212, 214, 216, or 302 can be shared as underlying computing resources, or even the verification tools 212, 214, 216, or 302 can be cloud computing resources. This means that the verification tools 212, 214, 216, or 302 can not be available at the moment when the verification target 402 is received.

[0045] Thus, the integration tool 200 can further determine a status of the plurality of verification tools 212, 214, 216, or 302. The status of a verification tool can include, for example, a running status, an occupancy status, etc. The running status can include running or not running. For a verification tool that is running, its occupancy status can further include a predicted available time, etc.

[0046] According to the status of the plurality of verification tools, the integration tool 200 can adjust the multi-tool verification flow. For example, according to the communication between the integration tool 200 and the plurality of verification tools, the integration tool 200 finds that the software simulation tool and the formal verification tool are both in idle state at present and in the future, the integration tool 200 can adjust the multi-tool verification flow to modify the verification tasks 4041 and 4042 from the initial sequential execution to parallel execution. For another example, the verification targets can have priorities. When a verification target with higher priority requests to invoke, for example, the debugging tool, the integration tool 200 can adjust the multi-tool verification flow to temporarily suspend the verification task 4043.

[0047] In some embodiments, the integration tool 200 can adjust the multi-tool verification flow according to the result of the currently executed verification task. For example, when the verification task 4041 is executed, the integration tool 200 can obtain the result of the verification task 4041. However, the result shows that the coverage is much lower than expected, at this time, the integration tool 200 can adjust the generation strategy of the test case, regenerate a new test case and re-execute a new verification task to achieve the required coverage.

[0048] It can be understood that in the above process, the user can directly issue user instructions / commands to intervene and change the execution of the multi-tool verification flow.

[0049] Therefore, the integration tool 200 can comprehensively determine when to invoke which verification tool according to the verification task, the user instruction, the available software and hardware resources, and the built-in automatic intelligent logic, to realize a dynamically optimized scheduling verification flow.

[0050] The integration tool 200 can also provide some preset libraries, graphical user interface (GUI) templates, etc., allowing the verification capabilities invoked from the verification tools 212, 214 and 216 to be constructed into customized verification functions and sequences by inputting scripts, command lines or configuration files. In some embodiments, different users have different flows for their own design project verification, such as specific verification targets using designated verification tools to complete, or different modules of the design project having a front-back sequence relationship of verification, or designated verification tools taking different follow-up steps according to the verification result output (such as opening the debugging tool for debugging for the verification case that fails verification), and these different user flows can be realized through the customization function of the integration tool 200.

[0051] It can be understood that the integration tool 200 and the verification tools 212, 214 and 216 can all run on the electronic device 100. In some embodiments, the verification tool 302 can run on the cloud.

[0052] After the verification tools 212, 214 and 216 are invoked, corresponding verification results can be generated. The verification results can be presented in the form of waveform data or other data. The integration tool 200 can also be configured to collect sub-verification data of the verification tools 212, 214 and 216 respectively, and integrate the sub-verification data into unified verification data. Because the verification target is usually measured by the functional point coverage and the code coverage as indicators, the integration tool 200 can determine the next verification invocation process according to the unified verification data results. In this process, the verification target (i.e., the verification function point or code covered by the verification) has been achieved by a certain verification tool (212, 214, 216), and there is no need to repeat the verification in other verification tools. Through such a process, the verification work required by a single verification tool can be effectively reduced.

[0053] Further, the integration tool 200 can also intelligently select the most suitable verification tool to complete the verification task currently submitted to the integration tool 200 according to the characteristics of the verification target and the available resources (such as the number of software licenses or the number of hardware resources) of the current verification tools, so as to maximize the comprehensive verification efficiency.

[0054] Embodiments of the present application also provide a method for verifying a logic system design.

[0055] Figure 5 A flowchart of a method 500 for verifying a logic system design according to embodiments of the present application is shown. The method 500 can be performed by the electronic device 100 of FIG. 1, and more specifically, by the integration tool (e.g., the integration tool 200 of FIG. 2) running on the electronic device 100. The method 500 can include the following steps. Figure 2

[0056] At step 502, the electronic device 100 can receive a verification target (e.g., the verification target 402 of FIG. 2) of a user. The verification target can be a detection target of a chip design. It can be understood that the chip design can be modified during the verification process to eventually achieve the verification target. Figure 4

[0057] At step 504, according to the verification target, the electronic device 100 can invoke a plurality of verification tools (e.g., the verification tools 212, 214, 216 or 302 of FIG. 2) via an invocation interface (e.g., the interface 202 of FIG. 2) of the integration tool 200. In some embodiments, a first verification tool in the plurality of verification tools is a tool (e.g., the verification tool 302 of FIG. 2) provided remotely in the cloud. Figure 2 3 Figure 2 3 Figure 3 ​​​​​​​

[0058] In some embodiments, the plurality of verification tools can respectively have an interface (e.g., the interface 2122, 2142, 2162 of the tool 2120, 2140, 2160 of FIG. 2 or 3) for being called by the integration tool. The interface can be an application programming interface or a command line invocation interface. Figure 2

[0059] In some embodiments, to call the plurality of verification tools respectively, the electronic device 100 can analyze the verification target to determine a plurality of verification tasks (e.g., the verification tasks 4041-4043 of FIG. 4) associated with the verification target and an execution order of the plurality of verification tasks (e.g., as indicated by the arrows of FIG. 4); and determine the plurality of verification tools to be called according to the plurality of verification tasks and the execution order. Figure 4 Figure 4

[0060] At step 506, the electronic device 100 can generate a multi-tool verification flow based on the verification target and the plurality of verification tools.

[0061] In some embodiments, to generate the multi-tool verification flow, the electronic device 100 can determine a status of the plurality of verification tools; and adjust the multi-tool verification flow according to a result of a currently executed verification task and the status of the plurality of verification tools.

[0062] As mentioned above, according to the status of the verification tools (e.g., a certain tool is temporarily occupied by a verification task with higher priority), the integration tool 200 can adaptively adjust the multi-tool verification flow. Accordingly, the verification target can have a certain priority. The status of the verification tools can include a running status, an occupation status, etc. The running status can include running or not running. For a verification tool that is running, its occupation status can further include a predicted available time (e.g., when it can be used, and a time period of availability, etc.), etc.

[0063] At step 508, the electronic device 100 can call the plurality of verification tools according to the multi-tool verification flow to achieve the verification target.

[0064] The verification tools can also return a result of an executed verification task to the integration tool. In some embodiments, the result of the executed verification task can not meet the requirement, and the integration tool 200 can automatically or invite a user to manually modify the multi-tool verification flow.

[0065] In some embodiments, the integration tool 200 can also respectively collect sub-verification data of the plurality of verification tools; and can integrate the sub-verification data of the plurality of verification tools into unified verification data.

[0066] ​​​The integration tool can also generate a graphical user interface based on the status of the plurality of verification tools and the results of the currently executed verification task.

[0067] By integrating and further editing the capabilities of the plurality of verification tools via the integration tool, the user can flexibly design verification functions as needed, improving the efficiency of the user in verifying the logic system design. In addition, in the case of a temporary lack of individual verification tools locally by the user, the integration tool provided by the embodiments of the present application can also call the individual verification tools from the cloud to meet the temporary needs of the user. It can be understood that in some embodiments, all verification tools can be provided from the cloud. In addition, the integration tool itself can also be provided in the cloud.

[0068] It should be noted that the method of the present application can be executed by a single device, such as a computer or a server, etc. The method of the present embodiment can also be applied in a distributed scenario, completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only execute one or more steps of the method of the present application, and the multiple devices will interact with each other to complete the method.

[0069] Embodiments of the present application also provide an electronic device. The electronic device includes a memory for storing a set of instructions, and at least one processor configured to execute the set of instructions to perform the method as described above.

[0070] The computer readable medium of the present embodiment includes permanent and non-permanent storage media for storing computer instructions that can be implemented when executed. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device.

[0071] The above describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different than the order in the embodiments and still achieve the desired result. In addition, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous or necessary.

[0072] Those of ordinary skill in the art will realize that the foregoing discussion of any of the embodiments has been presented for the purpose of illustration and description and is not intended to limit the scope of the application (including the claims) to the examples set forth in the description or illustration of specific embodiments. Further, the same or equivalent techniques can be employed in different embodiments without departing from the true scope of the application. Thus, many changes and modifications can be made to the embodiments described herein, with the terms used in the description meant to be interpreted as limiting only as desired. As such, the scope of the application is to be understood not limited to the specific examples described herein, but only by the claims that follow, along with their full scope of equivalents.

[0073] In addition, to simplify the description and discussion, and so as not to obscure the application, well-known power / ground connections to integrated circuit (IC) chips and other components can or can not be shown in the provided figures. Furthermore, devices can be shown in block diagram form in order to avoid obscuring the application, and this also is intended to include all such hardware implementations with respect to the functions described by the various blocks. In the description provided herein, numerous specific

[0074] While the application has been described in connection with specific embodiments thereof, it will be understood that many modifications, changes, and variations will be specific embodiments. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can use the embodiments discussed.

[0075] It is intended to cover all such changes, modifications and variations of this application, included within the scope of the appended claims and their equivalents. Accordingly, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the present application should be included in the scope of the present application.

Claims

1. A method for verifying a logical system design, comprising: receiving a verification target of a user; invoking a plurality of verification tools respectively via an invocation interface of an integration tool according to the verification target, the plurality of verification tools comprising a software simulation tool, a formal verification tool and a debugging tool; generating a multi-tool verification flow based on the verification target and the plurality of verification tools; and invoking the plurality of verification tools according to the multi-tool verification flow to achieve the verification target; wherein invoking the plurality of verification tools respectively via the invocation interface of the integration tool according to the verification target further comprises: analyzing the verification target to determine a plurality of verification tasks associated with the verification target and an execution order of the plurality of verification tasks, the plurality of verification tasks comprising a first verification task for dynamic verification by the software simulation tool, a second verification task for static verification by the formal verification tool, and a third verification task for sending a failure assertion or a test case of the dynamic verification and the static verification to the debugging tool; determining the plurality of verification tools to be invoked according to the plurality of verification tasks and the execution order; wherein generating the multi-tool verification flow based on the verification target and the plurality of verification tools comprises: determining a status of the plurality of verification tools; adjusting the multi-tool verification flow according to a result of a currently executed verification task and the status of the plurality of verification tools; wherein determining the status of the plurality of verification tools comprises determining that the software simulation tool and the formal verification tool are in an idle state for a predetermined time period; adjusting the multi-tool verification flow according to the result of the currently executed verification task and the status of the plurality of verification tools comprises changing an execution order of the first verification task and the second verification task to parallel execution. 2.The method of claim 1, further comprising: generating a graphical user interface according to the status of the plurality of verification tools and the result of the currently executed verification task. A first verification tool of the plurality of verification tools is a tool provided remotely in the cloud.

3. The method of claim 1, wherein, 4.The method of claim 1, wherein the plurality of verification tools respectively have an interface for being invoked by the integration tool. 5.The method of claim 1, further comprising: collecting sub-verification data of the plurality of verification tools respectively via the integration tool; and integrating the sub-verification data of the plurality of verification tools into unified verification data. The verification target has a specific priority. 7.An electronic device, comprising:

6. The method of claim 1, wherein, a memory configured to store a set of instructions; and at least one processor configured to execute the set of instructions to perform the method of any one of claims 1 to 6. 8.A non-transitory computer-readable storage medium storing a set of instructions of an electronic device, the set of instructions configured to cause the electronic device to perform the method of any one of claims 1 to 6. ​ ​ ​

Images