Demultiplexer and driving method thereof, display panel having the same

Abstract

The application provides a demultiplexer and a driving method thereof, and a display panel with the demultiplexer, which makes each output channel input a data signal to K data lines in time-sharing mode, wherein each output channel is connected with K-1 data lines through K-1 switch transistors and directly connected with another data line; one metal plate is arranged near the another data line of each output channel to form a coupling capacitor between each metal plate and the corresponding another data line, so that the potential of the data line is changed based on the coupling capacitor by controlling the potential change of the metal plate, thereby making the feedthrough effect of the corresponding another data line of each output channel close to the feedthrough effect of the other K-1 data lines, so that the display panel can realize better display uniformity on the basis of reducing the circuit size and power consumption.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a multiplexer and its driving method, and a display panel having the multiplexer. Background Technology

[0002] As display panel sizes and resolutions continue to increase, the cost increases due to the increased number of source driver ICs when each output channel of the source driver IC is connected to each data line of the display panel in a 1:1 ratio. Therefore, to reduce the number of source driver ICs, a demultiplexer (DEMUX) is placed between the source driver ICs and data lines in the non-display area of ​​the display panel. This demultiplexer distributes the data signals from one output channel of the source driver IC to multiple data lines in a time-division manner, thereby reducing the number of data driver ICs and thus lowering costs.

[0003] Referring to Figures 1(a) and 1(b), taking a traditional 1:K DEMUX circuit as an example, each output channel CH (also called the output source) of the source driver IC is decomposed into K data lines. A thin-film transistor (TFT) is set between the output channel CH and each data line as a switch, and the MUX control signal controls the on / off state of the TFT. For N output channels, K MUX control signals and KN TFTs are required, which occupies a certain area, making it difficult to achieve a narrow bezel and resulting in high power consumption. Figures 2(a) and 2(b) are the structure diagram and timing diagram of a traditional DEMUX circuit with 2 output channels, where each output channel is decomposed into 3 data lines.

[0004] In view of this, as shown in Figure 3(a), some patents have improved the traditional 1:K DEMUX circuit by directly connecting each output channel to the corresponding last data line, i.e., the Kth data line, omitting the TFT and the Kth MUX control signal between each output channel and the corresponding Kth data line. In the end, only (K-1)N TFTs and K-1 MUX control signals are used, thereby reducing the size of the demultiplexer and reducing its power consumption, which is more conducive to achieving narrow bezels and saving power in the display panel.

[0005] Specifically, referring to Figures 3(a) and 3(b), if each output channel sequentially inputs data signals to the first to the Kth data lines, then when the first MUX control signal is high, the first TFT of each output channel turns on, and each output channel inputs a data signal to the corresponding first data line; when the second MUX control signal is high, the second TFT of each output channel turns on, and each output channel inputs a data signal to the corresponding second data line, and so on. When the (K-1)th MUX control signal is high, the (K-1)th TFT of each output channel turns on, and each output channel inputs a data signal to the corresponding (K-1)th data line. Meanwhile, in the (K-1)th MUX control signal... When all MUX control signals are low, the TFTs between each output channel and the corresponding K-1 data lines are all turned off, causing each output channel to input the final display image to the corresponding K-th data line, thus completing the display of one frame. It should be noted that although each output channel also inputs data signals to the directly connected K-th data line when the K-1 MUX control signals are successively high, the K-th data line ultimately displays the data signals input by the output channels when the K-1 MUX control signals are all low. Therefore, when the K-1 MUX control signals are successively high, the data signals input by each output channel to the K-th data line will not affect the display result of each frame.

[0006] However, the 1:K DEMUX circuit shown in Figure 3(a) has the following problem: When the MUX control signal changes from low to high or from high to low, the TFT has gate-source parasitic capacitance Cgs and gate-drain parasitic capacitance Cgd. Under the influence of parasitic capacitance, the voltage of the data line will rise or fall to a certain extent, which is the feedthrough effect. Since each output channel is directly connected to the corresponding Kth data line, the Kth data line does not have a feedthrough effect. This will cause the brightness of the pixel unit controlled by the Kth data line to differ from the brightness of the pixel units controlled by the other K-1 data lines. Especially in the final displayed image, the brightness of the pixel unit controlled by the Kth data line is slightly brighter than the brightness of the pixel units controlled by the other K-1 data lines, which leads to the problem of uneven display on the display panel. Figures 4(a) and 4(b) are the structure diagram and timing diagram of the improved DEMUX circuit, taking two output channels as an example, decomposing each output channel to three data lines.

[0007] Therefore, there is an urgent need for a new type of demultiplexer that can reduce size and power consumption by reducing the number of MUX control signals and TFTs, while also ensuring good display uniformity of the display panel. Summary of the Invention

[0008] To address the aforementioned problems, embodiments of the present invention provide a multiplexer and its driving method, as well as a display panel having the multiplexer.

[0009] In a first aspect, embodiments of the present invention provide a multiplexer, comprising:

[0010] There are N output channels. Each output channel is connected to K-1 data lines through K-1 switching transistors and directly connected to another data line. The K-1 switching transistors corresponding to each output channel are connected to K-1 multiplexing control signal lines. N is a positive integer and K is a positive integer greater than 1.

[0011] N metal plates are interconnected, and each metal plate is stacked with the other data line corresponding to each output channel to form a coupling capacitor between each metal plate and the corresponding other data line.

[0012] In some embodiments, the source of the switching transistor is connected to the output channel, the drain of the switching transistor is connected to the data line, and the coupling capacitor has the same capacitance value as the gate-drain parasitic capacitance of the switching transistor.

[0013] In some embodiments, the source of the switching transistor is connected to the data line, the drain of the switching transistor is connected to the output channel, and the coupling capacitor has the same capacitance value as the gate-drain parasitic capacitance of the switching transistor.

[0014] In some embodiments, the multiplexer further includes a coupling capacitor control signal line, and all N metal plates are connected to the coupling capacitor control signal line.

[0015] Secondly, embodiments of the present invention also provide a driving method for a multiplexer, comprising the following steps:

[0016] S1. During the K-1 time periods in each scan cycle, K-1 multiplexed control signal lines are sequentially provided with high level so that each output channel provides data signal to the corresponding K-1 data lines in a time-division manner.

[0017] S2. In the Kth time period of each scan cycle, all K-1 multiplexing control signal lines are provided with a low level and the coupling capacitor control signal line is provided with a high level, so that each output channel provides a data signal to the corresponding other data line.

[0018] In some embodiments, step S1 specifically includes the following steps:

[0019] In the first time period of each scan cycle, the first multiplexing control signal line is made high so that each output channel provides a data signal to the corresponding first data line and the other data line;

[0020] In the second time period of each scan cycle, the second multiplexing control signal line is made high so that each output channel provides a data signal to the corresponding second data line and the other data line;

[0021] Similarly, during the (k-1)th time period of each scan cycle, the (k-1)th multiplexing control signal line is made high, so that each output channel provides a data signal to the corresponding (k-1)th data line and the other data line.

[0022] In some embodiments, step S2 specifically includes the following steps:

[0023] During the Kth time period of each scan cycle, all K-1 multiplexing control signal lines are provided with a low level, and the coupling capacitor control signal line is provided with a high level;

[0024] When the coupling capacitor control signal line changes from low level to high level, the coupling capacitor formed between each metal plate and the corresponding other data line causes the potential of the other data line to rise.

[0025] When the coupling capacitor control signal line changes from high level to low level, a coupling capacitor is formed between each metal plate and the corresponding other data line, causing the potential of the other data line to drop.

[0026] Thirdly, embodiments of the present invention also provide a display panel, including a source driver, N*K data lines connected in sequence, and a multiplexer as described above, wherein the source driver inputs data signals to the corresponding K data lines through each output channel of the multiplexer in a time-division manner.

[0027] In some embodiments, the display panel further includes gate lines and a pixel definition layer, wherein the metal electrode plate of the multiplexer and the data lines are disposed on different layers; the metal electrode plate is disposed on the same layer as at least one of the gate lines and the pixel definition layer.

[0028] In some embodiments, the display panel further includes a coupling capacitor signal control line, and the metal electrode plate and the coupling capacitor signal control line are disposed on the same layer; or, the metal electrode plate and the coupling capacitor signal control line are multiplexed.

[0029] The multi-channel demultiplexer and its driving method, and the display panel with the multi-channel demultiplexer provided in this invention embodiment, enable each output channel to input data signals to K data lines in a time-division manner. Each output channel is connected to K-1 data lines through K-1 switching transistors and directly connected to another data line. A metal plate is set near the other data line of each output channel to form a coupling capacitor between each metal plate and the corresponding other data line. By controlling the potential change of the metal plate, the potential of the data line changes accordingly based on the coupling capacitor. This makes the feedthrough effect of the other data line corresponding to each output channel similar to that of the other K-1 data lines. This ensures that the brightness of the pixel unit controlled by the other data line corresponding to each output channel is basically the same as the brightness of the pixel unit controlled by the other K-1 data lines. Thus, while reducing the size and power consumption of the DEMUX circuit, it can also achieve better display uniformity of the display panel. Attached Figure Description

[0030] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0031] Figure 1(a) is a schematic diagram of the structure of a conventional 1:K DEMUX circuit in the prior art;

[0032] Figure 1(b) is a timing diagram of the DEMUX circuit in Figure 1(a);

[0033] Figure 2(a) is a schematic diagram of the structure of a conventional 1:3 DEMUX circuit in the prior art;

[0034] Figure 2(b) is a timing diagram of the DEMUX circuit in Figure 2(a);

[0035] Figure 3(a) is a schematic diagram of the structure of the improved 1:K DEMUX circuit in the prior art;

[0036] Figure 3(b) is a timing diagram of the DEMUX circuit in Figure 3(a);

[0037] Figure 4(a) is a schematic diagram of the structure of the improved 1:K DEMUX circuit in the prior art;

[0038] Figure 4(b) is a timing diagram of the DEMUX circuit in Figure 4(a);

[0039] Figure 5(a) is a schematic diagram of the structure of the 1:K DEMUX circuit provided in the embodiment of the present invention;

[0040] Figure 5(b) is a timing diagram of the DEMUX circuit in Figure 5(a);

[0041] Figure 6(a) is a schematic diagram of the structure of a 1:3 DEMUX circuit provided in an embodiment of the present invention;

[0042] Figure 6(b) is a timing diagram of the DEMUX circuit in Figure 6(a);

[0043] Figure 7 This is a schematic diagram of the first type of film layer for forming coupling capacitors in the DEMUX circuit provided in an embodiment of the present invention;

[0044] Figure 8 This is a schematic diagram of the second type of film layer for forming coupling capacitors in the DEMUX circuit provided in an embodiment of the present invention;

[0045] Figure 9 A schematic diagram of the third film layer for forming coupling capacitors in the DEMUX circuit provided in an embodiment of the present invention;

[0046] Figure 10 This is a flowchart illustrating the driving method for a multi-path decomposer provided in an embodiment of the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0048] Referring to Figures 5(a) and 5(b), an embodiment of the present invention provides a multiplexer, comprising:

[0049] There are N output channels. Each output channel is connected to K-1 data lines through K-1 switching transistors and directly connected to another data line. The K-1 switching transistors corresponding to each output channel are connected to K-1 multiplexing control signal lines. N is a positive integer and K is a positive integer greater than 1.

[0050] N metal plates are interconnected, and each metal plate is stacked with the other data line corresponding to each output channel to form a coupling capacitor between each metal plate and the corresponding other data line.

[0051] It should be noted that in Figure 5(a), the other data line corresponding to each output channel is designated as the Kth data line. Specifically, the N output channels are CH1, CH2…CH(N); the K-1 multiplexing control signal lines are MUX1, MUX2…MUX(K-1); the other data line is D1k, D2k…DNk; the switching transistors connected to the first output channel CH1 are T11, T12…T1(k-1), and the first output channel CH1 is used to input data signals to data lines D11, D12…D1(k-1), D1k, and the corresponding other data line D1K; the second output channel CH… The switching transistors connected to the second output channel CH(N) are T21, T22...T2(k-1). The second output channel CH2 is used to input data signals to data lines D21, D22...D2(k-1), D2k and the corresponding other data line D2K. Similarly, the switching transistors connected to the Nth output channel CH(N) are TN1, TN2...TN(k-1). The Nth output channel CH(N) is used to input data signals to data lines DN1, DN2...DN(k-1) and the corresponding other data line DNk.

[0052] Specifically, the working principle of this multiplexer is as follows: each output channel inputs data signals to K data lines in a time-division manner. Each output channel is connected to K-1 data lines (e.g., data lines 1 to K-1) via K-1 switching transistors, and is also directly connected to another data line (e.g., data line K). A metal plate is placed near the other data line of each output channel, forming a coupling capacitor between each output channel and its nearby metal plate. The potential change of the coupling capacitor causes a corresponding change in the potential of the other data line. This reduces the feedthrough effect on the other data line corresponding to each output channel, thus reducing the difference in brightness between the pixel unit controlled by the other data line and the pixel unit controlled by the other K-1 data lines, thereby improving the display uniformity of the display panel.

[0053] Compared to the conventional DEMUX circuit shown in Figure 1(a), the DEMUX circuit provided in this embodiment of the invention directly connects each output channel to its corresponding data line without using a switching transistor. This reduces the size and power consumption of the DEMUX circuit. Furthermore, compared to the improved DEMUX circuit shown in Figure 3(a), the data line corresponding to each output channel forms a coupling capacitor with a nearby metal plate. This coupling capacitor compensates for the potential of the data line corresponding to each output channel, making the feedthrough effect on the data line similar to that on other data lines. This ensures that the brightness of the pixel unit controlled by the data line corresponding to each output channel is essentially the same as that controlled by other data lines, thereby improving the display uniformity of the display panel. Therefore, the DEMUX circuit provided in this embodiment of the invention reduces the size and power consumption of the DEMUX circuit while also achieving good display uniformity of the display panel.

[0054] The multiplexer also includes a coupling capacitor control signal line CUX. All N metal plates can be connected to the coupling capacitor control signal line CUX, and the potential of the N metal plates can be uniformly controlled through the coupling capacitor control signal line CUX.

[0055] It should be noted that when setting the metal electrode, the coupling capacitance formed between the metal electrode and the corresponding other data line can be made as similar as possible to the capacitance value of the gate-source capacitance Cgd or gate-drain capacitance Cgd of the switching transistor. This makes the feedthrough effect experienced by the other data line corresponding to each output channel comparable to that of other data lines, thereby making the brightness of the pixel unit controlled by the other data line corresponding to each output channel basically the same as that of the pixel unit controlled by other data lines.

[0056] Understandably, the area of ​​the metal plate and the spacing between the metal plate and the corresponding other data line are adjustable so that the capacitance value of the coupling capacitor is adjusted to make the capacitance value of the coupling capacitor equal to that of the gate-source capacitance Cgd or gate-drain capacitance Cgd of the switching transistor.

[0057] In some embodiments, the source of the switching transistor is connected to the output channel, the drain of the switching transistor is connected to the data line, and the coupling capacitor has the same capacitance value as the gate-drain parasitic capacitance of the switching transistor; or, in some embodiments, the source of the switching transistor is connected to the data line, the drain of the switching transistor is connected to the output channel, and the coupling capacitor has the same capacitance value as the gate-drain parasitic capacitance of the switching transistor.

[0058] Specifically, the coupling capacitor formed by the other data line corresponding to each output channel and the metal plate is used to couple the potential of the other data line. This coupling capacitor is equal to the parasitic capacitance between the switching transistor and the data line connected to the output channel and the other K-1 data lines. Therefore, when the source of the switching transistor is connected to the data line, the coupling capacitor is the same as the gate-source capacitance Cgs of the switching transistor; when the drain of the switching transistor is connected to the data line, the coupling capacitor is the same as the gate-drain capacitance Cgd of the switching transistor. This allows the feedthrough effect experienced by the other data line corresponding to each output channel to be basically the same as that of the other K-1 data lines, thereby making the brightness of the pixel unit controlled by the other data line basically the same as that of the other K-1 data lines.

[0059] Based on the above embodiments, this invention also provides a display panel, including a source driver, N*K data lines Data, and a multiplexer as described above, wherein the source driver inputs data signals to the corresponding K data lines Data through each output channel of the multiplexer in a time-division manner.

[0060] Furthermore, the display panel also includes a gate line (Gate) and a pixel definition layer (PXL), wherein the metal electrode C of the multiplexer and the data line (Data) are disposed on different layers; the metal electrode C is disposed on the same layer as at least one of the gate line (Gate) and the pixel definition layer.

[0061] Furthermore, the display panel also includes a coupling capacitor signal control line, and the metal electrode C and the coupling capacitor signal control line CUX are disposed on the same layer; or, the metal electrode C and the coupling capacitor signal control line are multiplexed (e.g., Figures 7-9 (in CUX / C).

[0062] Specifically, the metal plate C is arranged on the same layer as the coupling capacitor control signal line CUX and on a different layer from the data line Data. That is, the metal plate C can be part of the coupling capacitor control signal CUX. An insulating layer is provided between the metal plate C and the data line Data, so that a coupling capacitor is formed between the metal plate C and the data line Data.

[0063] In some embodiments, as shown in FIG5(a), the coupling capacitor control signal line CUX is arranged in parallel with K-1 multiplexed control signal lines, and the coupling capacitor control signal line CUX is connected to the metal plate C through a connecting line, wherein the connecting line, the metal plate C and the coupling capacitor control signal line CUX are on the same layer.

[0064] In some embodiments, the metal electrode C and the coupling capacitor control signal line CUX are disposed on the same layer as the gate line Gate, or the metal electrode C and the coupling capacitor control signal line CUX are disposed on the pixel definition layer.

[0065] Specifically, such as Figure 7 As shown, the metal plate C and the coupling capacitor control signal line CUX are disposed on the same layer as the gate line Gate on the first metal layer M1. The insulating layer between the metal plate C and the coupling capacitor control signal line CUX and the other data line Data corresponding to each output channel is the gate insulating layer GI, so that a coupling capacitor is formed between the metal plate C and the coupling capacitor control signal line CUX and the other data line Data corresponding to each output channel.

[0066] In addition, such as Figure 8 As shown, the metal plate C and the coupling capacitor control signal line CUX are disposed on the pixel definition layer PXL. The insulating layer between the metal plate C and the coupling capacitor control signal line CUX and the other data line Data corresponding to each output channel is a first transparent insulating layer PV1, a polarizing layer PFA, and a second transparent insulating layer PV2, so that a coupling capacitor is formed between the metal plate C and the coupling capacitor control signal line CUX and the other data line Data corresponding to each output channel.

[0067] In addition, such as Figure 9 As shown, a portion of the metal plate C and the coupling capacitor control signal line CUX are disposed on the same layer as the gate line Gate on the first metal layer M1, and another portion is disposed on the pixel definition layer PXL. Specifically, a dedicated space is reserved in the pixel definition layer PXL for a portion of the metal plate C and the coupling capacitor control signal line CUX, while the other portion is disposed on the first metal layer M1. These two portions of the coupling capacitor control signal line CUX are connected by vias. The insulating layer between the metal plate C and the coupling capacitor control signal line CUX and the other data line Data corresponding to each output channel consists of a gate insulating layer GI, a first transparent insulating layer PV1, a polarizing layer PFA, and a second transparent insulating layer PV2, thereby forming a coupling capacitor between the metal plate C and the coupling capacitor control signal line CUX and the other data line Data corresponding to each output channel.

[0068] It should be noted that, Figure 7 , Figure 8 and Figure 9 In the diagram, glass is the glass substrate, M2 is the second metal layer, Vcom is the common electrode layer, and ACT is the active semiconductor layer. Both the common electrode layer Vcom and the pixel definition layer PXL are made of ITO material.

[0069] Based on the above embodiments, and in conjunction with Figures 5(a), 5(b), and Figure 10 As shown, this embodiment of the invention also provides a driving method for a multiplexer, comprising the following steps:

[0070] S1. During the K-1 time periods in each scan cycle, the K-1 multiplexed control signal lines MUX1 to MUX(K-1) are sequentially provided with high level, so that each output channel provides data signal to the corresponding K-1 data lines in a time-division manner.

[0071] S2. In the Kth time period of each scan cycle, make all K-1 multiplexing control signal lines provide a low level and the coupling capacitor control signal line CUX provide a high level, so that each output channel provides a data signal to the corresponding other data line.

[0072] In some embodiments, step S1 specifically includes the following steps:

[0073] In the first time period of each scan cycle, the first multiplexing control signal line MUX1 is made high so that each output channel provides data signals to the corresponding first data line and the other data line.

[0074] In the second time period of each scan cycle, the second multiplexing control signal line MUX2 is made high so that each output channel provides data signals to the corresponding second data line and the other data line;

[0075] Similarly, during the (k-1)th time period of each scan cycle, the (k-1)th multiplexing control signal line MUX(K-1) is made high, so that each output channel provides data signals to the corresponding (k-1)th data line and the other data line.

[0076] In some embodiments, step S2 specifically includes the following steps:

[0077] In the Kth time period of each scan cycle, all K-1 multiplexing control signal lines are provided with a low level MUX1~MUX(K-1), and the coupling capacitor control signal line CUX is provided with a high level;

[0078] When the coupling capacitor control signal line CUX changes from low level to high level, the coupling capacitor formed between each metal plate and the corresponding other data line causes the potential of the other data line to rise.

[0079] When the coupling capacitor control signal line CUX changes from high level to low level, a coupling capacitor is formed between each metal plate and the corresponding other data line, causing the potential of the other data line to drop.

[0080] Specifically, each scan cycle includes K time periods. In the first time period, MUX1 provides a high level, and MUX2 to MUX(K-1) provide a low level. CH1 inputs a data signal to D11 through T11 and directly inputs a data signal to D1K. CH2 inputs a data signal to D21 through T21 and directly inputs a data signal to D2K... CH(N) inputs a data signal to DN1 through TN1 and directly inputs a data signal to DNK. In the second time period, MUX2 provides a high level, and MUX1, MUX3 to MUX(K-1) provide a low level. CH1 inputs a data signal to D12 through T12 and directly inputs a data signal to D1K. CH2 inputs a data signal to D22 through T22 and directly inputs a data signal to D2K... CH(N) inputs a data signal to DN2 through TN2 and directly inputs a data signal to DNK, and so on. During the K-1 time period, MUX(K-1) provides a high level, and MUX1 to MUX(K-2) provide a low level. CH1 inputs a data signal to D1(K-1) through T1(K-1) and directly inputs a data signal to D1K. CH2 inputs a data signal to D2(K-1) through T2(K-1) and directly inputs a data signal to D2K, and so on. CH(N) inputs a data signal to DN(K-1) through TN(K-1) and directly inputs a data signal to DNK. During the K-th time period, MUX1 to MUX(K-1) provide a low level, and CUX provides a high level. CH1 directly inputs a data signal to D1K, and CUX is coupled to the potential of D1K through C1K. CH2 directly inputs a data signal to D2K, and CUX is coupled to the potential of D2K through C2K, and so on. CH(N) directly inputs a data signal to DNK, and CUX is coupled to the potential of DNK through CNK.

[0081] That is, from the first time period to the (K-1)th time period of each scan cycle, MUX1 to MUX(K-1) provide high level sequentially. Each output channel inputs data signal to the corresponding first data line to the (K-1)th data line, and also inputs data signal to the corresponding other data line, i.e., the Kth data line. In the Kth time period, MUX1 to MUX(K-1) all provide low level, and the coupling capacitor control signal line CUX provides high level. Each output channel only inputs data signal to the corresponding other data line, i.e., the Kth data line, thus forming the final displayed image of each frame. In the Kth time period, when the coupling capacitor control signal is at the rising edge from low to high, the coupling capacitor formed by the other data line corresponding to each output channel and the metal plate causes the potential of the Kth data line to rise; when the coupling capacitor control signal is at the falling edge from high to low, the coupling capacitor formed by the other data line corresponding to each output channel and the metal plate causes the potential of the Kth data line to fall. As a result, the feedthrough effect experienced by the Kth data line is basically the same as that of the other K-1 data lines, and the brightness of the pixel unit controlled by the Kth data line is basically the same as that of the pixel units controlled by the other K-1 data lines, thereby improving the display uniformity of the display panel.

[0082] It should be noted that the other data line corresponding to each output channel can be any one of the K data lines that input data signals to each output channel in a time-division multiplexing manner. However, it should be noted that since the data signal received by the other data line needs to be received in the last time period so that the pixel unit controlled by the other data line can realize the data signal of the final image displayed, in the last time period, each output channel should only input data signals to this other data line, while the other K-1 data lines should not input data signals.

[0083] Based on the above embodiments, as shown in Figures 6(a) and 6(b), taking N=2 and K=3 as an example, the multiplexer, under the control of two multiplexing control signal lines MUX1 and MUX2 and one coupling capacitor control signal line CUX, decomposes the two output channels CH1 and CH2 into six data lines D1, D2, D3, D4, D5 and D6 through four switching transistors T1, T2, T3 and T4 and two capacitors C1 and C2. Among them, the first output channel CH1 inputs data signals to the data lines D1, D3 and D5 in a time-division manner, and the second output channel CH2 inputs data signals to the data lines D2, D4 and D6 in a time-division manner.

[0084] Specifically, in the first period of each line scan cycle, MUX1 provides a high level, MUX2 and CUX provide a low level, T1 and T2 are turned on, CH1 inputs a data signal to D1 through T1 and directly inputs a data signal to T5, and CH2 inputs a data signal to D2 through T2 and directly inputs a data signal to T6; in the second period of each line scan cycle, MUX2 provides a high level, MUX1 and CUX provide a low level, CH1 inputs a data signal to D3 through T3 and directly inputs a data signal to D5, and CH2 inputs a data signal to D4 through T4 and directly inputs a data signal to D6; in the third period of each line scan cycle, MUX1 and MUX2 provide... When CUX is at a low level and CUX is at a high level, CH1 directly inputs data signals to D5, and CH2 directly inputs data signals to D6. At this time, when CUX changes from low to high, the coupling effect of C1 causes the potential of D5 to rise, and the coupling effect of C2 causes the potential of D6 to rise. When CUX changes from high to low, the coupling effect of C1 causes the potential of D5 to fall, and the coupling effect of C2 causes the potential of D6 to fall. That is, the feedthrough effect experienced by D5 and D6 is basically the same as that experienced by D1, D2, D3, and D4. The brightness of the pixel units controlled by D5 and D6 is basically the same as that of the pixels controlled by D1, D2, D3, and D4, thereby improving the display uniformity of the display panel.

[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0086] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multiplexer, characterized in that, include: There are N output channels. Each output channel is connected to K-1 data lines through K-1 switching transistors and directly connected to another data line. The K-1 switching transistors corresponding to each output channel are connected to K-1 multiplexing control signal lines. N is a positive integer and K is a positive integer greater than 1. N metal plates are connected to each other, and each metal plate is stacked with the other data line corresponding to each output channel to form a coupling capacitor between each metal plate and the corresponding other data line. In this configuration, the source of the switching transistor is connected to the output channel, the drain of the switching transistor is connected to the data line, and the coupling capacitor has the same capacitance value as the gate-drain parasitic capacitance of the switching transistor; or, the source of the switching transistor is connected to the data line, the drain of the switching transistor is connected to the output channel, and the coupling capacitor has the same capacitance value as the gate-source parasitic capacitance of the switching transistor. The area of ​​the metal electrode plate and the spacing between the metal electrode plate and the corresponding other data line are adjustable so that the coupling capacitor has the same capacitance value as the gate-drain parasitic capacitance or the gate-source parasitic capacitance of the switching transistor. The multiplexer further includes a coupling capacitor control signal line, and all N metal plates are connected to the coupling capacitor control signal line; the metal plates and the coupling capacitor signal control line are arranged on the same layer, or the metal plates and the coupling capacitor signal control line are multiplexed.

2. A driving method for a multiplexer, characterized in that, For driving the multiplexer as described in claim 1; the driving method includes the following steps: S1. During the K-1 time periods in each scan cycle, K-1 multiplexed control signal lines are sequentially provided with high level so that each output channel provides data signal to the corresponding K-1 data lines in a time-division manner. S2. In the Kth time period of each scan cycle, make K-1 multiplexing control signal lines provide a low level and the coupling capacitor control signal line provide a high level, so that each output channel provides a data signal to the corresponding other data line. Step S2 includes the following steps: During the Kth time period of each scan cycle, all K-1 multiplexing control signal lines are provided with a low level, and the coupling capacitor control signal line is provided with a high level; When the coupling capacitor control signal line changes from low level to high level, the coupling capacitor formed between each metal plate and the corresponding other data line causes the potential of the other data line to rise. When the coupling capacitor control signal line changes from high level to low level, a coupling capacitor is formed between each metal plate and the corresponding other data line, causing the potential of the other data line to drop.

3. The driving method for a multiplexer as described in claim 2, characterized in that, Step S1 specifically includes the following steps: In the first time period of each scan cycle, the first multiplexing control signal line is made high so that each output channel provides a data signal to the corresponding first data line and the other data line; In the second time period of each scan cycle, the second multiplexing control signal line is made high so that each output channel provides a data signal to the corresponding second data line and the other data line; Similarly, during the (k-1)th time period of each scan cycle, the (k-1)th multiplexing control signal line is made high, so that each output channel provides a data signal to the corresponding (k-1)th data line and the other data line.

4. A display panel, characterized in that, It includes source drivers connected in sequence, N*K data lines, and a multiplexer as described in claim 1; wherein the source drivers input data signals to the corresponding K data lines through each output channel of the multiplexer in a time-division manner.

5. The display panel as described in claim 4, characterized in that, The display panel further includes gate lines and a pixel definition layer, wherein the metal electrode plate of the multiplexer and the data line are disposed on different layers; the metal electrode plate is disposed on the same layer as at least one of the gate lines and the pixel definition layer.

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