Driving method for a display panel and display device

Abstract

The driving method and display device of the display panel provided by the embodiments of the present disclosure can enable the display panel to realize the function of time-division display and touch by setting a scanning stage and a touch stage within one display frame. Moreover, since in the next scanning stage after the touch stage ends, a new register bank is controlled to scan the coupled gate lines, it is possible to avoid the problem of display horizontal stripes that occurs in the prior art due to the intermediate pause of the shift register scanning and then the resumption of scanning during line-by-line scanning. In addition, the embodiments of the present disclosure reserve scanning time for other integrated functions and insert them between the display scanning stages to avoid the leakage problem of the long-time display level.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a driving method for a display panel and a display device. Background Art

[0002] In displays such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, there are generally multiple pixel units. Each pixel unit may include multiple sub-pixels of different colors. By controlling the brightness corresponding to each sub-pixel, the desired displayed color is mixed to display a color image. Summary of the Invention

[0003] The driving method for a display panel provided by an embodiment of the present disclosure, the display panel includes: multiple gate lines, a gate driving circuit respectively coupled to the multiple gate lines, and multiple frame start signal lines coupled to the gate driving circuit; the gate driving circuit includes multiple shift registers, a driving output end of one of the shift registers is coupled to one of the gate lines, and the multiple shift registers are divided into M register groups, and different register groups are coupled to different frame start signal lines; M is an integer greater than 1;

[0004] The driving method includes:

[0005] Dividing a display frame into M scanning stages and N touch stages; in the m-th scanning stage of the M scanning stages, loading a frame start signal to the frame start signal line coupled to the m-th register group among the M register groups, loading different clock signals to the multiple clock signal lines, controlling the shift register units in the m-th register group to output gate scanning signals to the coupled gate lines, and loading a cut-off control signal to the frame start signal lines coupled to the remaining register groups;

[0006] Setting one of the N touch stages between two adjacent scanning stages of the M scanning stages, and in the touch stage, scanning the touch electrodes in the display panel, and loading a cut-off control signal to each of the frame start signal lines and loading the cut-off control signal to each of the clock signal lines; N is an integer greater than 0.

[0007] In some possible implementation manners, in the M scanning stages, one of the N touch stages is set between every two adjacent scanning stages.

[0008] In some possible embodiments, in two adjacent display frames, the two display frames include a first display frame and a second display frame, and a target touch stage is set between the M-th scanning stage of the first display frame and the first scanning stage of the second display frame;

[0009] The target touch stage is one of the N touch stages of the second display frame; or, the target touch stage is one of the N touch stages of the first display frame.

[0010] In some possible embodiments, the shift registers in each of the register groups are respectively coupled to gate lines spaced M - 1 rows apart;

[0011] In the m-th scanning stage, a frame start signal is loaded onto the frame start signal line coupled to the m-th register group, different clock signals are loaded onto the clock signal lines coupled to the m-th register group, and each shift register in the m-th register group is controlled to sequentially scan the gate lines coupled thereto at intervals of M - 1 rows.

[0012] In some possible embodiments, the periods of the clock signals corresponding to different register groups are the same and the timings are the same.

[0013] The display device provided by the embodiments of the present disclosure includes:

[0014] A display panel, including: a plurality of gate lines, a gate driving circuit respectively coupled to the plurality of gate lines, and a plurality of frame start signal lines coupled to the gate driving circuit; the gate driving circuit includes a plurality of shift registers, one shift register is coupled to one of the gate lines, the plurality of shift registers are divided into M register groups, and different register groups are coupled to different frame start signal lines; M is an integer greater than 1;

[0015] A timing controller configured to divide a display frame into M scanning stages and N touch stages; in the m-th scanning stage of the M scanning stages, a frame start signal is loaded onto the frame start signal line coupled to the m-th register group of the M register groups, different clock signals are loaded onto the plurality of clock signal lines, and the shift register units in the m-th register group are controlled to output gate scanning signals to the coupled gate lines, and a cut-off control signal is loaded onto the frame start signal lines coupled to the remaining register groups; and, in each touch stage of the N touch stages, a cut-off control signal is loaded onto each of the frame start signal lines, and the cut-off control signal is loaded onto each of the clock signal lines;

[0016] The touch driving circuit is configured to set one of the N touch stages between two adjacent scan stages of the M scan stages, and in the touch stage, scan the touch electrodes in the display panel; N is an integer greater than 0.

[0017] In some possible implementation manners, the shift registers in each of the register groups are respectively coupled to the gate lines spaced M - 1 rows apart;

[0018] The register group includes at least two cascaded groups, the shift registers in the same cascaded group are cascaded, and the shift registers in the same cascaded group are respectively coupled to the gate lines spaced multiple rows apart.

[0019] In some possible implementation manners, M = 2, the shift registers in the first register group are respectively coupled to the gate lines of odd rows, and the shift registers in the second register group are respectively coupled to the gate lines of even rows;

[0020] The first register group includes a first cascaded group and a second cascaded group, and the shift registers in the first cascaded group are respectively coupled to the gate lines spaced 3 rows apart, and the shift registers in the second cascaded group are respectively coupled to the gate lines spaced 3 rows apart;

[0021] The second register group includes a third cascaded group and a fourth cascaded group, and the shift registers in the third cascaded group are respectively coupled to the gate lines spaced 3 rows apart, and the shift registers in the fourth cascaded group are respectively coupled to the gate lines spaced 3 rows apart.

[0022] In some possible implementation manners, the first register group is disposed at the first end of the multiple gate lines, and the second register group is disposed at the second end of the multiple gate lines;

[0023] Alternatively, each of the shift registers includes a left shift register disposed at the left side of the first end of the same gate line and a right shift register disposed at the second end, and the left shift register and the right shift register coupled to the same gate line output the gate scan signal simultaneously;

[0024] Alternatively, the first cascaded group and the third cascaded group are disposed at the first end of the multiple gate lines, and the second cascaded group and the fourth cascaded group are disposed at the second end of the multiple gate lines;

[0025] Alternatively, the first register group and the second register group are both located at the same end of the multiple gate lines.

[0026] In some possible implementation manners, the display panel further includes: multiple clock signal lines, and different register groups are coupled to the same clock signal line.

[0027] In some possible embodiments, two adjacent gate lines form a gate line group, and the shift registers corresponding to the same gate line group are coupled to the same clock signal line.

[0028] In some possible embodiments, the shift register includes: an output transistor and a clock selection circuit;

[0029] The gate of the output transistor is coupled to a first node, the second pole of the output transistor is coupled to the driving output end, and the first pole of the output transistor is coupled to the clock selection circuit;

[0030] The clock selection circuit is configured to conduct, in response to a signal at the selection signal terminal, the first pole of the output transistor to a clock signal terminal coupled to the corresponding clock signal line.

[0031] In some possible embodiments, the display panel further includes a plurality of selection signal lines;

[0032] The selection signal terminals of the shift registers in the same register group are coupled to the same selection signal line, and different register groups are coupled to different selection signal lines.

[0033] In some possible embodiments, the shift register further includes: an input circuit, a reset circuit, at least one control circuit, and a pull-down circuit corresponding to the control circuit one by one;

[0034] The input circuit is configured to provide, in response to a signal at the input signal terminal, the signal at the first scan selection signal terminal to the first node;

[0035] The reset circuit is configured to provide, in response to a signal at the reset signal terminal, the signal at the second scan selection signal terminal to the first node;

[0036] The control circuit is configured to control the levels of the signals at the first node and the corresponding second node to be opposite;

[0037] The pull-down circuit is configured to provide, in response to the signal at the corresponding second node, the signal at the reference signal terminal to the driving output end.

[0038] In some possible embodiments, there are two control circuits, the first control circuit of the two control circuits is coupled to a first control signal terminal, and the second control circuit is coupled to a second control signal terminal;

[0039] The plurality of selection signal lines include a first selection signal line and a second selection signal line; wherein, the first control signal terminal in the first register group is coupled to the first selection signal line, and the second control signal terminal in the second register group is coupled to the second selection signal line. Description of the Drawings

[0040] Figure 1 Some structural schematic diagrams of the display device in the embodiments of the present disclosure;

[0041] Figure 2 Some structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0042] Figure 3 Some structural schematic diagrams of the shift register in the embodiments of the present disclosure;

[0043] Figure 4 Some other structural schematic diagrams of the shift register in the embodiments of the present disclosure;

[0044] Figure 5 Some signal timing diagrams in the embodiments of the present disclosure;

[0045] Figure 6a Some structural schematic diagrams of the gate driving circuit in the embodiments of the present disclosure;

[0046] Figure 6b Some other structural schematic diagrams of the gate driving circuit in the embodiments of the present disclosure;

[0047] Figure 6c Some other structural schematic diagrams of the gate driving circuit in the embodiments of the present disclosure;

[0048] Figure 7a Some other structural schematic diagrams of the gate driving circuit in the embodiments of the present disclosure;

[0049] Figure 7b Some other structural schematic diagrams of the gate driving circuit in the embodiments of the present disclosure;

[0050] Figure 7c Some other structural schematic diagrams of the gate driving circuit in the embodiments of the present disclosure;

[0051] Figure 7d Some other structural schematic diagrams of the gate driving circuit in the embodiments of the present disclosure;

[0052] Figure 8a Some other structural schematic diagrams of the gate driving circuit in the embodiments of the present disclosure;

[0053] Figure 8b Some other structural schematic diagrams of the gate driving circuit in the embodiments of the present disclosure;

[0054] Figure 9 Some other signal timing diagrams in the embodiments of the present disclosure;

[0055] Figure 10 Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0056] Figure 11a Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0057] Figure 11b Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0058] Figure 12 Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0059] Figure 13 Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0060] Figure 14a Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0061] Figure 14b Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0062] Figure 15 Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0063] Figure 16 Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0064] Figure 17 Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0065] Figure 18 Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure. Detailed implementation manners

[0066] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. And without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are merely used to distinguish different components. Words such as "including" or "comprising" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0068] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of this disclosure. Also, the same or similar reference numerals throughout indicate the same or similar elements or elements having the same or similar functions.

[0069] See Figure 1 and Figure 2 , the display device may include: a display panel 100, a timing controller 200, and a touch driving circuit 300. Among them, the display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (for example, GA1, GA2, GA3, GA4), a plurality of data lines DA (for example, DA1, DA2, DA3), a gate driving circuit 110, and a source driving circuit 120. The gate driving circuit 110 is respectively coupled to the gate lines GA1, GA2, GA3, GA4, and the source driving circuit 120 is respectively coupled to the data lines DA1, DA2, DA3. Among them, the timing controller 200 may input a clock signal to the gate driving circuit 110 through a level shift circuit, so that the gate driving circuit 110 outputs a gate scanning signal to the coupled gate lines GA1, GA2, GA3, GA4, thereby scanning the gate lines GA1, GA2, GA3, GA4. The timing controller 200 inputs display data to the source driving circuit 120, so that the source driving circuit 120 inputs a data voltage to the data lines according to the received display data, thereby charging the sub-pixels SPX, and enabling the sub-pixels SPX to input the corresponding data voltage, to implement the screen display function of this display frame. Exemplarily, the source driving circuit 120 may be set to 2, and one of the source driving circuits 120 is connected to half of the number of data lines, and the other source driving circuit 120 is connected to the other half of the number of data lines. Of course, the source driving circuit 120 may also be set to 3, 4, or more, and it can be designed and determined according to the actual application requirements, and is not limited herein.

[0070] Exemplarily, each pixel unit includes a plurality of sub-pixels SPX. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing can be performed through red, green, and blue to achieve color display. Alternatively, a pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed through red, green, blue, and white to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0071] In some embodiments, referring to Figure 2 as shown, each sub-pixel SPX includes a transistor 01 and a pixel electrode 02. Among them, one row of sub-pixels SPX corresponds to one gate line, and one column of sub-pixels SPX corresponds to one data line. The gate of the transistor 01 is electrically connected to the corresponding gate line, the source of the transistor 01 is electrically connected to the corresponding data line, and the drain of the transistor 01 is electrically connected to the pixel electrode 02.

[0072] In some embodiments, the pixel array structure of the present disclosure may also be a double-gate structure, that is, two gate lines are provided between adjacent two rows of pixels. This arrangement can reduce the number of data lines by half, that is, some of the data lines are included between adjacent two columns of pixels, and some of the adjacent two columns of pixels do not include data lines. The specific pixel arrangement structure and the arrangement of data lines and scan lines are not limited.

[0073] It should be noted that the display panel in the embodiments of the present disclosure may be a liquid crystal display panel. Exemplarily, a liquid crystal display panel generally includes an upper substrate and a lower substrate that are opposed to each other, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate. When displaying a picture, since there is a voltage difference between the data voltage applied to the pixel electrode of each sub-pixel and the common electrode voltage applied to the common electrode, this voltage difference can form an electric field, so that the liquid crystal molecules are deflected under the action of this electric field. Since different intensities of the electric field cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixels is different, so that the sub-pixels can achieve different gray-scale brightnesses, and thus the picture display is realized.

[0074] In order to implement different application scenarios, the display panel may be provided with multiple different refresh frequencies. For example, in some application scenarios, in order to save power consumption, it is necessary for the display panel to display at a reduced frequency. For example, from 60HZ to 30HZ. In other scenarios, for example, when performing high-frequency games, it is necessary to increase the frequency of the display panel. For example, from 60HZ to 90HZ or 120HZ, so as to make the picture smoother. Therefore, in order to be applicable to different scenarios, the display panel can change the display frequency, that is, dynamic frame rate display.

[0075] In the embodiments of the present disclosure, a plurality of touch electrodes are further provided in the display panel (the specific values of the touch electrodes can be determined according to the requirements of actual applications). Exemplarily, the touch electrodes can be self-capacitance touch electrodes, so that the touch function can be implemented by using the self-capacitance technology. The touch electrodes can also be mutual-capacitance touch electrodes, so that the touch function can be implemented by using the mutual-capacitance technology. The touch electrodes can also be pressure-sensitive capacitance touch electrodes, so that the touch function can be implemented by using the pressure-sensitive capacitance technology.

[0076] In the embodiments of the present disclosure, the touch electrodes can be embedded between the upper substrate and the lower substrate of the cell of the display panel. Exemplarily, the common electrode can be reused as the touch electrode. And, the touch driving circuit 300 is electrically connected to each touch electrode respectively to scan the touch electrodes in the display panel, so as to implement the touch function.

[0077] In some embodiments of the present disclosure, the gate driving circuit can include a plurality of shift registers, and the driving output terminal GO of one shift register is coupled to one gate line. Exemplarily, as Figure 3 shown, the shift register can include: an input circuit 1, a reset circuit 2, at least one control circuit, a pull-down circuit corresponding to the control circuit one by one, an output transistor M0, and a clock selection circuit 5. Among them, the input circuit 1 is configured to provide the signal of the first scan selection signal terminal VDS to the first node N1 in response to the signal of the input signal terminal INP. The reset circuit 2 is configured to provide the signal of the second scan selection signal terminal VSD to the first node N1 in response to the signal of the reset signal terminal. The control circuit is configured to control the levels of the signals of the first node N1 and the corresponding second node N2 to be opposite. The pull-down circuit is configured to provide the signal of the reference signal terminal VREF to the driving output terminal GO in response to the signal of the corresponding second node. The gate of the output transistor M0 is coupled to the first node N1, the second pole of the output transistor M0 is coupled to the driving output terminal GO, and the first pole of the output transistor M0 is coupled to the clock selection circuit 5. The clock selection circuit 5 is configured to conduct the first pole of the output transistor M0 and the clock signal terminal CK coupled to the corresponding clock signal line in response to the signal of the selection signal terminal CKX.

[0078] In some embodiments of the present disclosure, as Figure 3As shown, the shift register may include: a control circuit and a pull-down circuit. The input circuit 1 includes a first transistor M1. Among them, the control electrode of the first transistor M1 is coupled to the input signal terminal INP, the first electrode of the first transistor M1 is coupled to the first scan selection signal terminal VDS, and the second electrode of the first transistor M1 is coupled to the first node N1. The reset circuit 2 includes a second transistor M2. Among them, the control electrode of the second transistor M2 is coupled to the reset signal terminal, the first electrode of the second transistor M2 is coupled to the second scan selection signal terminal VSD, and the second electrode of the second transistor M2 is coupled to the first node N1. The control circuit 3 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The control electrode and the first electrode of the third transistor M3 are both coupled to the control signal terminal VN, the second electrode of the third transistor M3 is coupled to the control electrode of the fifth transistor M5, the first electrode of the fifth transistor M5 is coupled to the control signal terminal VN, and the second electrode of the fifth transistor M5 is coupled to the second node N2. The control electrode of the fourth transistor M4 is coupled to the first node N1, the first electrode of the fourth transistor M4 is coupled to the reference signal terminal VREF, and the second electrode of the fourth transistor M4 is coupled to the control electrode of the fifth transistor M5. The control electrode of the sixth transistor M6 is coupled to the first node N1, the first electrode of the sixth transistor M6 is coupled to the reference signal terminal VREF, and the second electrode of the sixth transistor M6 is coupled to the second node N2. The control electrode of the seventh transistor M7 is coupled to the second node, the first electrode of the seventh transistor M7 is coupled to the reference signal terminal VREF, and the second electrode of the seventh transistor M7 is coupled to the second node N2. The seventh transistor M7 pulls down the first node under the control of the second node. The pull-down circuit includes an eighth transistor M8. The control electrode of the eighth transistor M8 is coupled to the second node N2, the first electrode of the eighth transistor M8 is coupled to the reference signal terminal VREF, and the second electrode of the eighth transistor M8 is coupled to the drive output. The eighth transistor M8 pulls down the drive output terminal GO under the control of the second node. The clock selection circuit 5 includes a ninth transistor M9. The control electrode of the ninth transistor M9 is coupled to the selection signal terminal CKX, the first electrode of the eighth transistor M8 is coupled to the first electrode of the output transistor M0, and the second electrode of the ninth transistor M9 is coupled to the corresponding clock signal terminal CK.

[0079] In some embodiments of the present disclosure, as Figure 3As shown, the shift register may further include: a first capacitor C1, a tenth transistor M10, and an eleventh transistor M11. A first electrode plate of the first capacitor C1 is coupled to the first node N1, and a second electrode plate of the first capacitor C1 is coupled to the driving output terminal GO. A control electrode of the tenth transistor M10 is coupled to the frame reset signal terminal STVO, a first pole of the tenth transistor M10 is coupled to the reference signal terminal VREF, and a second pole of the tenth transistor M10 is coupled to the first node N1. A control electrode of the eleventh transistor M11 is coupled to the frame reset signal terminal STVO, a first pole of the eleventh transistor M11 is coupled to the reference signal terminal VREF, and a second pole of the eleventh transistor M11 is coupled to the driving output terminal GO. That is, under the control of STVO, the tenth transistor M10 and the eleventh transistor M11 are respectively used to reduce noise for the first node and the driving output terminal.

[0080] In some embodiments of the present disclosure, as Figure 4 shown, the shift register may include: two control circuits and two pull-down circuits. Among them, the two control circuits include a first control circuit 3-1 and a second control circuit 3-2. The two pull-down circuits include a first pull-down circuit 4-1 and a second pull-down circuit 4-2. The first control circuit 3-1 is coupled to the first node N1, the first second node N2-1, and the first control signal terminal VN-1, and includes a first third transistor M3-1, a first fourth transistor M4-1, a first fifth transistor M5-1, a first sixth transistor M6-1, and a first seventh transistor M7-1. The second control circuit 3-2 is coupled to the first node N1, the second second node N2-2, and the second control signal terminal VN-2, and includes a second third transistor M3-2, a second fourth transistor M4-2, a second fifth transistor M5-2, a second sixth transistor M6-2, and a second seventh transistor M7-2.

[0081] The first pull-down circuit 4-1 is coupled to the first second node N2-1 and includes a first eighth transistor M8-1.

[0082] The second pull-down circuit 4-2 is coupled to the second second node N2-2 and includes a second eighth transistor M8-2. The specific connection manner may refer to the above connection manner and will not be elaborated here.

[0083] It should be noted that the control electrode may be its gate, the first pole may be its source, and the second pole may be its drain. Or, the control electrode may be its gate, the first pole may be its drain, and the second pole may be its source. And, the N-type transistor is turned on under the control of a high-level signal and turned off under the control of a low-level signal. The P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal.

[0084] In some embodiments of the present disclosure, taking the Figure 4 shift register shown as an example, Figure 4 the signal timing diagram corresponding to the operation of the shift register shown in the nth frame Fn is as Figure 5 shown. Wherein, inp represents the signal of the input signal terminal INP, ck represents the signal of the clock signal terminal CK, ga represents the gate scan signal of the driving output terminal GO, re represents the signal of the reset signal terminal, and stvo represents the signal of the frame reset signal terminal STVO. Exemplarily, the driving output terminal GO is coupled to the corresponding gate line. The effective level of the gate scan signal ga can control the transistor in the pixel coupled to the corresponding gate line to turn on, and the ineffective level can control the transistor in the pixel coupled to the corresponding gate line to turn off. Exemplarily, the transistor in the shift register is an N-type transistor, the effective level of the gate scan signal ga can be a high level, the ineffective level is a low level, and the signal vref is a fixed voltage of a low level. Alternatively, the transistor in the shift register is a P-type transistor, the effective level of the gate scan signal ga can also be a low level, the ineffective level is a high level, and the signal vref is a fixed voltage of a high level. This is not limited herein.

[0085] It should be noted that in the above shift register provided by the embodiments of the present disclosure, the first transistor M1 and the second transistor M2 are symmetrically designed and can achieve function interchange. Therefore, the above shift register provided by the embodiments of the present disclosure can achieve bidirectional scanning. During forward scanning, the first transistor M1 is used as the input transistor, and the second transistor M2 is used as the reset transistor. And, taking the effective level of the gate scan signal ga as a high level and the ineffective level as a low level as an example, the signal of the first scan control terminal VDS is a fixed voltage of a high level, and the signal of the second scan control terminal VSD is a fixed voltage of a low level. During reverse scanning, the second transistor M2 is used as the input transistor, and the first transistor M1 is used as the reset transistor. And, taking the effective level of the gate scan signal ga as a high level and the ineffective level as a low level as an example, the signal of the first scan control terminal VDS is a fixed voltage of a low level, and the signal of the second scan control terminal VSD is a fixed voltage of a low level.

[0086] In some embodiments of the present disclosure, the display panel may further include a plurality of clock signal lines and a plurality of frame start signal lines, and the plurality of clock signal lines and the plurality of frame start signal lines are respectively coupled to the gate driving circuit. In this way, the corresponding clock signal can be input to the gate driving circuit through the clock signal line, and the clock signal is input to the clock signal terminal of the shift register, so that the shift register outputs a gate scan signal to the coupled gate line. Exemplarily, as Figure 6a shown, the display panel may include 4 clock signal lines CKS1 to CKS4, and the 4 clock signal lines CKS1 to CKS4 are coupled to the gate driving circuit 110. It should be noted thatFigure 6a Only taking 4 clock signal lines as an example for illustration, in practical applications, the specific number of clock signal lines can be determined according to the requirements of practical applications, which is not limited herein. For example, it can also be other numbers of clock signal lines that are integer multiples of 2, such as 2, 6, 8, 10, 12, etc.

[0087] In some embodiments of the present disclosure, the frame reset signal terminals STVO of each stage of the shift register are all coupled to the same frame reset signal line, so as to uniformly reset each shift register. Optionally, the first node and the driving output terminal GO are reset.

[0088] In some embodiments of the present disclosure, a plurality of shift registers are divided into M register groups, and different register groups are coupled to different frame start signal lines; M is an integer greater than 1. Optionally, the shift registers in each register group are respectively coupled to the gate lines separated by M - 1 rows. The register group includes at least two cascaded groups, and the shift registers in the same cascaded group are cascaded, and each shift register in the same cascaded group is respectively coupled to the gate lines separated by multiple rows. Exemplarily, M can be 2, 3, 4, 5, 6 or more, which is not limited herein. Hereinafter, M = 2 is taken as an example for illustration.

[0089] Exemplarily, M = 2, such as Figures 7a to 8bAs shown, multiple shift registers are divided into two register groups: the first register group ZGOA1 and the second register group ZGOA2. Among them, the first register group ZGOA1 includes shift registers SR1, SR3, SR5, SR7, and the second register group ZGOA2 includes shift registers SR2, SR4, SR6, SR8. Moreover, each shift register in the first register group ZGOA1 is respectively coupled to the gate lines of odd rows (i.e., GA1, GA3, GA5, GA7), and each shift register in the second register group ZGOA2 is respectively coupled to the gate lines of even rows (i.e., GA2, GA4, GA6, GA8). Also, the first register group ZGOA1 is coupled to the frame start signal line STV1, and the input signal terminal INP of the shift registers included in the first register group ZGOA1 is coupled to the frame start signal line STV1. Optionally, the input signal terminal INP of the first shift register included in the first register group ZGOA1 is coupled to the frame start signal line STV1. Here, the coupling can refer to direct electrical connection or indirect electrical connection (i.e., other circuit components are also provided therebetween), which is not limited herein. The second register group ZGOA2 is coupled to the frame start signal line STV2, and the input signal terminal INP of the shift registers included in the second register group ZGOA2 is coupled to the frame start signal line STV2. Optionally, the input signal terminal INP of the first shift register included in the second register group ZGOA2 is coupled to the frame start signal line STV1. Also, the drive output terminal GO of the shift register SR1 is coupled to the gate line GA1, the drive output terminal GO of the shift register SR2 is coupled to the gate line GA2, the drive output terminal GO of the shift register SR3 is coupled to the gate line GA3,..., the drive output terminal GO of the shift register SR7 is coupled to the gate line GA7, and the drive output terminal GO of the shift register SR8 is coupled to the gate line GA8.

[0090] In some embodiments of the present disclosure, different register groups are coupled to the same clock signal line. Such a setting can reduce the number of clock signal lines. For example, in the prior art, 8 clock signal lines need to be set, while the present invention can set 4 clock signal lines to achieve the same practical effect, and thus the border can be reduced. For example, the first register group ZGOA1 is coupled to the first clock signal line CKS1 to the fourth clock signal line CKS4, and the second register group ZGOA2 is also coupled to the first clock signal line CKS1 to the fourth clock signal line CKS4. Refer to Figure 6b , the shift registers SR1 and SR2 are connected to the same clock signal line CKS1. Exemplarily, as Figures 7a to 8bAs shown, the clock signal terminal CK of the 8k-7th stage shift register SR8k-7 is coupled to the first clock signal line CKS1, the clock signal terminal CK of the 8k-5th stage shift register SR8k-5 is coupled to the second clock signal line CKS2, the clock signal terminal CK of the 8k-3rd stage shift register SR8k-3 is coupled to the third clock signal line CKS3, the clock signal terminal CK of the 8k-1st stage shift register SR8k-1 is coupled to the fourth clock signal line CKS4, the clock signal terminal CK of the 8k-6th stage shift register SR8k-6 is coupled to the first clock signal line CKS1, the clock signal terminal CK of the 8k-4th stage shift register SR8k-4 is coupled to the second clock signal line CKS2, the clock signal terminal CK of the 8k-2nd stage shift register SR8k-2 is coupled to the third clock signal line CKS3, and the clock signal terminal CK of the 8kth stage shift register SR8k is coupled to the fourth clock signal line CKS4. K is an integer greater than 0.

[0091] Exemplarily, as Figures 6a to 8b shown, taking two adjacent gate lines as a gate line group, the shift registers corresponding to the same gate line group are coupled to the same clock signal line. For example, gate lines GA1 and GA2 form a gate line group, and the clock signal terminals CK of the first-stage shift register SR1 and the second-stage shift register SR2 are both coupled to the first clock signal line CKS1. Gate lines GA3 and GA4 form a gate line group, and the clock signal terminals CK of the third-stage shift register SR3 and the fourth-stage shift register SR4 are both coupled to the second clock signal line CKS2. Gate lines GA5 and GA6 form a gate line group, and the clock signal terminals CK of the fifth-stage shift register SR5 and the sixth-stage shift register SR6 are both coupled to the second clock signal line CKS2. The rest can be deduced by analogy and will not be elaborated here.

[0092] Exemplarily, as Figure 6c 、 Figures 7a to 8bAs shown, the first register group ZGOA1 includes a first cascade group ZJL1 and a second cascade group ZJL2. Among them, the shift registers in the first cascade group ZJL1 are respectively coupled to the gate lines with an interval of 3 rows, and the shift registers in the second cascade group ZJL2 are respectively coupled to the gate lines with an interval of 3 rows. Among them, both the first cascade group ZJL1 and the second cascade group ZJL2 are coupled to the frame start signal line STV1. The first cascade group ZJL1 includes shift registers SR1 and SR5, and the input signal terminal INP of the shift register SR1 is coupled to the frame start signal line STV1, and the input signal terminal INP of the shift register SR5 is coupled to the driving output terminal GO of the shift register SR1. And, the driving output terminal GO of the shift register SR5 is coupled to the reset signal terminal RE of the shift register SR1. The second cascade group ZJL2 includes shift registers SR3 and SR7, and the input signal terminal INP of the shift register SR3 is coupled to the frame start signal line STV1, and the input signal terminal INP of the shift register SR7 is coupled to the driving output terminal GO of the shift register SR3. And, the driving output terminal GO of the shift register SR7 is coupled to the reset signal terminal RE of the shift register SR3.

[0093] Exemplarily, as Figures 7a to 8b As shown, the second register group ZGOA2 includes a third cascade group ZJL3 and a fourth cascade group ZJL4, and the shift registers in the third cascade group ZJL3 are respectively coupled to the gate lines with an interval of 3 rows, and the shift registers in the fourth cascade group ZJL4 are respectively coupled to the gate lines with an interval of 3 rows. Among them, both the third cascade group ZJL3 and the fourth cascade group ZJL4 are coupled to the frame start signal line STV2. The third cascade group ZJL3 includes shift registers SR2 and SR6, and the input signal terminal INP of the shift register SR2 is coupled to the frame start signal line STV2, and the input signal terminal INP of the shift register SR6 is coupled to the driving output terminal GO of the shift register SR2. And, the driving output terminal GO of the shift register SR6 is coupled to the reset signal terminal RE of the shift register SR2. The fourth cascade group ZJL4 includes shift registers SR4 and SR8, and the input signal terminal INP of the shift register SR4 is coupled to the frame start signal line STV2, and the input signal terminal INP of the shift register SR8 is coupled to the driving output terminal GO of the shift register SR4. And, the driving output terminal GO of the shift register SR8 is coupled to the reset signal terminal RE of the shift register SR4.

[0094] In some embodiments of the present disclosure, as Figure 7aAs shown, the first register group ZGOA1 can be set at the first end of multiple gate lines, and the second register group ZGOA2 can be set at the second end of multiple gate lines. Exemplarily, the first register group ZGOA1 is set on the left side of multiple gate lines, the second register group ZGOA2 is set on the right side of multiple gate lines, and the first register group ZGOA1 and the second register group ZGOA2 drive different gate lines respectively.

[0095] In some embodiments of the present disclosure, as Figure 7b shown, the first register group ZGOA1 and the second register group ZGOA2 can also be located at the same end of multiple gate lines. Exemplarily, the first register group ZGOA1 and the second register group ZGOA2 can both be located on the left side of multiple gate lines.

[0096] In some embodiments of the present disclosure, as Figure 7c shown, each shift register can also include a left shift register set at the left side of the first end of the same gate line and a right shift register set at the second end, and the left shift register and the right shift register coupled to the same gate line output gate scan signals simultaneously. Exemplarily, two first-stage shift registers SR1 are provided, one is the left shift register SR1, and the other is the right shift register SR1. And the left shift register SR1 and the right shift register SR1 input gate scan signals to the gate line GA1 simultaneously. Two second-stage shift registers SR2 are also provided, one is the left shift register SR2, and the other is the right shift register SR2. And the left shift register SR2 and the right shift register SR2 input gate scan signals to the gate line GA2 simultaneously. Two third-stage shift registers SR3 are also provided, one is the left shift register SR3, and the other is the right shift register SR3. And the left shift register SR3 and the right shift register SR3 input gate scan signals to the gate line GA3 simultaneously. The rest is the same by analogy, and will not be elaborated here.

[0097] In some embodiments of the present disclosure, as Figure 7d 、 Figure 8a and Figure 8b shown, the first cascade group ZJL1 and the third cascade group ZJL3 can also be set at the first end of multiple gate lines, and the second cascade group ZJL2 and the fourth cascade group ZJL4 can be set at the second end of multiple gate lines. Exemplarily, the first cascade group ZJL1 and the third cascade group ZJL3 are set on the left side of multiple gate lines, and the second cascade group ZJL2 and the fourth cascade group ZJL4 are set on the right side of multiple gate lines. Specifically, please refer to Figure 7d and Figure 8a, the first cascaded group ZJL1 includes shift registers SR1 and SR5. The second cascaded group ZJL2 includes shift registers SR3 and SR7. Please refer to Figure 7d and Figure 8b , the third cascaded group ZJL3 includes shift registers SR2 and SR6. The fourth cascaded group ZJL4 includes shift registers SR4 and SR8.

[0098] In some embodiments of the present disclosure, the display panel further includes a plurality of selection signal lines; the selection signal terminals CKX of the shift registers in the same register group are coupled to the same selection signal line, and different register groups are coupled to different selection signal lines. Exemplarily, M = 2, as Figure 8a and Figure 8b shown, the plurality of selection signal lines include a first selection signal line CXS1 and a second selection signal line CXS2. Among them, the selection signal terminals CKX of the shift registers in the first register group ZGOA1 are all coupled to the first selection signal line CXS1, and the selection signal terminals CKX of the shift registers in the second register group ZGOA2 are all coupled to the second selection signal line CXS2.

[0099] In some embodiments of the present disclosure, in combination with Figure 4 , Figure 7b , Figure 8a and Figure 8b shown, the first control signal terminal VN-1 and the selection signal terminal CKX of each shift register (i.e., the odd-numbered shift register) in the first register group ZGOA1 are both coupled to the first selection signal line CXS1 to input the same control signal. The second control signal terminal VN-2 and the selection signal terminal CKX of each shift register (i.e., the even-numbered shift register) in the second register group ZGOA2 are both coupled to the second selection signal line CXS2 to input the same control signal. When a valid level (such as a high level) is loaded on the first selection signal line CXS1 and an invalid level (such as a low level) is loaded on the second selection signal line CXS2, scanning of the odd-numbered row gate lines can be achieved. When an invalid level (such as a low level) is loaded on the first selection signal line CXS1 and a valid level (such as a high level) is loaded on the second selection signal line CXS2, scanning of the even-numbered row gate lines can be achieved.

[0100] Exemplarily, as Figure 6b , Figure 6c and Figure 7bAs shown, the control signal terminal VN and the selection signal terminal CKX of each shift register (i.e., the odd-numbered shift register) in the first register group ZGOA1 are coupled to the first selection signal line CXS1 to input the same control signal. The control signal terminal VN and the selection signal terminal CKX of each shift register (i.e., the even-numbered shift register) in the second register group ZGOA2 are coupled to the second selection signal line CXS2 to input the same control signal. When the first selection signal line CXS1 is loaded with a valid level (such as a high level) and the second selection signal line CXS2 is loaded with an invalid level (such as a low level), scanning of odd-numbered gate lines can be achieved. When the first selection signal line CXS1 is loaded with an invalid level (such as a low level) and the second selection signal line CXS2 is loaded with a valid level (such as a high level), scanning of even-numbered gate lines can be achieved. It should be noted that, Figure 6c The structure of the shift register in Figure 3 For example.

[0101] Some embodiments of the present disclosure provide a driving method, including: dividing a display frame into M scanning stages and N touch stages; in the m-th scanning stage among the M scanning stages, loading a frame start signal on a frame start signal line coupled to the m-th register group among the M register groups, loading different clock signals on multiple clock signal lines, controlling the shift register unit in the m-th register group to output a gate scanning signal to the coupled gate line, and loading a cutoff control signal on the frame start signal lines coupled to the remaining register groups; and setting one touch stage among the N touch stages between two adjacent scanning stages among the M scanning stages, scanning the touch electrodes in the display panel in the touch stage, loading a cutoff control signal on each frame start signal line, and loading a cutoff control signal on each clock signal line; N is an integer greater than 0.

[0102] In the above-mentioned driving method provided by the embodiment of the present disclosure, by setting the scanning stage and the touch stage in one display frame, the display panel can realize the function of display and touch in time sharing. In addition, since a new register group is controlled to scan the coupled gate lines in the next scanning stage after the touch stage, the problem of horizontal stripes in the display caused by pausing the shift register scanning and then restarting the scanning in the prior art during the line-by-line scanning can be avoided. In addition, the embodiment of the present disclosure avoids the leakage problem of the display level for a long time by reserving the scanning time for other integrated functions and inserting them between the display scanning stages.

[0103] In some embodiments of the present disclosure, one of the N touch stages may be set between every two adjacent scanning stages in the M scanning stages. Optionally, in two adjacent display frames, the two display frames include a first display frame and a second display frame, and a target touch stage is set between the Mth scanning stage of the first display frame and the first scanning stage of the second display frame. Wherein, the target touch stage is one of the N touch stages of the second display frame. Exemplarily, as Figure 9 shown, the gth display frame F_g has two touch stages tu1_g and tu2_g, and the tu1_g stage is the target touch stage in the gth display frame F_g. The (g + 1)th display frame F_g+1 has two touch stages tu1_g+1 and tu2_g+1, and the tu1_g+1 stage is the target touch stage in the (g + 1)th display frame F_g+1. Of course, the target touch stage may be one of the N touch stages of the first display frame, which is not limited herein.

[0104] In some embodiments of the present disclosure, in the mth scanning stage, a frame start signal is loaded onto the frame start signal line coupled to the mth register bank, different clock signals are loaded onto the clock signal lines coupled to the mth register bank, and each shift register pair in the mth register bank is controlled to sequentially scan the gate lines at intervals of M - 1 rows.

[0105] Exemplarily, the periods of the clock signals corresponding to different register banks are the same and the timings are the same.

[0106] Exemplarily, taking M = 2 and N = 2 (of course, N can also be set to other values, which is not limited herein) as an example, as Figure 9As shown, cks1_1 represents the clock signal on the first clock signal line CKS1, cks2_1 represents the clock signal on the second clock signal line CKS2, cks3_1 represents the clock signal on the third clock signal line CKS3, cks4_1 represents the clock signal on the fourth clock signal line CKS4, stv1_1 represents the signal on the first frame start signal line, and stv2_1 represents the signal on the second frame start signal line. ga1_1 represents the gate scan signal input to the gate line GA1 from the drive output GO of the first-stage shift register SR1, ga3_1 represents the gate scan signal input to the gate line GA3 from the drive output GO of the third-stage shift register SR3, ga5_1 represents the gate scan signal input to the gate line GA5 from the drive output GO of the fifth-stage shift register SR5, ga7_1 represents the gate scan signal input to the gate line GA7 from the drive output GO of the seventh-stage shift register SR7, ga2_1 represents the gate scan signal input to the gate line GA2 from the drive output GO of the second-stage shift register SR2, ga4_1 represents the gate scan signal input to the gate line GA4 from the drive output GO of the fourth-stage shift register SR4, ga6_1 represents the gate scan signal input to the gate line GA6 from the drive output GO of the sixth-stage shift register SR6, and ga8_1 represents the gate scan signal input to the gate line GA8 from the drive output GO of the eighth-stage shift register SR8.

[0107] Moreover, the g-th display frame F_g includes two scan phases and two touch phases. Among them, the two scan phases included in the g-th display frame F_g are: the first scan phase sm1_g and the second scan phase sm2_g. The two touch phases included in the g-th display frame F_g are: the first touch phase tu1_g and the second touch phase tu2_g. The first touch phase tu1_g is located before the first scan phase sm1_g, and the second touch phase tu2_g is located between the first scan phase sm1_g and the second scan phase sm2_g. The (g + 1)-th display frame F_g+1 includes two scan phases and two touch phases. Among them, the two scan phases included in the (g + 1)-th display frame F_g+1 are: the first scan phase sm1_g+1 and the second scan phase sm2_g+1. The two touch phases included in the (g + 1)-th display frame F_g+1 are: the first touch phase tu1_g+1 and the second touch phase tu2_g+1. The first touch phase tu1_g+1 is located between the second scan phase sm2_g and the first scan phase sm1_g+1, and the second touch phase tu2_g+1 is located between the first scan phase sm1_g+1 and the second scan phase sm2_g+1.

[0108] In the g-th display frame F_g, during the first touch stage tu1_g, the touch electrodes in the display panel are scanned, and a cut-off control signal with a low level is respectively loaded on the first frame start signal line and the second frame start signal line, and a cut-off control signal with a low level is respectively loaded on the first clock signal line CKS1 to the fourth clock signal line CKS4, so that each shift register in each register group maintains an output signal with a low level. In addition, a frame reset signal is loaded on the frame reset signal line to control each shift register to be reset.

[0109] In the first scanning stage sm1_g, a frame start signal with a high level is loaded on the first frame start signal line, and a cut-off control signal with a low level is loaded on the second frame start signal line. An enable control signal with a high level is loaded on the first selection signal line CXS1, and a cut-off control signal with a low level is loaded on the second selection signal line CXS2, so that the ninth transistor M9 of each shift register in the first register can be turned on, and the ninth transistor M9 of each shift register in the second register can be turned off. Moreover, signals cks1_1 to cks4_1 are respectively loaded on the first clock signal line CKS1 to the fourth clock signal line CKS4 to control the shift register units in the first register group ZGOA1 to output gate scan signals ga1_1, ga3_1, ga5_1, ga7_1 to the coupled gate lines GA1, GA3, GA5, GA7. And the second register group ZGOA2 is controlled to maintain an output signal with a low level.

[0110] In the second touch stage tu2_g, the touch electrodes in the display panel are scanned, and a cut-off control signal with a low level is respectively loaded on the first frame start signal line and the second frame start signal line, a cut-off control signal with a low level is respectively loaded on the first clock signal line CKS1 to the fourth clock signal line CKS4, and a cut-off control signal with a low level is loaded on the first selection signal line CXS1 and the second selection signal line CXS2, so that each shift register in each register group maintains an output signal with a low level.

[0111] In the second scanning stage sm2_g, a frame start signal with a high level is loaded onto the second frame start signal line, and a cut-off control signal with a low level is loaded onto the first frame start signal line. A turn-on control signal with a high level is loaded onto the second selection signal line CXS2, and a cut-off control signal with a low level is loaded onto the first selection signal line CXS1, so that the ninth transistor M9 of each shift register in the second register can be turned on, and the ninth transistor M9 of each shift register in the first register can be turned off. Also, signals cks1_1 to cks4_1 are respectively loaded onto the first clock signal line CKS1 to the fourth clock signal line CKS4, controlling the shift register units in the second register group ZGOA2 to output gate scan signals ga2_1, ga4_1, ga6_1, ga8_1 to the coupled gate lines GA2, GA4, GA6, GA8. And the first register group ZGOA1 is controlled to keep outputting a signal with a low level.

[0112] In the (g + 1)-th display frame F_g+1, in the first touch stage tu1_g+1, the touch electrodes in the display panel are scanned, and cut-off control signals with low levels are respectively loaded onto the first frame start signal line and the second frame start signal line, cut-off control signals with low levels are respectively loaded onto the first clock signal line CKS1 to the fourth clock signal line CKS4, and cut-off control signals with low levels are loaded onto the first selection signal line CXS1 and the second selection signal line CXS2, so that each shift register in each register group keeps outputting a signal with a low level. Also, a frame reset signal is loaded onto the frame reset signal line to control each shift register to be reset.

[0113] In the first scanning stage sm1_g+1, a frame start signal with a high level is loaded onto the first frame start signal line, and a cut-off control signal with a low level is loaded onto the second frame start signal line. A turn-on control signal with a high level is loaded onto the first selection signal line CXS1, and a cut-off control signal with a low level is loaded onto the second selection signal line CXS2, so that the ninth transistor M9 of each shift register in the first register can be turned on, and the ninth transistor M9 of each shift register in the second register can be turned off. Also, signals cks1_1 to cks4_1 are respectively loaded onto the first clock signal line CKS1 to the fourth clock signal line CKS4, controlling the shift register units in the first register group ZGOA1 to output gate scan signals ga1_1, ga3_1, ga5_1, ga7_1 to the coupled gate lines GA1, GA3, GA5, GA7. And the second register group ZGOA2 is controlled to keep outputting a signal with a low level.

[0114] In the second touch stage tu2_g+1, the touch electrodes in the display panel are scanned, and a low-level cut-off control signal is respectively loaded on the first frame start signal line and the second frame start signal line, a low-level cut-off control signal is respectively loaded on the first clock signal line CKS1 to the fourth clock signal line CKS4, and a low-level cut-off control signal is loaded on the first selection signal line CXS1 and the second selection signal line CXS2, so that each shift register in each register group maintains an output signal of low level.

[0115] In the second scan stage sm2_g+1, a high-level frame start signal is loaded on the second frame start signal line, and a low-level cut-off control signal is loaded on the first frame start signal line. A high-level enable control signal is loaded on the second selection signal line CXS2, and a low-level cut-off control signal is loaded on the first selection signal line CXS1, so that the ninth transistor M9 of each shift register in the second register can be turned on, and the ninth transistor M9 of each shift register in the first register can be turned off. And, signals cks1_1 to cks4_1 are respectively loaded on the first clock signal line CKS1 to the fourth clock signal line CKS4, and the shift register units in the second register group ZGOA2 are controlled to output gate scan signals ga2_1, ga4_1, ga6_1, ga8_1 to the coupled gate lines GA2, GA4, GA6, GA8. And the first register group ZGOA1 is controlled to maintain an output signal of low level.

[0116] It should be noted that in the embodiments of the present disclosure, the two register groups can be switched to work separately in one display frame to provide segmented scanning time for touch, that is, the touch scanning frequency can be twice the display scanning frequency, that is, the display panel can achieve a display scanning frequency of 60Hz + a touch scanning frequency of 120Hz or a display scanning frequency of 120Hz + a touch scanning frequency of 240Hz, etc. And, the embodiments of the present disclosure can avoid the horizontal stripe problem of the brightness difference of the upper and lower sub-pixels caused by pausing the shift register scanning during the display process. Of course, the touch scanning frequency can also be three times the display scanning frequency, that is, the display panel can achieve a display scanning frequency of 60Hz + a touch scanning frequency of 180Hz, etc. The touch scanning frequency can also be four times the display scanning frequency, that is, the display panel can achieve a display scanning frequency of 60Hz + a touch scanning frequency of 240Hz, etc.

[0117] In some embodiments of the present disclosure, such as Figure 10As shown, a column of sub-pixels has the same color, and the red sub-pixel columns, green sub-pixel columns, and blue sub-pixel columns are arranged in sequence and repeated. For example, red sub-pixel columns R11 to R81, green sub-pixel columns G11 to G81, blue sub-pixel columns B11 to B81, red sub-pixel columns R12 to R82, green sub-pixel columns G12 to G82, blue sub-pixel columns B12 to B82. Also, one row of sub-pixels SPX is correspondingly coupled to one gate line, and one column of sub-pixels SPX is correspondingly coupled to one data line. Exemplarily, in combination with Figures 9 to 11b As shown, in the g-th display frame F_g, in the first scanning stage sm1_g, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA6, so that the sub-pixels R11 to B12, R31 to B32, R51 to B52, R71 to B72 can input the corresponding data voltages. In the second scanning stage sm2_g, the polarity of the data voltage is flipped once. When the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA6, so that the sub-pixels R21 to B22, R41 to B42, R61 to B62, R81 to B82 can input the corresponding data voltages. In this way, the polarity of each sub-pixel in the g-th display frame F_g is in the dot inversion mode as shown in Figure 11a As shown. In the (g + 1)-th display frame F_g+1, in the first scanning stage sm1_g+1, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA6, so that the sub-pixels R11 to B12, R31 to B32, R51 to B52, R71 to B72 can input the corresponding data voltages. In the second scanning stage sm2_g+1, the polarity of the data voltage is flipped once. When the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA6, so that the sub-pixels R21 to B22, R41 to B42, R61 to B62, R81 to B82 can input the corresponding data voltages. So that the polarity of each sub-pixel in the (g + 1)-th display frame F_g+1 is in the dot inversion mode as shown in Figure 11b As shown. Figure 11a And Figure 11b In, “+” represents the positive polarity and “-” represents the negative polarity. In this way, compared with the method of flipping the data voltage multiple times within one display frame when scanning the gate lines row by row, the embodiments of the present disclosure can achieve the dot inversion effect only by flipping the polarity of the data voltage once within one display frame, which can reduce power consumption.

[0118] In some other embodiments of the present disclosure, as shown in Figure 12As shown, a column of sub-pixels has the same color, and the red sub-pixel columns, green sub-pixel columns, and blue sub-pixel columns are arranged in sequence and repeated. For example, red sub-pixel columns R11 to R81, green sub-pixel columns G11 to G81, blue sub-pixel columns B11 to B81, red sub-pixel columns R12 to R82, green sub-pixel columns G12 to G82, blue sub-pixel columns B12 to B82. Also, one row of sub-pixels SPX is correspondingly coupled to one gate line, and one column of sub-pixels SPX is correspondingly coupled to two data lines. Among them, in the same column of sub-pixels, the odd-row sub-pixels are coupled to the data line on the left side of the column of sub-pixels, and the even-row sub-pixels are coupled to the data line on the right side of the column of sub-pixels. Exemplarily, in combination with Figure 9 and Figures 11a to 12 as shown, in the g-th display frame F_g, in the first scanning stage sm1_g, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA7, so that the sub-pixels R11 to B12, R31 to B32, R51 to B52, R71 to B72 can input the corresponding data voltages. In the second scanning stage sm2_g, the polarity of the data voltage is flipped once. When the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA7, so that the sub-pixels R21 to B22, R41 to B42, R61 to B62, R81 to B82 can input the corresponding data voltages. In this way, the polarity of each sub-pixel in the g-th display frame F_g is the dot inversion mode as shown in Figure 11a as shown. In the (g + 1)-th display frame F_g+1, in the first scanning stage sm1_g+1, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA7, so that the sub-pixels R11 to B12, R31 to B32, R51 to B52, R71 to B72 can input the corresponding data voltages. In the second scanning stage sm2_g+1, the polarity of the data voltage is flipped once. When the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA7, so that the sub-pixels R21 to B22, R41 to B42, R61 to B62, R81 to B82 can input the corresponding data voltages. So that the polarity of each sub-pixel in the (g + 1)-th display frame F_g+1 is the dot inversion mode as shown in Figure 11b as shown. Figure 11a and Figure 11bIn it, "+" represents the positive polarity and "-" represents the negative polarity. In this way, compared with the method of flipping the data voltage multiple times within a display frame when scanning the gate lines line by line, the embodiments of the present disclosure only need to flip the polarity of the data voltage once within a display frame to achieve the dot flipping effect, which can reduce power consumption. Moreover, in each scanning stage, each data line only charges the sub-pixels of the same color, which can avoid the problem of color mixing FinePitch Mura.

[0119] In some other embodiments of the present disclosure, as Figure 13 shown, a column of sub-pixels is of the same color, and the red sub-pixel columns, green sub-pixel columns, and blue sub-pixel columns are arranged in sequence and repeatedly. For example, the red sub-pixel columns R11~R41, green sub-pixel columns G11~G41, blue sub-pixel columns B11~B41, red sub-pixel columns R12~R42, green sub-pixel columns G12~G42, blue sub-pixel columns B12~B42. Moreover, one row of sub-pixels SPX corresponds to two gate lines (i.e., Dual Gate), and adjacent two columns of sub-pixels SPX correspond to one data line. Among them, the sub-pixels in adjacent two columns of sub-pixels are all coupled to their corresponding data lines. And for the two sub-pixels coupled to the same data line in the same row, the left sub-pixel is coupled to the gate line above this row, and the right sub-pixel is coupled to the gate line below this row. Exemplarily, combined with Figure 9 and Figures 13 to 14b shown, in the g-th display frame F_g, in the first scanning stage sm1_g, the polarity of the data voltage is flipped once. When the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at high level, the corresponding data voltages are respectively loaded on the data lines DA1~DA3, so that the sub-pixels R11~R41, R12~R42, B12~B42 can input the corresponding data voltages. In the second scanning stage sm2_g, when the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at high level, the corresponding data voltages are respectively loaded on the data lines DA1~DA3, so that the sub-pixels G11~G41, B11~B41, G12~G42 can input the corresponding data voltages. In this way, the polarities of the sub-pixels in the g-th display frame F_g are as Figure 14aThe column inversion method shown. In the (g + 1)-th display frame F_g+1, within the first scanning stage sm1_g+1, the polarity of the data voltage is inverted once. When the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA3, so that the sub-pixels R11 to R41, R12 to R42, B12 to B42 can input the corresponding data voltages. In the second scanning stage sm2_g+1, when the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA3, so that the sub-pixels G11 to G41, B11 to B41, G12 to G42 can input the corresponding data voltages. So that the polarity of each sub-pixel in the (g + 1)-th display frame F_g+1 is as Figure 14b the dot inversion method shown. Figure 14a and Figure 14b In, "+" represents the positive polarity and "-" represents the negative polarity. In this way, compared with the method of inverting the data voltage multiple times within one display frame when scanning the gate lines row by row, the embodiments of the present disclosure only need to invert the polarity of the data voltage once within one display frame to achieve the column inversion effect, which can reduce power consumption. Moreover, in each scanning stage, each data line only charges sub-pixels of the same color. When monochromatic color mixing occurs, the data line does not need to be inverted from positive to negative to 0V, and the inversion between positive and negative is changed to 0V to positive or 0V to negative, and the pre-charge Margin increases, showing better performance at low temperatures, which can solve the vertical stripe problem of the display panel with a Dual Gate structure during monochromatic color mixing.

[0120] In some other embodiments of the present disclosure, the register group can also be divided into three, which can also make Figure 13 the display panel shown achieve the dot inversion effect. And, the touch scanning frequency is three times the display scanning frequency, that is, the display panel can achieve a 60Hz display scanning frequency + 180Hz touch scanning frequency.

[0121] In some other embodiments of the present disclosure, such as Figure 15As shown, a column of sub-pixels has the same color, and the red sub-pixel columns, green sub-pixel columns, and blue sub-pixel columns are arranged in sequence and repeated. For example, red sub-pixel columns R11 to R41, green sub-pixel columns G11 to G41, blue sub-pixel columns B11 to B41, red sub-pixel columns R12 to R42, green sub-pixel columns G12 to G42, blue sub-pixel columns B12 to B42. Also, one row of sub-pixels SPX corresponds to two gate lines (i.e., Dual Gate), and two adjacent columns of sub-pixels SPX correspond to two data lines. Multiple sub-pixels in the display panel can be divided into multiple sub-pixel groups, and each sub-pixel group can include two adjacent sub-pixels in the same row. And, one sub-pixel in the sub-pixel group is electrically connected to one of the corresponding two gate lines, and the other sub-pixel is electrically connected to the other of the corresponding two gate lines. Also, one column of sub-pixel groups can be arranged between every two adjacent data lines, and for two adjacent data lines, one data line is connected to the odd rows of one column of sub-pixel groups arranged between the two data lines, and the other data line is connected to the even rows of one column of sub-pixel groups arranged between the two data lines. It can also be said that two adjacent columns of sub-pixels are arranged between two adjacent data lines. This can reduce the power consumption of the source driver circuit. Exemplarily, in combination with Figure 9 、 Figure 11a 、 Figure 11b and Figure 15 shown, in the g-th display frame F_g, in the first scanning stage sm1_g, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA4, so that the sub-pixels R11 to R41, R12 to R42, B12 to B42 can input the corresponding data voltages. In the second scanning stage sm2_g, when the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA4, so that the sub-pixels G11 to G41, B11 to B41, G12 to G42 can input the corresponding data voltages. This makes the polarities of the sub-pixels in the g-th display frame F_g as shown in Figure 11aThe dot inversion method shown. In the (g + 1)-th display frame F_g+1, in the first scanning stage sm1_g+1, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA4, so that the sub-pixels R11 to R41, R12 to R42, B12 to B42 can input the corresponding data voltages. In the second scanning stage sm2_g+1, when the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA4, so that the sub-pixels G11 to G41, B11 to B41, G12 to G42 can input the corresponding data voltages. So that the polarities of the sub-pixels in the (g + 1)-th display frame F_g+1 are as Figure 11b shown in the dot inversion method. In this way, compared with the method of flipping the data voltage multiple times within a display frame when scanning the gate lines row by row, the embodiment of the present disclosure only needs to flip the polarity of the data voltage once within a display frame to achieve the dot inversion effect, which can reduce power consumption. Moreover, the odd-numbered gate lines charge the red sub-pixels, and the even-numbered gate lines charge the green sub-pixels and the blue-green mixed color of the blue sub-pixels, which requires a flip from 0V to positive or negative polarity, but there is no continuous pre-charge. Taking a blue-green mixed color screen (that is, the blue sub-pixels and the green sub-pixels are lit and the red sub-pixels are black) as an example, in the prior art, the gate lines GA1 to GA8 are scanned row by row, and the blue sub-pixels B12, B23 and the green sub-pixel G23 are continuously pre-charged, resulting in adjacent green sub-pixels and blue sub-pixels being too bright and serious vertical stripes in the picture. In the technical solution of the embodiment of the present disclosure, in the first scanning stage, the odd-numbered gate lines are scanned row by row, so that the data line DA3 can charge the blue sub-pixels B12, B32. In the second scanning stage, the even-numbered gate lines are scanned row by row, so that the data line DA3 can charge the green sub-pixels G12, the blue sub-pixel B21, the green sub-pixel G32, and the blue sub-pixel B41, and there is no continuous pre-charge, which can improve the brightness uniformity of the display picture.

[0122] In some other embodiments of the present disclosure, as Figure 16 shown, a row of sub-pixels is of the same color, and the rows of red sub-pixels, green sub-pixels, and blue sub-pixels are arranged in sequence and repeated. For example, the row of red sub-pixels R11 to R16, the row of green sub-pixels G11 to G16, the row of blue sub-pixels B11 to B16, the row of red sub-pixels R21 to R26, the row of green sub-pixels G21 to G26, the row of blue sub-pixels B21 to B26, the row of red sub-pixels R31 to R36, the row of green sub-pixels G31 to G36. Moreover, a row of sub-pixels SPX is correspondingly coupled to a gate line, and a column of sub-pixels SPX is correspondingly coupled to a data line. Exemplarily, in combination with Figure 9 and Figure 11a 、 Figure 11band to Figure 16 As shown, in the g-th display frame F_g, during the first scanning stage sm1_g, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, and GA7 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA6, so that the sub-pixels R11 to R16, B11 to B16, G21 to G26, and R31 to R36 can input the corresponding data voltages. During the second scanning stage sm2_g, the polarity of the data voltage is flipped once. When the gate scanning signals loaded on the gate lines GA2, GA4, GA6, and GA8 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA6, so that the sub-pixels G11 to G16, R21 to R26, B21 to B26, and G31 to G36 can input the corresponding data voltages. In this way, the polarity of each sub-pixel in the g-th display frame F_g is the dot inversion method as Figure 11a shown. In the (g + 1)-th display frame F_g+1, during the first scanning stage sm1_g+1, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, and GA7 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA6, so that the sub-pixels R11 to R16, B11 to B16, G21 to G26, and R31 to R36 can input the corresponding data voltages. During the second scanning stage sm2_g+1, the polarity of the data voltage is flipped once. When the gate scanning signals loaded on the gate lines GA2, GA4, GA6, and GA8 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA6, so that the sub-pixels G11 to G16, R21 to R26, B21 to B26, and G31 to G36 can input the corresponding data voltages. So that the polarity of each sub-pixel in the (g + 1)-th display frame F_g+1 is the dot inversion method as Figure 11b shown. In this way, compared with the method of flipping the data voltage multiple times within one display frame when scanning the gate lines row by row, in the embodiments of the present disclosure, it is only necessary to flip the polarity of the data voltage once within one display frame to achieve the dot inversion effect, which can reduce power consumption. And, this can also avoid the problem of display horizontal stripes.

[0123] In some other embodiments of the present disclosure, the register group can also be divided into 6. At this time, 6 frame start signal lines are set, that is, 6 different frame start signals need to be input, and this can also make Figure 16 the display panel shown achieve the dot inversion effect. And, make the touch scanning frequency 6 times that of the display scanning frequency, that is, the display panel can achieve a display scanning frequency of 60Hz + a touch scanning frequency of 360Hz. The register group can also be divided into 3. At this time, 3 frame start signal lines are set, that is, 3 different frame start signals need to be input, and make the polarities of adjacent columns in the same row different, so as to also improve the horizontal stripe problem. And, this can also makeFigure 16 The shown display panel achieves an effect similar to dot inversion. Moreover, the touch scanning frequency is three times the display scanning frequency, that is, the display panel can achieve a display scanning frequency of 60 Hz + a touch scanning frequency of 180 Hz.

[0124] In some other embodiments of the present disclosure, as Figure 17 shown, a row of sub-pixels is of the same color, and the red sub-pixel rows, green sub-pixel rows, and blue sub-pixel rows are arranged in sequence and repeated. For example, red sub-pixel rows R11 - R16, green sub-pixel rows G11 - G16, blue sub-pixel rows B11 - B16, red sub-pixel rows R21 - R26, green sub-pixel rows G21 - G26, blue sub-pixel rows B21 - B26, red sub-pixel rows R31 - R36, green sub-pixel rows G31 - G36. And, one row of sub-pixels SPX is correspondingly coupled to one gate line, and one column of sub-pixels SPX is correspondingly coupled to two data lines. Among them, in the same column of sub-pixels, the odd-row sub-pixels are coupled to the data line on the left side of the column of sub-pixels, and the even-row sub-pixels are coupled to the data line on the right side of the column of sub-pixels. Exemplarily, in combination with Figure 9 and Figure 11a 、 Figure 11b and up to Figure 17 shown, in the g-th display frame F_g, in the first scanning stage sm1_g, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 - DA7, so that the sub-pixels R11 - R16, B11 - B16, G21 - G26, R31 - R36 can input corresponding data voltages. In the second scanning stage sm2_g, the polarity of the data voltage is inverted once. When the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 - DA7, so that the sub-pixels G11 - G16, R21 - R26, B21 - B26, G31 - G36 can input corresponding data voltages. This makes the polarity of each sub-pixel in the g-th display frame F_g as Figure 11aThe dot inversion method shown. In the (g + 1)-th display frame F_g+1, in the first scanning stage sm1_g+1, when the gate scanning signals loaded on the gate lines GA1, GA3, GA5, GA7 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA7, so that the sub-pixels R11 to R16, B11 to B16, G21 to G26, R31 to R36 can input the corresponding data voltages. In the second scanning stage sm2_g+1, the polarity of the data voltage is inverted once. When the gate scanning signals loaded on the gate lines GA2, GA4, GA6, GA8 are at a high level, corresponding data voltages are respectively loaded on the data lines DA1 to DA7, so that the sub-pixels G11 to G16, R21 to R26, B21 to B26, G31 to G36 can input the corresponding data voltages. So that the polarity of each sub-pixel in the (g + 1)-th display frame F_g+1 is as Figure 11b shown in the dot inversion method. In this way, compared with the method of inverting the data voltage multiple times within one display frame when scanning the gate lines row by row, the embodiment of the present disclosure can invert the polarity of the data voltage only once within one display frame to achieve the dot inversion effect, which can reduce power consumption. And, this can also avoid the problem of display horizontal stripes.

[0125] In some other embodiments of the present disclosure, the register group can also be divided into three. At this time, three frame start signal lines are set, that is, three different frame start signals need to be input. Using the frame start signals stv1_1, stv2_1, stv3_1 to control the timing, a similar dot inversion effect can be achieved. The frame start signal stv1_1 controls a register group to drive the gate lines GA1 and GA4, so that the red sub-pixels R11 and R22 have the same positive polarity, the red sub-pixels R12 and R23 have the same negative polarity, and the positive and negative are flipped in the next frame. The positive and negative polarities of adjacent red sub-pixels in the same column can be alternated, and adjacent two sub-pixels in the same row have different polarities. For example, the polarity of the sub-pixels in the first column in the previous frame is: + - + + - + + -, and the polarity of the sub-pixels in the first column in the next frame is - + - - + - - +. Therefore, through the three frame start signals, the Figure 17 display panel shown can also achieve a similar dot inversion effect. Compared with Figure 16 the architecture of the display panel shown, the number of frame start signal lines and frame start signals is reduced. And, the touch scanning frequency is three times the display scanning frequency, that is, the display panel can achieve a 60Hz display scanning frequency + 180Hz touch scanning frequency.

[0126] In some other embodiments of the present disclosure, such as Figure 18As shown, a selection control circuit MUX can also be provided between the drive output terminal of the gate drive circuit and the gate lines, so as to combine the gate drive circuit and the selection control circuit MUX to drive and implement interlaced scanning display. Specifically, the selection control circuit MUX can control the grouping of the gate lines. For example, the selection control circuit MUX includes selection control transistors each coupled to a corresponding gate line. The first pole of the selection control transistor is coupled to the drive output terminal of the shift register, the second pole is coupled to the corresponding gate line, and the control pole is coupled to the selection gate line control terminal. Taking the odd-numbered gate lines as one group and the even-numbered gate lines as another group, the control poles of the selection control transistors corresponding to the odd-numbered gate lines are all coupled to the same selection gate line control terminal, and the control poles of the selection control transistors corresponding to the even-numbered gate lines are all coupled to the same selection gate line control terminal. When only scanning the odd-numbered gate lines, the selection control transistors corresponding to the odd-numbered gate lines can be controlled to conduct, and the selection control transistors corresponding to the even-numbered gate lines can be controlled to cut off. When only scanning the even-numbered gate lines, the selection control transistors corresponding to the even-numbered gate lines can be controlled to conduct, and the selection control transistors corresponding to the odd-numbered gate lines can be controlled to cut off.

[0127] It should be noted that the timing controller is configured to divide a display frame into M scanning stages and N touch stages; in the m-th scanning stage among the M scanning stages, a frame start signal is loaded onto the frame start signal line coupled to the m-th register group among the M register groups, different clock signals are loaded onto multiple clock signal lines, the shift register units in the m-th register group are controlled to output gate scanning signals to the coupled gate lines, and a cut-off control signal is loaded onto the frame start signal lines coupled to the remaining register groups; and, in each touch stage among the N touch stages, a cut-off control signal is loaded onto each frame start signal line, and a cut-off control signal is loaded onto each clock signal line. The working principle and specific implementation of this timing controller are the same as those in the above embodiments. Therefore, the working process of this timing controller can be implemented by referring to the specific implementation of the driving method in the above embodiments, and will not be elaborated here.

[0128] It should be noted that the touch drive circuit is configured to set one touch stage among the N touch stages between two adjacent scanning stages of the M scanning stages. In the touch stage, the touch electrodes in the display panel are scanned; N is an integer greater than 0. The working principle and specific implementation of this touch drive circuit are the same as those in the above embodiments. Therefore, the working process of this touch drive circuit can be implemented by referring to the specific implementation of the driving method in the above embodiments, and will not be elaborated here.

[0129] In specific implementation, in the embodiments of the present disclosure, the display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be elaborated herein, nor should they be regarded as a limitation to the present disclosure.

[0130] The driving method and display device of the display panel provided by the embodiments of the present disclosure enable the display panel to perform display and touch functions separately by setting a scanning stage and a touch stage within one display frame. Moreover, since in the next scanning stage after the touch stage ends, a new register group is controlled to scan the coupled gate lines, it is possible to avoid the problem of display horizontal stripes that occur in the prior art due to pausing the shift register scanning in the middle and then restarting the scanning during line-by-line scanning. The embodiments of the present disclosure reserve scanning time for other integrated functions and insert them between the display scanning stages to avoid the leakage problem of long-time display levels.

[0131] Those skilled in the art should understand that the embodiments of the present disclosure may be provided as a method, a system, or a computer program product. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0132] The present disclosure is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or blocks or the combination of multiple flows and / or blocks.

[0133] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in Figure 1 one or more of the flows Figure 1 or blocks or the combination of multiple flows and / or blocks.

[0134] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are executed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions for implementing the steps for the functions specified in one process or a plurality of processes and / or blocks Figure 1 one process or a plurality of processes and / or blocks Figure 1 in one block or a plurality of blocks.

[0135] Although the preferred embodiments of the present disclosure have been described, additional changes and modifications can be made by those skilled in the art once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to cover the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0136] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. A driving method for a display panel, characterized in that, The display panel includes: a plurality of gate lines, a gate driving circuit respectively coupled to the plurality of gate lines, a plurality of clock signal lines and a plurality of frame start signal lines coupled to the gate driving circuit; the gate driving circuit includes a plurality of shift registers, a driving output end of one of the shift registers is coupled to one of the gate lines, and the plurality of shift registers are divided into M register groups, and different register groups are coupled to different frame start signal lines; M is an integer greater than 1; The shift register includes: an output transistor and a clock selection circuit; A gate of the output transistor is coupled to a first node, a second pole of the output transistor is coupled to the driving output end, and a first pole of the output transistor is coupled to the clock selection circuit; The clock selection circuit is configured to conduct, in response to a signal of a selection signal terminal, a first pole of the output transistor and a clock signal terminal coupled to a corresponding clock signal line; The driving method includes: Dividing a display frame into M scanning phases and N touch phases; in the m-th scanning phase of the M scanning phases, loading a frame start signal on a frame start signal line coupled to the m-th register group among the M register groups, loading different clock signals on the plurality of clock signal lines, controlling the shift registers in the m-th register group to output gate scanning signals to the coupled gate lines, and loading a cut-off control signal on the frame start signal lines coupled to the remaining register groups; Setting one of the N touch phases between two adjacent scanning phases of the M scanning phases, and in the touch phase, scanning touch electrodes in the display panel, and loading a cut-off control signal on each of the frame start signal lines and loading the cut-off control signal on each of the clock signal lines; N is an integer greater than 0.

2. The driving method for a display panel according to claim 1, characterized in that, In the M scanning phases, one of the N touch phases is set between every two adjacent scanning phases.

3. The driving method for a display panel according to claim 1, characterized in that, In two adjacent display frames, the two display frames include a first display frame and a second display frame, and a target touch phase is set between the M-th scanning phase of the first display frame and the first scanning phase of the second display frame; The target touch phase is one of the N touch phases of the second display frame; or, the target touch phase is one of the N touch phases of the first display frame.

4. The driving method for a display panel according to any one of claims 1-3, characterized in that, The shift registers in each of the register groups are respectively coupled to gate lines spaced M-1 rows apart; In the m-th scanning phase, loading a frame start signal on a frame start signal line coupled to the m-th register group, loading different clock signals on the clock signal lines coupled to the m-th register group, and controlling the shift registers in the m-th register group to sequentially scan the gate lines spaced M-1 rows apart that are coupled thereto row by row.

5. The driving method for a display panel according to claim 4, characterized in that, The periods of the clock signals corresponding to different register groups are the same and the timings are the same.

6. A display device, characterized in that, Including: A display panel, comprising: a plurality of gate lines, a gate driving circuit respectively coupled to the plurality of gate lines, a plurality of clock signal lines and a plurality of frame start signal lines coupled to the gate driving circuit; the gate driving circuit includes a plurality of shift registers, a driving output end of one shift register is coupled to one of the gate lines, and the plurality of shift registers are divided into M register groups, and different register groups are coupled to different frame start signal lines; M is an integer greater than 1; A timing controller, configured to divide a display frame into M scanning phases and N touch phases; in the m-th scanning phase of the M scanning phases, a frame start signal is loaded onto the frame start signal line coupled to the m-th register group among the M register groups, different clock signals are loaded onto the plurality of clock signal lines, and the shift registers in the m-th register group are controlled to output gate scanning signals to the coupled gate lines, and a cut-off control signal is loaded onto the frame start signal lines coupled to the remaining register groups; and, in each touch phase of the N touch phases, a cut-off control signal is loaded onto each of the frame start signal lines, and the cut-off control signal is loaded onto each of the clock signal lines; A touch driving circuit, configured to set one touch phase of the N touch phases between two adjacent scanning phases of the M scanning phases, and in the touch phase, scan touch electrodes in the display panel; N is an integer greater than 0; Wherein, the shift register includes: an output transistor and a clock selection circuit; A gate of the output transistor is coupled to a first node, a second pole of the output transistor is coupled to the driving output end, and a first pole of the output transistor is coupled to the clock selection circuit; The clock selection circuit is configured to conduct the first pole of the output transistor to a clock signal end coupled to a corresponding clock signal line in response to a signal at a selection signal end.

7. The display device according to claim 6, characterized in that, The shift registers in each of the register groups are respectively coupled to gate lines spaced M-1 rows apart; The register group includes at least two cascaded groups, the shift registers in the same cascaded group are cascaded, and the shift registers in the same cascaded group are respectively coupled to gate lines spaced multiple rows apart.

8. The display device according to claim 7, characterized in that, M = 2, the shift registers in the first register group are respectively coupled to the gate lines of odd rows, and the shift registers in the second register group are respectively coupled to the gate lines of even rows; The first register group includes a first cascaded group and a second cascaded group, and the shift registers in the first cascaded group are respectively coupled to gate lines spaced 3 rows apart, and the shift registers in the second cascaded group are respectively coupled to gate lines spaced 3 rows apart; The second register group includes a third cascaded group and a fourth cascaded group, and the shift registers in the third cascaded group are respectively coupled to gate lines spaced 3 rows apart, and the shift registers in the fourth cascaded group are respectively coupled to gate lines spaced 3 rows apart.

9. The display device according to claim 8, characterized in that, The first register group is disposed at a first end of the plurality of gate lines, and the second register group is disposed at a second end of the plurality of gate lines; Alternatively, each of the shift registers includes a left shift register disposed on the left side of the first end of the same gate line and a right shift register disposed on the second end, and the left shift register and the right shift register coupled to the same gate line output the gate scanning signal simultaneously; Alternatively, the first cascaded group and the third cascaded group are disposed at the first end of the multiple gate lines, and the second cascaded group and the fourth cascaded group are disposed at the second end of the multiple gate lines; Alternatively, both the first register group and the second register group are located at the same end of the multiple gate lines.

10. The display device according to any one of claims 6-9, characterized in that,Different register groups are coupled to the same clock signal line.

11. The display device according to claim 10, wherein Taking two adjacent gate lines as a gate line group, the shift registers corresponding to the same gate line group are coupled to the same clock signal line.

12. The display device according to claim 8 or 9, wherein The display panel further includes multiple selection signal lines; The selection signal terminals of the shift registers in the same register group are coupled to the same selection signal line, and different register groups are coupled to different selection signal lines.

13. The display device according to claim 12, wherein The shift register further includes: an input circuit, a reset circuit, at least one control circuit, and a pull-down circuit corresponding to the control circuit one by one; The input circuit is configured to provide the signal of the first scan selection signal terminal to the first node in response to the signal of the input signal terminal; The reset circuit is configured to provide the signal of the second scan selection signal terminal to the first node in response to the signal of the reset signal terminal; The control circuit is configured to control the levels of the signals of the first node and the corresponding second node to be opposite; The pull-down circuit is configured to provide the signal of the reference signal terminal to the drive output terminal in response to the signal of the corresponding second node; 14. The display device according to claim 13, wherein There are two control circuits. The first control circuit in the two control circuits is coupled to the first control signal terminal, and the second control circuit is coupled to the second control signal terminal; The multiple selection signal lines include a first selection signal line and a second selection signal line; wherein, the first control signal terminal in the first register group is coupled to the first selection signal line, and the second control signal terminal in the second register group is coupled to the second selection signal line.

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