In-situ si n overgrown gan-based heterostructure device and method of fabricating the same

Abstract

The application provides an in-situ SiN overlayer GaN-based heterostructure device and a preparation method thereof, relates to the technical field of semiconductors, and the etching method of the in-situ SiN overlayer of the device is as follows: first, the in-situ SiN overlayer is modified by using fluorocarbon plasma; and then, the in-situ SiN overlayer is removed by using Ar plasma bombardment. The etching depth is accurately controlled through two-step continuous atomic layer etching process, the surface morphology etching damage is reduced, a smooth etching surface is obtained, the surface state, the defect density, the defect size of the surface after selective etching of the in-situ SiN overlayer are effectively reduced, the electrical performance loss of the GaN-based heterostructure is reduced, the device ohmic electrode preparation process is optimized, and the in-situ SiN overlayer is more widely applied in the preparation field of GaN-based heterostructure devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an in-situ SiN capping layer etching method, an ohmic contact electrode preparation method, an in-situ SiN capping layer GaN-based heterostructure device and a preparation method thereof. Background Art

[0002] Compared with AlGaN / GaN heterostructures, InAlN / GaN heterostructures exhibit stress-free characteristics and high two-dimensional electron gas (2-DEG) density brought about by strong spontaneous polarization, which can improve device reliability and output current density.

[0003] In recent years, the research on InAlN / GaN HEMTs has gradually become a hot topic in the field of GaN-based HEMTs. However, due to the limitations of the high surface states and high-density V-pit defects caused by the quality of InAlN epitaxial materials, its device level is not enough to compete with AlGaN / GaN devices in many aspects. The biggest gap is that the gate leakage of InAlN devices is large, reaching 10 -5 -10 -7 mA / mm, while the leakage level of general AlGaN devices is only 10 -10 mA / mm. This means that InAlN devices can only be used in specific low-voltage environments, greatly limiting their application in the field of power devices.

[0004] The application of in-situ SiNx capping layers to InAlN / GaN heterostructures can effectively address the high leakage current and low breakdown voltage issues currently encountered in InAlN devices. However, the selective continuous dry etching method for the capping layer cannot precisely control the etching depth during HEMT device fabrication, and can cause significant post-etch surface damage and high surface roughness. Furthermore, after the in-situ SiNx capping layer is completely etched, certain plasma and morphological damage can be inflicted on the InAlN surface, negatively impacting subsequent device fabrication processes. Summary of the Invention

[0005] The purpose of this application is to provide an in-situ SiN capping layer etching method, aiming to solve the problem that the existing in-situ SiN capping layer cannot accurately control the etching depth, causing large surface damage after etching and high etched surface roughness.

[0006] To achieve the above objectives, the present application provides an in-situ SiN capping layer etching method, comprising:

[0007] Modifying the in-situ SiN capping layer using fluorocarbon plasma to form a polymer modified adhesion layer on the in-situ SiN capping layer;

[0008] removing the polymer modified adhesion layer by bombarding with Ar plasma, thereby forming a first etching cycle;

[0009] Complete at least one or more first etching cycles.

[0010] Preferably, the etching rate of the first etching cycle is 0.1-0.5 nm / cycle.

[0011] Preferably, the ICP power of the fluorocarbon plasma is between 50 and 300 W, and the RF power is between 0 and 50 W; the ICP power of the Ar plasma is 0 W, and the RF power is 0 to 30 W.

[0012] Preferably, the fluorocarbon comprises any one of CF4, CHF3, C2F6, C3F6, CH2F2, CH3F and C4F8.

[0013] The present application also provides a method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device, comprising:

[0014] The in-situ SiN capping layer of the ohmic contact electrode pattern is etched away using the above-mentioned in-situ SiN capping layer etching method to obtain an ohmic contact electrode region;

[0015] An ohmic contact metal is evaporated in the ohmic contact electrode region to form an ohmic contact electrode.

[0016] Preferably, after etching away the in-situ SiN capping layer of the ohmic contact electrode pattern to obtain the ohmic contact electrode region, the method further comprises:

[0017] Modifying the surface of the GaN-based heterostructure exposed in the ohmic contact electrode region using O2 plasma to form an oxide layer;

[0018] BCl3 plasma bombardment is used to remove the oxide layer, forming a second etching cycle;

[0019] The second etching cycle is completed at least once or multiple times to achieve surface treatment of the GaN-based heterostructure.

[0020] Preferably, the ICP power of the O2 plasma is 50-300W, and the RF power is 0-100W; the ICP power of the BCl3 plasma is 0W, and the RF power is 0-30W.

[0021] Preferably, the thickness of the surface treatment of the GaN-based heterostructure is less than 1 nm;

[0022] Preferably, the surface treatment thickness of the GaN-based heterostructure is 1 to 3 atomic layers thick;

[0023] Preferably, the etching rate of the second etching cycle is 0.1-0.3 nm / cycle.

[0024] Preferably, the GaN-based heterostructure includes any one of an AlGaN / GaN heterostructure, an InAlN / GaN heterostructure, an InAlN / AlN / GaN heterostructure and an InAlGaN / AlGaN / GaN heterostructure.

[0025] The present application also provides a method for preparing an in-situ SiN capping layer GaN-based heterostructure device, and an ohmic contact electrode is prepared using the above-mentioned method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device.

[0026] The present application also provides an in-situ SiN capping layer GaN-based heterostructure device, which is prepared using the above-mentioned method for preparing an in-situ SiN capping layer GaN-based heterostructure device.

[0027] Compared with the prior art, the advantages of this application include:

[0028] The in-situ SiN capping layer etching method provided in the present application first uses a fluorocarbon plasma to modify the in-situ SiN capping layer, and then uses Ar plasma bombardment to remove it. Through a two-step continuous cyclic atomic layer etching process, the etching depth is precisely controlled, the surface morphology etching damage is reduced, and a smooth etched surface is obtained. The surface state, defect density, defect size and electrical performance loss of the GaN-based heterostructure after selective etching of the in-situ SiN capping layer are effectively reduced, the device ohmic electrode preparation process is optimized, and the in-situ SiN capping layer is more widely used in the field of GaN-based heterostructure device preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope of the present application.

[0030] Figure 1 Schematic diagram of the epitaxial structure of InAlN / AlN / GaN heterostructure with in-situ SiN capping layer;

[0031] Figure 2 Schematic diagram of the structure after the epitaxial structures are isolated;

[0032] Figure 3 This is a schematic diagram of the structure after the ohmic contact electrode pattern is defined in the epitaxial structure;

[0033] Figure 4Schematic diagram of the structure for etching to obtain the ohmic contact electrode area and processing the surface of the InAlN / AlN / GaN heterostructure;

[0034] Figure 5 A schematic diagram of a structure for depositing ohmic contact electrode metal to form an ohmic contact electrode;

[0035] Figure 6 A schematic diagram of a structure for depositing gate metal to form a gate;

[0036] Figure 7 Schematic diagram of etching of in-situ SiN capping layer;

[0037] Figure 8 Schematic diagram of surface treatment of InAlN / AlN / GaN heterostructure;

[0038] Figure 9 Schematic diagram of the process of etching the in-situ SiN capping layer;

[0039] Figure 10 A schematic flow chart of an embodiment of a method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device;

[0040] Figure 11 A schematic flow chart of another embodiment of a method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device;

[0041] Figure 12 Schematic diagram of the process for surface treatment of GaN-based heterostructures. DETAILED DESCRIPTION

[0042] As used herein:

[0043] "Prepared from" is synonymous with "comprising." As used herein, the terms "comprising," "including," "having," "containing," or any other variations thereof, are intended to cover a non-exclusive inclusion. For example, a composition, process, method, article, or apparatus that comprises the listed elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, process, method, article, or apparatus.

[0044] The conjunction "consisting of" excludes any unspecified element, step, or component. If used in a claim, this phrase renders the claim closed, excluding materials other than those described, except for conventional impurities associated therewith. When the phrase "consisting of" appears in a clause of the body of a claim, rather than immediately following the subject matter, it limits only the elements described in that clause; other elements are not excluded from the claim as a whole.

[0045] When an amount, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper preferred values ​​and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pairing of any range upper limit or preferred value with any range lower limit or preferred value, regardless of whether the range is disclosed alone. For example, when a range of "1 to 5" is disclosed, the described range should be interpreted as including the range "1 to 4", "1 to 3", "1 to 2", "1 to 2 and 4 to 5", "1 to 3 and 5", etc. When a numerical range is described herein, unless otherwise stated, the range is intended to include its end values ​​and all integers and fractions within the range.

[0046] In these examples, parts and percentages are by mass unless otherwise indicated.

[0047] "Parts by mass" refers to the basic unit of measurement used to express the mass ratio of multiple components. One part can represent any unit of mass, such as 1g or 2.689g. If we say that the mass of component A is a parts and the mass of component B is b parts, this means the ratio of the mass of component A to the mass of component B is a:b. Alternatively, we could say that the mass of component A is aK and the mass of component B is bK (K is an arbitrary number representing a multiplication factor). It's important to note that, unlike parts by mass, the sum of the mass of all components is not limited to 100 parts.

[0048] "And / or" is used to indicate that one or both of the stated situations may occur, for example, A and / or B includes (A and B) and (A or B).

[0049] This application provides an in-situ SiN capping layer etching method, please refer to Figure 9 ,include:

[0050] S110: modifying the in-situ SiN capping layer using fluorocarbon plasma to form a polymer modified adhesion layer on the in-situ SiN capping layer.

[0051] The in-situ SiN capping layer is a high-crystalline quality SiN material layer grown at high temperature using Metal-organic Chemical Vapor Deposition (MOCVD). It can be used as a dielectric passivation layer for a variety of GaN-based heterostructure materials, mostly to reduce leakage and increase breakdown voltage. For InAlN materials, the growth of the in-situ SiN capping layer improves the epitaxial disadvantages of InAlN itself and also serves as a dielectric passivation layer.

[0052] The fluorocarbons include any one of CF4, CHF3, C2F6, C3F6, CH2F2, CH3F and C4F8.

[0053] Fluorocarbon plasma has strong chemical activity and can react with Si-N bonds at a certain depth in the in-situ SiN capping layer to generate Si-F bonds and CN bonds. A polymer-modified adhesion layer is formed on the in-situ SiN capping layer through fluorocarbon plasma modification. This polymer-modified adhesion layer forms an interface with the in-situ SiN capping layer and reacts, replacing Si-N bonds at a certain depth in the SiN surface layer with Si-F bonds and CN bonds.

[0054] S120: using Ar plasma bombardment to remove the polymer modified adhesion layer, forming a first etching cycle.

[0055] Ar plasma ionizes argon gas into positively charged ions. Applying a bias voltage at low pressure accelerates the ions, bombarding the polymer modified adhesion layer. Energy exchange between the high-energy inert gas ions and the atoms in the polymer modified adhesion layer removes the modified atoms. Low RF power Ar plasma physically bombards and removes the modified in-situ SiN capping layer, forming a closed etching cycle, the first etching cycle.

[0056] Because Ar is an inert gas, its plasma involves physical bombardment but virtually no chemical reaction, an effect not seen in gases used in conventional inductively coupled plasma etchers (ICP-RIE). The modified SiN surface forms Si-F compounds, which have lower bond energies than Si-N. Therefore, low-power physical bombardment can be used for removal, allowing for selective etching of the Si-F modifications.

[0057] The etching depth of Ar plasma is consistent with the modification depth of fluorocarbon plasma. The deeper the modification, the deeper the etching. The unmodified part is not etched, thus forming a self-limiting effect.

[0058] In the first etching cycle, the etching rate of the in-situ SiN capping layer needs to reach 0.1 to 0.5 nm / cycle. The rate can be adjusted according to the thickness of the in-situ SiN capping layer, and the surface morphology effect of the surface roughness after etching is ≤ the initial surface roughness of the in-situ SiN capping layer. The initial surface roughness of the in-situ SiN capping layer is about 0.5 nm.

[0059] S130: completing at least one or more first etching cycles.

[0060] The first etching cycle is continuously cycled to completely etch the in-situ SiN capping layer. The number of cycles can be one, two, three or any number of times until the in-situ SiN capping layer is completely etched.

[0061] The in-situ SiN capping layer etching method provided in the present application first uses a fluorocarbon plasma to modify the in-situ SiN capping layer, and then uses Ar plasma bombardment to remove it. Through a two-step continuous cyclic atomic layer etching process, the etching depth is precisely controlled, the surface morphology etching damage is reduced, and a smooth etched surface is obtained. The surface state, defect density, defect size and electrical performance loss of the GaN-based heterostructure after selective etching of the in-situ SiN capping layer are effectively reduced, the device ohmic electrode preparation process is optimized, and the in-situ SiN capping layer is more widely used in the field of GaN-based heterostructure device preparation.

[0062] Preferably, the ICP power of the fluorocarbon plasma is between 50 and 300 W, for example, it can be (50, 55, 60, 65, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290 or 300) W, and the RF power of the fluorocarbon plasma is between 0 and 50 W, for example, it can be (0, 2, 5, 10, 15, 20, 25, 30, 35, 40, 45 or 50) W.

[0063] Preferably, the ICP power of the Ar plasma is 0 W, and the RF power is 0 to 30 W, for example, (0, 1, 3, 5, 10, 12, 15, 18, 20, 23, 25, 27, 28 or 30) W.

[0064] Among them, ICP power determines the plasma activity. The higher the ICP power, the higher the ion activity, and the easier it is to produce chemical reactions. RF power determines the downward power of the plasma, determines the etching rate, and determines the intensity of physical bombardment.

[0065] This application also provides a method for preparing an ohmic contact electrode of an in-situ SiN capping GaN-based heterostructure device. Figure 10 ,include:

[0066] S100: using an in-situ SiN capping etching method to etch away the in-situ SiN capping layer of the ohmic contact electrode pattern to obtain an ohmic contact electrode region.

[0067] The GaN-based heterostructure includes any one of an AlGaN / GaN heterostructure, an InAlN / GaN heterostructure, an InAlN / AlN / GaN heterostructure and an InAlGaN / AlGaN / GaN heterostructure.

[0068] Specifically, an ohmic contact electrode pattern is defined on the epitaxial layer of the in-situ SiN capping layer GaN-based heterostructure device, and the in-situ SiN capping layer at the position of the ohmic contact electrode pattern is etched and removed using the above method to obtain an ohmic contact electrode region. The ohmic contact electrode region exposes the GaN-based heterostructure for forming an ohmic contact electrode. The ohmic contact electrode can be, for example, a source, a drain, etc.

[0069] S300: Vapor-depositing an ohmic contact metal in the ohmic contact electrode region to form an ohmic contact electrode.

[0070] By using the above-mentioned in-situ SiN capping layer etching method to prepare source and drain ohmic electrodes, the etching damage of the surface morphology of the in-situ SiN capping layer in a selected area can be reduced, a smooth etched surface can be obtained, and the surface state, defect density, defect size and electrical performance loss of the GaN-based heterostructure after the in-situ SiN capping layer is selectively etched can be effectively reduced. The device ohmic electrode preparation process is optimized, the resistance value of the obtained ohmic contact electrode is reduced, and the source and drain leakage current is reduced, allowing the in-situ SiN capping layer to be more widely used in the field of GaN-based heterostructure device preparation.

[0071] In a preferred embodiment, see Figure 11 After S100: etching away the in-situ SiN capping layer of the ohmic contact electrode pattern using an in-situ SiN capping etching method to obtain an ohmic contact electrode region, the method further includes:

[0072] S200: processing the surface of the GaN-based heterostructure exposed in the ohmic contact electrode region.

[0073] For details, please refer to Figure 12 , step S200 includes:

[0074] S210: Using O2 plasma to modify the surface of the GaN-based heterostructure exposed in the ohmic contact electrode region to form an oxide layer.

[0075] The surface layer of the GaN-based heterostructure is oxidized to form an oxide layer by O2 plasma modification, and the oxidation products include In2O3, Al2O3, etc. Preferably, the ICP power of the O2 plasma is 50-300W, for example, (50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, or 300)W; the RF power is 0-100W, for example, (0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, or 100)W.

[0076] S220: using BCl3 plasma bombardment to remove the oxide layer, forming a second etching cycle.

[0077] Then, the oxide layer is bombarded and removed using BCl3 plasma, and low-power BCl3 plasma is used to remove the oxide layer, thereby forming a closed etching cycle, the second etching cycle. Preferably, the ICP power of the BCl3 plasma is 0W, and the RF power is 0-30W, for example, (0, 2, 5, 10, 15, 16, 18, 20, 22, 25, 26, 28 or 30)W.

[0078] The main reason for choosing BCl3 for physical bombardment is that the properties of BCl3 itself are more sensitive to oxide etching, so using BCl3 can increase the selectivity of oxide layer etching.

[0079] The second etching cycle needs to achieve an etching rate of about 0.1 to 0.3 nm / cycle, which can be adjusted according to the height of the barrier layer, and the surface roughness after etching is less than the surface morphology effect of the initial surface roughness of InAlN, which is about 0.4 to 0.7 nm.

[0080] S230: completing at least one or more second etching cycles to achieve surface treatment of the GaN-based heterostructure.

[0081] The second etching cycle is repeated to make the surface of the GaN-based heterostructure have a thickness of 1 to 3 atomic layers (less than 1 nm). The second etching cycle can be performed once or multiple times.

[0082] This process only requires 1-5 cycles of etching to improve the surface morphology of the GaN-based heterostructure, reduce the defect state density, and contribute to lower source-drain leakage and improved electrical properties of the heterostructure. Furthermore, because the oxidation modification step of the GaN-based heterostructure surface is similar to the oxygen plasma treatment step (a conventional surface treatment method used in device manufacturing), after the GaN-based heterostructure surface is treated, the two-dimensional electron gas density and sheet-resistance (Rsh) of the sample can be improved, which helps the device achieve higher saturation output current and lower on-resistance.

[0083] The fluorocarbon and O2 modification depths of this application tend to saturate as the modification step duration increases, and the modification depth will not increase indefinitely. However, the Ar and BCl3 removal steps can both continuously increase the etching depth over time, making both etching techniques quasi-self-limiting. This quasi-self-limiting property allows both techniques to avoid the transport limitations, high coupling parameters, and damage front propagation limitations of continuous etching techniques, thereby achieving better etching results than traditional continuous dry etching.

[0084] The present application also provides an in-situ SiN capping layer GaN-based heterostructure device and a preparation method thereof. The preparation method of the in-situ SiN capping layer GaN-based heterostructure device uses the above-mentioned ohmic contact electrode preparation method of the in-situ SiN capping layer GaN-based heterostructure device to prepare an ohmic contact electrode.

[0085] This application takes the preparation method of the in-situ SiN capping layer InAlN / AlN / GaN heterostructure HEMTs device as an example to explain in detail the preparation process of the in-situ SiN capping layer GaN-based heterostructure device.

[0086] Figure 1 The epitaxial structure of the in-situ SiN capping InAlN / AlN / GaN heterostructure HEMT device shown in the figure is, from top to bottom, in-situ SiN capping layer / InAlN barrier layer / AlN layer / intrinsic GaN layer / buffer layer / substrate. The in-situ SiN capping layer can be 1 to 10 nm thick, the InAlN barrier layer has an In composition of approximately 0.17 and an Al composition of approximately 0.83; the InAlN layer can be 1 to 15 nm thick, and the AlN layer can be 0.5 to 1.5 nm thick. The substrate can be made of high-resistance Si, sapphire, GaN, or SiC.

[0087] Step 1: Figure 1 The epitaxial substrate shown is partitioned and isolated to obtain Figure 2 The epitaxial substrate shown will Figure 2 The epitaxial substrate shown was sequentially cleaned with acetone ultrasonic cleaning for 5 minutes, isopropanol ultrasonic cleaning for 10 minutes, rinsed with deionized water for 10 minutes, and dried with nitrogen to remove impurities on the sample surface.

[0088] Step 2: Perform the following steps on the cleaned epitaxial substrate sample: coating, pre-baking, photolithography, development, post-baking, etc. to define the ohmic contact electrode pattern of the source and drain, such as Figure 3 shown.

[0089] Step 3: Place the sample processed in step 2 in the transfer chamber of the ICP-RIE etching equipment, and etch away the in-situ SiN capping layer of the source and drain ohmic contact electrode patterns using a two-step continuous cycle atomic layer etching process based on CHF3 plasma modification and Ar plasma removal to obtain the ohmic contact electrode area, such as Figure 4 The etching schematic diagram of the in-situ SiN capping layer is shown in FIG. Figure 7 shown.

[0090] Step 4: The sample processed in step 3 is placed in the transfer chamber of the ICP-RIE etching equipment. The InAlN surface layer of the source and drain regions is etched away by a two-step continuous cycle atomic layer etching process based on low-power O2 ion modification and BCl3 plasma removal. The thickness is about 1-3 InAlN atomic layers (<1nm), and the InAlN surface treatment is achieved. Figure 4 As shown, the processing method of the InAlN surface layer in the source and drain regions is as follows Figure 8 shown.

[0091] Step 5: Place the sample processed in step 4 into the transfer chamber of the magnetron sputtering evaporation equipment, and evaporate the ohmic contact metal. The ohmic contact metal can be Ti / Al / Ti / Au to form an ohmic contact electrode. The ohmic contact electrode includes a source and a drain, such as Figure 5 shown.

[0092] Step 6: Immerse the sample, where the ohmic contact metal was deposited in Step 5, in a dimethyl sulfoxide solution and heat it in a 60-80°C water bath to achieve metal stripping. After stripping, rinse with isopropyl alcohol for 10 minutes, deionized water for 10 minutes, and then blow dry with nitrogen.

[0093] Step 7: After the metal stripping in step 6, the sample is thermally annealed in a N2 atmosphere. The annealing temperature is set between 800-900°C to obtain a better ohmic contact effect.

[0094] Step 8: Deposit gate metal to obtain a gate electrode. The gate metal can be Ni / Au, such as Figure 6 shown.

[0095] Step 9: Deposit test metal electrodes on the metal surfaces of the source, drain and gate to prepare the in-situ SiN capping layer InAlN / AlN / GaN heterostructure HEMTs device.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

[0097] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and to form distinct embodiments. For example, in the claims above, any of the claimed embodiments may be used in any combination. The information disclosed in this background section is intended solely to enhance understanding of the overall background of this application and should not be construed as an admission or any implication that such information constitutes prior art known to those skilled in the art.

Claims

1. A method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device, characterized in that: include: The in-situ SiN capping layer of the ohmic contact electrode pattern is etched away using an in-situ SiN capping layer etching method to obtain an ohmic contact electrode region; Vapor-depositing an ohmic contact metal in the ohmic contact electrode region to form an ohmic contact electrode; The in-situ SiN capping layer etching method comprises: Modifying the in-situ SiN capping layer using fluorocarbon plasma to form a polymer modified adhesion layer on the in-situ SiN capping layer; removing the polymer modified adhesion layer by bombarding with Ar plasma, thereby forming a first etching cycle; completing at least one or more of the first etching cycles; After etching away the in-situ SiN capping layer of the ohmic contact electrode pattern to obtain the ohmic contact electrode region, the method further includes: Modifying the surface of the GaN-based heterostructure exposed in the ohmic contact electrode region using O2 plasma to form an oxide layer; BCl3 plasma bombardment is used to remove the oxide layer, forming a second etching cycle; The second etching cycle is completed at least once or multiple times to achieve surface treatment of the GaN-based heterostructure.

2. The method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device according to claim 1, characterized in that: The etching rate of the first etching cycle is 0.1-0.5 nm / cycle.

3. The method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device according to claim 1, characterized in that: The ICP power of the fluorocarbon plasma is between 50 and 300 W, and the RF power is between 0 and 50 W; the ICP power of the Ar plasma is 0 W, and the RF power is 0 to 30 W.

4. The method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device according to claim 1, characterized in that: The fluorocarbon compound includes any one of CF4, CHF3, C2F6, C3F6, CH2F2, CH3F and C4F8.

5. The method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device according to claim 1, characterized in that: The ICP power of the O2 plasma is 50-300W, and the RF power is 0-100W; the ICP power of the BCl3 plasma is 0W, and the RF power is 0-30W.

6. The method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device according to claim 1, characterized in that: The thickness of the surface treatment of the GaN-based heterostructure is less than 1 nm.

7. The method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device according to claim 6, characterized in that: The thickness of the surface treatment of the GaN-based heterostructure is 1 to 3 atomic layers.

8. The method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device according to claim 1, characterized in that: The etching rate of the second etching cycle is 0.1-0.3 nm / cycle.

9. The method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device according to any one of claims 1 to 8, characterized in that: The GaN-based heterostructure includes any one of an AlGaN / GaN heterostructure, an InAlN / GaN heterostructure, an InAlN / AlN / GaN heterostructure and an InAlGaN / AlGaN / GaN heterostructure.

10. A method for preparing an in-situ SiN capping layer GaN-based heterostructure device, characterized in that: An ohmic contact electrode is prepared using the method for preparing an ohmic contact electrode of an in-situ SiN capping layer GaN-based heterostructure device according to any one of claims 1 to 9.

11. An in-situ SiN capping layer GaN-based heterostructure device, characterized in that: The device is prepared using the method for preparing an in-situ SiN capping layer GaN-based heterostructure device according to claim 10.

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