A time slot allocation processing method, device and storage medium

Abstract

The application discloses a time slot allocation processing method and device and a storage medium, and relates to the technical field of time slot allocation, and in particular relates to a method for determining the time delay of a time slot from one input port to another output port in a node device, a device for determining the time delay for time slot allocation of an end-to-end channel, and a device for receiving the time delay sent by each node device and allocating the time slot of the end-to-end channel according to the time delay.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a time slot allocation processing method, device, and storage medium. Background Technology

[0002] With the development of 5G and the increasing number of users in vertical industries, the demand for network slicing is increasing. The industry has conducted many beneficial explorations in Ethernet-based slicing isolation technologies. For example, the FlexE (Flex Ethernet) technology, led by the OIF (Optical Internet Forum), provides a slicing mechanism based on Ethernet physical interfaces, offering effective interface-level isolation. However, FlexE is currently only an interface-level technology and cannot meet the networking requirements of operator networks. MTN (Metro Transport Network) is a new transport network technology system defined by the ITU-T (International Telecommunication Union Telecommunication Standardization Sector) for the needs of new services such as 5G. It can effectively integrate TDM (Time Division Multiplexing) and packet switching, and consists of a Section layer and a Path layer. The metropolitan area transport network (MAN) section layer supports time slot partitioning and port bonding, and is compatible with the underlying Ethernet protocol stack and standard Ethernet optical modules. The MAN path layer supports TDM switching based on 66B code blocks, has a complete end-to-end OAM (Operation Administration and Maintenance) mechanism, and supports cross-multiplexing of channelized customer signals of any Nx5G or smaller bandwidth granularity.

[0003] The shortcoming of the existing technology is that the current method of establishing end-to-end slice channels will lead to increased processing latency within the node due to the time slot allocation method. Summary of the Invention

[0004] This invention provides a time slot allocation processing method, device, and storage medium to solve the problem that the time slot allocation method can lead to increased processing latency within a node.

[0005] This invention provides the following technical solutions:

[0006] A time slot allocation processing method, comprising:

[0007] The node device determines the time delay from one input port time slot to another port time slot within the node device, wherein the node device is a node device on an end-to-end channel;

[0008] The node device determines this delay for allocating time slots to establish end-to-end channels.

[0009] During implementation, the node device determines this delay for allocating time slots to establish end-to-end channel connections, including:

[0010] The node device sends the delay to the centralized system; and / or,

[0011] After determining the available time slot for its own node based on the time slot with the optimal latency, the node device sends it to the next node device on the channel.

[0012] In practice, the delay determined by the node device is determined spontaneously by the node device; and / or,

[0013] The node device determines the delay after receiving the delay determination request.

[0014] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0015] In practice, the node device determines the internal delay from one input port time slot to another port time slot. This is done after the node device determines the internal delay from one input port time slot A (p) to another output port time slot B (q), and then determines the delay values ​​between other time slots.

[0016] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0017] During implementation, it further includes:

[0018] The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0019] After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel.

[0020] A time slot allocation processing method, comprising:

[0021] The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0022] After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel; where:

[0023] The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation.

[0024] In practice, the delay determined by the node device is determined spontaneously by the node device; and / or,

[0025] The node device determines the delay after receiving the delay determination request.

[0026] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0027] In practice, the node device determines the internal delay from one input port time slot to another port time slot. This is done after the node device determines the internal delay from one input port time slot A (p) to another output port time slot B (q), and then determines the delay values ​​between other time slots.

[0028] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0029] A time slot allocation processing method, comprising:

[0030] The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0031] After determining the available time slots for this node device based on the time slot with optimal latency, end-to-end channel time slot allocation is performed according to the available time slots for each node device; where:

[0032] The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation.

[0033] In practice, the delay determined by the node device is determined spontaneously by the node device; and / or,

[0034] The node device determines the delay after receiving the delay determination request.

[0035] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0036] In practice, the node device determines the internal delay from one input port time slot to another port time slot. This is done after the node device determines the internal delay from one input port time slot A (p) to another output port time slot B (q), and then determines the delay values ​​between other time slots.

[0037] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0038] A time slot allocation processing method, comprising:

[0039] Receive the delay sent by each node device. The delay is the delay within the node device from determining a time slot at one input port to another time slot. The node device is a node device on an end-to-end channel. The delay is used to establish the time slot allocation for the end-to-end channel.

[0040] End-to-end channel time slot allocation is performed based on each delay.

[0041] In practice, the delay determined by the node device is determined spontaneously by the node device; and / or,

[0042] The node device determines the delay after receiving the delay determination request.

[0043] During implementation, it further includes:

[0044] After determining the node device path through which an end-to-end channel passes, the delay determination request is sent to the node devices on the node device path.

[0045] In implementation, end-to-end channel time slot allocation is performed based on this delay information, including:

[0046] Starting from the source node device and moving towards the destination node device, the time slot with the optimal latency for each node device is selected as the available time slot, and time slots are allocated based on the determined available time slots.

[0047] A node device, comprising:

[0048] The processor is used to read programs from memory and execute the following procedures:

[0049] Determine the time delay within a node device from one input port timeslot to another, where the node device is a node device on an end-to-end channel;

[0050] This delay is determined for the allocation of time slots to establish end-to-end channel connections;

[0051] A transceiver is used to receive and send data under the control of a processor.

[0052] In implementation, the time delay is determined for establishing end-to-end channel time slot allocation, including:

[0053] Send the delay to the centralized system; and / or,

[0054] After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel.

[0055] In practice, the time delay is determined spontaneously by the node devices; and / or,

[0056] The determination delay is determined by the node device after receiving the determination delay request.

[0057] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0058] In practice, determining the time delay from one input port time slot to another port time slot within the node device involves the node device determining the internal time delay from one input port time slot A (p) to another output port time slot B (q), and then determining the time delay values ​​between other time slots.

[0059] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0060] During implementation, it further includes:

[0061] The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0062] After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel.

[0063] A node device, comprising:

[0064] The first determining module is used to determine the time delay from one input port time slot to another port time slot within the node device, wherein the node device is a node device on an end-to-end channel;

[0065] The first transmitting module is used to determine the delay for establishing end-to-end channel time slot allocation.

[0066] In implementation, the first sending module is further used to send the delay to the centralized system; and / or,

[0067] After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel.

[0068] In practice, the first determining module is further used to spontaneously determine the delay; and / or, to determine the delay after receiving a delay determination request.

[0069] In practice, the first sending module is further used to receive the delay determination request sent by the centralized system to the node devices on the node device path after determining the node device path through which an end-to-end channel passes.

[0070] In practice, the first determining module is further used to determine the delay values ​​between other time slots after determining the delay between a certain input port time slot A and another port time slot within the node device, and after determining the delay between a certain input port time slot A and another output port time slot B.

[0071] In practice, the first determining module is further used to determine the time delay values ​​between other time slots based on the time slot frame structure and the pre-acquired node time delay change model.

[0072] In practice, the first sending module is further used to receive the available time slot determined by the previous node device on the channel based on the time slot with the optimal delay; after determining the available time slot of this node device based on the time slot with the optimal delay, it sends it to the next node device on the channel.

[0073] A node device, comprising:

[0074] The processor is used to read programs from memory and execute the following procedures:

[0075] The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0076] After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel; where:

[0077] The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation.

[0078] A transceiver is used to receive and send data under the control of a processor.

[0079] In practice, the time delay is determined spontaneously by the node devices; and / or,

[0080] The determination delay is determined by the node device after receiving the determination delay request.

[0081] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0082] In practice, determining the time delay from one input port time slot to another port time slot within the node device involves the node device determining the internal time delay from one input port time slot A (p) to another output port time slot B (q), and then determining the time delay values ​​between other time slots.

[0083] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0084] A node device, comprising:

[0085] The first receiving module is used to receive the available time slot determined by the previous node device on the channel based on the time slot with optimal latency;

[0086] The second sending module is used to determine the available time slot of the current node device based on the time slot with the optimal latency, and then send it to the next node device on the channel.

[0087] Among them: the delay for determining available time slots is the delay within the node device for each node device to determine a time slot for one input port to another. The node device is the node device on the end-to-end channel, and the delay is used to establish the time slot allocation for the end-to-end channel.

[0088] In practice, the second sending module is further used to spontaneously determine the delay; and / or, to determine the delay after receiving a delay determination request.

[0089] In practice, the second sending module is further used to receive the delay determination request sent by the centralized system to the node devices on the node device path after determining the node device path through which an end-to-end channel passes.

[0090] In practice, the second sending module is further used to determine the delay values ​​between other time slots after determining the internal delay of the node device from one input port time slot p A to another output port time slot q B when determining the delay of the node device from one input port time slot p A to another output port time slot q B.

[0091] In practice, the second sending module is further used to determine the time delay values ​​between other time slots based on the time slot frame structure and the pre-acquired node time delay change model.

[0092] A node device, comprising:

[0093] The processor is used to read programs from memory and execute the following procedures:

[0094] The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0095] After determining the available time slots for this node device based on the time slot with optimal latency, end-to-end channel time slot allocation is performed according to the available time slots for each node device; where:

[0096] The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation.

[0097] A transceiver is used to receive and send data under the control of a processor.

[0098] In practice, the time delay is determined spontaneously by the node devices; and / or,

[0099] The determination delay is determined by the node device after receiving the determination delay request.

[0100] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0101] In practice, determining the time delay from one input port time slot to another port time slot within the node device involves the node device determining the internal time delay from one input port time slot A (p) to another output port time slot B (q), and then determining the time delay values ​​between other time slots.

[0102] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0103] A node device, comprising:

[0104] The second receiving module is used to receive the available time slot determined by the previous node device on the channel based on the time slot with optimal latency;

[0105] The first allocation module is used to determine the available time slots for the local node device based on the time slot with optimal latency, and then perform end-to-end channel time slot allocation based on the available time slots for each node device; wherein:

[0106] The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation.

[0107] In practice, the first allocation module is further used to spontaneously determine the delay; and / or, to determine the delay after receiving a delay determination request.

[0108] In practice, the first allocation module is further used to receive the delay determination request sent by the centralized system to the node devices on the node device path after determining the node device path through which an end-to-end channel passes.

[0109] In practice, the first allocation module is further used to determine the delay values ​​between other time slots after determining the internal delay of the node device from one input port time slot p A to another output port time slot q B when determining the delay of the node device from one input port time slot p A to another output port time slot q B.

[0110] In practice, the first allocation module is further used to determine the time delay values ​​between other time slots based on the time slot frame structure and the pre-acquired node time delay change model.

[0111] A centralized system, comprising:

[0112] The processor is used to read programs from memory and execute the following procedures:

[0113] Receive the delay sent by each node device. The delay is the delay within the node device from determining a time slot at one input port to another time slot. The node device is a node device on an end-to-end channel. The delay is used to establish the time slot allocation for the end-to-end channel.

[0114] End-to-end channel time slot allocation is performed based on each delay;

[0115] A transceiver is used to receive and send data under the control of a processor.

[0116] In practice, the time delay is determined spontaneously by the node devices; and / or,

[0117] The determination delay is determined by the node device after receiving the determination delay request.

[0118] During implementation, it further includes:

[0119] After determining the node device path through which an end-to-end channel passes, the delay determination request is sent to the node devices on the node device path.

[0120] In implementation, end-to-end channel time slot allocation is performed based on this delay information, including:

[0121] Starting from the source node device and moving towards the destination node device, the time slot with the optimal latency for each node device is selected as the available time slot, and time slots are allocated based on the determined available time slots.

[0122] A centralized system, comprising:

[0123] The third receiving module is used to receive the delay sent by each node device. The delay is the delay within the node device from determining a certain input port time slot to another port time slot. The node device is a node device on an end-to-end channel. The delay is used to establish the end-to-end channel time slot allocation.

[0124] The second allocation module is used to allocate channel time slots end-to-end based on each delay.

[0125] In practice, the third receiving module is further used to receive the delay spontaneously determined by the node device; and / or the delay determined by the node device after receiving the delay determination request.

[0126] In practice, the third receiving module is further used to receive the delay determination request sent to the node devices on the node device path after determining the node device path through which an end-to-end channel passes.

[0127] In practice, the second allocation module is further used to determine the available time slots for each node device in the direction from the source node device to the destination node device when allocating end-to-end channel time slots based on the delay information, and then allocate time slots based on the determined available time slots.

[0128] A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program that performs the above-described time slot allocation processing method.

[0129] The beneficial effects of this invention are as follows:

[0130] In the technical solution provided in the embodiments of the present invention, the node device determines the intra-node delay from one input port time slot to another port time slot. Since this delay information is taken into consideration as the input condition for establishing end-to-end channel time slot allocation when allocating time slots, the delay caused by time slot allocation in a channel can be reduced, thereby reducing end-to-end channel delay. Attached Figure Description

[0131] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0132] Figure 1 This is a schematic diagram of time slot allocation for the end-to-end channel in an embodiment of the present invention;

[0133] Figure 2 This is a schematic diagram illustrating the impact of time slot selection on node delay in an embodiment of the present invention;

[0134] Figure 3This is a schematic diagram illustrating the implementation process of the time slot allocation method in an embodiment of the present invention;

[0135] Figure 4 This is a schematic diagram of channel path establishment in an embodiment of the present invention;

[0136] Figure 5 This is a schematic diagram illustrating the implementation process of the time slot allocation processing method on the centralized system in an embodiment of the present invention;

[0137] Figure 6 This is a schematic diagram illustrating the implementation process of the time slot allocation method on the intermediate node device side in an embodiment of the present invention;

[0138] Figure 7 This is a schematic diagram illustrating the implementation process of the time slot allocation method on the destination node device side in this embodiment of the invention;

[0139] Figure 8 This is a schematic diagram illustrating the process of sequentially determining the optimal time slot in an embodiment of the present invention;

[0140] Figure 9 This is a schematic diagram of the node device structure in an embodiment of the present invention;

[0141] Figure 10 This is a schematic diagram of the second node device structure in an embodiment of the present invention;

[0142] Figure 11 This is a schematic diagram of the node device structure in an embodiment of the present invention;

[0143] Figure 12 This is a schematic diagram of the centralized system structure in an embodiment of the present invention. Detailed Implementation

[0144] The inventor noticed the following during the invention process:

[0145] To establish an end-to-end channel, such as from source node NE1 to destination node NEn, the port slots of each node need to be configured, as shown in the figure below. For example, if the end-to-end channel requires 10Mbps bandwidth, and the minimum bandwidth granularity of each slot is 10Mbps, then one slot needs to be configured for each node. Figure 1 The diagram illustrates the time slot allocation for an end-to-end channel. NE1 is configured to use the m-th time slot (time slot m), NE2 to use the n-th time slot (time slot n), and NE3 to use the q-th time slot (time slot q). An end-to-end time slot channel can only be established when time slots for each node in the end-to-end channel are allocated correctly.

[0146] In existing technologies, time slot allocation is completed in one step. The allocation of time slots for each node in a channel mainly considers availability, and the required number of time slots can be allocated from the available time slot resources of each node port.

[0147] However, as the time slot bandwidth decreases, the processing latency within the node increases accordingly. Node processing latency becomes a crucial factor to consider. How to reduce processing latency is a key question. A significant portion of this latency is related to time slot allocation. Figure 2 A diagram illustrating the impact of time slot selection on node delay, for example. Figure 2 As shown, assuming a 10M slice granularity time slot structure using SPN (Slicing Packet Network), there are 480 time slots to choose from within a 5G calendar slot. Whether the first, last, or any other time slot is selected significantly impacts node latency. If an incoming time slot channel completes its cross-connection within the node and then needs to send data out, and it happens to align with the first of the 480 time slots, and the selected outgoing time slot is also the first, then the latency is minimized. However, if the outgoing data aligns with the first of the 480 time slots, but the selected outgoing time slot is the last of the 480 time slots, then the node must wait until the last time slot to fill the slot before sending, resulting in a longer latency.

[0148] Based on this, this embodiment of the invention proposes a new end-to-end channel establishment time slot allocation scheme, which can optimize the latency caused by time slot allocation in a single channel and meet technical and application requirements.

[0149] The specific embodiments of the present invention will now be described with reference to the accompanying drawings.

[0150] In this explanation, the implementation of the end-to-end channel will be described from the perspectives of the source node devices, intermediate node devices, destination node devices, and the centralized system (e.g., a control system). Examples of their coordinated implementation will then be provided to better understand the implementation of the solutions presented in this embodiment. This explanation does not imply that they must be implemented in conjunction or individually. In fact, when implemented separately, each addresses its own problem, while combining them yields better technical results.

[0151] In this embodiment of the invention, two schemes are provided for time slot allocation: one is allocation by a centralized system, and the other is allocation by individual node devices. The implementation of determining the time delay and transmission delay by the node devices will be... Figure 3 The explanation will be provided in the section on centralized system allocation schemes. Figure 5 The explanation will be provided in the section on the scheme allocated by each node device. Figure 6 (Intermediate node device) Figure 7 The explanation will be provided in the section on (host node devices).

[0152] Figure 3 The flowchart of the time slot allocation process is shown in the figure, and may include:

[0153] Step 301: The node device determines the time delay from one input port time slot to another port time slot within the node device. The node device is a node device on an end-to-end channel.

[0154] Step 302: The node device determines the delay to be used for the allocation of time slots for establishing end-to-end channel connections.

[0155] During implementation, the node device determines this delay for allocating time slots to establish end-to-end channel connections, including:

[0156] The node device sends the delay to the centralized system; and / or,

[0157] After determining the available time slot for its own node based on the time slot with the optimal latency, the node device sends it to the next node device on the channel.

[0158] In practice, the node device determines the intra-node delay from one input port time slot to another port time slot, and uses this delay information as the input condition for establishing end-to-end channel time slot allocation.

[0159] Specifically, when a node device detects a specific flag in a certain time slot at the inlet, it records a timestamp. When it reaches a flag in a certain time slot at the outlet, it records another timestamp. By subtracting the two timestamp values, the time delay from one time slot at the input port to another time slot at the output port can be obtained.

[0160] In practice, the delay determined by the node device is determined spontaneously by the node device; and / or,

[0161] The node device determines the delay after receiving the delay determination request.

[0162] Specifically, the node device determines the latency either spontaneously or by accepting a request.

[0163] Node devices can determine the intra-node latency from one input port timeslot to another (e.g., during device startup), or the node device can determine the intra-node latency from one input port timeslot to another only when it receives a request.

[0164] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0165] Specifically, after the centralized system determines a channel path, it requests the intra-node delay from the input port time slot to the output port time slot of the corresponding ports of these nodes on the determined path.

[0166] Figure 4 A schematic diagram of the channel path is shown in the figure. The request can be received as follows: After the centralized system (such as the management system) determines that an end-to-end channel with a certain bandwidth from node m to another node n needs to be established, the centralized system calculates and determines a path from node m to node n based on network information (such as network topology, available time slot resources of nodes, etc.), including intermediate node information, the ingress port and egress port of each node. At this time, it requests the intra-node delay from the input port time slot to the output port time slot of the corresponding ports of these nodes on the determined path.

[0167] The node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q), and then determines the delay values ​​between other time slots.

[0168] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0169] Specifically, after determining the intra-node delay from one input port p time slot A to another output port q time slot B, the node device calculates the delay values ​​between other time slots based on the time slot frame structure and the pre-acquired node delay change model.

[0170] Once a node device determines the intra-node delay from a certain input port p time slot A to another output port q time slot B, it does not need to test and determine the intra-node delay from other time slots of port p (e.g., time slot C) to other time slots of port q (e.g., time slot D). Instead, it can calculate the delay value from input port p time slot A to output port q time slot B based on the time slot frame structure and the pre-acquired node delay variation model.

[0171] The following will explain each point separately.

[0172] 1. Time slot allocation is performed by a centralized system.

[0173] Figure 5 The flowchart of the time slot allocation processing method on the centralized system is shown in the figure, and it may include:

[0174] Step 501: Receive the delay sent by each node device. The delay is the delay within the node device from determining a certain input port time slot to another port time slot. The node device is a node device on an end-to-end channel. The delay is used to establish the end-to-end channel time slot allocation.

[0175] Step 502: Allocate channel time slots end-to-end based on each delay.

[0176] In practice, the delay determined by the node device is determined spontaneously by the node device; and / or,

[0177] The node device determines the delay after receiving the delay determination request.

[0178] In practice, it may further include:

[0179] After determining the node device path through which an end-to-end channel passes, the delay determination request is sent to the node devices on the node device path.

[0180] In implementation, end-to-end channel time slot allocation is performed based on this delay information, including:

[0181] Starting from the source node device and moving towards the destination node device, the time slot with the optimal latency for each node device is selected as the available time slot, and time slots are allocated based on the determined available time slots.

[0182] Optimal latency is not necessarily the minimum latency. Minimum latency is one possibility, and other strategies are also possible. The optimal allocation of available time slots for each node can be the time slot with the minimum latency, or it can be the time slot with the second-lowest latency, chosen while tolerating a certain amount of jitter. This is because if the time slot with the minimum latency experiences jitter and its phase changes slightly ahead, the output might not be able to keep up with the current time slot, requiring it to wait until the next time slot, which could actually increase the latency significantly.

[0183] Specifically, after a node device determines the intra-node delay from one input port time slot A to another port time slot B, it reports this to the centralized system. The centralized system, having obtained all delay information along this path, sequentially determines the optimal available time slot allocation for each node, starting from the source node and proceeding to the destination node. After determining the time slots, the centralized system allocates the time slots and establishes the channel.

[0184] Second, time slots are allocated by each node device.

[0185] In the absence of a centralized system or where a centralized system is not required, time slot allocation can be determined by each node and then sent to the next node via a message, thereby sequentially determining and selecting the available time slot allocation with the optimal latency for each node.

[0186] Figure 6 The flowchart illustrating the time slot allocation process for intermediate node devices is shown in the figure, and may include:

[0187] Step 601: The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0188] Step 602: After determining the available time slots for this node device based on the time slot with the optimal latency, send it to the next node device on the channel;

[0189] Among them: the delay for determining available time slots is the delay within the node device for each node device to determine a time slot for one input port to another. The node device is the node device on the end-to-end channel, and the delay is used to establish the time slot allocation for the end-to-end channel.

[0190] Figure 7 The flowchart of the time slot allocation process on the destination node device side is shown in the figure, and may include:

[0191] Step 701: The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0192] Step 702: After determining the available time slots of this node device based on the time slot with the optimal latency, perform end-to-end channel time slot allocation based on the available time slots of each node device;

[0193] Among them: the delay for determining available time slots is the delay within the node device for each node device to determine a time slot for one input port to another. The node device is the node device on the end-to-end channel, and the delay is used to establish the time slot allocation for the end-to-end channel.

[0194] Figure 8 The diagram illustrates the process of sequentially determining the optimal time slot. In the above time slot allocation process, each node allocates the available time slot with the optimal delay. This optimal delay could be the time slot with the highest delay, or it could be the time slot with the second lowest delay, chosen while tolerating a certain amount of jitter. Because if jitter occurs in the optimal time slot, causing a phase shift that occurs slightly ahead, the output might not be able to keep up with the current time slot. In this case, it would have to wait for a round before being placed in the next time slot, resulting in a relatively large delay.

[0195] For bidirectional channels, the above process can be performed independently in each direction, and the time slots used can be determined separately.

[0196] Based on the same inventive concept, this invention also provides a node device, a centralized system, and a computer-readable storage medium. Since the principle of these devices in solving the problem is similar to the time slot allocation processing method on the node device and the centralized system, the implementation of these devices can refer to the implementation of the method, and the repeated parts will not be described again.

[0197] When implementing the technical solutions provided in the embodiments of the present invention, they can be implemented in the following manner.

[0198] Figure 9 This is a schematic diagram of a node device structure. As shown in the figure, the node device includes:

[0199] Processor 900 is used to read the program from memory 920 and execute the following procedures:

[0200] Determine the time delay within a node device from one input port timeslot to another, where the node device is a node device on an end-to-end channel;

[0201] This delay is determined for the allocation of time slots to establish end-to-end channel connections;

[0202] Transceiver 910 is used to receive and send data under the control of processor 900.

[0203] In implementation, the time delay is determined for establishing end-to-end channel time slot allocation, including:

[0204] Send the delay to the centralized system; and / or,

[0205] After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel.

[0206] In practice, the time delay is determined spontaneously by the node devices; and / or,

[0207] The determination delay is determined by the node device after receiving the determination delay request.

[0208] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0209] In practice, determining the time delay from one input port time slot to another port time slot within the node device involves the node device determining the internal time delay from one input port time slot A (p) to another output port time slot B (q), and then determining the time delay values ​​between other time slots.

[0210] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0211] During implementation, it further includes:

[0212] The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0213] After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel.

[0214] Among them, Figure 9 In this context, the bus architecture can include any number of interconnected buses and bridges, specifically linking various circuits together, represented by one or more processors (processor 900) and memory (memory 920). The bus architecture can also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface. The transceiver 910 can be multiple elements, including transmitters and receivers, providing a unit for communicating with various other devices over a transmission medium. The processor 900 is responsible for managing the bus architecture and general processing, and the memory 920 can store data used by the processor 900 during operation.

[0215] This invention also provides a node device, comprising:

[0216] The first determining module is used to determine the time delay from one input port time slot to another port time slot within the node device, wherein the node device is a node device on an end-to-end channel;

[0217] The first transmitting module is used to determine the delay for establishing end-to-end channel time slot allocation.

[0218] In practice, the first sending module is further used to send the delay to the centralized system; and / or, after determining the available time slot of the node device based on the time slot with the optimal delay, send it to the next node device on the channel.

[0219] In practice, the first determining module is further used to spontaneously determine the delay; and / or, to determine the delay after receiving a delay determination request.

[0220] In practice, the first sending module is further used to receive the delay determination request sent by the centralized system to the node devices on the node device path after determining the node device path through which an end-to-end channel passes.

[0221] In practice, the first determining module is further used to determine the delay values ​​between other time slots after determining the delay between a certain input port time slot A and another port time slot within the node device, and after determining the delay between a certain input port time slot A and another output port time slot B.

[0222] In practice, the first determining module is further used to determine the time delay values ​​between other time slots based on the time slot frame structure and the pre-acquired node time delay change model.

[0223] In practice, the first sending module is further used to receive the available time slot determined by the previous node device on the channel based on the time slot with the optimal delay; after determining the available time slot of this node device based on the time slot with the optimal delay, it sends it to the next node device on the channel.

[0224] For ease of description, the various parts of the device described above are divided into modules or units according to their functions. Of course, in implementing this invention, the functions of each module or unit can be implemented in one or more software or hardware components.

[0225] Figure 10 This is a schematic diagram of node device structure two. As shown in the figure, the node device includes:

[0226] Processor 1000 is used to read the program from memory 1020 and execute the following procedures:

[0227] The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0228] After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel; where:

[0229] The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation.

[0230] Transceiver 1010 is used to receive and send data under the control of processor 1000.

[0231] In practice, the time delay is determined spontaneously by the node devices; and / or,

[0232] The determination delay is determined by the node device after receiving the determination delay request.

[0233] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0234] In practice, determining the time delay from one input port time slot to another port time slot within the node device involves the node device determining the internal time delay from one input port time slot A (p) to another output port time slot B (q), and then determining the time delay values ​​between other time slots.

[0235] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0236] Among them, Figure 10 In this context, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits together, represented by one or more processors (processor 1000) and memory (memory 1020). The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface. The transceiver 1010 may be multiple elements, including a transmitter and a receiver, providing a unit for communicating with various other devices over a transmission medium. The processor 1000 is responsible for managing the bus architecture and general processing, and the memory 1020 may store data used by the processor 1000 during operation.

[0237] This invention also provides a node device, comprising:

[0238] The first receiving module is used to receive the available time slot determined by the previous node device on the channel based on the time slot with optimal latency;

[0239] The second sending module is used to determine the available time slot of the current node device based on the time slot with the optimal latency, and then send it to the next node device on the channel.

[0240] Among them: the delay for determining available time slots is the delay within the node device for each node device to determine a time slot for one input port to another. The node device is the node device on the end-to-end channel, and the delay is used to establish the time slot allocation for the end-to-end channel.

[0241] In practice, the second sending module is further used to spontaneously determine the delay; and / or, to determine the delay after receiving a delay determination request.

[0242] In practice, the second sending module is further used to receive the delay determination request sent by the centralized system to the node devices on the node device path after determining the node device path through which an end-to-end channel passes.

[0243] In practice, the second sending module is further used to determine the delay values ​​between other time slots after determining the internal delay of the node device from one input port time slot p A to another output port time slot q B when determining the delay of the node device from one input port time slot p A to another output port time slot q B.

[0244] In practice, the second sending module is further used to determine the time delay values ​​between other time slots based on the time slot frame structure and the pre-acquired node time delay change model.

[0245] For ease of description, the various parts of the device described above are divided into modules or units according to their functions. Of course, in implementing this invention, the functions of each module or unit can be implemented in one or more software or hardware components.

[0246] Figure 11 This is a schematic diagram of the node device structure. As shown in the figure, the node device includes:

[0247] Processor 1100 is used to read the program from memory 1120 and execute the following procedures:

[0248] The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay.

[0249] After determining the available time slots for this node device based on the time slot with optimal latency, end-to-end channel time slot allocation is performed according to the available time slots for each node device; where:

[0250] The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation.

[0251] Transceiver 1110 is used to receive and send data under the control of processor 1100.

[0252] In practice, the time delay is determined spontaneously by the node devices; and / or,

[0253] The determination delay is determined by the node device after receiving the determination delay request.

[0254] In practice, the delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

[0255] In practice, determining the time delay from one input port time slot to another port time slot within the node device involves the node device determining the internal time delay from one input port time slot A (p) to another output port time slot B (q), and then determining the time delay values ​​between other time slots.

[0256] In practice, the time delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node time delay variation model.

[0257] Among them, Figure 11 In this context, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits together, represented by one or more processors (processor 1100) and memory (memory 1120). The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface. The transceiver 1110 may be multiple elements, including transmitters and receivers, providing a unit for communicating with various other devices over a transmission medium. The processor 1100 is responsible for managing the bus architecture and general processing, and the memory 1120 may store data used by the processor 1100 during operation.

[0258] This invention also provides a node device, comprising:

[0259] The second receiving module is used to receive the available time slot determined by the previous node device on the channel based on the time slot with optimal latency;

[0260] The first allocation module is used to determine the available time slots for the local node device based on the time slot with optimal latency, and then perform end-to-end channel time slot allocation based on the available time slots for each node device; wherein:

[0261] The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation.

[0262] In practice, the first allocation module is further used to spontaneously determine the delay; and / or, to determine the delay after receiving a delay determination request.

[0263] In practice, the first allocation module is further used to receive the delay determination request sent by the centralized system to the node devices on the node device path after determining the node device path through which an end-to-end channel passes.

[0264] In practice, the first allocation module is further used to determine the delay between one input port time slot and another port time slot within the node device when determining the delay within the node device from one input port time slot p A to another output port time slot q B. Then, based on the time slot frame structure and the pre-acquired node delay change model, the node device determines the delay values ​​between other time slots.

[0265] In practice, the first allocation module is further used to determine the time delay values ​​between other time slots based on the time slot frame structure and the pre-acquired node time delay change model.

[0266] For ease of description, the various parts of the device described above are divided into modules or units according to their functions. Of course, in implementing this invention, the functions of each module or unit can be implemented in one or more software or hardware components.

[0267] Figure 12 The diagram shows a centralized system architecture. The centralized system includes:

[0268] Processor 1200 is used to read the program from memory 1220 and execute the following procedures:

[0269] Receive the delay sent by each node device. The delay is the delay within the node device from determining a time slot at one input port to another time slot. The node device is a node device on an end-to-end channel. The delay is used to establish the time slot allocation for the end-to-end channel.

[0270] End-to-end channel time slot allocation is performed based on each delay;

[0271] Transceiver 1210 is used to receive and send data under the control of processor 1200.

[0272] In practice, the time delay is determined spontaneously by the node devices; and / or,

[0273] The determination delay is determined by the node device after receiving the determination delay request.

[0274] During implementation, it further includes:

[0275] After determining the node device path through which an end-to-end channel passes, the delay determination request is sent to the node devices on the node device path.

[0276] In implementation, end-to-end channel time slot allocation is performed based on this delay information, including:

[0277] Starting from the source node device and moving towards the destination node device, the time slot with the optimal latency for each node device is selected as the available time slot, and time slots are allocated based on the determined available time slots.

[0278] Among them, Figure 12In this context, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits together, represented by one or more processors (processor 1200) and memory (memory 1220). The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides an interface. Transceiver 1210 may be multiple elements, including transmitters and receivers, providing a unit for communicating with various other devices over a transmission medium. Processor 1200 is responsible for managing the bus architecture and general processing, and memory 1220 may store data used by processor 1200 during operation.

[0279] This invention also provides a centralized system, comprising:

[0280] The third receiving module is used to receive the delay sent by each node device. The delay is the delay within the node device from determining a certain input port time slot to another port time slot. The node device is a node device on an end-to-end channel. The delay is used to establish the end-to-end channel time slot allocation.

[0281] The second allocation module is used to allocate channel time slots end-to-end based on each delay.

[0282] In practice, the third receiving module is further used to receive the delay spontaneously determined by the node device; and / or the delay determined by the node device after receiving the delay determination request.

[0283] In practice, the third receiving module is further used to receive the delay determination request sent to the node devices on the node device path after determining the node device path through which an end-to-end channel passes.

[0284] In practice, the second allocation module is further used to determine the available time slots for each node device in the direction from the source node device to the destination node device when allocating end-to-end channel time slots based on the delay information, and then allocate time slots based on the determined available time slots.

[0285] For ease of description, the various parts of the device described above are divided into modules or units according to their functions. Of course, in implementing this invention, the functions of each module or unit can be implemented in one or more software or hardware components.

[0286] This invention also provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program that performs the above-described time slot allocation processing method.

[0287] For specific implementation details, please refer to the implementation of time slot allocation processing methods for one or a combination of node devices, intermediate node devices, destination node devices, and centralized systems.

[0288] In summary, in the technical solution provided by the embodiments of the present invention, the node device determines the intra-node delay from one input port time slot to another port time slot, and uses this delay information as an input condition for establishing end-to-end channel time slot allocation. Specifically, it also provides:

[0289] The node device determines the latency either spontaneously or upon receiving a request.

[0290] After the centralized system determines a channel path, it requests the intra-node delay from the input port time slot to the output port time slot of the corresponding ports of these nodes on the determined path.

[0291] After acquiring all latency information along the path, the centralized system sequentially determines the optimal available time slot allocation for each node, starting from the source node and proceeding to the destination node. Following the time slot allocation, the centralized system performs time slot allocation and establishes the channel.

[0292] Time slot allocation can also be determined by each node and then sent to the next node via a message, thereby sequentially determining the available time slot allocation with the optimal latency for each node.

[0293] For bidirectional channels, the above process is performed independently in each direction, and the time slots used are determined separately.

[0294] After determining the intra-node delay from one input port p time slot A to another output port q time slot B, the node device calculates the delay values ​​between other time slots based on the time slot frame structure and the pre-acquired node delay change model.

[0295] This solution proposes an effective end-to-end channel establishment scheme, including time slot allocation, which can optimize the latency caused by time slot allocation in a single channel and reduce end-to-end channel latency.

[0296] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0297] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0298] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0299] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0300] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A time slot assignment processing method characterized by comprising: include: The node device determines the time delay from one input port time slot to another port time slot within the node device, wherein the node device is a node device on an end-to-end channel; The node device determines this delay for allocating time slots to establish end-to-end channels; The node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A to another output port time slot B, and then determines the delay values ​​between other time slots. The delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node delay variation model.

2. The method of claim 1, wherein, The node device determines the time slot allocation used to establish end-to-end channel connections, including: The node device sends the delay to the centralized system; and / or, After determining the available time slot for its own node based on the time slot with the optimal latency, the node device sends it to the next node device on the channel.

3. The method of claim 1, wherein, The node device determines the latency spontaneously; and / or, The node device determines the delay after receiving the delay determination request.

4. The method as described in claim 3, characterized in that, The delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

5. The method according to any one of claims 1 to 4, characterized in that, Further includes: The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay. After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel.

6. A time slot assignment processing method characterized by comprising: include: The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay. After determining the available time slots for this node device based on the time slot with the optimal latency, it sends the information to the next node device on the channel. Specifically: the delay for determining available time slots refers to the delay within the node device determined by each node device from a time slot at a certain input port to a time slot at another port. The node device is the node device on the end-to-end channel. The delay is used to allocate time slots for establishing the end-to-end channel. The delay within the node device for determining a time slot from a time slot at a certain input port to a time slot at another port is determined by the node device after determining the internal delay from a time slot A at a certain input port p to a time slot B at another output port q. The delay values ​​between other time slots are determined based on the time slot frame structure and the pre-acquired node delay change model.

7. The method of claim 6, wherein, The node device determines the latency spontaneously; and / or, The node device determines the delay after receiving the delay determination request.

8. The method of claim 7, wherein, The delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

9. A time slot assignment processing method characterized by comprising: include: The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay. After determining the available time slots for this node device based on the time slot with optimal latency, end-to-end channel time slot allocation is performed according to the available time slots for each node device; where: The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation. The node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, it determines the delay values ​​between other time slots based on the time slot frame structure and the pre-acquired node delay variation model.

10. The method as described in claim 9, characterized in that, The node device determines the latency spontaneously; and / or, The node device determines the delay after receiving the delay determination request.

11. The method as described in claim 10, characterized in that, The delay determination request is sent by the centralized system to the node devices along the node device path after determining the node device path through which an end-to-end channel passes.

12. A time slot allocation processing method, characterized in that, include: Receive the delay sent by each node device. The delay is the delay within the node device from determining a time slot at one input port to another time slot. The node device is a node device on an end-to-end channel. The delay is used to establish the time slot allocation for the end-to-end channel. End-to-end channel time slot allocation is performed based on each delay; Specifically, the node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, the node device determines the delay values ​​between other time slots based on the time slot frame structure and a pre-acquired node delay variation model.

13. The method as described in claim 12, characterized in that, The node device determines the latency spontaneously; and / or, The node device determines the delay after receiving the delay determination request.

14. The method as described in claim 13, characterized in that, Further includes: After determining the node device path through which an end-to-end channel passes, the delay determination request is sent to the node devices on the node device path.

15. The method as described in claim 12, characterized in that, Based on this delay information, end-to-end channel time slot allocation is performed, including: Starting from the source node device and moving towards the destination node device, the time slot with the optimal latency for each node device is selected as the available time slot, and time slots are allocated based on the determined available time slots.

16. A node device, characterized in that, include: The processor is used to read programs from memory and execute the following procedures: Determine the time delay within a node device from one input port timeslot to another, where the node device is a node device on an end-to-end channel; This delay is determined for the allocation of time slots to establish end-to-end channel connections; A transceiver is used to receive and send data under the control of a processor; Specifically, the node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, the node device determines the delay values ​​between other time slots based on the time slot frame structure and a pre-acquired node delay variation model.

17. A node device, characterized in that, include: The first determining module is used to determine the time delay from one input port time slot to another port time slot within the node device, wherein the node device is a node device on an end-to-end channel; The first transmitting module is used to determine the delay for establishing end-to-end channel time slot allocation; Specifically, the node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, the node device determines the delay values ​​between other time slots based on the time slot frame structure and a pre-acquired node delay variation model.

18. A node device, characterized in that, include: The processor is used to read programs from memory and execute the following procedures: The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay. After determining the available time slots for this node device based on the time slot with optimal latency, it sends the information to the next node device on the channel; where: The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation. A transceiver is used to receive and send data under the control of a processor; Specifically, the node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, the node device determines the delay values ​​between other time slots based on the time slot frame structure and a pre-acquired node delay variation model.

19. A node device, characterized in that, include: The first receiving module is used to receive the available time slot determined by the previous node device on the channel based on the time slot with optimal latency; The second sending module is used to determine the available time slot of the current node device based on the time slot with the optimal latency, and then send it to the next node device on the channel. Among them: the delay for determining available time slots is the delay within the node device from determining a time slot at one input port to another. The node device is the node device on the end-to-end channel, and the delay is used to establish the time slot allocation for the end-to-end channel. Specifically, the node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, the node device determines the delay values ​​between other time slots based on the time slot frame structure and a pre-acquired node delay variation model.

20. A node device, characterized in that, include: The processor is used to read programs from memory and execute the following procedures: The available time slot is determined by the previous node device on the receiving channel based on the time slot with the optimal delay. After determining the available time slots for this node device based on the time slot with optimal latency, end-to-end channel time slot allocation is performed according to the available time slots for each node device; where: The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation. A transceiver is used to receive and send data under the control of a processor; Specifically, the node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, the node device determines the delay values ​​between other time slots based on the time slot frame structure and a pre-acquired node delay variation model.

21. A node device, characterized in that, include: The second receiving module is used to receive the available time slot determined by the previous node device on the channel based on the time slot with optimal latency; The first allocation module is used to determine the available time slots for the local node device based on the time slot with optimal latency, and then perform end-to-end channel time slot allocation based on the available time slots for each node device; wherein: The delay for determining available time slots is the delay within each node device for determining a time slot at one input port to another. Node devices are node devices on an end-to-end channel, and the delay is used to establish end-to-end channel time slot allocation. Specifically, the node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, the node device determines the delay values ​​between other time slots based on the time slot frame structure and a pre-acquired node delay variation model.

22. A centralized system, characterized in that, include: The processor is used to read programs from memory and execute the following procedures: Receive the delay sent by each node device. The delay is the delay within the node device from determining a time slot at one input port to another time slot. The node device is a node device on an end-to-end channel. The delay is used to establish the time slot allocation for the end-to-end channel. End-to-end channel time slot allocation is performed based on each delay; A transceiver is used to receive and send data under the control of a processor; Specifically, the node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, the node device determines the delay values ​​between other time slots based on the time slot frame structure and a pre-acquired node delay variation model.

23. A centralized system, characterized in that, include: The third receiving module is used to receive the delay sent by each node device. The delay is the delay within the node device from determining a certain input port time slot to another port time slot. The node device is a node device on an end-to-end channel. The delay is used to establish the end-to-end channel time slot allocation. The second allocation module is used to allocate channel time slots end-to-end based on each delay. Specifically, the node device determines the internal delay from one input port time slot to another port time slot by determining the internal delay from one input port time slot A (p) to another output port time slot B (q). Then, the node device determines the delay values ​​between other time slots based on the time slot frame structure and a pre-acquired node delay variation model.

24. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 15.

Images