Method and apparatus for systematic encoding of data in error correction coding using triangular decomposition of a generator matrix

Abstract

A system encoder 300 reliably transmits a source data block (SDB) 311, configured for an outer transform matrix U and an inner transform matrix L. The inner encoder 301 receives the SDB and generates an output constraint block (OCB) 312, which is an image of the SDB under the inverse of a submatrix of the inner transform matrix. The outer encoder 302 receives a fixed data block (FDB) 313 and the OCB, and generates a transform output block (TOB) 315, which is an image of a transform input block (TIB) 314 under the outer transform matrix. The TIB transparently contains the FDB in its subblocks, and the TOB transparently contains the OCB in its subblocks. The inner encoder receives the TOB and generates a transmitted code block (TCB), which transparently contains the SDB in its subblocks.

Description

Technical Field

[0001] The present invention generally relates to methods and apparatus for systematically encoding data in a communication system, and more particularly to systematically encoding data using a triangular decomposition of a generator matrix. Background Art

[0002] In modern digital data transmission (wireless telephony, wireless data transmission, optical disc transmission to a player, music players receiving music data, etc.), a channel encoder can receive a source data block (SDB) and add redundancy to it (by subjecting the SDB to a transformation) to produce a transmitted code block (TCB), which is better protected from noise in the transmission channel than the SDB from which the TCB was derived. A receiver at the other end of the transmission channel receives a received code block (RCB), which is a version of the TCB corrupted by channel noise and / or distortion, and uses a channel decoder to generate a decoded source data block (DSDB) from the RCB. The DSDB is then forwarded to its destination (e.g., a music player that plays the decoded data as audio or a storage device that stores the decoded data as a file).

[0003] If the DSDB is not an identical copy of the SDB, a frame error is considered to have occurred. A generally accepted design goal of channel coding is to reduce the frame error rate (FER) to an acceptable level. A second measure of channel coding performance is the symbol error rate (SER), which is the average number of symbols (coordinates) for which the DSDB differs from the SDB. If the data symbols are binary, the term bit error rate (BER) is used instead of SER. Channel codes that reduce FER / SER at the expense of excessive computation are of little practical use. In the prior art, there are many classes of channel coders (e.g., linear block coders) that can achieve an acceptable compromise between FER / SER and implementation complexity.

[0004] One type of encoder for linear block codes is a non-systematic encoder, which encodes the SDB into a TCB by multiplying the SDB by a generator matrix. In non-systematic encoding, the SDB is not guaranteed to appear transparently as part of the TCB. An alternative encoding method is systematic encoding, in which the SDB is guaranteed to appear transparently as part of the TCB.

[0005] Systematic coding offers several advantages over non-systematic coding. First, having the SDB appear transparently as part of the TCB may be a system requirement, rather than an option. Second, systematic coding typically improves SER / BER performance without causing degradation in FER performance. Third, systematic coding makes it possible to bypass the decoding function when a "hard decision" on the RCB produces a valid TCB (where validity can be verified by checking whether certain parity checks are satisfied). Bypassing the decoder saves energy, which is important in battery-operated devices. Fourth, systematic coding is necessary in some coding schemes (such as Turbo coding [BER1996]) where iterative decoding methods are employed that rely on systematic coding for operation.

[0006] The present invention provides a systematic encoding method for triangular factorization (TF) codes, which are a newer type of linear block code disclosed in [ARI2019b]. TF codes are based on the triangular decomposition of the code generation matrix into an outer transformation matrix and an inner transformation matrix. In one embodiment of the TF code, the outer transformation matrix is ​​an invertible upper-triangular (IUT) matrix, and the inner transformation matrix is ​​an invertible lower-triangular (ILT) matrix. A more specific embodiment of the TF code is the polarization adjusted convolutional (PAC) code, which is also introduced in [ARI2019b] and further discussed in [ARI2019c].

[0007] There are no existing methods specifically designed for systematic encoding of TF or PAC codes. The present invention provides a systematic encoding method for TF codes and their various embodiments (e.g., PAC codes). The systematic encoding method provided herein exploits the unique characteristics of TF codes and their various embodiments to reduce the complexity of systematic encoding.

[0008] In PAC codes, the outer transform matrix is ​​an IUT Toeplitz matrix. The IUT Toeplitz outer transform matrix of a PAC code produces an irregular convolutional code. Convolutional codes are a well-known class of error-correcting codes introduced by Elias [ELI 1954]. Irregular convolutional codes are generalized convolutional codes in which the number of source bits received by the encoder varies over time according to polarization phenomena [ARI 2009b]. The systematic encoder for irregular convolutional codes is a novel feature of the present invention and has no counterpart in the prior art.

[0009] In PAC codes, the inner transformation matrix is ​​a polarization transformation, a transformation introduced in conjunction with polar codes in [ARI2009]. Polar codes are a class of codes that achieve channel capacity through low-complexity encoding and decoding algorithms [ARI2009]. Systematic encoding of polar codes was first discussed in [ARI2011]. A recursive method for performing systematic encoding of polar codes in a low-complexity manner was disclosed in [ARI2013]. Specific methods for systematic polarization encoding that utilize the recursive principle in [ARI2013] have been proposed in [CHE2016], [SAR2014], [SAR2016], and [WAN2014].

[0010] Existing methods for systematic coding of polar codes cannot be directly used as part of the systematic coding of PAC codes. Unlike polar codes, the polarization-transformed input to PAC coding is not guaranteed to have any frozen symbols. In fact, as explained in [ARI2009c], the main motivation for PAC coding is to avoid fixing any coordinates of the polarization-transformed input in order to avoid loss of channel capacity.

[0011] The present invention provides a method for systematically encoding any internal transform that can be expressed as an ILT matrix, which is a class of internal transforms that is wider than the class of polarization transforms. This is another aspect of the present invention that differs from the prior art in the systematic encoding of polar codes.

[0012] In addition to systematic coding, the principles of the present invention can be used to shorten TF and PAC codes. Shortening is a method of adjusting the block length of a given code. Prior art on polar codes (e.g., [HUA2016], [WAN2014], [ARI2019a]) shows how shortening and systematic coding can be implemented. According to the principles of the present invention, a similar approach can be applied to integrate shortening into the systematic coding of TF codes.

[0013] References:

[0014] [ARI2009] E. Arikan, “Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels,” IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051–3073, July 2009.

[0015] [ARI2011] E. Arikan, “Systematic Polar Coding,” IEEE Communications Letters, vol. 15, no. 8, pp. 860–862, August 2011.

[0016] [ARI2013] E. Arikan, “Method and system for error correction intransmitting data using low complexity systematic encoder,” U.S. Patent No. 8,347,186 B1, January 1, 2013.

[0017] [ARI2019a] E. Arikan, “Method and system for error correction intransmitting data using low complexity systematic encoder,” U.S. Patent Gazette No. 20190165887, May 30, 2019.

[0018] [ARI2019b] E. Arikan, “Methods and apparatus for error correction coding with triangular factorization of generator matrix,” U.S. Patent Application No. 16,453,887, 84, June 26, 2019.

[0019] [ARI2019c] E. Ar1kan, “From sequential decoding to channel polarization and back again,” arXiv:1908.09594 [cs, IT], 26 August 2019.

[0020] [BER1996] C. Berrou and A. Glavieux, “Near optimum error correcting coding and decoding: turbo-codes,” IEEE Transactions on Communications, vol. 44, no. 10, pp. 1261–1271, October 1996.

[0021] [CHE2016] G.T. Chen, Z. Zhang, C. Zhong, and L. Zhang, “A Low Complexity Encoding Algorithm for Systematic Polar Codes,” IEEE Communications Letters, vol. 20, no. 7, pp. 1277–1280, July 2016.

[0022] [ELI1954] P. Elias, “Error-free Coding,” Transactions of the IRE Professional Group on Information Theory, vol. 4, no. 4, pp. 29–37, September 1954.

[0023] [HUA2016]R1-167209, Polar code design and rate matching, Huawei, HiSilicon, 3GPP TSG RAN WG1 Meeting #86, Gothenburg, Sweden, August 22-26, 2016.

[0024] [SAR2014] G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W.J. Gross, “Fast Polar Decoders: Algorithm and Implementation,” IEEE Journal on Selected Areas in Communications, vol. 32, no. 5, pp. 946–957, May 2014.

[0025] [SAR2016] G. Sarkis, I. Tal, P. Giard, A. Vardy, C. Thibeault, and W.J. Gross, “Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes,” IEEE Transactions on Communications, vol. 64, no. 7, pp. 2732–2745, July 2016.

[0026] [WAN2014] R. Wang and R. Liu, “A Novel Puncturing Scheme for Polar Codes,” IEEE Communications Letters, vol. 18, no. 12, pp. 2081–2084, December 2014.

[0027] [WAN2016] H. Vangala, Y. Hong, and E. Viterbo, “Efficient Algorithms for Systematic Polar Encoding,” IEEE Communications Letters, vol. 20, no. 1, pp. 17–20, January 2016.

[0028] The above publications are incorporated herein by reference. Summary of the Invention

[0029] A system encoder apparatus for reliably transmitting a source data block (SDB) in a communication system is configured for an outer transform matrix and an inner transform matrix. Within the system encoder apparatus, an inner encoder is configured to receive the SDB and generate an output constraint block (OCB) as an image of the SDB under the inverse of a submatrix of the inner transform matrix, and an outer encoder is configured to receive a fixed data block (FDB) and the OCB and generate a transform output block (TOB) as an image of a transform input block (TIB) under the outer transform matrix, the TIB transparently including the FDB in its subblocks, and the TOB transparently including the OCB in its subblocks. The inner encoder is further configured to receive the TOB and generate a transmit code block (TCB), the TCB transparently including the SDB in its subblocks. The outer transform matrix is ​​optionally an invertible upper triangular (IUT) matrix. The subblocks of the TOB optionally include elements whose indices of the TOB belong to an index set, and the subblocks of the TIB optionally include elements whose indices of the TIB belong to a complement set of the index set. The inner transform matrix is ​​optionally an invertible lower triangular (ILT) matrix, wherein a submatrix of the inner transform matrix includes elements whose row indices of the inner transform matrix belong to an index set and whose column indices belong to an index set, a subblock of the TCB includes elements whose indices of the TCB belong to an index set, and the TCB is an image of the TOB under the inner transform matrix. The outer encoder optionally includes a feedforward calculation circuit, wherein the feedforward calculation circuit is configured to receive a sequence of TIB elements and generate a feedforward value for each received TIB element. In embodiments where the outer transform matrix is ​​an IUT Toeplitz matrix, the feedforward calculation circuit optionally includes a convolution circuit, wherein the convolution circuit includes a plurality of registers, a multiplier, and an adder, and is configured based on an impulse response derived from the first row of the IUT Toeplitz matrix. In some embodiments, the outer encoder is optionally further configured to use the feedforward value together with a current element of the FDB or a current element of the OCB to generate a next element of the TIB and a next element of the TOB.

[0030] A method for reliably transmitting a source data block (SDB) in a communication system employs a system encoder apparatus configured for an outer transform matrix and an inner transform matrix. Within the method, an inner encoder is configured to receive the SDB and generate an output constraint block (OCB) as an image of the SDB under the inverse of a submatrix of the inner transform matrix, and an outer encoder is configured to receive a fixed data block (FDB) and the OCB and generate a transform output block (TOB) as an image of a transform input block (TIB) under the outer transform matrix, the TIB transparently including the FDB in its subblocks, and the TOB transparently including the OCB in its subblocks. The inner encoder is further configured to receive the TOB and generate a transmit code block (TCB), the TCB transparently including the SDB in its subblocks. The outer transform matrix may optionally be an invertible upper triangular (IUT) matrix, the subblocks of the TOB may optionally include elements whose indices of the TOB belong to an index set, and the subblocks of the TIB may optionally include elements whose indices of the TIB belong to a complement of the index set. In an embodiment where the inner transform matrix is ​​an invertible lower triangular (ILT) matrix, a submatrix of the inner transform matrix optionally includes elements whose column indices of the inner transform matrix belong to an index set and whose row indices belong to an index set, a subblock of the TCB optionally includes elements whose indices of the TCB belong to an index set, and the TCB is an image of the TOB under the inner transform matrix. The outer encoder optionally includes a feedforward calculation circuit, wherein the feedforward calculation circuit is configured to receive a sequence of TIB elements and generate a feedforward value for each received TIB element. In an embodiment where the outer transform matrix is ​​an IUT Toeplitz matrix, the feedforward calculation circuit optionally includes a convolution circuit comprising a plurality of registers, a multiplier, and an adder, the convolution circuit being configured based on an impulse response obtained from the first row of the IUT Toeplitz matrix. The outer encoder can also be configured to use the feedforward value together with the current element of the FDB or the current element of the OCB to generate the next element of the TIB and the next element of the TOB. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram illustrating a communication system 100 in which an embodiment of the principles of the present invention may be used;

[0032] Figure 2 is a block diagram illustrating a non-systematic encoder 200;

[0033] Figure 3 is a diagram showing a system encoder 300 in accordance with the principles of the present invention;

[0034] Figure 4A is a flow chart of an IUT encoding method 400 according to the principles of the present invention;

[0035] Figure 4B is a diagram illustrating an exemplary calculation 450 according to the IUT encoding method 400;

[0036] Figure 5A is a flow chart illustrating an IUT Toeplitz encoding method 500 according to the principles of the present invention;

[0037] Figure 5B is a diagram illustrating an exemplary calculation 550 according to the IUT Toeplitz encoding method 500;

[0038] Figure 6 is a schematic diagram of a convolution circuit 600;

[0039] Figure 7 is a schematic diagram of an IUT Toeplitz encoder circuit 700 according to the principles of the present invention;

[0040] Figure 8 is a schematic diagram of a transposed form convolution circuit 800;

[0041] Figure 9A is a flow chart of an IUT Toeplitz transposed form encoder method 900 according to the principles of the present invention;

[0042] Figure 9B is a diagram illustrating an exemplary calculation 950 according to the IUT Toeplitz transposed form encoding method 900;

[0043] Figure 10 is a schematic diagram of a transposed form IUT Toeplitz encoder circuit 1000 according to the principles of the present invention;

[0044] Figure 11 An example wireless network is illustrated in accordance with the present invention within which systematic encoding of data in error correction coding using triangular decomposition of a generator matrix may be implemented;

[0045] Figure 12A illustrates an example user equipment network within which systematic encoding of data in error correction coding using triangular decomposition of a generator matrix may be implemented according to the present invention; and

[0046] Figure 12B An example enhanced Node B (eNB) network is illustrated within which systematic encoding of data in error correction coding using triangular decomposition of a generator matrix may be implemented in accordance with the present invention. DETAILED DESCRIPTION

[0047] Discussed below Figures 1 to 12B The various embodiments used to describe the principles of the present invention in this patent document are merely illustrative and should not be interpreted as limiting the scope of the present invention in any way. Those skilled in the art will appreciate that the principles of the present invention can be implemented in any appropriately arranged communication system.

[0048] We will begin by introducing some notations, terms, and definitions. We will also state some known facts about matrices that will be needed in the subsequent discussion of the principles of the invention.

[0049] We use script letters (e.g. ) to represent a set. express The number of elements in (the cardinality of ).

[0050] symbol represents the finite field with elements {0,1,…,q-1}.

[0051] symbol Indicates that a is a row vector a=(a1,a2,…,a n ), where for i=1,2,…,n, for and Indicates that The subvector of the elements of a with indices in same, Represented by a set The subvector of the elements of a with indices in , where represents {1,2,…,n} For example, if m = 8 and So, and By convention, we write So that the coordinates of a are in increasing order appears; therefore, whether it is the collection Designated as still Subvector All by given.

[0052] Indicates that it has The set of all m×n matrices with elements of . Symbol Indicates that A is a matrix with m rows and n columns. Usually, we pass the matrix Written explicitly as a two-dimensional array [a i,j :1≤i≤m,1≤j≤n] to define the matrix, where a i,j represents the element (entry) in the i-th row and j-th column of A. For the element a of matrix A i,j , we call index i the row index and index j the column index. i,j is considered to be in the i-th row and j-th column of the matrix A.

[0053] The symbol 0 will represent a matrix whose elements are all 0. (The dimension of 0 will be clear from the context.)

[0054] If for all i≠j, a i,j = 0, then the matrix A is said to be diagonal. A diagonal matrix with 1s on the diagonal is called the identity matrix and is denoted by I.

[0055] If there is a matrix (called the inverse of A), so that AB=BA=I, then the matrix is called reversible. If it exists, then the inverse of A is represented by A -1 .

[0056] If the matrix With is a square matrix and or form So Therefore, if and only if and When both are reversible, A is reversible.

[0057] If for all 1≤i <j≤n,a i,j =0, then the matrix is called lower triangular. If for all 1≤j <i≤n,a i,j =0, then the matrix It is called upper triangular.

[0058] If there is a vector Let A be an upper triangular matrix where for j ≥ i, a i,j =a j-i (i.e., if A is of the form) then the matrix It is called the upper triangular Toeplitz:

[0059]

[0060] Such a Toeplitz matrix is ​​invertible if and only if a0≠0. The Toeplitz matrices we will consider below will be invertible. If A is a matrix with the first row a=(a0,a1,…,a n-1 ), and m∈{0,1,…,n-1} is the largest index such that a m ≠0, then we will take the initial segment of a (a0, a1, ..., a m ) is called the impulse response, and the upper triangular Toeplitz matrix A is considered to be composed of the impulse response (a0, a1, ..., a m )definition.

[0061] Two matrices and The Kronecker product of is defined as the matrix:

[0062]

[0063] The nth Kronecker power of matrix A is inductively defined as And for n ≥ 2, it is defined as

[0064] Hereinafter, the term "transformation" is used in the sense of a linear mapping from one vector space to another. Matrices are used to represent a particular form of transformation relative to a particular basis vector. The term "transformation matrix A" will refer to a specific implementation of a transformation in the form of a particular matrix A. When two vectors a and b are related by the transformation relation b = aA, we consider b to be the image of a under the transformation matrix A.

[0065] In the following description, we use row vectors to represent signals (e.g., source data blocks and encoded data blocks); and, multiplications involving vector a and matrix A will always have the form aA (left multiplication). It will be apparent that the present principles can be readily implemented using column vectors rather than row vectors, and right multiplication rather than left multiplication. All such variations of the methods presented below based on different representations of vector spaces or matrix representations of transformations acting on such vector spaces fall within the scope of the present principles.

[0066] If all entries of P are either 0 or 1 and P has exactly one 1 in each row and exactly one 1 in each column, then the matrix is called a permutation matrix. If there exists a permutation matrix and Let A=PBQ, then we will consider the two matrices and are permutation equivalent. Permutation equivalent matrices differ from one another only in the permutation of rows and columns, which in a communication system corresponds to receiving source data or sending coded data in a different (permuted) order. Hereinafter, the principles of the present invention will be described using a matrix representation that is most convenient for the purpose of explaining the basic idea; however, those skilled in the art will have no difficulty in applying the principles of the present invention to situations where it may be more desirable to use an alternative matrix representation.

[0067] The main motivation for the present principles is to provide a systematic coding method that can be used in conjunction with TF codes, and more specifically, with PAC codes (which are a subclass of TF codes). TF codes are a class of linear block codes whose generator matrices are decomposed into triangular matrices (or matrices permuted equivalent to triangular matrices) for encoding and decoding. Before discussing the details of the present principles, we would like to restate the motivation for systematic coding in more general terms, which will help better understand the benefits and practicality of the present principles.

[0068] A channel encoder is said to be systematic if it encodes source data into codewords in such a way that the source data appears transparently as part of the codewords. For a given linear block code, the source data can be encoded in either a systematic or non-systematic form. Systematic coding offers several advantages over non-systematic coding. First, systematic coding offers better bit error rate / symbol error rate (BER / SER) performance than non-systematic coding. This alone is often a sufficient reason to prefer systematic coding. Second, in many application scenarios, making the source data appear transparently as part of the codeword is a system requirement, not an option. Third, systematic coding allows decoding to be completed immediately when a "hard decision" on a received codeword produces a valid codeword. Fourth, systematic coding will be necessary in various cascaded coding schemes where two or more decoders exchange information on systematically coded data bits (such as in Turbo coding).

[0069] Although systematic coding has advantages, there is no systematic coding method specifically for TF codes in the prior art. The present invention fills this gap in the prior art by providing a systematic coding method for TF codes that utilizes the special structure of TF codes. Figures 1 to 12B The details of the principles of the present invention and its specific embodiments are described.

[0070] Figure 1 is a block diagram illustrating a communication system 100 in which an embodiment of the present principles may be used. The communication system 100 includes an encoder 110 on the transmitter side, a channel 120 connecting the transmitter to a receiver, and a decoder 130 on the receiver side.

[0071] The communication system 100 receives a source data block (SDB) d from a source and uses it as a decoded source data block (DSDB) (The source and destination are not shown in the figure because they are considered given and fall outside the scope of the present invention.) When DSDB When it does not completely match SDB d (i.e. when A frame error is considered to have occurred when . The main performance criterion of the communication system 100 is the frame error rate (FER), which is defined as the probability It is generally preferred to have a communication system 100 with the smallest possible FER. Encoder 110 and decoder 130 implement a channel coding scheme to reduce the FER at the expense of increased channel bandwidth, equipment cost, and latency. Details of the channel coding operation are as follows.

[0072] Encoder 110 receives SDB d and encodes it into a transmit code block (TCB) x. Channel 120 includes a channel input and a channel output. Encoder 110 applies TCB x to the channel input. The channel responds to TCB x applied to the channel input by generating a receive code block (RCB) y at the channel output. Decoder 130 receives RCB y from the channel output and processes RCB y to generate DSDB.

[0073] It will be apparent to those skilled in the art that a typical communication system includes many functional blocks (e.g., modulators and demodulators, digital-to-analog and analog-to-digital converters, amplifiers, transmit and receive antennas, signal acquisition and synchronization circuits) that are necessary to transmit and receive signals across the channel 120. From the perspective of the present principles, such functional blocks are considered part of the channel 120 and are outside the scope of the present principles.

[0074] The present invention is mainly concerned with the specific implementation of the encoder 110. Some symbolic conventions and terminology regarding the encoding operation are as follows. Throughout the following, we denote SDB and TCB as row vectors d = (d1, d2, ..., d K ) and x=(x1,x2,…,x N ), where K is the source block length and N is the code block length. The mapping from SDB d to TCB x is called a code. Throughout this paper, we will consider codes such that both d and x are common finite fields The ratio R = K / N is called the code rate, and we will assume that the code rate R is a number that satisfies 0≤R≤1.

[0075] If the SDB d appears transparently as part of the TCB x, the encoder 110 is said to be systematic. The present principles relate to the systematic encoding of TF codes. TF codes are linear block codes based on the reversible transformation matrix (Generator Matrix) Triangular decomposition into an invertible upper triangular (IUT) matrix and the invertible lower triangular (ILT) matrix The product of . We call U the outer transformation matrix and L the inner transformation matrix. The preferred embodiment of the TF code is the PAC code. For the PAC code, the outer transformation matrix is ​​the IUT Toeplitz matrix, and the inner transformation matrix is ​​the polarization transformation matrix (Kronecker power of the kernel matrix). The existing technology for encoding TF codes is based on non-systematic coding.

[0076] Figure 2 is a block diagram illustrating a non-systematic encoder 200 for a TF code as described in [ARI2019b]. Figure 1 In the case of the encoder 110, the overall function of the non-system encoder 200 is to receive SDB from the source And encode it into TCB Where TCB x is a codeword from the TF code.

[0077] The non-systematic encoder 200 includes a data inserter 211, an outer transform 212, and an inner transform 213. The encoding operation of the non-systematic encoder 200 is based on four parameters To configure, where is the external transformation matrix, is the internal transformation matrix, is an index set (of size K), and is a fixed data block (FDB). Assume that the matrix representation of the outer transform and the inner transform is such that U is the IUT matrix and L is the ILT matrix.

[0078] Data inserter 211 receives SDB And generate the transform input block (TIB) Make and in, Represents an index set The outer transform 212 receives the TIB v and generates a transform output block TOB So that w=vU. Inner transform 213 receives TOB w and generates TCB Let x = wL. In other words, TOB is the image of TIB under the external transformation matrix, and TCB is the image of TOB under the internal transformation matrix.

[0079] The present principles provide a solution to the systematic encoding problem of TF codes.Before we begin describing the specific method, it is useful to discuss the mathematical nature of the systematic encoding problem of TF codes to understand whether a solution exists and under what conditions.

[0080] In general, the system encoding of TF code can be composed of five parameters: To specify, where is the external transformation matrix, is the internal transformation matrix, is the first index set (of size K), is the second index set (of size NK), and is the FDB. We assume that the matrix representations of the external and internal transforms are such that U is the IUT matrix and L is the ILT matrix.

[0081] With parameters The system encoder receives SDB And generate a pair of vectors and So that x=vUL, as well as In order to analyze whether such a pair of vectors v and x exists, let G=UL represent the generator matrix of the TF code, and rewrite the equation x=vUL as and Substitute according to the system coding constraints and And solve We obtain the formal solution Among them, we have defined and If and only if the submatrix of the generator matrix G The solution is valid only if it is reversible. The sufficient conditions for reversibility are given below.

[0082] Proposition 1. If Then you can select As {1,2,…,N} The complement of Reversible.

[0083] Prove.Hypothesis And set Then, equal It is also equal to Using Assumptions We obtain because and are principal submatrices of triangular matrices, so they are invertible. Since the product of two invertible matrices is invertible, It is reversible.

[0084] if and If Proposition 1 is chosen, the system coding equation becomes and in, When implementing such a system encoder, the matrix can be pre-computed and vector And configure the system encoder accordingly.

[0085] We have shown that the system encoding problem is feasible under the conditions of Proposition 1. However, by computing It is very impractical to directly solve the system encoding problem. Computing the product dE directly involves O((NK) 2 ) arithmetic operations (domain addition and multiplication in ), which is often too complex for many practical applications.

[0086] The purpose of the present invention is to reduce the complexity of the system coding of TF codes. To this end, the present invention utilizes the triangular decomposition of the generator matrix G into U and L when solving the system coding problem. We begin by describing the general framework of the application of the present invention. In describing the general framework, we limit our attention to is in {1,2,…,N} The complement of the case uses four parameters instead of will be enough.

[0087] Figure 3 is a block diagram illustrating a systematic encoder 300 for TF codes according to the principles of the present invention. As in the case of the non-systematic encoder 200, the TF codes of the systematic encoder 300 are characterized by a set of four parameters in, is the external transformation matrix, is the internal transformation matrix, is an index set of size K, and is a fixed data block (FDB). Assume that the matrix representation of the outer transform and the inner transform is such that U is the IUT matrix and L is the ILT matrix. Further, assume that the parameters are chosen such that

[0088] The system encoder 300 includes an inner encoder 301 and an outer encoder 302, and operates according to the system encoding constraints 320. The operation of the system encoder 300 will be described by dividing the operation into three steps.

[0089] In the first step, the inner encoder 301 receives the SDB 311 and generate an external constraint block (OCB) Make In other words, OCB 312γ is generated as a sub-matrix of the internal transformation matrix of SDB d 311 As mentioned above, due to the assumption that therefore It is reversible.

[0090] In the second step, the outer encoder 302 receives the FDB a 313 and the OCB γ 312 and generates the TIB v 314 and the TOBw 315 so as to satisfy the outer transform constraint w=vU 321 and the OCB constraint 322 and FDB constraints 323. In the third step, the inner encoder 301 receives the TOB w 315 and generates a TCB x 316 such that the inner transform constraint x=wL 324 is satisfied. We now provide that at the end of the third step we have in TCB x 316 the systematic coding constraint 325 in the sense of obtaining proof of system coding.

[0091] We observe that the inner transformation operation x=wL in the third step contains the equation A subset of . (by assumption) and (via the second step), so the operation in the third step is equivalent to Substitute the values ​​from the first step We see that the third step produces This argument demonstrates that the system encoder 300 is indeed systematic.

[0092] The above arguments also reveal the conditions related to the principle of the present invention As a condition for selecting code parameters The introduction of decomposing the systematic encoding of TF codes into three smaller sub-problems is an important novel aspect of the present invention. We now discuss how the various steps can be implemented and evaluate their complexity.

[0093] The first step of the system encoder 300 involves calculating the OCB because is an ILT matrix (which inherits properties from L) and since the inverse of an ILT matrix is ​​ILT, the matrix is an ILT. If L has no other structure besides being an ILT, then Direct computation of may be the only option. In this case, the matrix can be precomputed And can use The inner encoder 301 is pre-configured with knowledge of . The storage complexity is O(K 2 ), and calculate The arithmetic complexity is also O(K 2 As already pointed out, for many applications, the complexity O(K 2Fortunately, the complexity of the inventive concept is reduced to a practical level when we consider the special case of TF coding (e.g., PAC coding).

[0094] An important special case of TF codes is PAC codes, in which the inner transform matrix L has the form of a Kronecker power, e.g., in And n = log2 N. The inverse of this internal transformation L is itself, L -1 =L, which is consistent with the condition Hint together In this case, the calculation The preferred method is to set and To prepare the vector x′, then calculate w′=x′L, and finally by setting The transformation step w′=x′L can be implemented by exploiting the recursive structure of L, resulting in a complexity of O(N log N), which may be significantly better than directly computing The complexity is O(K 2 (The problem with direct calculation is that when we consider the submatrix , the recursive structure of L may be lost. )

[0095] Those skilled in the art will recognize that the above method of calculating OCBγ by utilizing the recursive structure of polarization transformation utilizes the existing technology on the systematic encoding of polar codes. When we impose the condition on the system encoder 300 Usually a collection of PAC codes In other words, the condition It does not necessarily imply a loss of optimality in the PAC code construction.

[0096] The comments on the complexity of the first step of the system encoder 300 are largely valid for the complexity of the third step. For a general ILT matrix L, the complexity of computing x=wL is O(N 2 ). On the other hand, for For PAC codes, the complexity of the third step is reduced to O(N log N), i.e., the complexity of encoding the polar code. Therefore, the first and third steps of the systematic encoder 250, performed by the inner encoder 301, have a combined complexity of O(N log N) in the case of PAC codes, which are the codes of primary interest to the present principles.

[0097] We now turn our attention to the complexity of the outer encoder 302 that performs the second step of the system encoder 300.

[0098] Proposition 2. For the parameter For any instance of O(N 2 ) arithmetic operations( The implementation of the outer encoder 302 solves the outer coding problem (finding a unique TIB v 314 and TOB w 315 pair that satisfies the constraints 321, 322, and 323) by using addition and multiplication in [ 314 ]. If U is an impulse response Toeplitz (in addition to being an IUT), then there is an implementation of the outer encoder 302 that solves the outer coding problem using O(mN) arithmetic operations.

[0099] Proof. We will prove this claim by giving an algorithm for computing the solution. Let u i,j represents the (i, j)th element of U. Since U is assumed to be upper triangular, for i>j, u i,j = 0. Therefore, the equation system w = vU can be written as w1 = v1u 1,1 、w2=v1u 1,2 +v2u 2,2 , and more generally for i = 1, 2, ..., N written as w i =v1u 1,i +…+v i-1 u i-1,i +v i u i,i These equations can be solved sequentially. The first equation is w1 = v1u 1,1 And we have two cases: or In the first case, (v1, w1) = (a1, a1u 1,1 ); in the second case, (v1,w1)=(γ1(u 1,1 ) -1 ,γ1), where (u 1,1 ) -1 is u 1,1 Note that since U is assumed to be reversible, u i,i ≠0, and for every i there exists a multiplicative inverse (u i,i ) -1 As an inductive hypothesis, assume that (v h ,w h ), and consider the next pair (v i ,w i ). Define feedforward variable s = v1u 1,i +…+v i-1 u i-1,iNote that the value of the feedforward variable s becomes available at the end of step i-1 of the above algorithm and can be used to calculate the value of (v i ,w i ). Since for some elements of FDB a, And v i =a k , or for some element γ of OCBγ j , And w i =γ j , so the two unknown quantities (v i ,w i ) is also known at step i. In either case, the remaining elements of the pair can be obtained from the relation w i =s+v i u i,i Specifically, if Then (v i ,w i )=(a k ,s+a k u i,i ); Alternatively, if Then (v i ,w i )=((γ j -s)(u i,i ) -1 ,γ j ). This completes the proof that the solution (v,w) exists and is unique.

[0100] The complexity of the above process is dominated by the computation of the feedforward variable s. There are N feedforward variable computations, each of which requires at most N multiplications and N-1 additions. Therefore, the overall complexity is O(N 2 ). If U is an impulse response IUT Toeplitz, then for i=1,2,…,N, w i =v i g0+v i-1 g1+…+v i- m g m , with a labeling rule: if j ≥ i, then v i-j = 0. The feedforward variable is s = v i-1 g1+…+v i-m g m Given that it requires at most m multiplications and m-1 additions. Therefore, the complexity of computing the feedforward variable s is reduced from O(N) to O(m), and the overall complexity becomes O(mN). This completes the proof of Proposition 2.

[0101] The process presented in the proof of Proposition 2 forms the basis of the outer encoder 302 according to the principles of the present invention. We will now give a more precise algorithmic description of this process.

[0102] Figure 4A FIG. 4 is a flow chart of an IUT encoding method 400 for implementing the outer encoder 302 according to the principles of the present invention. The IUT encoding method 400 (hereinafter referred to as method 400) is configured to utilize four parameters: The method 400 solves the outer coding problem by computing a pair of TIB v 314 and TOB w 315 that satisfies the constraints 321, 322, and 323. The method 400 begins operation in a start step 401 and when a new OCB 312 becomes available for encoding, is shifted into the OCB input step 402. In the OCB input step 402, the method 400 obtains the OCB gamma 312 from the outside (eg, from the inner encoder 301).

[0103] After OCB input step 402, method 400 moves to variable initialization step 403 and initializes loop counter i, FDB constraint counter j, and OCB constraint counter k. Loop counter i counts the number of times method 400 executes the main loop, which begins with loop counter increment step 404. In step 403, loop counter i is initially set to 0. FDB constraint counter j is initialized to j←min{1,NK}, and at any time during the operation of method 400, counter j indicates which of the NK FDB constraints 323 will be processed next by method 400. If the number of FDB constraints 323 is zero, that is, if NK=0, then FDB constraint counter j is set to 0 in step 403 and remains at 0 throughout the remainder of method 400. OCB constraint counter k is initialized to k←min{1,K}, and at any time during the operation of method 400, counter k indicates which of the K OCB constraints 322 will be processed next by method 400. If the number of OCB constraints is 0, that is, if K=0, then the OCB constraint counter k is set to 0 in step 403 and remains 0 throughout the remaining operations of method 400 .

[0104] After the variable initialization step 403, the method 400 performs a loop counter increment step 404 by adding 1 to the loop counter i. Step 404 marks the beginning of the main loop of the method 400. The main loop is executed N times. During the i-th execution of the main loop, the method 400 compares the feedforward value s with the current element a of the FDB a 313. j or the current element of OCBγ312γ kProcessed together to generate the next element v of TIB v 314 i and the next element w of TOB w 315 i The details of the main loop are as follows.

[0105] After step 404, method 400 enters a loop counter check step 405 and checks whether loop counter i is still less than or equal to its final value N. If the result of the check is no, method 400 moves to an exit step 406. (If the next OCB is available for encoding, exit step 406 can be bypassed and method 400 can proceed to process the next OCB by re-entering OCB input step 402.) If the result of the check in step 405 is yes, method 400 moves to a feedforward calculation step 407 and calculates the feedforward value If i=1, the feedforward value is set to zero, s=0. The next step after step 407 is a constraint type check step 408 .

[0106] In the constraint type check step 408, a check is made to see that the next constraint to be processed is the FDB constraint 323 (by b i = 0) or OCB constraint 322 (indicated by b i =1 indicates). Here, b = (b1, b2, ..., b N ) is from the index set The constraint type indicator (CTI) is derived so that if Then b i =1, and if Then b i = 0. In other words, CTI b is the index set By looking at the i-th coordinate of CTI b, we can check whether Than search collection to see if it is more efficient to include i. Using a Boolean vector for this purpose is particularly useful in the hardware implementation discussed below.

[0107] If the result of the constraint type check step 408 is no, then the method 400 proceeds by setting w i =a j u i,i +s and v i =a j The FDB constraint processing step 409 is executed. Step 409 is always followed by step 411, in which the FDB constraint counter j is updated to j←min{j+1,NK}. At the end of step 411, if there are still FDB constraints left, the FDB constraint counter j points to the next FDB constraint 323 to be processed; if all FDB constraints 323 have been processed, the value of j remains at NK.

[0108] If the result of the constraint type check step 408 is yes, then the method 400 proceeds by setting w i =γ k and v i =(γ k -s)(u i,i ) -1 The OCB constraint processing step 410 is executed. Step 410 is always followed by step 412, in which the OCB constraint counter k is updated to k←min{k+1,K}. At the end of step 412, if there are still OCB constraints left, the OCB constraint 322 counter k points to the next OCB constraint to be processed; if all OCB constraints 322 have been processed, the value of k remains at K.

[0109] Steps 411 and 412 are followed by an output step 413, in which the method 400 outputs the i-th element w of TOB w 315. i Optionally, the method 400 may output the ith element v of the TIB v 314. i As part of the output step 413 .

[0110] After outputting step 413, method 400 loops back to step 404 and continues operating as described above.

[0111] Method 400 can be simplified slightly by eliminating all "min" operations and using j←1 and k←1 instead of j←min{1,NK} and k←min{1,K} in step 403, and using j←j+1 and k←1 instead of j←min{j+1,NK} and k←min{k+1,K} in steps 411 and 412. This simplification allows j or k to take out-of-range values, but inspection of method 400 reveals that TIBv 314 and TOBw 315 will still be calculated correctly. This type of simplification is also effective in more specific embodiments of method 400, as discussed below in conjunction with Figures 5 and 9.

[0112] When the diagonal elements of the IUT matrix U are all 1 ( Another simplification occurs in the implementation of method 400 when the multiplication identity in step 409 is used. i =a j u i,i +s is simplified to w i =a j +s, and the operation v in step 410 i =(γ k -s)(u i,i ) -1 Simplified to v i=γ k -s. In particular, when the transformation operation is in the binary domain When the above is performed, all multiplication and division operations in method 400 can be replaced with simpler operations, which reduces the complexity of implementing outer encoder 302 in both hardware and software.

[0113] Figure 4B is a diagram illustrating an exemplary calculation 450 according to method 400. The exemplary calculation 450 uses an exemplary IUT matrix U 452, an exemplary CTI b 453, an exemplary FDB a 454, and an exemplary OCBγ 455. Assume that the exemplary calculation 450 is in the binary domain. By examining the exemplary parameters 453 and 454, we understand that the length parameters in this exemplary calculation are N=8 and K=3. The details of the exemplary calculation 450 are shown in Table 451. The i-th row of Table 451 lists the values ​​of the variables of method 400, where these values ​​are sampled immediately after the FDB constraint processing step 409 or the OCB constraint processing step 410 is completed. At the end of the exemplary calculation, an exemplary TIB v 456 and an exemplary TOB w 457 are obtained. It can be easily verified that the exemplary variables 452 to 457 satisfy the transformation constraint w=vU 321, the FDB constraint and OCB constraints in and

[0114] Although the method 400 provides a solution to the external encoding problem, it is not suitable for general LUT matrices. With complexity O(N 2 ), which is often prohibitive in practice. The complexity can be reduced if U has a special structure. A particularly important case is when U is Toeplitz in addition to being an IUT, as in the case of PAC codes. We now turn our attention to this important special case.

[0115] Figure 5A is a flow chart illustrating an IUT Toeplitz encoding method 500 for implementing the outer encoder 302 according to the principles of the present invention. The IUT Toeplitz encoding method 500 (hereinafter referred to as method 500) is a special instance of method 400, which is suitable for the case where the outer transform matrix U is an IUT Toeplitz matrix. According to the IUT Toeplitz assumption, the method 500 is configured for the impulse response where g0≠0 and g m ≠0, and where the impulse response g is transformed from the external matrix The first line of the export.

[0116] The method 500 begins operation in a start step 501 and when the OCB 312 becomes available for encoding, is shifted into the OCB input step 502. In the OCB input step 502, the method 500 obtains the OCB gamma 312 from the outside (eg, from the inner encoder 301).

[0117] After the OCB input step 502, the method 500 moves to the variable initialization step 503 and initializes the loop counter i, the FDB constraint counter j, the OCB constraint counter k, and sets r for i=1, ..., m. i ←0 to initialize the register array r=(r1,…,r m ). Counters i, j, and k perform the same counting function as in the case of method 400. The role of register array r will become clear in the following discussion.

[0118] As with method 400, the initialization and updating of counters j and k may be simplified by removing the "min" operation in the same manner as described for method 400. This simplification does not affect the final values ​​of TIB v 314 and TOB w 315 calculated by method 500.

[0119] After the variable initialization step 503, the method 500 performs a loop counter increment step 504 by adding 1 to the loop counter i. Step 504 marks the beginning of the main loop of the method 500. Each time the method 500 is called, the main loop is executed N times. During the i-th execution of the main loop, the method 500 compares the feedforward value s with the current element a of the FDB a 313. j or the current element of OCBγ312γ k Processed together to generate the next element v of TIB v 314 i and the next element w of TOB w 315 i The details of the main loop are as follows.

[0120] After step 504, method 500 enters loop counter check step 505 and checks whether loop counter i is still less than or equal to its final value N. If the result of the check is no, method 500 moves to exit step 506. (If the next OCB 312 is available for encoding, exit step 506 can be bypassed and method 500 can proceed to encoding the next OCB by re-entering OCB input step 502.) If the result of the check in step 505 is yes, method 500 moves to feedforward calculation step 507 to calculate the feedforward value And move to the constraint type checking step 508.

[0121] In the constraint type check step 508, a check is made to see that the next constraint to be processed is the FDB constraint 323 (by bi = 0) or OCB constraint 322 (indicated by b i =1 indication).

[0122] If the result of the constraint type check step 508 is no, then the method 500 proceeds by setting w i =a j g0+s and v i =a j The FDB constraint processing step 509 is executed. Following step 509, step 511 is performed, in which the FDB constraint counter j is updated to j←min{j+1,NK}. At the end of step 511, if there are still FDB constraints left, the FDB constraint counter j points to the next FDB constraint 323 to be processed. If all FDB constraints 323 have been processed, the value of j remains at NK.

[0123] If the result of the constraint type check step 508 is yes, then the method 500 proceeds by setting w i =γ k and v i =(γ k -s)(g0) -1 The OCB constraint processing step 510 is performed. Following step 510, step 512 updates the OCB constraint counter k to k←min{k+1,K}. At the end of step 512, if OCB constraints remain, the OCB constraint counter k points to the next OCB constraint 322 to be processed. If all OCB constraints 322 have been processed, the value of k remains at K.

[0124] Steps 511 and 512 are followed by a register update step 513, in which the registers are updated by setting r in the order h = m, m-1, ..., 2. h ←r h-1 , then set r1←v i , to shift the contents of register array r one position to the right.

[0125] Step 513 is followed by an output step 514 in which the method 500 outputs the i-th element w of TOB w 315. i Optionally, the method 500 may output the ith element v of the TIB v 314. i As part of the output step 514 .

[0126] After outputting step 514, method 500 loops back to step 504 and continues operating as described above.

[0127] The complexity of method 500 is O(mN), which is usually significantly smaller than the complexity of method 400, which is O(N2 ). For example, in the case of PAC codes, the parameter m is usually a fixed small integer, while N can be arbitrarily large.

[0128] The main benefit of the present invention principle becomes apparent at this point. Since the systematic coding problem of TF codes is decomposed into three steps, an outer encoder is obtained that can fully exploit the Toeplitz form of the outer transform matrix and solve the outer coding problem with a complexity of O(mN). This complexity is comparable to the complexity of the general systematic encoder for TF codes, which is O(N 2 ) is very advantageous compared to the above. In particular, the direct method of systematic encoding of TF codes as described above will be achieved by setting and to compute the TCB x. The direct method does not exploit any Toeplitz structure of the outer transformation matrix and is subject to O(N 2 ) complexity, and the principle of the present invention reduces the complexity to O(mN).

[0129] Method 500 can be simplified by eliminating all "minimum" operations as in the case of method 400. As in the case of method 400, when the diagonal elements of the IUT transform U are all 1 ( multiplication identity in ) or when the transformation is in the binary domain As above, another simplification occurs in the implementation of method 500 .

[0130] Figure 5B is a diagram illustrating in tabular form an exemplary calculation 550 according to method 500. The exemplary calculation 550 uses an exemplary IUT Toeplitz matrix U 552, an exemplary CTI b 553, an exemplary FDB a 554, and an exemplary OCB γ 555. Assume that the exemplary calculation 550 is in the binary field By examining the exemplary parameters 553 and 554, we understand that the length parameters in the exemplary calculation 550 are N=8 and K=3. The details of the exemplary calculation 550 are shown in Table 551. The i-th row of Table 551 lists the values ​​of the variables of the method 500, where these values ​​are sampled immediately after the FDB constraint processing step 509 or the OCB constraint processing step 510 is completed. At the end of the exemplary calculation 550, the exemplary TIB v 556 and the exemplary TOB w 557 are obtained. It can be easily verified that the exemplary variables 552 to 557 satisfy the transformation constraint w=vU 321, the FDB constraint and OCB constraints in and

[0131] We now turn our attention to providing an efficient hardware implementation of method 500. The most computationally intensive step of method 500 is the feedforward calculation step 507. This step can be performed using a well-known convolution circuit. For the purpose of discussing such a circuit, it is convenient to use a polynomial representation of the Toeplitz matrix operation.

[0132] Proposition 3. Let For the first row The upper triangular Toeplitz matrix of Be an arbitrary vector, and let Defined by the product w = vU. Define the polynomial g(D) = g0 + g1D + ... + g N-1 D N-1 、v(D)=v1+v2D+…+v N D N-1 and w(D)=w1+w2D+…+w N D N -1 Then, the relationship w = vU can be expressed as w(D) = v(D)g(D) mod D using a polynomial. N .

[0133] Proof. Assume w = vU. Then, by the definition of matrix multiplication, for 1≤i≤N, we have Since U is upper triangular and Toeplitz, if 1≤h≤i≤N, we have u h,i =g i-h Otherwise, u h,i = 0. Therefore, for 1≤i≤N, We observe that for 1≤i≤N, the term w i is D in the product v(D)g(D) i-1 In other words, w(D) is equal to v(D)g(D)mod D N , as requested.

[0134] Those skilled in the art of digital signal processing will recognize that the relationship w(D) = v(D)g(D) mod D N Or equivalently the equation The convolution relationship between TIB v 314 and TOB w 315 is defined. Specifically, when TIB v 314 is applied as input, TOB w 315 can be considered as a vector with impulse response g=(g0, g1, ..., g N-1 ) produces the first N terms of a linear time-invariant filter. There are many circuits for implementing such filters in hardware, which can be used to implement method 500 in the present context. To minimize hardware complexity, we will therefore omit the impulse response g = (g0, g1, ..., g N-1) with trailing zeros, and write g=(g0,g1,…,g m ), where m is the largest integer i in the range 0≤i≤N-1 such that g i ≠ 0. In the circuit implementation given below, the parameter m will be the number of register stages required. In a typical application of the principles of the present invention, the parameter m will be fixed to a number significantly smaller than the code block length N.

[0135] Figure 6 is a schematic diagram of a convolution circuit 600. The convolution circuit 600 is configured to calculate the product w(D)=v(D)g(D)mod D in Proposition 3. N , where g(D) = g0 + g1D + ... + g m D m is a fixed polynomial, v(D)=v1+v2D+…+v N D N-1 and w(D)=w1+w2D+…+w N D N-1 are the input polynomial and the output polynomial respectively.

[0136] The convolution circuit 600 includes an input port 601, an output port 602, registers 611-613, multipliers 621-625, and adders 631-634. The convolution circuit 600 receives the first and second signals in the natural order v1 (first), v2, ..., v N Receives the coefficients v of the input polynomial v(D) i , and at the output port 602 in the natural order w1 (first), w2, ..., w N Calculate and send the coefficients w of the output polynomial w(D) i Before receiving the first input v1, registers r1, r1, ..., r m The contents of 611-613 are initialized to 0. For i=1,2,…,N, the circuit implementation relationship Among them, v i-j For ij<1, it is interpreted as 0. Therefore, the first output coefficient w1 is given by w1=g0v1; the second output coefficient is given by w2=g0v2+g1v1; and the final output coefficient is given by w N =g0v N +g1v N-1 +…+g m v N-m Given. It takes N time units for the convolution circuit 600 to complete its operation. The convolution circuit 600 can compute the product w(D) = g(D)v(D) mod D in any domain N If the coefficient g of the polynomial g(D) is fixed iIf g1 is zero, then the corresponding multiplier and adder circuits can be eliminated to simplify the circuit. For example, if g1 = 0, then the multiplier 621 and adder 631 can be eliminated. i = 1 (multiplication identity), in which case the corresponding multiplier can be eliminated. In particular, when the operand is a binary domain, no multipliers are required, and addition operations can be implemented using logical exclusive-OR (XOR) gates. Convolution circuit 600 and various implementations thereof in digital logic are well known in the art.

[0137] Figure 7 FIG. 7 is a schematic diagram of an IUT Toeplitz encoder circuit 700 for implementing the outer encoder 302 according to the principles of the present invention. The IUT Toeplitz encoder circuit 700 is a hardware implementation of the method 500 using commonly available digital logic elements (e.g., adders, multipliers, random access memories, shift registers, and multiplexers). The circuit 700 includes an element a for receiving the FDB a 313. j FDB input port 701 for receiving element γ of OCBγ312 k OCB input port 702 for receiving element b of CTI b i CTI input port 703, element w for sending TOB w 315 i The TOB output port 704 and the element v for sending the TIB v 314 i TIB output port 705.

[0138] Circuit 700 also includes a feedforward calculation circuit 710, a first multiplexer MUX1 720, and a second multiplexer MUX2 730. Circuit 700 follows the steps of method 500. Certain steps in the implementation of method 500 are not explicitly shown in circuit 700 to avoid cluttering circuit 700 with unnecessary detail. In particular, the clock circuitry, control logic, and storage elements used to maintain FDB a 313, OCBγ 312, and CTI b are not shown in circuit 700. Logic circuitry for initializing and incrementing counters j, k, and i, which are used to retrieve element a from their respective storage locations, is also not shown in circuit 700. j , γ k and b i A person skilled in the art of digital circuit design will have no difficulty in completing these routine details of the control logic of circuit 700 in order to obtain a complete implementation of method 500.

[0139] The feedforward calculation circuit 710 is inspired by the convolution circuit 600. The function of the feedforward calculation circuit 710 is to execute step 507 of the method 500. The feedforward calculation circuit 710 receives the element v of the TIB v 314. i As input, and generate feedforward value As the output, similar to step 503 of method 500 , at the start of the operation, the contents of the registers within the feedforward calculation circuit 710 are initialized to 0.

[0140] Multiplexers MUX1 720 and MUX2 730 are conventional 2-to-1 multiplexers commonly used in digital circuits. Specifically, the 2-to-1 multiplexer employed here has two input ports, IN1 and IN0, a control port SEL, and an output port OUT. When the signal at the control port SEL is a logic 1 (or logic 0, respectively), the 2-to-1 multiplexer forwards the logic signal at the input port IN1 (or input port IN0, respectively) to the output port OUT.

[0141] The constraint type checking step 508 is implemented by connecting the CTI input port 703 to the SEL inputs 723 and 733 of multiplexers MUX1 720 and MUX2 730, respectively.

[0142] When b i = 0, the first multiplexer MUX1 720 converts the signal a j g0+s is routed from input port IN0 722 to output port OUT 724, and a second multiplexer MUX2 730 converts the signal a j Routed from input port IN0 732 to output port OUT 734. Therefore, when b i = 0, the signal at the TOB output port 704 is obtained as w i =a j g0+s, and the signal at the TIB output port 705 is obtained as v i =a j , as required by step 509 of method 500. When b i =0, the control logic updates the FDB constraint counter j according to step 511 of method 500 .

[0143] When b i =1, the first multiplexer MUX1 720 converts the signal γ k The signal (γ) is routed from the input port IN1 721 to the output port OUT 724, and the second multiplexer MUX2 730 converts the signal (γ k -s)(g0) -1 Routed from input port IN1 731 to output port OUT 734. Therefore, when b i= 1, the signal at the TOB output port 704 is obtained as w i =γ k , and the signal at the output port 705 is obtained as v i =(γ k -s)(g0) -1 , as required by step 510 of method 500. When b i =1, the control logic updates the OCB constraint counter k according to step 512 of method 500 .

[0144] At the end of round i, the signal v i The next signal is changed at the input of the feedforward calculation circuit 710, and the registers r1, r2, ..., r m-1 Shifts the contents of _one position to the right.

[0145] After the above description, one skilled in the art will have no difficulty implementing circuit 700 so that it performs as described in method 500. One skilled in the art will also recognize that there are various alternative implementations of method 500 that involve pipelining and parallelization to reduce processing latency and increase throughput.

[0146] When the outer transform matrix is ​​IUT Toeplitz, the outer encoder 302 can be implemented using the transposed form of the convolution circuit 600. We will now discuss this transposed form circuit, compare it with the direct form circuit 600, and present an alternative implementation of the outer encoder 302 based on the transposed form convolution.

[0147] Figure 8 is a schematic diagram of a transposed convolution circuit 800. Transposed convolution circuit 800 performs the same function as convolution circuit 600, but may be preferred due to certain implementation advantages. Transposed convolution circuit 800 is configured to compute the product w(D) = v(D) g(D) mod D as in Proposition 3. N , where g(D) = g0 + g1D + ... + g m D m is a fixed polynomial, v(D)=v1+v2D+…+v N D N-1 and w(D)=w1+w2D+…+w N D N-1 are the input polynomial and the output polynomial respectively.

[0148] The transposed convolution circuit 800 is obtained from the convolution circuit 600 by Mason's formula (for example, see page 156 of the book "A.V. Oppenheim and R.W. Schafer, Digital Signal Processing, Prentice-Hall, Englewood Cliffs, New Jersey, 1975"). The transposed convolution circuit 800 includes an input port 801, an output port 802, registers 811-813, multipliers 821-825, and adders 831-834.

[0149] The transposed convolution circuit 800 receives the first, second, third, and fourth vectors at the input port 801 in the natural order v1 (first), v2, ..., v N Receives the coefficients v of the input polynomial v(D) i , and at the output port 802 in the natural order w1 (first), w2, ..., w N Calculate and send the coefficients w of the output polynomial w(D) i Before receiving the first input v1, registers r1, r1, ..., r m The contents of 811-813 are initialized to 0. It takes N time units for the transposed convolution circuit 800 to complete its operation. The transposed convolution circuit 800 can calculate the product w(D)=g(D)v(D)mod D in any domain. N If the coefficient g of the polynomial g(D) is fixed i is zero, then the corresponding multiplier and adder circuits can be eliminated to simplify the circuit. i =1 (multiplication identity), in which case the corresponding multiplier can be eliminated. In particular, when the operand is a binary domain, no multipliers are required, and logical exclusive-OR (XOR) gates can be used to implement the addition operation. The details of the operation of the transposed form convolution circuit 800 and its various implementations in digital logic are well known in the art.

[0150] It will be apparent to those skilled in the art of digital circuit design that, from an implementation perspective, direct form convolution circuit 600 (direct form circuit 600 for short) and transposed form convolution circuit 800 (transposed form circuit 800 for short) have certain advantages and disadvantages relative to one another. A disadvantage of direct form circuit 600 is that it has a greater delay (also known as latency or critical path) than transposed form circuit 800. The delay of direct form circuit 600 is determined by the calculation of output 602, which takes mT. add +T mult time units, where T add is the adder delay, T multis the delay of the multiplier. Conversely, the delay of the transposed circuit 800 is T add +T mult Thus, the transposed form circuit 800 can run at a higher clock frequency than the direct form circuit 600, which is important for high throughput applications. On the other hand, one skilled in the art will recognize that pipelining can be introduced into the direct form circuit 600 and its latency reduced to T by adding additional pipeline registers in series with the various existing registers. add +T mult If the two circuits are compared in terms of the fanout of the signals, the input 801 in the transposed form circuit 800 has a fanout of m, while the direct form circuit 600 does not use any signal with a fanout greater than two. When m is large, the fanout becomes a factor to consider.

[0151] Figure 9A 1 is a flow chart of an IUT Toeplitz transposed form encoder method 900 according to an embodiment of the present invention. The IUT Toeplitz transposed form encoding method 900 (hereinafter referred to as method 900) is configured for an IUT having an impulse response IUT Toeplitz matrix where g0≠0 and g m ≠ 0. The method 900 starts operation in the start step 901 and when the new OCB 312 becomes available for encoding, is shifted into the OCB input step 902. In the OCB input step 902, the method 900 obtains the OCB gamma 312 from the outside (eg, from the inner encoder 301).

[0152] After the OCB input step 902, the method 900 moves to the variable initialization step 903 and initializes the loop counter i, the FDB constraint counter j, the OCB constraint counter k, and sets r for i=1, ..., m. i ←0 to initialize the register array r=(r1,…,r m ). Counters i, j, and k perform the same counting function as in the case of method 400. The role of register array r is explained below.

[0153] As with method 400, the initialization and updating of counters j and k can be simplified by removing the "min" operation in the same manner as described for method 400. This simplification does not affect the final values ​​of TIB v 314 and TOB v 315 calculated by method 900.

[0154] After the variable initialization step 903, the method 900 performs a loop counter increment step 904 by adding 1 to the loop counter i. Step 904 marks the beginning of the main loop of the method 900. Each time the method 900 is called, the main loop is executed N times. During the i-th execution of the main loop, the method 900 compares the feedforward value s with the current element a of the FDB a 313. j or the current element of OCBγ312γ k Processed together to generate the next element v of TIB v 314 i and the next element w of TOB w 315 i The details of the main loop are as follows.

[0155] After step 904, method 900 enters loop counter check step 905 and checks whether loop counter i is still less than or equal to its final value N. If the result of the check is no, method 900 moves to exit step 906. (If the next OCB 312 is available for encoding, exit step 906 can be bypassed and method 900 can proceed to encoding the next OCB by re-entering parameter initialization step 902.)

[0156] If the result of the check in step 905 is yes, the method 900 moves to the constraint type check step 907 and checks whether the next constraint to be processed is the FDB constraint 323 (set by b i = 0) or OCB constraint 322 (indicated by b i =1 indication).

[0157] If the result of the constraint type check step 907 is no, then the method 900 proceeds by setting w i =a j g0+r1 and v i =a j The FDB processing step 908 is executed. Following step 908, step 910 is performed, in which the FDB constraint counter j is updated to j←min{j+1,NK}. At the end of step 910, if there are still FDB constraints left, the FDB constraint counter j points to the next FDB constraint 323 to be processed. If all OCB constraints 323 have been processed, the value of j remains at NK.

[0158] If the result of the constraint type check step 907 is yes, then the method 900 proceeds by setting w i =γ k and v i =(γ k -r1)(g0) -1The OCB processing step 909 is executed. Following step 909, step 911 updates the OCB constraint counter k to k←min{k+1,K}. At the end of step 911, if there are still OCB constraints left, the OCB constraint counter k points to the next OCB constraint 322 to be processed. If all OCB constraints 322 have been processed, the value of k remains at K.

[0159] Steps 910 and 911 are followed by a register update step 912, in which the contents of the register array r are updated to r by following the order h=1, 2, ..., m-1. h ←r h+1 +v i g h , then r m ←v i g m Here, r1 acts as the feedforward variable s.

[0160] The next step after step 912 is output step 913, in which method 900 outputs the i-th element w of TOB w 315. i Optionally, the method 500 may output the ith element v of the TIB v 314. i As part of output step 913.

[0161] After outputting step 913, method 900 loops back to step 904 and continues operating as described above.

[0162] The complexity of method 900 is O(mN), which is the same as the complexity of method 500, but can be significantly smaller than the complexity O(N) of method 400 when m is small compared to N. 2 ).

[0163] Method 900 can be simplified by eliminating all "minimum" operations as in the case of method 400. As in the case of method 400, when the diagonal elements of the IUT transform U are all 1 ( multiplication identity in ) or when the transformation is in the binary domain As above, another simplification occurs in the implementation of method 900 .

[0164] Figure 9B is a diagram illustrating in tabular form an exemplary calculation 950 according to method 900. The exemplary calculation 950 uses an exemplary transposed matrix U 952, an exemplary CTI b 953, an exemplary FDB a 954, and an exemplary OCBγ 955. Assume that the exemplary calculation 950 is in the binary domain. By examining the exemplary parameters b 953 and a 954, we understand that the length parameters in the exemplary calculation 950 are N=8 and K=3. The details of the exemplary calculation 950 are shown in Table 951. The i-th row of Table 951 lists the values ​​of the variables of method 900, where these values ​​are sampled immediately after the FDB constraint processing step 908 or the OCB constraint processing step 909 is completed. At the end of the exemplary calculation 950, the exemplary TIB v 956 and the exemplary TOB w 957 are obtained. It can be easily verified that the exemplary variables 952-957 satisfy the transformation constraint w=vU 321, the FDB constraint and OCB constraints in and

[0165] Note that the input parameters are the same for exemplary calculation 550 and exemplary calculation 950. As expected, both 550 and 950 produce the same TIB v 314 and the same TOB w 315 as output.

[0166] Next, we present the hardware implementation of the method 900 based on the transposed convolution circuit 800 .

[0167] Figure 10 FIG1 is a schematic diagram of a transposed form IUT Toeplitz encoder circuit 1000 according to an embodiment of the present invention. The transposed form IUT Toeplitz encoder circuit 1000 (hereinafter referred to as circuit 1000) is a way to implement method 900 in hardware using commonly available digital logic elements (such as adders, multipliers, random access memories, shift registers, and multiplexers). Circuit 1000 includes an element a for receiving FDB a 313. j FDB input port 1001, for receiving element γ of OCBγ312 k OCB input port 1002, element b for receiving CTI b i CTI input port 1003, element w for sending TOB w 315 i The TOB output port 1004 and the element v for sending the TIB v 314 i TIB output port 1005.

[0168] Circuit 1000 also includes a transposed form feedforward calculation circuit 1010, a first multiplexer MUX1 1020, and a second multiplexer MUX2 1030. Circuit 1000 follows the steps of method 900. Certain steps in the implementation of method 900 are not explicitly shown in circuit 1000 to avoid cluttering circuit 1000 with unnecessary detail. In particular, the clock circuitry, control logic, and storage elements used to maintain FDB a 313, OCBγ 312, and CTI b are not shown in circuit 1000. Logic circuitry for initializing and incrementing counters j, k, and i, which are used to retrieve element β from their respective storage locations, is also not shown in circuit 1000. j , γ k and b i A person skilled in the art of digital circuit design will have no difficulty completing these routine details of circuit 1000 in order to obtain a complete implementation of method 900.

[0169] The transposed form feedforward calculation circuit 1010 is inspired by the transposed form convolution circuit 800. The function of the transposed form feedforward calculation circuit 1010 is to execute step 912 of the method 900. The transposed form feedforward calculation circuit 1010 receives the element v of the TIB v 314. i As input, it generates r1 as the feedforward variable s at its output. As in step 903 of method 900, at the start of the operation, the contents of the registers within the transposed form feedforward calculation circuit 1010 are initialized to 0.

[0170] Multiplexers MUX1 1020 and MUX2 1030 are conventional 2-to-1 multiplexers commonly used in digital circuits. Specifically, the 2-to-1 multiplexer employed here has two input ports, IN1 and IN0, a control port SEL, and an output port OUT. When the signal at the control port SEL is a logic 1 (or logic 0, respectively), the 2-to-1 multiplexer forwards the logic signal at the input port IN1 (or input port IN0, respectively) to the output port OUT.

[0171] The constraint type checking step 907 is implemented by connecting the CTI input port 1003 to the SEL ports 1023 and 1033 of multiplexers MUX1 1020 and MUX2 1030, respectively.

[0172] When b i = 0, the first multiplexer MUX1 1020 converts the signal a j The signal is routed from the input port IN0 1021 to the output port OUT 1024, and the second multiplexer MUX2 1030 converts the signal a j g0+r1 is routed from input port IN0 1031 to output port OUT 1034. Therefore, when bi = 0, the signal at the TOB output port 1004 is obtained as w i =a j g0+r1, and the signal at the TIB output port 1005 is obtained as v i =a j , as required by step 908 of method 900. When b i =0, the control logic updates the FDB constraint counter j according to step 910 of method 900 .

[0173] When b i =1, the first multiplexer MUX1 1020 converts the signal (γ k -r1)(g0) -1 The signal γ is routed from the input port IN1 1022 to the output port OUT 1024, and the second multiplexer MUX2 1030 converts the signal γ k Routed from input port IN1 1032 to output port OUT 1034. Therefore, when b i = 1, the signal at the TOB output port 1004 is obtained as w i =γ k , and the signal at the TIB output port 1005 is obtained as v i =(γ k -r1)(g0) -1 , as required by step 909 of method 900. When b i =1, the control logic updates the OCB constraint counter k according to step 911 of method 900 .

[0174] At the end of round i, the signal v i The next input of the feedforward calculation circuit 1010 is converted into a transposed form, and the registers r1, r2, ..., r are updated according to step 912 of the method 900. m-1 After the above description, those skilled in the art will have no difficulty in implementing circuit 1000 so that it performs as described in method 900. Those skilled in the art will also recognize various alternative implementations of method 900 that involve pipelining and parallelization to reduce processing latency and increase throughput.

[0175] The embodiments of the present invention principles described above can be modified or expanded in several ways to obtain alternative embodiments. We will list some of these alternatives.

[0176] In some implementations of the outer encoder 302, it may be preferable to use a dual method. The idea of ​​the dual method is to use the dual set of parameters to replace the original set of parameters of the outer encoder 302 In the dual method, the above method is applied to the dual case. We will state two basic results that form the basis of the dual method.

[0177] Proposition 4. For any N ≥ 1, the class of all N*N IUT matrices forms a group under matrix multiplication; in other words, the product of two IUT matrices is an IUT matrix, and the inverse of an IUT matrix is ​​an IUT matrix.

[0178] We omit the proof of Proposition 4 because it is a well-known result.

[0179] Proposition 5. The class of all N*N IUT Toeplitz matrices forms a group under matrix multiplication. Let For the first row The IUT Toeplitz matrix. Then, U -1 is the IUT Toeplitz matrix, which has for k = 1, 2, ..., N-1 the recursive formula h0 = (1 / g0) and The first line given Equivalently, the polynomial g(D) = g0 + g1D + ... + g N-1 D N-1 and h(D)=h0+h1D+…+h N-1 D N-1 By h(D) = [1 / g(D)] mod D N .Related.

[0180] We omit the proof of Proposition 5 because it is a known result (see, for example, D. Commenges and M. Monsion, “Fast inversion of triangular Toeplitz matrices,” IEEE Transactions on Automatic Control, vol. 29, no. 3, pp. 250–251, March 1984).

[0181] The following example shows that in some cases the dual Toeplitz transform may not be too complex to implement.

[0182] Sample Command is the IUT Toeplitz matrix with the first row g = (1,1,1,1,0,0,0,0,1,1,0,1,1,0,1,0). By Proposition 5, the inverse is the IUT Toeplitz matrix with a first row h = (1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0). We observe that g(D) has degree 14 and h(D) has degree 10. Therefore, implementing circuits 700 and 1000 using the dual polynomial h(D) requires 10 shift registers compared to when using g(D).

[0183] We omit the details of the dual method for implementing the outer encoder 302, as those skilled in the art will have no difficulty in implementing such a method from the above description. Next, we turn to another direction in which the principles of the present invention can be extended.

[0184] In the above embodiments of the present invention, for example Figure 3 For the purposes of this presentation, we assume that the outer transform matrix is ​​an IUT matrix and the inner transform is an ILT matrix. A person skilled in the art will readily appreciate that the principles of the present invention can be applied to perform systematic encoding on any code whose generator matrix G is split into the product G=AB of the outer transform A and the inner transform B, where A=PUQ and B=RLS for some IUT matrix U, ILT matrix L, and permutation matrices P, Q, R, S. A person skilled in the art will be able to modify the system encoder 300 (and its Figure 4A 、 Figure 5A 、 Figure 7 、 Figure 9A and Figure 10 ), to implement a system encoder based on a modified triangular decomposition G=AB.

[0185] Another extension of the principles of the present invention is as follows. In the above-described systematic encoding process of TF codes, we assume that the various transforms considered are represented by square matrices. The principles of the present invention can be extended to the case where systematic encoding is desired for a code with a generator matrix, where the generator matrix is ​​specified as a non-square matrix. In this case, the non-square generator matrix can be expanded by additional rows or columns to make it a square matrix, and the triangular decomposition of the resulting square matrix can be used in combination with the principles of the present invention to obtain a systematic encoder for the code. All such embodiments that explicitly or implicitly use the principles of the present invention fall within the scope of the principles of the present invention.

[0186] Finally, we note that the principles of the present invention can be readily applied to code shortening. Shortening is a method of providing flexibility with respect to code length. Several code families have some natural code length dictated by the way the code is constructed. The natural code length of a given code may not be suitable for the special requirements of a particular application, in which case it is desirable to have a method for adjusting the code length. In shortening, a portion of the TCB is set equal to a fixed shortening block (FSB), where the FSB is a fixed pattern of symbols (usually an all-zero pattern). The TCB is shortened by not sending the FSB on the transmission channel. When shortening is applied, it is common practice to ensure that the decoder in the system is aware of the FSB so that it can recover the lost portion of the TCB before starting the decoding task.

[0187] For joint shortening and systematic encoding of TF codes, the principles of the present invention can be applied by embedding the FSB in the SDB. If shortening of non-systematic encoding of TF codes is desired, the SDB can be embedded in the FDB, and systematic encoding according to the principles of the present invention can be performed using the FSB embedded in the TCB as if it were an SDB.

[0188] This completes our description of various embodiments of the present principles. We now turn to some examples of communication systems in which the present principles may be employed.

[0189] Figure 11 An example wireless network is illustrated within which data encoding in error correction coding using triangular transforms may be implemented according to the present invention. Figure 11 The embodiment of wireless network 1100 shown is for illustration only. Other embodiments of wireless network 1100 may be used without departing from the scope of the present invention. Wireless network 1100 includes eNodeB (eNB) 1101, eNB 1102, and eNB 1103. eNB 1101 communicates with eNB 1102 and eNB 1103. eNB 1101 also communicates with at least one Internet Protocol (IP) network 1130, such as the Internet, a proprietary IP network, or other data network.

[0190] Depending on the type of network, other well-known terms may be used instead of "eNodeB" or "eNB", such as "base station" or "access point". For convenience, the terms "eNodeB" and "eNB" are used in this patent document to refer to network infrastructure components that provide wireless access to remote terminals. Also, depending on the type of network, other well-known terms may be used instead of "user equipment" or "UE", such as "mobile station" (or "MS"), "subscriber station" (or "SS"), "remote terminal", "wireless terminal" or "user device". For convenience, the terms "user equipment" and "UE" are used in this patent document to refer to a remote wireless device that wirelessly accesses an eNB, regardless of whether the UE is a mobile device (such as a mobile phone or smartphone) or is generally considered to be a fixed device (such as a desktop computer or vending machine).

[0191] eNB 1102 provides wireless broadband access to a network 1130 for a plurality of first user equipment (UEs) within a coverage area 1120 of eNB 1102. The plurality of first UEs include: UE 1111, which may be located in a small business (SB); UE 1112, which may be located in an enterprise (E); UE 1113, which may be located in a WiFi hotspot (HS); UE 1114, which may be located in a first residence (R1); UE 1115, which may be located in a second residence (R2); and UE 1116, which may be a mobile device (M) such as a cellular phone, wireless laptop, wireless personal digital assistant (PDA), tablet computer, etc. eNB 1103 provides wireless broadband access to a network 1130 for a plurality of second UEs within a coverage area 1125 of eNB 1103. The plurality of second UEs include UE 1115 and UE 1116. In some embodiments, one or more of the eNBs 1101-1103 may communicate with each other and with the UEs 1111-1116 using 3G, 4G or 5G, Long Term Evolution (LTE), LTE-A, WiMAX, or other advanced wireless communication technologies.

[0192] Dashed lines illustrate the approximate extents of coverage areas 1120 and 1125, which are shown as generally circular for purposes of illustration and explanation only. It should be clearly understood that coverage areas associated with eNBs, such as coverage areas 1120 and 1125, may have other shapes, including irregular shapes, depending on the configuration of the eNB and variations in the radio environment associated with natural and man-made obstacles.

[0193] As described in more detail below, one or more of eNB 1101, eNB 1102, and eNB 1103 include a 2D antenna array as described in embodiments of the present invention. In some embodiments, one or more of eNB 1101, eNB 1102, and eNB 1103 supports codebook design and structure for systems with 2D antenna arrays.

[0194] although Figure 11 An example of a wireless network 1100 is illustrated, but may be used for Figure 11Various changes may be made. For example, wireless network 1100 may include any number of eNBs and any number of UEs in any suitable arrangement. Furthermore, eNB 1101 may communicate directly with any number of UEs and provide these UEs with wireless broadband access to network 1130. Similarly, each of eNBs 1102 and 1103 may communicate directly with network 1130 and provide the UEs with direct wireless broadband access to network 1130. Furthermore, eNBs 1101, 1102, and / or 1103 may provide access to other or additional external networks, such as an external telephone network or other type of data network.

[0195] As described in further detail below, the example channel decoding systems depicted in the figures and described above may be implemented in an eNB (eg, eNB 1102) and / or a UE (eg, UE 1116).

[0196] Figure 12A An example user equipment network is illustrated within which data encoding in error correction coding using triangular transforms may be implemented according to the present invention. Figure 12A The illustrated embodiment of the UE 1116 is for illustration only, and Figure 11 UEs 1111-1115 may have the same or similar configurations. However, UEs appear in a variety of configurations, and Figure 12A The scope of the present invention is not limited to any particular implementation of a UE.

[0197] UE 1116 includes an antenna 1205, a radio frequency (RF) transceiver 1210, a transmit (TX) processing circuit 1215 (which may be Figure 1 ), a microphone 1220, and a receive (RX) processing circuit 1225 (which may be part of the transmit subsystem 110 in FIG. Figure 1 1260). The UE 1116 also includes a speaker 1230, a main processor 1240, an input / output (I / O) interface (IF) 1245, a keypad 1250, a display 1255, and a memory 1260. The memory 1260 includes a basic operating system (OS) program 1261 and one or more applications 1262. One of the OS program 1261 and the application 1262, or some combination thereof, can implement the following: Figures 1 to 10 The various embodiments described herein are for programming using error correction coding.

[0198] RF transceiver 1210 receives an incoming RF signal from antenna 1205, transmitted by an eNB of network 1100. RF transceiver 1210 may downconvert the incoming RF signal to generate an intermediate frequency (IF) or baseband signal, which is sent to receiver (Rx) processing circuitry 1225. Rx processing circuitry 1225 sends the processed signal to speaker 1230 (e.g., for voice data) or to main processor 1240 for further processing (e.g., for web browsing data).

[0199] Transmit (Tx) processing circuitry 1215 receives analog or digital voice data from microphone 1220 or other output baseband data (e.g., network data, email, or interactive video game data) from host processor 1240 as at least some input data for the source data block. Tx processing circuitry 1215 performs encoding. RF transceiver 1210 receives the processed baseband or IF signal output from Tx processing circuitry 1215 and up-converts the baseband or IF signal into an RF signal for transmission via antenna 1205.

[0200] The main processor 1240 may include one or more processors or other processing devices and execute a basic OS program 1261 stored in the memory 1260 to control the overall operation of the UE 1116. For example, the main processor 1240 may control the reception of forward channel signals and the transmission of reverse channel signals by the RF transceiver 1210, the Rx processing circuit 1225, and the Tx processing circuit 1215 according to well-known principles. In some embodiments, the main processor 1240 includes at least one programmable microprocessor or microcontroller, while in other embodiments, the main processor includes dedicated circuits (e.g., for systematic and / or non-systematic encoding or decoding processes, shortening processes, data mapping, etc.) and (optionally) programmable logic or processing circuits.

[0201] The main processor 1240 is also capable of executing other processes and programs residing in the memory 1260, such as operations for channel quality measurement and reporting for systems with 2D antenna arrays. The main processor 1240 can move data and / or instructions into or out of the memory 1260 as required by the executing process. In some embodiments, the main processor 1240 is configured to execute applications 1262 based on the OS program 1261 or in response to signals received from the eNB or operator. The main processor 1240 is also coupled to the I / O interface 1245, which provides the UE 1116 with the ability to connect to other devices, such as laptops and handheld computers. The I / O interface 1245 is the communication path between these accessories and the main processor 1240.

[0202] The main processor 1240 is also coupled to a keypad 1250 (which may be simply a single button or may be an array or other group of buttons) and a display unit 1255. The operator of the UE 1116 may use the keypad 1250 to enter data into the UE 1116. The display 1255 may be a touch screen display or other display capable of presenting text and / or at least limited graphics (e.g., from a website) and receiving touch input from the user in accordance with known practices.

[0203] The memory 1260 is coupled to the main processor 1240, and at least a portion of the memory 1260 may include a random access memory (RAM), and another portion of the memory 1260 may include a flash memory or other read-only memory (ROM).

[0204] although Figure 12A An example of UE 1116 is shown, but the Figure 12A Make various changes. For example, Figure 12A The various components in the can be combined, further subdivided, or omitted, and additional components can be added as needed. As a specific example, the main processor 1240 can be divided into multiple processors, such as one or more central processing units (CPUs), one or more application specific integrated circuits (ASICs), one or more field programmable gate arrays (FPGAs), and one or more graphics processing units (GPUs). Moreover, although Figure 12A The UE 1116 is illustrated as being configured as a mobile phone or smartphone, but the UE may be configured to operate as other types of mobile or stationary devices.

[0205] Figure 12B An example enhanced Node B (eNB) network is illustrated within which data encoding in error correction coding using triangular transforms may be implemented according to the present invention. Figure 12B The embodiment of the eNB 1102 shown is for illustration only and Figure 11 Other eNBs may have the same or similar configuration. However, eNBs appear in a variety of configurations, and Figure 12B The scope of the present invention is not limited to any particular implementation of an eNB. Note that eNB 1101 and eNB 1103 may include the same or similar structure as eNB 1102.

[0206] like Figure 12BAs shown, the eNB 1102 includes multiple antennas 1270a-1270n, multiple RF transceivers 1272a-1272n, transmit (Tx) processing circuitry 1274, and receive (Rx) processing circuitry 1276. In some embodiments, one or more of the multiple antennas 1270a-1270n include a 2D antenna array. The eNB 1102 also includes a controller / processor 1278, memory 1280, and a backhaul or network interface 1282.

[0207] RF transceivers 1272a-1272n receive incoming RF signals from antennas 1270a-1270n, such as signals transmitted by a UE or other eNB. RF transceivers 1272a-1272n downconvert the incoming RF signals to generate IF or baseband signals. The IF or baseband signals are sent to Rx processing circuitry 1276, which filters, decodes, and / or digitizes the baseband or IF signals to generate processed signals. Rx processing circuitry 1276 sends the processed signals to controller / processor 1278 for further processing.

[0208] The Tx processing circuit 1274 receives analog or digital data (e.g., voice data, network data, email, or interactive video game data) from the controller / processor 1278 as at least some input data for the source data block 11. The Tx processing circuit 1274 implements circuitry that encodes, multiplexes, and / or digitizes the output baseband data to generate processed signals. The RF transceivers 1272a-1272n receive the output processed signals from the Tx processing circuit 1274 and up-convert the baseband or IF signals into RF signals for transmission via the antennas 1270a-1270n.

[0209] The controller / processor 1278 may include one or more processors or other processing devices that control the overall operation of the eNB 1102. For example, the controller / processor 1278 may control the reception of forward channel signals and the transmission of reverse channel signals by the RF transceivers 1272a-1272n, the Rx processing circuitry 1276, and the Tx processing circuitry 1274 in accordance with well-known principles. The controller / processor 1278 may also support additional functionality (e.g., more advanced wireless communication functionality). The controller / processor 1278 may support any of a variety of other functions within the eNB 1102. In some embodiments, the controller / processor 1278 includes at least one microprocessor or microcontroller, while in other embodiments, the main processor includes dedicated circuitry (e.g., for systematic and / or non-systematic encoding processes, shortening processes, data mapping, etc.) and, optionally, programmable logic or processing circuitry.

[0210] The controller / processor 1278 can also execute programs and other processes residing in the memory 1280, such as the base operating system. The controller / processor 1278 can also support channel quality measurement and reporting for systems with 2D antenna arrays. In some embodiments, the controller / processor 1278 supports communication between entities. The controller / processor 1278 can move data and / or instructions into or out of the memory 1280 as needed by the executing process.

[0211] The controller / processor 1278 is also coupled to a backhaul or network interface 1282. The backhaul or network interface 1282 allows the eNB 1102 to communicate with other devices or systems via a backhaul connection or over a network. The interface 1282 may support communication over any suitable wired or wireless connection. For example, when the eNB 1102 is implemented as part of a cellular communication system (e.g., a cellular communication system supporting 3G, 4G, 5G, LTE, or LTE-A), the interface 1282 may allow the eNB 1102 to communicate with other eNBs over a wired or wireless backhaul connection. When the eNB 1102 is implemented as an access point, the interface 1282 may allow the eNB 1102 to communicate over a wired or wireless local area network or over a wired or wireless connection to a larger network (e.g., the Internet). The interface 1282 includes any suitable structure (e.g., an Ethernet or RF transceiver) that supports communication over a wired or wireless connection.

[0212] Memory 1280 is coupled to controller / processor 1278. A portion of memory 1280 may include RAM, and another portion of memory 1280 may include flash memory or other ROM. In some embodiments, a plurality of instructions are stored in memory. The instructions are configured to cause controller / processor 1278 to perform systematic and / or non-systematic encoding or decoding processes, shortening processes, data mapping, and the like.

[0213] although Figure 12B An example of eNB 1102 is shown, but the Figure 12B Various changes may be made. For example, the eNB 1102 may include any number of the various components shown. As a specific example, the access point may include multiple interfaces 1282, and the controller / processor 1278 may support routing functions to route data between different network addresses. As another specific example, although shown as including a single instance of the Tx processing circuit 1274 and a single instance of the Rx processing circuit 1276, the eNB 1102 may include multiple instances of each (e.g., one for each RF transceiver).

[0214] Although specific embodiments of methods and apparatus for systematically encoding data in error-correcting codes using a triangular decomposition of a generator matrix are described in detail herein and depicted in the accompanying drawings, it should be understood that the subject matter covered by the present invention is limited only by the claims. Although the present invention has been described using exemplary embodiments, various changes and modifications may be devised by those skilled in the art. The present invention is intended to cover such changes and modifications as fall within the scope of the appended claims. The description in this application should not be construed as implying that any particular element, step, or function is essential or critical to be included in the scope of the claims: the scope of the patented subject matter is limited only by the allowed claims. Moreover, none of the claims is intended to invoke 35 USC §112(f) with respect to any of the appended claims or claim elements unless the exact words "means for" or "step for" are expressly used in a particular claim, followed by a participle phrase identifying the function. The use of terms such as (but not limited to) “mechanism,” “module,” “device,” “unit,” “component,” “element,” “member,” “device,” “machine,” “system,” “processor,” or “controller” within the claims is understood and intended to refer to structures known to persons skilled in the relevant art, as further modified or enhanced by the features of the claims themselves, and is not intended to invoke 35 USC §112(f).

Claims

1. A system encoder apparatus for reliably transmitting a source data block SDB in a communication system, the system encoder apparatus being configured for an outer transform matrix and an inner transform matrix, the system encoder apparatus comprising: Internal encoder; and External encoder, The inner encoder is configured to obtain the SDB and generate an output constraint block OCB, wherein the OCB is the SDB multiplied by the inverse matrix of the submatrix of the inner transformation matrix. wherein the outer encoder is configured to obtain a fixed data block FDB and the OCB, and generate a transform output block TOB, the TOB being subject to a first systematic coding constraint that the TOB is a transform input block TIB multiplied by the outer transform matrix, a second systematic coding constraint that the TOB contains the OCB in a sub-block of the TOB, and a third systematic coding constraint that the TIB contains the FDB in a sub-block of the TIB, The inner encoder is further configured to obtain the TOB and generate a transmitted code block TCB, wherein the TCB is subject to a fourth systematic coding constraint that the TCB is the TOB multiplied by the inner transformation matrix and a fifth systematic coding constraint that the TCB contains the SDB in a sub-block of the TCB.

2. The system encoder device according to claim 1, wherein: The external transformation matrix is ​​a reversible upper triangular IUT matrix, wherein the sub-block of the TOB includes elements whose indices of the TOB belong to an index set, and The sub-block of the TIB includes elements whose indexes of the TIB belong to the complement of the index set.

3. The system encoder device according to claim 2, wherein: The inner transformation matrix is ​​a reversible lower triangular ILT matrix, wherein the submatrix of the inner transformation matrix includes elements whose column indices of the inner transformation matrix belong to the index set and whose row indices belong to the index set, and The sub-block of the TCB includes elements whose indexes of the TCB belong to the index set.

4. The system encoder device according to claim 2, wherein: The outer encoder includes a feedforward computation circuit, and The feedforward calculation circuit is configured to receive a sequence of TIB elements and generate a feedforward value for each received TIB element.

5. The system encoder device according to claim 4, wherein: The outer transformation matrix is ​​the IUT Toeplitz matrix, and The feedforward calculation circuit includes a convolution circuit, which includes a plurality of registers, a multiplier, and an adder. The convolution circuit is configured according to an impulse response, which is derived from the first row of the IUT Toeplitz matrix.

6. The system encoder device according to claim 5, wherein: The outer encoder is further configured to use the feedforward value along with a current element of the FDB or a current element of the OCB to generate a next element of the TIB and a next element of the TOB.

7. A method for reliably transmitting a source data block (SDB) in a communication system, the method employing a system encoder apparatus configured for an outer transform matrix and an inner transform matrix, the method comprising: An inner encoder is configured to obtain the SDB and generate an output constraint block OCB, the OCB being the SDB multiplied by an inverse matrix of a submatrix of the inner transform matrix; as well as an outer encoder configured to obtain a fixed data block FDB and the OCB, and generate a transform output block TOB, the TOB being subject to a first systematic coding constraint that the TOB is a transform input block TIB multiplied by the outer transform matrix, a second systematic coding constraint that the TOB contains the OCB in a subblock of the TOB, and a third systematic coding constraint that the TIB contains the FDB in a subblock of the TIB, The inner encoder is further configured to obtain the TOB and generate a transmitted code block TCB, wherein the TCB is subject to a fourth systematic coding constraint that the TCB is the TOB multiplied by the inner transformation matrix and a fifth systematic coding constraint that the TCB contains the SDB in a sub-block of the TCB.

8. The method according to claim 7, wherein: The external transformation matrix is ​​a reversible upper triangular IUT matrix, wherein the sub-block of the TOB includes elements whose indices of the TOB belong to an index set, and The sub-block of the TIB includes elements whose indexes of the TIB belong to the complement of the index set.

9. The method according to claim 8, wherein The inner transformation matrix is ​​a reversible lower triangular ILT matrix, wherein the submatrix of the inner transformation matrix includes elements whose row indices belong to the index set and whose column indices belong to the index set, and The sub-block of the TCB includes elements whose indexes of the TCB belong to the index set.

10. The method according to claim 9, wherein: The outer encoder includes a feedforward calculation circuit, and wherein the feedforward calculation circuit is configured to receive a sequence of TIB elements and generate a feedforward value for each received TIB element.

11. The method according to claim 10, wherein: The outer transformation matrix is ​​the IUT Toeplitz matrix, and The feedforward calculation circuit includes a convolution circuit, which includes a plurality of registers, a multiplier, and an adder. The convolution circuit is configured according to an impulse response obtained from the first row of the IUT Toeplitz matrix.

12. The method according to claim 11, wherein The outer encoder is further configured to use the feedforward value along with a current element of the FDB or a current element of the OCB to generate a next element of the TIB and a next element of the TOB.

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