Method of forming an interconnect structure
By forming a multi-layer mask structure on the dielectric layer and controlling the opening size and angle, the problem of forming high aspect ratio conductive dielectric windows was solved, enabling more efficient manufacturing of conductive features and improving the quality and reliability of semiconductor interconnect structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2022-03-07
- Publication Date
- 2026-05-22
Smart Images
Figure CN115050697B_ABST
Abstract
Description
Technical Field
[0001] The embodiments disclosed herein relate to an interconnect structure and a method for forming the same. Background Technology
[0002] As the semiconductor industry introduces next-generation integrated circuits (ICs) with higher efficiency and more functionality, the density of components forming ICs has increased, while the size, dimensions, and spacing between components have decreased. Previously, such miniaturization was limited only by the ability to define structures on lithography, but the geometry of smaller components creates new constraints. For example, as the aspect ratio of conductive features in the dielectric material of back-end interconnect structures becomes higher, the process of forming conductive dielectric windows becomes more difficult. Therefore, improved methods for forming interconnects are needed. Summary of the Invention
[0003] This disclosure provides a method for forming an interconnect structure, comprising forming a mask structure on a dielectric layer, the mask structure including a first layer disposed on the dielectric layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method further includes forming a first opening having a first size in the first layer, and forming a multilayer structure above the first layer. The multilayer structure includes a bottom layer disposed in the first opening and above the first layer, an intermediate layer disposed on the bottom layer, and a photoresist layer disposed on the intermediate layer. The bottom layer comprises a material different from the first, second, and third layers. The method further includes forming a second opening having a second size in the bottom layer to expose a portion of the dielectric layer, the second size being smaller than the first size. Each second opening has a coverage error ranging from about 2 nm to about 3 nm. The method further includes extending the second opening to the dielectric layer.
[0004] This disclosure provides a method for forming an interconnect structure, comprising forming a first opening of a first size in a first layer disposed on a dielectric layer, forming a second layer in and above the first opening, and forming a second opening of a second size in the second layer to expose a portion of the dielectric layer. The first layer and the second layer comprise different materials. The second size is smaller than the first size. The method further comprises extending the second opening into the dielectric layer, removing the second layer, and simultaneously extending the first opening into the dielectric layer and extending the second opening through the dielectric layer. A portion of the second opening is converted into the first opening. Each second opening has an opening angle ranging from about 115 degrees to about 120 degrees. The method further comprises forming second conductive features in the first and second openings in the dielectric layer. Each second conductive feature includes a first portion disposed above the second portion, and the first portion has a larger size than the second portion.
[0005] This disclosure provides a method for forming an interconnect structure, comprising forming a mask structure on a dielectric layer, the mask structure including a first layer disposed on the dielectric layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method further includes forming a first opening of a first size in the first layer, forming a fourth layer in the first opening and above the first layer, and forming a second opening of a second size in the fourth layer to expose a portion of the dielectric layer. The second size is smaller than the first size. The method further includes extending the second opening into the dielectric layer, each second opening having a bottom portion a distance from an etch stop layer disposed beneath the dielectric layer, the distance being approximately 5% to approximately 10% of the dielectric layer thickness. The method further includes removing the second layer, and simultaneously extending the first opening into the dielectric layer and extending the second opening through the dielectric layer. Attached Figure Description
[0006] The following detailed description, when read in conjunction with the accompanying drawings, will provide the best understanding of the various features disclosed herein. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased to make the discussion clear.
[0007] Figure 1A This is a perspective view of one of the multiple stages of manufacturing a semiconductor device structure according to some embodiments;
[0008] Figure 1B It is in accordance with some embodiments along Figure 1A The AA section is a side view of this stage of manufacturing a semiconductor device structure.
[0009] Figure 2 This is a cross-sectional side view of a stage in the manufacturing of a semiconductor device structure according to some embodiments;
[0010] Figures 3A to 3J These are cross-sectional side views of various stages of manufacturing the interconnect structure according to some embodiments;
[0011] Figure 4 It is based on some embodiments along Figure 3G The top view of the internal connecting line structure of section AA shown.
[0012] [Symbol Explanation]
[0013] 100: Semiconductor Component Structure
[0014] 102: Substrate
[0015] 108: Passage Area
[0016] 114: Quarantine Zone
[0017] 122: Gate spacer wall
[0018] 123: Fin-type sidewall spacer
[0019] 124: Source / Drain Region
[0020] 126: Contact Etching Stop Layer
[0021] 128: Interlayer dielectric layer
[0022] 136: Gate dielectric layer
[0023] 138: Gate electrode layer
[0024] 140: Gate Stack
[0025] 200: Components
[0026] 300: Internal Wiring Structure
[0027] 302: Intermetallic dielectric layer
[0028] 304: Electrical conductivity characteristics
[0029] 306: Electrical conductivity characteristics
[0030] 310: Dielectric layer
[0031] 312: Electrical conductivity characteristics
[0032] 314: First etch stop layer
[0033] 316: Second etch stop layer
[0034] 318: Dielectric layer
[0035] 320: Dome Structure
[0036] 322: First Floor
[0037] 324: Second layer
[0038] 326: Third Floor
[0039] 328: Opening
[0040] 329: Curved top
[0041] 330: Multi-layer structure
[0042] 332: Bottom layer
[0043] 334: Intermediate Layer
[0044] 336: Photoresist layer
[0045] 338: Opening
[0046] 340: Bottom
[0047] 342: Barrier Layer
[0048] 344: Electrical conductivity characteristics
[0049] 346: Part One
[0050] 348: Part Two
[0051] A: Opening angle of the mesopan window
[0052] AA: Line, Section
[0053] CD1: Key Dimensions
[0054] CD2: Key Bottom Dimensions
[0055] D: Distance
[0056] T: Coverage error Detailed Implementation
[0057] The following disclosure provides many different implementations or embodiments to implement different features of the provided object. Specific embodiments of the components and configurations described below are provided to simplify this disclosure. Of course, these are merely embodiments and not intended to be limiting. For example, in the description, forming a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, or implementations where additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or words may be repeated in various embodiments of this disclosure. This repetition is for the purpose of simplicity and clarity and is not, in itself, intended to specify relationships between the various implementations and / or architectures discussed.
[0058] In addition, this document may use spatial relation terms such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper,” and similar terms to concisely describe the relationship between one component or feature depicted in the accompanying drawings and another component or feature(s). Besides the directions depicted in the accompanying drawings, spatial relation terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and therefore the spatial relation descriptors used herein can be interpreted in the same manner.
[0059] Figure 1A and Figure 1B This diagram illustrates one stage in the fabrication of a semiconductor device structure 100. Figure 1A and Figure 1BAs shown, the semiconductor device structure 100 includes a substrate 102 and one or more devices 200 formed on the substrate 102. The substrate 102 may be a semiconductor substrate. In some embodiments, the substrate 102 includes at least a single-crystal semiconductor layer on the surface of the substrate 102. The substrate 102 may contain crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). For example, the substrate 102 is made of Si. In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate, including an insulating layer (not shown) disposed between two silicon layers. In one embodiment, the insulating layer is an oxygen-containing material, such as an oxide.
[0060] Substrate 102 may include one or more buffer layers (not shown) located on the surface of substrate 102. The buffer layers can be used to progressively change the lattice constant from the substrate to the lattice constant of the source / drain regions. The buffer layers may be formed from epitaxially grown crystalline semiconductor materials, such as, but not limited to, Si, Ge, germanium tin (GeSn), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In one embodiment, substrate 102 includes a SiGe buffer layer epitaxially grown on silicon substrate 102. The germanium concentration of the SiGe buffer layer may increase from 30 atomic percent germanium at the bottom layer to 70 atomic percent germanium at the top layer.
[0061] The substrate 102 may include different regions that have been appropriately doped with impurities (e.g., p-type or n-type impurities). The dopants are, for example, phosphorus for n-type fin field-effect transistors (FinFETs) and boron for p-type FinFETs.
[0062] As described above, element 200 can be any suitable element, such as a transistor, diode, image sensor, resistor, capacitor, inductor, memory cell, or a combination thereof. In some embodiments, element 200 is a transistor, such as a planar field-effect transistor (FET), FinFET, nanostructure transistor, or other suitable transistor. Nanostructure transistors may include nanosheet transistors, nanowire transistors, gate all-loop (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding a channel. An example of element 200 formed on substrate 102 is a FinFET, shown in... Figure 1A and Figure 1B In the middle. Component 200 includes source / drain (S / D) regions 124 and gate stack 140 (in Figure 1A (Only one is shown in the image). Each gate stack 140 may be disposed between the source / drain region 124 serving as the source region and the source / drain region 124 serving as the drain region. For example, each gate stack 140 may extend along the Y-axis between one or more source / drain regions 124 serving as the source region and one or more source / drain regions 124 serving as the drain region. Figure 1B As shown, two gate stacks 140 are formed on the substrate 102. In some embodiments, more than two gate stacks 140 are formed on the substrate 102. A channel region 108 is formed between the source / drain region 124, which serves as the source region, and the source / drain region 124, which serves as the drain region.
[0063] The source / drain region 124 may comprise a semiconductor material, such as Si or Ge, a III-V compound semiconductor, a II-VI compound semiconductor, or other suitable semiconductor materials. The exemplary source / drain region 124 may comprise, but is not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, and similar materials. The source / drain region 124 may comprise a p-type dopant, such as boron; an n-type dopant, such as phosphorus or arsenic; and / or other suitable dopant combinations thereof. The source / drain region 124 may be formed using epitaxial growth methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). Channel region 108 may comprise one or more semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, or InP. In some embodiments, channel region 108 comprises the same semiconductor material as substrate 102. In some embodiments, element 200 is a FinFET, and channel region 108 consists of a plurality of fins disposed below gate stack 140. In some embodiments, element 200 is a nanostructure transistor, and gate stack 140 surrounds channel region 108.
[0064] As shown in the figure Figure 1A and Figure 1BAs shown, each gate stack 140 includes a gate electrode layer 138 disposed above the channel region 108 (or surrounding the channel region 108 of the nanostructure transistor). The gate electrode layer 138 may be a metallic material, such as tungsten (W), cobalt (Co), aluminum (Al), ruthenium (Ru), copper (Cu), multiples thereof, or similar materials, and may be deposited using ALD, plasma-enhanced chemical vapor deposition (PECVD), MBD, physical vapor deposition (PVD), or any suitable deposition technique. Each gate stack 140 may also include a gate dielectric layer 136 disposed above the channel region 108. The gate electrode layer 138 may be disposed above the gate dielectric layer 136. In some embodiments, an interface layer (not shown) may be disposed between the channel region 108 and the gate dielectric layer 136, and one or more work function layers (not shown) may be formed between the gate dielectric layer 136 and the gate electrode layer 138. The interface dielectric layer may comprise a dielectric material, such as an oxygen-containing or nitrogen-containing material, or multiple layers thereof, and may be formed by any suitable deposition method, such as CVD, PECVD, or ALD. The gate dielectric layer 136 may comprise a dielectric material, such as an oxygen-containing or nitrogen-containing material, a high-k dielectric material having a k-value higher than that of silicon dioxide, or multiple layers thereof, and may be formed by any suitable method, such as CVD, PECVD, or ALD. In some embodiments, the gate dielectric layer 136 may be a conformal layer. The term "conformal" may be used herein to concisely describe layers having substantially the same thickness over different regions. One or more work function layers may comprise titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, or similar materials.
[0065] Gate spacer 122 is formed along the sidewalls of gate stack 140 (e.g., the sidewalls of gate dielectric layer 136). Gate spacer 122 may comprise silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbon nitride, similar materials, multilayers thereof, or combinations thereof, and may be deposited by CVD, ALD, or other suitable deposition techniques.
[0066] like Figure 1A As shown, finned sidewall spacers 123 may be disposed on opposite sides of each source / drain region 124, and the finned sidewall spacers 123 may comprise the same material as the gate spacers 122. A portion of the gate stack 140, gate spacers 122, and finned sidewall spacers 123 may be disposed on an isolation region 114. The isolation region 114 is disposed on a substrate 102. The isolation region 114 may comprise an insulating material, such as an oxygen-containing material, a nitrogen-containing material, or a combination thereof. In some embodiments, the isolation region 114 is a shallow trench isolation (STI). The insulating material may be fabricated using high-density plasma chemical vapor deposition (HDP-CVD), flow-through chemical vapor deposition (FCVD), or other suitable deposition processes. In one embodiment, the isolation region 114 comprises silicon oxide formed using an FCVD process.
[0067] like Figure 1A and Figure 1B As shown, a contact etch stop layer (CESL) 126 is formed on the source / drain region 124 and the isolation region 114, while an interlayer dielectric (ILD) layer 128 is formed on the contact etch stop layer 126. When an opening is formed within the interlayer dielectric layer 128, the contact etch stop layer 126 provides a mechanism to stop the etch process. The contact etch stop layer 126 may be conformally deposited on the surfaces of the source / drain region 124 and the isolation region 114. The contact etch stop layer 126 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbide nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, or similar materials, or combinations thereof, and may be deposited using CVD, PECVD, ALD, or any suitable deposition technique. The interlayer dielectric layer 128 may comprise an oxide formed using tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), organosilicon glass (OSG), silicon oxycarbide (SiOC), and / or any suitable low-k dielectric material (e.g., a material having a dielectric constant lower than that of silicon dioxide), and may be deposited by spin coating, CVD, FCVD, PECVD, PVD, or any suitable deposition technique.
[0068] Conductive contacts (not shown) may be disposed in the interlayer dielectric layer 128 and above the source / drain region 124. The conductive contacts may be conductive and comprise one or more of the following materials: Ru, molybdenum (Mo), Co, nickel (Ni), W, titanium (Ti), tantalum (Ta), Cu, Al, titanium nitride (TiN), or tantalum nitride (TaN). The conductive contacts may be formed by any suitable method, such as electrochemical plating (ECP) or PVD. A silicide layer (not shown) may be disposed between the conductive contacts and the source / drain region 124.
[0069] like Figure 2As shown, the semiconductor device structure 100 may further include an interconnect structure 300 disposed above the device 200 and the substrate 102. The interconnect structure 300 includes a plurality of conductive features, such as a first plurality of conductive features 304 and a second plurality of conductive features 306, and an inter-metal dielectric (IMD) layer 302 for separating and isolating the conductive features 304 and 306. In some embodiments, the first plurality of conductive features 304 are conductive lines, and the second plurality of conductive features 306 are conductive dielectric windows. The interconnect structure 300 includes several layers of conductive features 304, and the conductive features 304 are disposed in each layer to provide electrical pathways to the devices 200 disposed below. The conductive features 306 provide vertical electrical wiring from the device 200 to the conductive features 304, and between the conductive features 304. For example, the bottommost conductive feature 306 of the interconnect structure 300 may be electrically connected to the source / drain region 124 ( Figure 1B ) and above the gate electrode layer 138 ( Figure 1B The conductive contacts are conductive. Conductive features 304 and 306 may be made of one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, conductive features 304 and 306 may be made of copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, titanium nitride silicon, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten nitride silicon, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof.
[0070] The intermetallic dielectric layer 302 includes one or more dielectric materials to provide isolation for the conductive features 304 and 306. The intermetallic dielectric layer 302 may comprise several dielectric layers embedded with several conductive features 304 and 306. The intermetallic dielectric layer 302 is made of a dielectric material, such as SiO2. x SiO x C y H z or SiO x C y It is made by means of x, y, and z, where x, y, and z are integers or non-integers. In some embodiments, the intermetallic dielectric layer 302 comprises a dielectric material having a k value ranging from about 1 to about 5.
[0071] Figures 3A to 3J This is a cross-sectional side view of various stages in the manufacture of the interconnect structure 300 according to some embodiments. Figure 3A As shown, the interconnect structure 300 includes a dielectric layer 310, which can be an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer. For example, the dielectric layer 310 can be an interlayer dielectric layer 128 (…). Figure 1A and Figure 1B ) or intermetallic dielectric layer 302 ( Figure 2The dielectric layer 310 may comprise the same material as the interlayer dielectric layer 128 or the intermetallic dielectric layer 302. In some embodiments, the dielectric layer 310 may comprise a low-k dielectric material, such as SiOCH. The dielectric layer 310 may be formed using CVD, FCVD, ALD, spin coating, or other suitable processes. The dielectric layer 310 includes one or more conductive features 312 (only one shown) disposed therein. The conductive feature 312 may comprise a conductive material, such as Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, alloys thereof, or other suitable materials. In some embodiments, the conductive feature 312 comprises a metal. The conductive feature 312 may be formed using PVD, CVD, ALD, or other suitable processes. In some embodiments, the conductive feature 312 may be a conductive contact disposed in the interlayer dielectric layer 128, or a conductive feature 304 or 306 disposed in the intermetallic dielectric layer 302. In some embodiments, the conductive feature 312 includes a barrier layer (not shown) disposed between the dielectric layer 310 and the conductive material of the conductive feature 312. The barrier layer may contain a conductive material, such as a metal or a metal nitride.
[0072] A first etch stop layer 314 is disposed on the dielectric layer 310. The first etch stop layer 314 may comprise a nitrogen-containing material or an oxygen-containing material. For example, the first etch stop layer 314 may be a nitride or oxide, such as silicon nitride, metal nitride, silicon oxide, or metal oxide. In some embodiments, the first etch stop layer 314 comprises the same material as the contact etch stop layer 126. Figure 1A and Figure 1B The first etch stop layer 314 can be formed using any suitable process, such as CVD, PECVD, ALD, PEALD, or any suitable process. In some embodiments, the first etch stop layer 314 is a conformal layer formed by ALD. A second etch stop layer 316 is disposed on the first etch stop layer 314. The second etch stop layer 316 may contain a nitrogen-containing or oxygen-containing material, such as a nitride or oxide, for example, silicon nitride, metal nitride, silicon oxide, or metal oxide. The second etch stop layer 316 may be formed using the same process as the first etch stop layer 314. The second etch stop layer 316 contains a material different from the first etch stop layer 314. In some embodiments, the second etch stop layer 316 is not present. In some embodiments, a third etch stop layer (not shown) may be disposed on the second etch stop layer 316.
[0073] Another dielectric layer 318 is disposed on the second etch stop layer 316. The dielectric layer 318 may contain the same material as the dielectric layer 310 and may be formed using the same process as the dielectric layer 310.
[0074] like Figure 3BAs shown, a mask structure 320 is disposed on a dielectric layer 318. The mask structure 320 includes a first layer 322, a second layer 324 disposed on the first layer 322, and a third layer 326 disposed on the second layer 324. The first layer 322 and the third layer 326 may contain the same material, while the second layer 324 contains a material different from that of the first layer 322 and the third layer 326. The first layer 322 and the dielectric layer 318 contain different materials. In some embodiments, the first layer 322 and the third layer 326 each contain an oxide, such as silicon dioxide, and contain a material different from the low-k material of the dielectric layer 318, such as SiOCH. The second layer 324 may contain a nitride, such as a metal nitride, such as titanium nitride (TiN).
[0075] like Figure 3B As shown, opening 328 is formed in the third layer 326 and the second layer 324. Opening 328 can be formed in two etching processes. In some embodiments, opening 328 is formed using two dry etching processes with inductively coupled plasma (ICP). For example, a first ICP etching process is performed to form opening 328 in the third layer 326, and then a second ICP etching process is performed to extend opening 328 into the second layer 324. The etchants used in the two ICP etching processes are different to provide etch selectivity for the second layer 324 and the third layer 326. Due to the high radical density, the ICP etching process provides a high etching rate. Therefore, as Figure 3B As shown, when forming the opening 328 in the second layer 324, a portion of the first layer 322 may be removed. Therefore, the opening 328 may extend into a portion of the first layer 322.
[0076] like Figure 3CAs shown, opening 328 extends into the first layer 322, exposing the dielectric layer 318. Opening 328 extends into the first layer 322 by removing a portion of it. The partial removal of the first layer 322 can be performed using a dry etching process with capacitively coupled plasma (CCP). Unlike dry etching processes using ICP, CCP etching processes have a lower radical density, reducing the likelihood of over-etching. Therefore, the dielectric layer 318 is substantially unaffected. In some embodiments, the CCP etching process can be a dual-frequency etching process having a high radio frequency (RF) frequency ranging from about 30 MHz to about 80 MHz and a low RF frequency ranging from about 2 MHz to about 15 MHz. The RF power of the high RF frequency can range from about 200 W to about 1000 W, while the RF power of the low RF frequency can range from about 50 W to about 500 W. Because opening 328 in the first layer 322 is a trench, the high RF frequency is used for most of the CPP etching process, for example, about 90% of the time. The chamber pressure in the CPP etching process ranges from approximately 10 mT to approximately 80 mT, while the process temperature ranges from approximately 0 degrees Celsius to approximately 50 degrees Celsius. The etchant used in the CPP etching process may contain C... x F y Where x and y are integers. For example, C4F6 can be used as the etchant. Additional gases, such as N2, O2, Ar, H2, or CH4, can be used in the etching process. x F y Besides C x F y Other than or replacing C x F y These gases can be used. C x F y The flow rate ranges from approximately 20 sccm to approximately 50 sccm, the flow rate of N2 ranges from approximately 0 sccm to approximately 100 sccm, the flow rate of O2 ranges from approximately 0 sccm to approximately 25 sccm, the flow rate of Ar ranges from approximately 600 sccm to approximately 1200 sccm, the flow rate of H2 ranges from approximately 0 sccm to approximately 100 sccm, and the flow rate of CH... x F y The flow rate ranges from approximately 0 sccm to approximately 100 sccm. The DC self-bias voltage range for the CPP etching process ranges from approximately 0 V to approximately 500 V. The CPP etching process can also have a flow rate of less than... The deviation in trench depth between the center and the edge of the line.
[0077] Through the aforementioned CPP etching process, the opening 328 extends within the first layer 322, exposing the dielectric layer 318 without over-etching of the dielectric layer 318. For example... Figure 3CAs shown, since the third layer 326 contains the same material as the first layer 322, the CPP etching process removes the third layer 326. Figure 3B Furthermore, the remainder of the second layer 324 between adjacent openings 328 has a curved top 329. The curved top 329 facilitates the subsequent formation of a dielectric window opening in the dielectric layer 318.
[0078] like Figure 3D As shown, a multilayer structure 330 is disposed on the second layer 324. The multilayer structure 330 includes a bottom layer 332, an intermediate layer 334 disposed on the bottom layer 332, and a photoresist layer 336 disposed on the intermediate layer 334. In some embodiments, the multilayer structure 330 is a three-layer photoresist. The bottom layer 332 and the intermediate layer 334 are made of different materials, making their optical properties and / or etching properties different from each other. In some embodiments, the bottom layer 332 may be an absorption layer, such as a chromium layer. In some embodiments, the bottom layer 332 may be disposed at the opening 328 (…). Figure 3C The intermediate layer 334 may be a silicon-rich layer, designed to provide etch selectivity between the intermediate layer 334 and the bottom layer 332. The photoresist layer 336 may be a chemically amplified photoresist layer and may be a positive or negative photoresist. The photoresist layer 336 may contain polymers such as phenolic resins, poly(norbornene)-co-malaic anhydride (COMA) polymers, poly(4-hydroxystyrene) (PHS) polymers, phenol-formaldehyde (hakelite) polymers, polyethylene (PE) polymers, polypropylene (PP) polymers, polycarbonate polymers, polyester fiber polymers, or acrylate-based polymers, such as polymethyl methacrylate (PMMA) polymers or polymethyl methacrylate (PMAA) polymers. The photoresist layer 336 may be formed by spin coating.
[0079] like Figure 3DAs shown, photoresist layer 336 is patterned. Patterning of photoresist layer 336 may involve exposing photoresist layer 336 to light / beams through a photomask (not shown). The light / beams may be deep ultraviolet (DUV) light, such as KrF excimer lasers and ArF excimer lasers, extreme ultraviolet (EUV) light with a wavelength of approximately 13.5 nm, X-rays, and / or electron beams. In some embodiments, multiple exposure processes are performed. After the exposure processes, a development process is performed to form the patterned photoresist layer 336. As a result of the patterning process, an opening 338 is formed in photoresist layer 336, exposing a portion of the intermediate layer 334. The opening 338 may be an opening 328 that is more likely to be a trench in size. Figure 3C Small interlayer window opening.
[0080] like Figure 3E As shown, the pattern of photoresist layer 336 is transferred to intermediate layer 334 and bottom layer 332. In some embodiments, portions of bottom layer 332 and intermediate layer 334 are removed using two etching processes to transfer opening 338 thereon. For example, a first etching process is used to remove the exposed portion of intermediate layer 334 to expose a portion of bottom layer 332, and a second etching process is used to remove the exposed portion of bottom layer 332. In some embodiments, opening 338 formed in photoresist layer 336 may be slightly misaligned with portions of bottom layer 332 disposed between mask structures 320. However, because the etching selectivity between bottom layer 332 and first layer 322 and second layer 324 is substantially different, the dielectric layer 318 exposed in opening 338 has substantially the same critical dimension (CD) regardless of whether misalignment occurs. Therefore, the coverage error T of opening 338 can be higher, for example from about 2 nm to about 3 nm, and the critical dimension CD1 of opening 338 in dielectric layer 318 remains substantially consistent. In other words, even if misalignment occurs due to overlay, the critical dimension CD1 of the opening 338 in the dielectric layer 318 will not be substantially affected by the large overlay error T.
[0081] like Figure 3F As shown, by removing a portion of the dielectric layer 318, the opening 338 extends into the dielectric layer 318. An etching process, such as a dry etching process, can be used to remove a portion of the dielectric layer 318. The etching process can be a selective etching process that does not substantially affect the first layer 322 and the second layer 324. The opening 338 formed in the dielectric layer 318 does not extend through the dielectric layer 318. Figure 3FAs shown, the bottom 340 of the opening 338 formed in the dielectric layer 318 is separated from the second etch stop layer 316 by a distance D. In some embodiments, the distance D ranges from about 5% to about 10% of the thickness of the dielectric layer 318. The portion of the dielectric layer 318 below the opening 338 is then removed to form a dielectric window opening. Therefore, if the distance D is less than about 5% of the thickness of the dielectric layer 318, the subsequently formed dielectric window opening may have a large critical size. On the other hand, if the distance D is greater than about 10% of the thickness of the dielectric layer 318, the dielectric window opening may not extend through the dielectric layer 318.
[0082] like Figure 3G As shown, the multilayer structure 330 has been removed. The multilayer structure 330 can be removed using one or more etching processes. For example, a first etching process is performed to remove the photoresist layer 336. Figure 3F A second etching process is performed to remove the intermediate layer 334. Figure 3F Then a third etching process is performed to remove the underlying 332 ( Figure 3F Because the etching process can be a selective etching process, it does not substantially affect the mask structure 320 and the dielectric layer 318. As a result of the etching process, openings 328 are formed in the first layer 322 and the second layer 324. As described above, openings 328 are trenches, while openings 338 formed in the dielectric layer 318 are dielectric window openings.
[0083] Figure 4 According to some embodiments along Figure 3G The top cross-sectional view of the inner connecting line structure 300 of section AA is shown. Figure 4 As shown, an opening 328, which may be a trench, is formed in the first layer 322, and a portion of the dielectric layer 318 is exposed in the opening 328. An opening 338, which may be a dielectric window opening, is formed in the dielectric layer 318.
[0084] Back Figure 3H The opening 328, which can be a trench, extends into the dielectric layer 318, while the opening 338, which can be a dielectric window opening, extends through the dielectric layer 318 to expose a portion of the second etch stop layer 316. Furthermore, the portion of the opening 338 initially formed in the dielectric layer 318 becomes the opening 328. In other words, the portion initially formed in the dielectric layer 318 becomes the opening 328. Figure 3G The dielectric window opening (opening 338) in a portion of the dielectric layer 318 shown is enlarged to become formed in such a way as Figure 3HThe trench (opening 328) in the dielectric layer 318 is shown. Therefore, opening 328 (trench) and opening 338 are simultaneously formed in the dielectric layer 318. A single etching process is used to extend opening 328 from the first layer 322 to the dielectric layer 318, to partially change opening 338 into opening 328, and to extend opening 338 through the dielectric layer 318 to expose a portion of the second etch stop layer 316. For example, the etching process removes a portion of the dielectric layer 318 to form opening 328 in the dielectric layer 318 and extends opening 338 through the dielectric layer 318. Figure 3F As stated above, because the distance D between the bottom 340 and the second etch stop layer 316 is approximately 5% to approximately 10% of the thickness of the dielectric layer 318, the opening 338, formed simultaneously with the opening 328, has a relatively small bottom critical dimension CD2. Furthermore, because it is formed by removing a portion of the dielectric layer 318... Figure 3H The final openings 328 and 338 shown indicate that the etching time is shorter compared to a process that forms openings 328 and 338 by removing portions of the first layer 322 and the dielectric layer 318. For example, in another embodiment, the multilayer structure 330 is formed on... Figure 3B On the interconnect structure 300 shown, one or more etching processes are used to form dielectric window openings in the first layer 322 and the dielectric layer 318. Then, one or more etching processes are used to form trenches in the first layer 322 and the dielectric layer 318. Because several processes are used to remove different materials and more material to form openings 328 and 338 in the dielectric layer 318, the etching time is longer and over-etching may occur, resulting in enlarged bottom critical dimensions and enlarged dielectric window opening angles. Therefore, the process of forming opening 328 in the first layer before forming the initial opening 338 in the dielectric layer 318 is as follows: Figures 3C to 3F The process shown helps to reduce the bottom critical dimension CD2, reduce the dielectric window opening angle A, and expand the dielectric window opening path. In some embodiments, the dielectric window opening angle A ranges from about 115 degrees to about 120 degrees. If the dielectric window opening angle A exceeds the above range, the bottom critical dimension CD2 may be too large, resulting in a reduced breakdown voltage of the dielectric layer 318.
[0085] like Figure 3I As shown, one or more etching processes are performed to remove portions of the second etch stop layer 316 and portions of the first etch stop layer 314 to expose portions of the conductive features 312. These one or more etching processes may be selective etching processes that do not substantially affect the dielectric layer 318.
[0086] like Figure 3JAs shown, the mask structure 320 is removed, forming a barrier layer 342 in the openings 328 and 338, and a conductive feature 344 is formed on the barrier layer 342. The mask structure 320 can be removed using any suitable process. The barrier layer 342 may contain a conductive material, such as a metal or metal nitride, and the conductive feature 344 may contain the same material as the conductive feature 312. The conductive feature 344 includes a first portion 346 formed in each of the openings 338 and a second portion 348 formed in each of the openings 328. The second portion 348 of the conductive feature 344 formed in the opening 328 may be a conductive line, while the first portion 346 of the conductive feature 344 formed in the opening 338 may be a conductive dielectric window. The first portion 346 has a smaller dimension than the second portion 348. A planarization process, such as a chemical mechanical polishing (CMP) process, can be performed to planarize the material. Figure 3J The top surface of the interconnect structure 300 shown. Application. Figures 3A to 3J The described process is used to form conductive features, such as conductive lines and dielectric windows, and the process can be an improved dual damascene process.
[0087] This disclosure provides methods for forming conductive features in a dielectric layer in various embodiments. This method may be a dual damascene process. In some embodiments, this method includes forming an opening 328 in a first layer 322 disposed on a dielectric layer 318, then forming an opening 338 in the dielectric layer 318, and then simultaneously extending the opening 328 from the first layer 322 to the dielectric layer 318 and extending the opening 338 through the dielectric layer 318. Some embodiments offer advantages. For example, forming the opening 328 in the first layer before forming the initial opening 338 in the dielectric layer 318 helps reduce the bottom critical dimension CD2, reduce the dielectric window opening angle A, and increase the dielectric window opening path.
[0088] One embodiment is a method of forming an interconnect structure. The method includes forming a mask structure on a dielectric layer, the mask structure including a first layer disposed on the dielectric layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method further includes forming a first opening having a first size in the first layer, and forming a multilayer structure above the first layer. The multilayer structure includes a bottom layer disposed in the first opening and above the first layer, an intermediate layer disposed on the bottom layer, and a photoresist layer disposed on the intermediate layer. The bottom layer includes a material different from the first, second, and third layers. The method further includes forming a second opening having a second size in the bottom layer to expose a portion of the dielectric layer, the second size being smaller than the first size. Each of the second openings has a coverage error ranging from about 2 nm to about 3 nm. The method further includes extending the second opening to the dielectric layer. In some embodiments, the first layer includes a first material, the second layer includes a second material different from the first material, and the third layer includes the first material. In some embodiments, the first opening is a trench, and the second opening is a dielectric window opening. In some embodiments, the method further includes forming a first opening in a second and a third layer before forming a first opening in a first layer. In some embodiments, the first opening in the third layer is formed using a first process, and the first opening in the first layer is formed using a second process different from the first process. In some embodiments, the first process is an inductively coupled plasma etching process, and the second process is a capacitively coupled plasma etching process. In some embodiments, the method further includes forming a second opening in a photoresist layer and an intermediate layer before forming a second opening in a bottom layer. In some embodiments, the bottom layer comprises chromium, and the dielectric layer comprises SiOCH.
[0089] Another embodiment is a method for forming an interconnect structure. This method includes forming a first opening of a first size in a first layer disposed on a dielectric layer, forming a second layer in and above the first opening, and forming a second opening of a second size in the second layer to expose a portion of the dielectric layer. The first and second layers comprise different materials. The second size is smaller than the first size. The method further includes extending the second opening into the dielectric layer, removing the second layer, and simultaneously extending the first opening into the dielectric layer and extending the second opening through the dielectric layer. A portion of the second opening is converted into the first opening. Each second opening has an opening angle ranging from about 115 degrees to about 120 degrees. The method further includes forming second conductive features in the first and second openings in the dielectric layer. Each second conductive feature includes a first portion disposed above the second portion, and the first portion has a larger size than the second portion. In some embodiments, the first opening is a trench, and the second opening is a dielectric window opening. In some embodiments, the method further includes simultaneously extending the first opening into the dielectric layer and extending the second opening through the dielectric layer, followed by removing the first layer. In some embodiments, the method further includes forming a first etch stop layer, forming a second etch stop layer on the first etch stop layer, forming a dielectric layer on the second etch stop layer, forming a first layer on the dielectric layer, forming a third layer on the first layer, and forming a fourth layer on the third layer. In some embodiments, the fourth layer is removed during the formation of a first opening in the first layer. In some embodiments, the method further includes removing portions of the first etch stop layer and portions of the second etch stop layer after removing the first layer to expose portions of the first conductive feature. In some embodiments, the method further includes forming a plurality of barrier layers in the first and second openings in the dielectric layer, wherein at least some of the barrier layers are in contact with the first conductive feature. In some embodiments, a first portion of the second conductive feature is a conductive line, and a second portion of the second conductive feature is a conductive dielectric window.
[0090] Another embodiment is a method for forming an interconnect structure. This method includes forming a mask structure on a dielectric layer, the mask structure including a first layer disposed on the dielectric layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method further includes forming a first opening of a first size in the first layer, forming a fourth layer in the first opening and above the first layer, and forming a second opening of a second size in the fourth layer to expose a portion of the dielectric layer. The second size is smaller than the first size. The method further includes extending the second opening into the dielectric layer, each second opening having a bottom at a distance from an etch stop layer disposed under the dielectric layer, the distance being approximately 5% to approximately 10% of the dielectric layer thickness. The method further includes removing the second layer, and simultaneously extending the first opening into the dielectric layer and extending the second opening through the dielectric layer. In some embodiments, the method further includes forming the first opening in the first layer before forming the first opening in the first layer. In some embodiments, the third layer is removed during the formation of the first opening in the first layer. In some embodiments, during the formation of the first opening in the first layer, a portion of the second layer is removed to form a curved top.
[0091] The foregoing has outlined the features of several embodiments, thus enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.
Claims
1. A method for forming an interconnect structure, characterized in that, The method includes: A mask structure is formed on a dielectric layer, wherein the mask structure includes a first layer disposed on the dielectric layer, a second layer disposed on the first layer, and a third layer disposed on the second layer; A plurality of first openings having a plurality of first dimensions are formed in the first layer; A multi-layer structure is formed above the first layer, wherein the multi-layer structure includes a bottom layer disposed in the first openings and above the first layer, an intermediate layer disposed on the bottom layer, and a photoresist layer disposed on the intermediate layer, wherein the bottom layer includes a plurality of materials different from the first layer, the second layer, and the third layer. A plurality of second openings having a plurality of second dimensions are formed in the substrate to expose a portion of the dielectric layer, wherein the second dimensions are smaller than the first dimensions, and wherein each of the second openings has a coverage error ranging from substantially 2 nm to substantially 3 nm. The second openings are extended into the dielectric layer, wherein a portion of the second openings is converted into the first openings, and each of the second openings has an opening angle ranging from substantially 115 degrees to substantially 120 degrees. as well as A plurality of second conductive features are formed in the first openings and the second openings in the dielectric layer, wherein each of the second conductive features includes a first portion disposed above a second portion, the first portion having a plurality of dimensions larger than a plurality of dimensions of the second portion.
2. The method according to claim 1, characterized in that, The first layer contains a first material, the second layer contains a second material different from the first material, and the third layer contains the first material.
3. The method according to claim 2, characterized in that, The first openings are channels, and the second openings are mesoscopic window openings.
4. The method according to claim 3, characterized in that, The method further includes forming the first openings in the second and third layers before forming the first openings in the first layer.
5. The method according to claim 4, characterized in that, The first openings in the third layer are formed using a first process, and the first openings in the first layer are formed using a second process different from the first process.
6. The method according to claim 5, characterized in that, The first process is an inductively coupled plasma etching process, and the second process is a capacitively coupled plasma etching process.
7. The method according to claim 1, characterized in that, The method also includes forming the second openings in the photoresist layer and the intermediate layer before forming the second openings in the bottom layer.
8. The method according to claim 7, characterized in that, The bottom layer contains chromium, and the dielectric layer contains SiOCH.
9. A method for forming an interconnect structure, characterized in that, The method includes: A plurality of first openings having a plurality of first dimensions are formed in a first layer disposed on a dielectric layer; A second layer is formed in the first openings and above the first layer, wherein the first layer and the second layer contain different materials; A plurality of second openings having a plurality of second dimensions are formed in the second layer to expose portions of the dielectric layer, wherein the second dimensions are smaller than the first dimensions; Extend these second openings into the dielectric layer; Remove the second layer; Simultaneously, the first openings extend into the dielectric layer, and the second openings extend through the dielectric layer, wherein a portion of the second openings is converted into the first openings, wherein each of the second openings has an opening angle ranging from substantially 115 degrees to substantially 120 degrees. as well as A plurality of second conductive features are formed in the first openings and the second openings in the dielectric layer, wherein each of the second conductive features includes a first portion disposed above a second portion, the first portion having a plurality of dimensions larger than a plurality of dimensions of the second portion.
10. The method according to claim 9, characterized in that, The first openings are channels, and the second openings are mesoscopic window openings.
11. The method according to claim 10, characterized in that, The method also includes simultaneously extending the first openings into the dielectric layer and extending the second openings through the dielectric layer, and then removing the first layer.
12. The method according to claim 11, characterized in that, The method also includes: Form a first etch stop layer; A second etch stop layer is formed on the first etch stop layer; The dielectric layer is formed on the second etch stop layer; The first layer is formed on the dielectric layer; A third layer is formed on top of the first layer; as well as A fourth layer is formed on top of the third layer.
13. The method according to claim 12, characterized in that, The fourth layer is removed during the formation of the first openings in the first layer.
14. The method according to claim 12, characterized in that, The method further includes removing a portion of the first etch stop layer and a portion of the second etch stop layer after removing the first layer, to expose a portion of a first conductive feature.
15. The method according to claim 14, characterized in that, The method further includes forming a plurality of barrier layers in a first opening and a second opening in a dielectric layer, wherein at least some of the barrier layers are in contact with the first conductive feature.
16. The method according to claim 15, characterized in that, The first portion of the second conductive feature is a conductive line, and the second portion of the second conductive feature is a conductive dielectric window.
17. A method for forming an interconnect structure, characterized in that, The method includes: A mask structure is formed on a dielectric layer, wherein the mask structure includes a first layer disposed on the dielectric layer, a second layer disposed on the first layer, and a third layer disposed on the second layer; A plurality of first openings having a plurality of first dimensions are formed in the first layer; A fourth layer is formed in and above the first openings; A plurality of second openings having a plurality of second dimensions are formed in the fourth layer to expose portions of the dielectric layer, wherein the second dimensions are smaller than the first dimensions; The second openings extend into the dielectric layer, each of the second openings having a bottom at a distance from an etch stop layer beneath the dielectric layer, wherein the distance is substantially 5% to substantially 10% of the thickness of the dielectric layer; Remove the second layer; Simultaneously, the first openings extend into the dielectric layer and the second openings extend through the dielectric layer, wherein a portion of the second openings is converted into the first openings, and each of the second openings has an opening angle ranging from substantially 115 degrees to substantially 120 degrees. as well as A plurality of second conductive features are formed in the first openings and the second openings in the dielectric layer, wherein each of the second conductive features includes a first portion disposed above a second portion, the first portion having a plurality of dimensions larger than a plurality of dimensions of the second portion.
18. The method according to claim 17, characterized in that, The method further includes forming the first openings in the second and third layers before forming the first openings in the first layer.
19. The method according to claim 18, characterized in that, During the formation of the first openings in the first layer, the third layer is removed.
20. The method according to claim 19, characterized in that, During the formation of the first openings in the first layer, portions of the second layer are removed to form a plurality of curved tops.