Adaptive power-on reset generator system and method for programmable logic devices

Abstract

Systems and methods for providing adaptive power-on reset (POR) signals for programmable logic devices (PLDs) and / or other semiconductor devices are disclosed. An example adaptive POR signal generator includes a logic device configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage, detect a second supply voltage ramp traversal across a second threshold ramp voltage, and generate a POR signal based at least in part on a nominal operating voltage associated with the supply voltage and / or the supply voltage and / or the ramp time associated with the first and second supply voltage ramp traversals. The second threshold ramp voltage is higher than the first threshold ramp voltage, and the first and second threshold ramp voltages are lower than the nominal operating voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority and benefit to U.S. Provisional Patent Application No. 62 / 944,457, filed December 6, 2019, entitled “Ramp-Rate Delay for Power-On Reset,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates generally to programmable logic devices, and more specifically to power-on reset signal generators for such devices. Background Technology

[0004] Programmable logic devices (PLDs) (e.g., field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field-programmable systems-on-chip (FPSCs), or other types of programmable devices) can be configured with various user designs to achieve desired functionality. Typically, the user design is synthesized and mapped to configurable resources (e.g., programmable logic gates, lookup tables (LUTs), embedded hardware, or other types of resources) and the interconnects available in the specific PLD. The physical placement and routing of the user design used for synthesis and mapping can then be determined to generate configuration data for the specific PLD.

[0005] PLDs can be used to control and / or integrate large arrays of different types of user equipment, and both the PLD and other circuitry and / or circuitry elements of the user equipment can withstand a relatively wide range of different supply voltages (e.g., VCC, typically between 1.2V and 3.3V, + / - 10%). Such supply voltages are generally stable during the operation of the user equipment / PLD, but can vary during the typical power-up sequence of the user equipment and / or PLD (e.g., ramp-up, or initially set to a power-up value and then ramp-up to the operating value). Furthermore, PLDs and / or other logic devices fabricated using advanced integrated circuit processes (e.g., 28nm fully depleted silicon-on-insulator (FDSOI) process) can be implemented with I / O transistors (e.g., relatively thick gate transistors) and / or other circuitry elements that can only tolerate voltages up to approximately 1.8V + / - 10% (e.g., source / drain Vds, gate / source Vgs, gate / drain Vgd voltages) and are guaranteed for at least 10 years of operating life without reliability issues. Therefore, there is a need in the art to provide systems and methods for supplying voltage protection for PLDs, especially during the power-on period of the PLD and / or user equipment controlled by and / or integrated with the PLD. Attached Figure Description

[0006] Figure 1A block diagram of a programmable logic device (PLD) according to an embodiment of the present disclosure is shown.

[0007] Figure 2 A block diagram of a logic block for a PLD according to an embodiment of the present disclosure is shown.

[0008] Figure 3 A design process for a PLD according to an embodiment of the present disclosure is illustrated.

[0009] Figure 4 A block diagram of a user equipment including a PLD and one or more adaptive power-on reset (POR) signal generators according to an embodiment of the present disclosure is shown.

[0010] Figure 5 A block diagram of an adaptive POR signal generator according to an embodiment of the present disclosure is shown.

[0011] Figure 6 An adaptive POR signal generation process according to an embodiment of the present disclosure is illustrated.

[0012] The embodiments and advantages of this disclosure can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements shown in one or more of the figures, which are for illustrative purposes and not for limiting the scope of this disclosure. Detailed Implementation

[0013] This disclosure provides systems and methods for providing adaptive power-on reset (POR) signal generation to protect programmable logic devices (PLDs) and / or other circuit elements for use with or in conjunction with various user devices used in computing applications and architectures, as described herein. For example, semiconductor circuitry is typically present in systems or other devices that are turned on and off. While turning on power (or supplying power to) a device or system containing semiconductor circuitry may appear to a human as an instantaneous event, this is not entirely accurate within the time and power domain of the system or device containing semiconductor circuitry. When a system or device is turned on, power may not be immediately available for every component in the device, or may not be available for each component at the desired level or stability for operation. Devices and systems can hold semiconductor chips or components in a reset state until a suitable power supply is available. The POR signal can be used to indicate the availability of an appropriate supply voltage for a particular chip or chipset in a device or system. For example, as described herein, a given POR signal may be generated by a specific chip for itself, or it may be generated by multiple chips for use.

[0014] In the various embodiments described herein, it is desirable to allow a chip or certain portions of a chip or system to be turned on as quickly as possible. However, allowing a chip or other circuitry to be turned on before it has a suitable power supply carries the risk of causing the circuitry and / or chip to fail or be damaged. Furthermore, particularly for PLDs or other circuitry elements intended to be integrated with a variety of different user devices and / or for a variety of different applications, such chips may be supplied with multiple supply voltages, and in many embodiments, the adaptive POR signal generator described herein provides relatively rapid turn-on for certain portions of a chip (or subsets of circuitry in a chip, device, or system). Such aspects include situations where it is desirable to accelerate system configuration, implement I / O functions, and / or begin device configuration or initiate startup control functions. For some applications (such as some portions of a chip potentially turning on before other portions (e.g., I / O circuitry before core logic portions)), prematurely releasing the POR can cause current inrush while other power supplies are rising, which can damage and / or otherwise shorten the lifespan of the circuitry.

[0015] Providing a relatively simple fixed delay (such as a worst-case expected voltage ramp) from the initial detection of a voltage applied to the integrated circuit before generating a POR signal does not allow for adaptability to fast ramp and / or variable ramp power supplies. If a POR signal that can adaptively support both slow and fast ramp supplies is provided, an integrated circuit with a voltage rail or power supplied by a fast ramp may turn on much faster. However, it is not necessarily expected that user equipment or chips will always require a fast ramp power supply, as such power supplies may be more expensive, require stricter design rules, and / or may have other relatively complex design constraints. Therefore, according to the embodiments described herein, it is desirable to employ an adaptive POR signal generator that can adapt to multiple power slew rates / ramp rates when generating the POR signal. Thus, integrated circuits incorporating adaptive POR signal generators are far more flexible than conventional circuit elements in terms of general system design constraints, including both overall system cost and performance.

[0016] In one embodiment, as described herein, an integrated circuit can utilize an adaptive POR signal generator to more quickly turn on certain input / output (I / O) circuitry, which generally improves overall system performance, security (e.g., by ensuring that safety measures function before system components are damaged in situ), and reliability (e.g., by helping to ensure that circuitry does not deteriorate or degrade over time due to power-on events). Such integrated / semiconductor circuits according to this disclosure can be any of or a combination of application-specific integrated circuits (ASICs), system-on-a-chip (SoCs), and power supplies (PLDs), including field-programmable gate arrays (FPGAs). In various embodiments, the adaptive POR signal generator as described herein can be configured to generate POR signals as part of an integrated circuit (e.g., one or more power or voltage domains on a chip), an entire integrated circuit located on a substrate, or multiple integrated circuits located across multiple substrates in the same package, such as using through-silicon via (TSV) technology, side-by-side packaging via interconnection, or other such technologies, or multiple integrated circuits on different chips. As described herein, multiple functional elements in a SoC can receive POR signals generated according to this disclosure.

[0017] For example, a PLD can be integrated into and / or configured to control various user equipment, each with different supply voltage requirements, typically selected as one or more of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. To increase the flexibility of a particular PLD, each user equipment or PLD can be implemented using an adaptive POR signal generator configured to prevent the PLD, its components, and / or other components of the user equipment from operating before the supply voltage reaches the minimum compatible operating voltage (including during power-on), wherein the various supply voltages supplied to the PLD and / or other components of the user equipment are ramped up to their operating levels.

[0018] Generally, an adaptive POR signal generator can be implemented by a logic device / controller configured to measure the ramp rate of the supply voltage before it reaches its nominal operating voltage, and to generate a POR signal that substantially coincides with the arrival of the supply voltage at its nominal operating voltage, based at least in part on the measured ramp rate and / or ramp rate characteristics. In a particular embodiment, the adaptive POR signal generator may include, for example, a counter or other timing device, and the logic device may be configured to use the counter to measure the ramp time between at least a first ramp voltage and a second ramp voltage of the supply voltage, and to generate a POR signal based at least in part on the ramp time measurement, wherein the first and second ramp voltages of the supply voltage are selected to be below the nominal operating voltage.

[0019] As described herein, a POR signal generator can be coupled to and / or integrated with a PLD, which itself may include various circuit elements and / or user designs configured to facilitate the operation of the POR signal generator and / or coupled user equipment. According to embodiments described herein, techniques for managing the implementation of user designs in a PLD are provided. In various embodiments, a user design can be translated into a set of PLD components (e.g., configured for logic, arithmetic, or other hardware functions) and their associated interconnections available in the PLD, and / or represented by a set of PLD components (e.g., configured for logic, arithmetic, or other hardware functions) and their associated interconnections available in the PLD. For example, a PLD may include multiple programmable logic blocks (PLBs), each PLB including multiple logic units, and configurable routing resources that can be used to interconnect the PLBs and / or logic units. In some embodiments, each PLB may be implemented with 2 to 16 or 2 to 32 logic units.

[0020] Generally, a PLD (e.g., FPGA) architecture includes one or more routing structures and an array of similarly arranged logic units arranged within programmable functional blocks (e.g., PFBs and / or PLBs). The purpose of the routing structure is to programmably interconnect the ports of the logic units / PLBs to achieve the desired functionality. Remote PLDs may include various additional "hard" engines or modules configured to provide a range of remote management functions that can be linked to the operation of the PLD architecture to provide configurable computational capabilities and / or architecture. Routing flexibility and configurable functionality can be embedded when synthesizing, mapping, placing, and / or routing user designs into multiple PLD components. User designs can be implemented relatively efficiently due to various user design optimization processes, thereby freeing up configurable PLD components that would otherwise be occupied by additional operational and routing resources. In some embodiments, the optimized user design can be represented by a netlist that identifies the various types of components provided by the PLD and their associated signals. In embodiments that generate a netlist of the transformed user design, the optimization process can be performed on such a netlist. Once optimized, such a configuration can be loaded into a PLD, and the PLD can boot and execute the configuration, which may include using various I / O buses to communicate with user equipment, as described in this document.

[0021] Now refer to the attached diagram, Figure 1A block diagram of a PLD 100 according to an embodiment of the present disclosure is shown. The PLD 100 (e.g., a Field Programmable Gate Array (FPGA), Complex Programmable Logic Device (CPLD), Field Programmable System-on-Chip (FPSC), or other type of programmable device) generally includes input / output (I / O) blocks 102 and logic blocks 104 (e.g., also referred to as programmable logic blocks (PLBs), programmable function units (PFUs), or programmable logic units (PLCs)). More generally, the various elements of the PLD 100 may be referred to as a PLD structure.

[0022] I / O block 102 provides I / O functionality for PLD 100 (e.g., supporting one or more I / O and / or memory interface standards), while programmable logic block 104 provides logic functionality for PLD 100 (e.g., LUT-based logic or gate array-based logic). Serializer / deserializer (SERDES) block 150 and Physical Coding Sublayer (PCS) block 152 can provide additional I / O functionality. PLD 100 may also include a hard intellectual property core (IP) block 160 to provide additional functionality (e.g., substantially predetermined functionality provided in hardware that can be configured with less programming than logic block 104).

[0023] The PLD 100 may also suitably include memory blocks 106 (e.g., EEPROM blocks, SRAM blocks, and / or flash memory), clock-related circuitry 108 (e.g., clock sources, PLL circuitry, and / or DLL circuitry), and / or various routing resources 180 (e.g., interconnects and appropriate switching logic to provide paths for routing signals throughout the PLD 100, such as for clock signals, data signals, or other signals). In general, the various elements of the PLD 100 can be used to perform their intended functions for the desired application, as will be understood by those skilled in the art.

[0024] For example, certain I / O blocks 102 may be used to program memory 106 or transfer information to / from PLD 100 (e.g., various types of user data and / or control signals). Other I / O blocks 102 include a first programming port (which may represent a central processing unit (CPU) port, a peripheral data port, an SPI interface, and / or a sysCONFIG programming port) and / or a second programming port, such as a Joint Test Action Group (JTAG) port (e.g., by adopting standards such as IEEE 1149.1 or 1532). In various embodiments, I / O blocks 102 may be included to receive configuration data and commands (e.g., via one or more connections 140) to configure PLD 100 for its intended use and to support serial or parallel device configuration and, where appropriate, information transfer with SERDES block 150, PCS block 152, hard IP block 160, and / or logic block 104.

[0025] It should be understood that the number and placement of various components are not limiting and can depend on the desired application. For example, various components may not be required for the desired application or design specifications (e.g., for the type of programmable device selected). Furthermore, it should be understood that, for clarity, the components are shown in block diagram form, and these various components will typically be distributed throughout the PLD 100, such as in logic block 104, hard IP block 160, and routing resources (e.g., Figure 2 The routing resources 180 are used to perform their regular functions (e.g., storing configuration data for PLD 100 or providing interconnection structures within PLD 100). It should also be understood that the various embodiments disclosed herein are not limited to programmable logic devices (such as PLD 100) and can be applied to a variety of other types of programmable devices, as will be understood by those skilled in the art.

[0026] External system 130 can be used to create the desired user configuration or design for PLD 100 and generate corresponding configuration data to program (e.g., configure) PLD 100. For example, system 130 can provide such configuration data to one or more I / O blocks 102, SERDES blocks 150, and / or other parts of PLD 100. Therefore, programmable logic blocks 104, various routing resources, and any other appropriate components of PLD 100 can be configured to operate according to user-specified applications.

[0027] In the illustrated embodiment, system 130 is implemented as a computer system. In this regard, system 130 includes one or more processors 132, which can be configured to execute instructions, such as software instructions, provided in one or more memories 134 and / or stored in a non-transitory form in one or more non-transitory machine-readable media 136 (e.g., which may be internal or external to system 130). For example, in some embodiments, system 130 may run PLD configuration software, such as Lattice DiamondSystem Planner software available from Lattice Semiconductor Corporation, to allow users to create desired configurations and generate corresponding configuration data to program PLD 100.

[0028] System 130 also includes, for example, a user interface 135 (e.g., a screen or display) for displaying information to a user, and one or more user input devices 137 (e.g., a keyboard, mouse, trackball, touchscreen, and / or other devices) for receiving user commands or design input to prepare the desired configuration of PLD 100.

[0029] Figure 2 A block diagram of logic block 104 of a PLD 100 according to an embodiment of the present disclosure is shown. As discussed, the PLD 100 includes a plurality of logic blocks 104, which include various components providing logical and arithmetic functions. Figure 2 In the example embodiment shown, logic block 104 includes a plurality of logic units 200 that may be interconnected internally within logic block 104 and / or externally interconnected using routing resource 180. For example, each logic unit 200 may include various components such as: lookup table (LUT) 202, mode logic circuitry 204, register 206 (e.g., flip-flops or latches), and various programmable multiplexers (e.g., programmable multiplexers 212 and 214) for selecting desired signal paths between logic units 200 and / or between logic units 200. In this example, LUT 202 accepts four inputs 220a-220d, making it a four-input LUT (which may be abbreviated as “4-LUT” or “LUT4”), which can be programmed by configuration data for PLD 100 to implement any appropriate logic operation with four or fewer inputs. Mode logic 204 may include various logic elements and / or additional inputs, such as input 220E, to support the functionality of various modes as described herein. In other examples, LUT 202 can be any other suitable size, with any other suitable number of inputs for a specific implementation of the PLD. In some embodiments, LUTs of different sizes can be provided for different logic blocks 104 and / or different logic units 200.

[0030] In some embodiments, the output signal 222 from LUT 202 and / or mode logic 204 can be passed through register 206 to provide the output signal 233 of logic unit 200. In various embodiments, as shown in the figures, the output signal 223 from LUT 202 and / or mode logic 204 can be directly passed to output terminal 223. Depending on the configuration of multiplexers 210-214 and / or mode logic 204, the output signal 222 can be temporarily stored (e.g., latched) in latch 206 according to control signal 230. In some embodiments, the configuration data of PLD 100 can configure the output terminals 223 and / or 233 of logic unit 200 as one or more input terminals of another logic unit 200 in a hierarchical or cascaded arrangement (e.g., comprising multiple levels) to configure logical operations that cannot be implemented in a single logic unit 200 (e.g., logical operations with too many inputs to be implemented by a single LUT 202). Furthermore, as described herein, the logic unit 200 can be implemented with multiple outputs and / or interconnects to facilitate selectable operating modes.

[0031] The modal logic circuit 204 can be used in some configurations of the PLD 100 to efficiently implement arithmetic operations, such as adders, subtractors, comparators, counters, or other operations; to efficiently form some extended logic operations (e.g., higher-order LUTs, operating on multi-bit data); to efficiently implement relatively small RAM; and / or allow selection between logic, arithmetic, extended logic, and / or other selectable operating modes. In this regard, the modal logic circuit 204 spanning multiple logic cells 202 can be linked together to pass carry input signals 205 and carry output signals 207, and / or other signals (e.g., output signals 222), as described herein, between adjacent logic cells 202. Figure 2 In some examples, carry input signal 205 may be passed directly to mode logic circuit 204, or it may be passed to mode logic circuit 204 by configuring one or more programmable multiplexers, as described herein. In some embodiments, mode logic circuit 204 may be linked across multiple logic blocks 104.

[0032] Figure 2 The logic unit 200 shown is merely an example, and the logic unit 200 according to different embodiments may include different combinations and arrangements of PLD components. Furthermore, although... Figure 2A logic block 104 with eight logic units 200 is shown, but according to other embodiments, a logic block 104 may include fewer or more logic units 200. Each logic unit 200 in the logic block 104 may be used to implement a portion of a user design implemented by the PLD 100. In this respect, the PLD 100 may include a plurality of logic blocks 104, each of which may include logic units 200 and / or other components for jointly implementing the user design.

[0033] As further described herein, when PLD 100 is configured to implement a user design, portions of the user design can be adjusted to occupy fewer logic units 200, fewer logic blocks 104, and / or place less burden on routing resources 180. Such adjustments, according to various embodiments, can identify certain logical, arithmetic, and / or extended logic operations that will be implemented in arrangements of multiple embodiments occupying logic units 200 and / or logic blocks 104. As further described herein, the optimization process can route various signal connections associated with the arithmetic / logic operations described herein, such that logical, ripple arithmetic, or extended logic operations can be implemented in one or more logic units 200 and / or logic blocks 104 associated with the preceding arithmetic / logic operations.

[0034] Figure 3 A design process 300 for a PLD according to an embodiment of the present disclosure is illustrated. For example, it can be performed by a system 130 running Lattice Diamond software to configure PLD 100. Figure 3 The process. In some embodiments, Figure 3 The various files and information referenced herein may be stored in one or more databases and / or other data structures, such as memory 134, machine-readable medium 136, and / or other devices. In various embodiments, such files and / or information may be encrypted or otherwise protected when stored and / or transmitted to PLD 100 and / or other devices or systems.

[0035] In operation 310, system 130 receives a user design specifying the desired functionality of PLD 100. For example, a user may interact with system 130 (e.g., via user input device 137 and Hardware Description Language (HDL) code representing the design) to identify various features of the user design (e.g., high-level logic operations, hardware configuration, and / or other features). In some embodiments, the user design may be provided in a register transfer level (RTL) description (e.g., a gate-level description). System 130 may perform one or more rule checks to verify that the user design describes a valid configuration of PLD 100. For example, system 130 may reject invalid configurations and / or request the user to provide appropriate new design information.

[0036] In operation 320, system 130 synthesizes the design to create a netlist (e.g., a synthesized RTL description) that identifies the abstract logic implementation of the user design as multiple logic components (e.g., also referred to as netlist components), which may include both programmable components and hard IP components of PLD 100. In some embodiments, the netlist may be stored in a local generic database (NGD) file in Electronic Design Exchange Format (EDIF).

[0037] In some embodiments, synthesizing the design into a netlist in operation 320 may involve transforming (e.g., translating) a high-level description of logical operations, hardware configuration, and / or other features in the user design into a set of PLD components (e.g., logic block 104, logic unit 200, and other components of PLD 100 configured to implement the logical, arithmetic, or other hardware features of the user design) and their associated interconnections or signals. According to embodiments, the transformed user design may be represented as a netlist.

[0038] In some embodiments, synthesizing the design into a netlist in operation 320 may further involve performing an optimization process on the user design (e.g., a user design that is transformed / translated into a set of PLD components and their associated interconnections or signals) to reduce propagation delay, PLD resource and routing resource consumption, and / or optimize PLD performance when configured to implement the user design. According to embodiments, the optimization process may be performed on a netlist representing the transformed / translated user design. According to embodiments, the optimization process may represent the optimized user design in the netlist (e.g., to generate an optimized netlist).

[0039] In some embodiments, the optimization process may include optimizing examples of logic function operations, ripple arithmetic operations, and / or extended logic function operations that, when the PLD is configured to implement a user design, will occupy multiple configurable PLD components (e.g., logic unit 200, logic block 104, and / or routing resources 180). For example, the optimization process may include detecting multi-mode or configurable logic units implementing logic function operations, ripple arithmetic operations, and extended logic function operations, and / or corresponding routing resources in the user design; interchange the operating modes of logic units implementing various operations to reduce the number of PLD components and / or routing resources used to implement the operations; and / or reduce propagation delays associated with the operations; and / or reprogramming the corresponding LUTs and / or mode logic to take into account the interchangeable operating modes.

[0040] In another example, the optimization process may include detecting extended logic function operations and / or corresponding routing resources in the user design, implementing the extended logic operations into multi-mode or convertible logic units with a single physical logic unit output, routing or coupling the logic unit outputs of the first set of logic units to the inputs of the second set of logic units to reduce the number of PLD components and / or routing resources used to implement the extended logic operations and / or reduce the propagation delay associated with the extended logic operations, and / or programming the corresponding LUTs and / or mode logic to implement the extended logic function operations using at least the first and second sets of logic units.

[0041] In another example, the optimization process may include detecting multi-mode or configurable logic units that implement logic function operations, ripple arithmetic operations, extended logic function operations, and / or corresponding routing resources in the user design; interchange the operating modes of logic units that implement various operations to provide programmable registers along signal paths within the PLD to reduce propagation delays associated with signal paths; and reprogramming the corresponding LUTs, mode logic, and / or other logic unit control bits / registers to account for interchangeable operating modes and / or programming programmable registers to store or latch signals on signal paths.

[0042] In operation 330, system 130 performs a mapping process that identifies components that can be used to implement the user-designed PLD 100. In this regard, system 130 can map an optimized netlist (e.g., stored in operation 320 as a result of the optimization process) to various types of components provided by PLD 100 (e.g., logic block 104, logic unit 200, embedded hardware, and / or other parts of PLD 100) and their associated signals (e.g., logically, but not yet specified in terms of placement or routing). In some embodiments, the mapping can be performed on one or more previously stored NGD files, with the mapping results stored as a physical design file (e.g., also known as an NCD file). In some embodiments, the mapping process can be performed as part of a synthesis process in operation 320 to generate netlists mapped to PLD components.

[0043] In operation 340, system 130 performs a placement process to assign mapped netlist components to specific physical components residing in specific physical locations on PLD 100 (e.g., specific logic unit 200, logic block 104, routing resource 180, and / or other physical components assigned to PLD 100), thereby determining the layout for PLD 100. In some embodiments, placement can be performed on one or more previously stored NCD files, wherein the placement result is stored as another physical design file.

[0044] In operation 350, system 130 performs a routing process to route connections between components of PLD 100 based on the placement layout determined in operation 340 (e.g., using routing resource 180) to achieve physical interconnections between the placed components. In some embodiments, routing may be performed on one or more previously stored NCD files, with the routing results stored as another physical design file.

[0045] In various embodiments, routing the connection in operation 350 may further involve performing an optimization process on the user design to reduce propagation latency, PLD resource and / or routing resource consumption, and / or optimize PLD performance when the PLD is configured to implement the user design. In some embodiments, the optimization process may be performed on a physical design file representing the transformed / translated user design, and the optimization process may represent the optimized user design in the physical design file (e.g., generating an optimized physical design file).

[0046] In some embodiments, the optimization process may include optimizing examples of logic function operations, ripple arithmetic operations, and / or extended logic function operations that, when the PLD is configured to implement a user design, will occupy multiple configurable PLD components (e.g., logic unit 200, logic block 104, and / or routing resources 180). For example, the optimization process may include detecting multi-mode or configurable logic units implementing logic function operations, ripple arithmetic operations, and extended logic function operations, and / or corresponding routing resources in the user design; interchange the operating modes of logic units implementing various operations to reduce the number of PLD components and / or routing resources used to implement the operations; and / or reduce propagation delays associated with the operations; and / or reprogramming the corresponding LUTs and / or mode logic to take into account the interchangeable operating modes.

[0047] In another example, the optimization process may include detecting extended logic function operations and / or corresponding routing resources in the user design, implementing the extended logic operations into multi-mode or convertible logic units with a single physical logic unit output, routing or coupling the logic unit outputs of the first set of logic units to the inputs of the second set of logic units to reduce the number of PLD components and / or routing resources used to implement the extended logic operations and / or reduce the propagation delay associated with the extended logic operations, and / or programming the corresponding LUTs and / or mode logic to implement the extended logic function operations using at least the first and second sets of logic units.

[0048] In another example, the optimization process may include detecting multi-mode or configurable logic units that implement logic function operations, ripple arithmetic operations, extended logic function operations, and / or corresponding routing resources in the user design; interchange the operating modes of logic units that implement various operations to provide programmable registers along signal paths within the PLD to reduce propagation delays associated with signal paths; and reprogramming the corresponding LUTs, mode logic, and / or other logic unit control bits / registers to account for interchangeable operating modes and / or programming programmable registers to store or latch signals on signal paths.

[0049] Changes in routing can propagate back to previous operations, such as synthesis, mapping, and / or placement, to further optimize various aspects of the user's design.

[0050] Therefore, after operation 350, one or more physical design files can be provided, which specify the user design after it has been synthesized (e.g., transformed and optimized), mapped, placed, and routed (e.g., further optimized) for PLD 100 (e.g., by combining the results of corresponding previous operations). In operation 360, system 130 generates configuration data for the synthesized, mapped, placed, and routed user design. In various embodiments, as part of such generation process, such configuration data may be encrypted, signed, and / or otherwise protected, as described more fully herein. In operation 370, system 130 configures PLD 100 with configuration data by loading a configuration data bitstream (e.g., a “configuration” or “configuration image”) into PLD 100, for example, via connection 140. For example, such configuration may be provided in encrypted, signed, or insecure / unauthenticated form, and PLD 100 may be configured to treat secure and insecure configurations differently, as described herein.

[0051] Figure 4A block diagram of a user equipment 430 according to an embodiment of the present disclosure is shown, which includes a PLD 410 and one or more adaptive power-on reset (POR) signal generators 500. In various embodiments, the user equipment 430 may include a power supply 462, the adaptive POR signal generator 500, and one or more electronic components facilitating operation of the user equipment 430, such as the PLD 410, a communication module 450, and other user equipment modules 460 configured, such as to facilitate remote management of the PLD 410 or to facilitate a particular user equipment application, as described herein. In various embodiments, the user equipment 430 may be implemented as a smartphone, laptop computer, tablet computer, desktop computer, smart environmental sensor, home automation device (e.g., sensors and / or actuators), network management device, smart display or television, automotive user interface, and / or other user equipment as described herein. More generally, the user equipment 430 may be implemented as an embedded device or any other computing or electronic device that may be integrated with one or more of the PLDs 410.

[0052] like Figure 4 As shown, power supply 462 can be configured to provide one or more supply voltages (e.g., one or more VCC, VAUX) to various components of user equipment 410 via power bus 464. For example, power supply 462 can be implemented as a battery or battery pack, for example, with integrated charging and monitoring electronics. In other embodiments, power supply 462 can be configured to receive power from the grid or other external sources and includes various power conditioning, adjustment, and / or conversion components configured to supply appropriate operating voltages to each component of user equipment 430 using one or more power buses 464. Power bus 464 can include one or more wires and / or traces configured to transmit such supply voltages to various components, as shown, and in some embodiments can include signaling traces configured to transmit and receive logic signals / data to facilitate the operation of power supply 462, user equipment 430, and / or various elements of user equipment 430. In some embodiments, as shown, power bus 464 can be configured to provide the same supply voltage to one or more adaptive POR generators 500.

[0053] In various embodiments, the adaptive POR signal generator 500 can be configured to receive one or more supply voltages from the power supply 462 via the power bus 464 and generate a POR signal configured to deactivate one or more components of the user equipment 430 from a restart state approximately when the corresponding supply voltage reaches a minimum compatible operating voltage for one or more components. Figure 4As shown, in some embodiments, such POR signals may be transmitted to each component via POR signal bus 580, and each device may include circuitry configured to maintain a component in a reset or power-safe state prior to receiving a POR signal via POR signal bus 580. For example, the POR signal may be a logic signal that transitions (e.g., from high to low, from low to high, from low to high to low, etc.) to release such a restart state, and the corresponding component receiving such a signal may be configured to latch or store such a restart-released state, for example, before user equipment 430 and / or power supply 462 are cyclically powered, or an adaptive POR signal generator 500 may generate a forced reset signal (e.g., a separate logic signal transition also transmitted via POR signal bus 580) configured to force the corresponding component back to a reset state, as described herein.

[0054] In some embodiments, for example, each component may include its own optional adaptive POR signal generator 500 to increase design flexibility for individual components in terms of power supply performance characteristics, operating voltage, and corresponding ramp time. More generally, user equipment 430 may include any combination of adaptive POR signal generators 500 configured to, for example, protect the operation of user equipment 430 and its components, while maintaining relatively high system performance by minimizing the delay between power-on of power supply 462 and operation of user equipment 430 and / or its individual components (e.g., minimizing boot time under variable conditions).

[0055] like Figure 4 As shown, PLD 410 can be manufactured by a similar method to that used for... Figure 1 The PLD 410 may be implemented using the elements described for PLD 100, and / or have additional configurable and / or hard IP elements configured to facilitate operation of PLD 410 in a particular computing application and / or architecture, as described herein. Specifically, PLD 410 may include a PLD structure 400 linked via various buses to a non-volatile memory (NVM) 420, a programmable I / O 404, and / or other integrated circuit (IC) module 406, all implemented on a single IC, as shown in the figure. Generally, PLD structure 400 may be implemented using any of the various elements described for PLD 100, and may use similar elements to those described for PLD 100. Figure 3 The described design process 300 is a design process configured to generate and program the PLD structure 400 according to a desired configuration. In some embodiments, the PLD 410 may include one or more adaptive POR signal generators 500 (e.g., as one or more hard IP components integrated with the PLD 410).

[0056] The NVM 420 can be implemented as a hard IP resource configured to provide secure and / or non-volatile storage for data used to facilitate the operation of the PLD 410. The NVM 420 may include multiple distinct sectors, such as one or more configuration image sectors, device key sectors (e.g., AES key sectors and separate public key / key pair sectors), user flash memory (UFM) sectors, and / or other defined storage sectors. For example, configuration image sectors may each store configurations for the PLD structure 400 to allow them to be selected (e.g., based on version or date) and used for programming the PLD structure 400. Decoration sectors may be used to store manufacturer decorations, device identifiers, device category identifiers, and / or other data specific to the PLD 410, such as modifiable customer-specific order part numbers and / or generated customer ID numbers. Device key sectors may be used to store encryption / decryption keys, public / private keys, and / or other security keys specific to the PLD 410. UFM sectors can be used to store user data that is generally accessible by the PLD structure 400, such as configuring or applying specific security keys, certificates, and / or other security(d) user data. Any one or more individual elements, portions, or sectors of the NVM 420 can be implemented as, for example, configurable memory or one-time programmable (OTP) memory, as described herein.

[0057] Programmable I / O 404 may be implemented as at least partially configurable resources and / or hard IP resources configured to provide or support a communication link between PLD structure 400 and external controllers, memories, and / or other devices (such as communication module 450), for example across bus 402 (e.g., configured to link portions of PLD structure 400 to the programmable I / O 404 and / or NVM 420 bus) and supply voltage according to one or more external bus interfaces, protocols, and / or bus voltages (e.g., external bus interface 408). Programmable I / O 404 may also be configured to support communication between PLD structure 400 and / or NVM 420 and communication module 450 across bus 402 and / or external bus interface 408, for example, as a supplement to or alternative to external system 130 / machine-readable medium 136, as described herein.

[0058] In some embodiments, bus 402 and / or programmable I / O 404 may be integrated with PLD structure 400. More generally, in Figure 4One or more components of the PLD 410, shown as separate components, may be integrated with and / or incorporated within each other. Other IC modules 406 may be implemented as hard IP resources and / or configurable IP resources configured to facilitate operation of the PLD 410. For example, other IC modules 406 may include a security engine implemented as a hard IP resource configured to provide various security functions used by the PLD structure 400 and / or user equipment 430; a configuration engine implemented as a hard IP resource configured to manage the configuration of various components of the PLD 410 and / or communication between them, including managing or controlling the configuration of the components of the PLD 410, booting the PLD structure 400, and flow control of the entire PLD 410; and one or more additional external access buses implemented according to one or more of JTAG, I2C, SPI, and / or other external access buses or protocols, for example, configured to provide access to and / or from the communication module 450 and / or other user equipment modules 460.

[0059] The communication module 450 may be implemented as a network communication IC configured to form a communication link to a remote external device for managing the operation of the PLD 410. For example, in some embodiments, the communication module 450 may be implemented as a wireless communication module configured to support wired and / or wireless communication links to a communication network (e.g., formed according to WiFi, Bluetooth, Zigbee, Z-wave, Near Field Communication (NFC), cellular, Ethernet, and / or other open and / or proprietary wired and / or wireless communication protocols), as described herein. In such embodiments, the communication module 450 may be configured to manage various security features of such wired and / or wireless communication links (e.g., establishing communication link certificates, using communication link certificates to establish communication links, negotiating encryption keys, such as Transport Layer Security (TLS), for encrypted communication tunnels established through such communication links), and / or may be configured to be controlled by the PLD 410 and / or other user equipment modules 460 to manage such security features.

[0060] Other user equipment module 460 may include various computing, sensor, and / or actuator elements configured to implement specific user equipment applications, such as remote sensor applications, remote controller applications, and / or remote computing applications as described herein. Other user equipment module 460 may also include various other communication buses, power storage and delivery elements, and user interfaces (e.g., buttons, keyboards, mice, trackpads, and / or displays / touchscreen displays) to support such user equipment applications. In one embodiment, other user equipment module 460 includes an electrical characteristic sensor configured to detect and / or measure the electrical state of a transducer element (e.g., also an element of other user equipment module 460) used to measure environmental conditions associated with user equipment 430. In another embodiment, other user equipment module 460 includes various electronic devices typically found in smartphones, laptops, tablets, and / or desktop computers.

[0061] Figure 5 A block diagram of an adaptive POR signal generator 500 according to an embodiment of the present disclosure is shown. Figure 5 The operation of the adaptive POR signal generator 500 will be described with reference to an example supply voltage (or a voltage derived from a supply voltage) that is nominally approximately 1.9V at full ramp. However, the embodiments are applicable to any supply voltage, and any particular value is merely an example from which those skilled in the art can understand how aspects of this disclosure can be applied to other implementations. The example supply voltage may be referred to as VCC. In general operation, the ramp supply voltage (e.g., VCC) is sampled (e.g., also referred to herein as the ramp voltage when sampled during ramping, depending on various different sampling techniques) as the ramping supply voltage (e.g., Vl ~ 1.38V) increases from a relatively low first threshold ramp voltage (e.g., Vl ~ 1.58V) to a relatively high second threshold ramp voltage (e.g., Vh ~ 1.58V) in order to characterize the ramp time required for ramping through the monitored supply voltage range.

[0062] Generally, both the first threshold ramp voltage Vl and the second threshold ramp voltage Vh should be less than the expected supply voltage for a full ramp (e.g., the minimum compatible operating voltage for the corresponding component). The first threshold voltage level Vl can be selected to be high enough to avoid premature turn-on periods of power supply 462, during which transients or other undesirable and / or unreliable power supply behavior may occur. In various embodiments, the ramp time can be characterized by counting the transitions of an embedded oscillator / clock source with a known frequency Fon. The time for each transition or the count based on the number of such transitions can be determined based on the known clock frequency Fon. In some implementations, as described herein, the assumption of a monotonic ramp of the supply voltage can be made or required to characterize both the ramp time and any delays required to properly generate the resulting POR signal.

[0063] In embodiments that include a counter as a timing device, the value of the counter can be used as a basis for determining when the POR signal should be generated in order to appropriately delay the generation of the POR signal when VCC ramps to Vh. In some embodiments, if the count starts from zero to represent the ramp time between Vl and Vh, the POR signal delay to release the reset (e.g., generate the POR signal) can be calculated based on, for example, how much Vh differs from the expected operating voltage of a full ramp, or the value at which the circuit or a portion thereof can operate. For example, if the operating voltage value of the supply voltage VCC is expected / anticipated to be 1.98V, then the POR signal (reset release) should be generated when VCC is approximately 1.98V. Assuming a linear ramp rate for the supply voltage VCC, if Vl = 1.38V and Vh = 1.58V (meaning a voltage level change of approximately 0.2V), then the voltage change between the final values ​​of Vh and VCC is approximately 0.4V or twice the voltage difference between the two threshold ramp voltages Vl and Vh. Therefore, under such conditions, the POR signal delay between the arrival of Vh and the generation of the POR signal should be approximately twice the ramp time between the arrival of VCC at Vl and then at Vh.

[0064] In one embodiment, the value of the counter when VCC reaches Vh (e.g., a ramp-time count at a given counter frequency Fon) can be used to implement a POR signal delay (e.g., in this digital example, by doubling the count value or halving the Fon frequency) and can be used to precisely determine when to generate the POR signal. For example, in some embodiments, the POR signal can be generated by counting down from the counter value (e.g., a determined ramp-time count) at a frequency of Fon / 2 based on the voltage and linear ramp assumptions described above. More generally, other values ​​for Vl and Vh can be selected, and / or Fon can be selected based on the number of bits to be allocated or available for the counter. Furthermore, the POR signal delay generated by the POR signal can be adjusted by modifying the count frequency or modifying the count value. The count frequency can be modified by changing the resistor values ​​for the counter and / or clock source / oscillator, which can be done (e.g., during manufacturing) by selecting from several resistors, by changing the metal layer or other suitable means (e.g., laser trimming), or by implementing a variable resistor or other programmable circuit element (e.g., which can be programmed to adjust during the operation of the adaptive POR signal generator 500). In various embodiments, the POR signal delay can be modified to account for, for example, process and temperature variations, which can be monitored and provided to the adaptive POR signal generator 500 via power bus 464 and / or POR signal bus 580. Safety margins or other POR signal delay adjustments can be modified on a continuous basis based on observed or possible nonlinearities of the VCC ramp rate, and the POR signal delay can be determined based on, for example, any linear or nonlinear ramp rate curve generated by and / or expected from power supply 462 and / or measured by the adaptive POR signal generator 500, as described herein.

[0065] In some embodiments, the adaptive POR signal generator 500 can be implemented in a simple and robust manner. Figure 5 The example implementation architecture presented illustrates aspects of this disclosure, which, in a relatively simple, compact, reliable, and low-power embodiment, provides POR signal generation (reset release) with adaptive timing based on voltage ramp rate. For example, Figure 5The embodiment of the adaptive POR signal generator 500 shown can be used with any or more supply voltages—internal and / or external sources or generated—and the amount of POR signal delay can depend on the ramp rate. For the example voltage values ​​disclosed above and a fast ramp (20 µs / V), the POR signal delay in this example will be close to 30 µs (microseconds), while for a slow ramp (50 ms / V), the POR signal delay will be around 20 ms. The POR signal delay can be changed by altering the oscillator frequency. The supported amount of POR signal delay can be changed by altering the available number of bits in the counter. For example, the available oscillator frequency can be changed by modifying the resistor (metal option) or soldering option. The output of the POR signal on the POR signal bus 580 can be further processed (e.g., OR and / or AND operations with one or more other signals) depending on the specific application requirements of the generated POR signal. The number of bits in the counter can be selected based on the maximum necessary or desired or expected POR signal delay to be supported. In one example, a 17-bit counter is sufficient to support the maximum POR signal delay required for the minimum permissible ramp rate (e.g., a ramp rate below the minimum permissible ramp rate tends to indicate a power supply 462 failure). A timeout feature may be included, wherein if the ramp supply / ramp voltage does not reach a second threshold ramp voltage Vh within the required time period (which can be indicated by a counter toggling and generating an overflow logic signal), a system / power supply / chip / POR signal generator restart signal can be generated to attempt a system / power supply / chip / POR signal generator restart, generate an alarm, and / or power off. In various embodiments, a monotonic voltage ramp in the monitored supply voltage is assumed; however, in alternative embodiments, the relatively noisy DC supply voltage and / or AC supply voltage can be accommodated by including appropriate filtering and / or monitoring circuitry (e.g., AC voltage peak monitoring circuitry) within the adaptive POR signal generator 500.

[0066] Figure 5 The circuitry described is an adaptive POR signal generator 500, which can be formed in a semiconductor as an integrated circuit or as part of an integrated circuit. Such an integrated circuit can be one of multiple independent and / or interconnected circuits formed on such a semiconductor. Figure 5 In the illustrated embodiment, during normal operation, a reference voltage 520 is generated by a reference voltage generator 510 and can then be supplied to a ramp traversal detector 522. The ramp traversal detector 522 can then generate a ramp traversal signal 523 and provide it to a controller 540, which can be configured to determine an appropriate POR signal delay, using this delay to generate a POR signal on the POR signal bus 580.

[0067] The controller 540 can be implemented as any suitable logic device (e.g., a processing device, microcontroller, processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), memory storage device, memory reader, or other device or combination of devices) adapted to execute, store, and / or receive appropriate instructions, such as software instructions that implement control loops for controlling various operations of the adaptive POR signal generator 500. Such software instructions can also implement methods for querying operating parameters to the device, selecting operating parameters for the device, or performing any of the various operations described herein (e.g., operations performed by the logic device of the various devices of the adaptive POR signal generator 500). Furthermore, the controller 540 can be implemented using a machine-readable medium for storing non-transitory instructions loaded into and executed by the controller 540. In these and other embodiments, the controller 540 can be implemented with other components where appropriate, such as volatile memory, non-volatile memory, one or more interfaces, and / or various analog and / or digital components for interfacing with the device and / or user equipment 430 of the adaptive POR signal generator 500.

[0068] like Figure 5 As shown, the reference voltage generator 510 can be implemented by a current mirror 514 and a linear resistor array 516. The current mirror 514 can be enabled / enabled by a bandgap transistor structure 518 and the linear resistor array 516, which is configured to provide a selected reference voltage based on the current output of the current mirror 514. In some embodiments, the current mirror 514 can be coupled to and / or powered by any available supply voltage, such as VCC and / or VAUX at inputs 511 and 512, and the bandgap transistor structure 518 can be gated by a bandgap signal at input 519 (e.g., transmitted via power bus 464 and / or POR signal bus 580), which can be configured to indicate that the supply voltage generated by power supply 462 (e.g., and provided to inputs 511 and / or 512) can be used to power the current mirror 514 and generate a stable and reliable reference voltage 520.

[0069] In some embodiments, the reference voltage generator 510 is turned on by a voltage signal generated from another circuit, such as a bandgap or even another POR generation circuit. Such a voltage signal may indicate that the supply voltage (e.g., VCC) at inputs 511 and / or 512 has reached a minimum voltage, such as 0.7 volts, 0.8 volts, or 0.9 volts. Thereafter, the current mirror 514 generates a stable and reliable reference voltage 520 via a linear resistor array 516. In various embodiments, the reference voltage generator 510 may be implemented using other circuit elements and / or circuit arrangements. Generally, the reference voltage generator 510 may be any combination of circuit elements configured to generate a relatively stable and reliable reference voltage 520 before the monitored supply voltage (e.g., provided at the monitored supply voltage input 531 of the ramp voltage selector 530) ramps up to its nominal operating voltage, for example, where the reference voltage 520 may be lower than the nominal operating voltage of the supply voltage monitored by the adaptive POR signal generator 500. In some embodiments, the reference voltage generator 510 can be implemented using hard and / or soft IP resources integrated with the PLD 410.

[0070] like Figure 5 As shown, a reference voltage 520 can be supplied to a ramp traversal detector 522, which in some embodiments can be implemented as a comparator. The ramp traversal detector 522 can be coupled to a ramp voltage selector 530 and configured to generate a ramp traversal signal 523 when the ramp voltage 530 supplied by the ramp voltage selector 530 traverses the reference voltage 520 (e.g., when the ramp voltage 530 becomes equal to and / or greater than the reference voltage 520 – this can be within a specified time / voltage tolerance or other approximation). In various embodiments, the ramp traversal detector 522 may include a programmable linear resistor array / divider 532, which may include resistors 533, 534, and 535 and a resistor bypass switch 536 configured to generate a ramp voltage 538 from the supply voltage input 531 (e.g., the monitored supply voltage VCC) based on the switching state of the resistor bypass switch 536. For example, resistor bypass switch 536 can be configured to selectively short-circuit resistor 535, thereby changing the voltage range generated by the ramp voltage selector and output as ramp voltage 538. As shown in the figure, programmable linear resistor array / divider 532 is coupled to VCC at input 531, which, as described above, is ramped. Therefore, ramp voltage 530 also increases with increasing VCC.

[0071] In some embodiments, resistors R1 / 533, R2 / 534, and R3 / 535 can be selected such that when the supply voltage VCC is approximately 1.38V, the ramp voltage 538 is equal to the reference voltage 520, and when VCC is approximately 1.58V (e.g., when the resistor bypass switch 536 is closed), the ramp voltage 538 is also equal to the reference voltage 520. Specifically, when the resistor bypass switch 536 is open, the ramp voltage 538 can be determined as (R2+R3) / (R1+R2+R3), and when the resistor bypass switch 536 is closed, the ramp voltage 538 can be determined as (R2 / (R1+R2)). Reasonable values ​​can be chosen for one or more of R1-R3, and the resulting equations for both cases can be solved. Note that the reference voltage 520 is not required and typically will not be equal to 1.38V or 1.58V.

[0072] In various embodiments, the adaptive POR signal generator 500 may include circuitry (e.g., a POR enabler 570) configured to enable and disable operation of the adaptive POR signal generator 500 when not needed, such as to save power. For example, signal input 571 (e.g., pmu_done) may indicate that the circuitry receiving the POR signal from the adaptive POR signal generator 500 has been successfully turned on, and therefore operation of the adaptive POR signal generator 500 is no longer required, while signal input 572 (e.g., bg_ready) may indicate that reference voltage 520 is ready to be (or is being) supplied to ramp traversal detector 522, allowing the adaptive POR signal generator 500 to be used to generate the POR signal. For example, signal input 572 may be coupled to the same bandgap signal at input 519. In some embodiments, if pmu_done is logically true, counter 560 should remain reset (e.g., via reset signal 574 generated by POR enabler 570) regardless of bg_ready, and counter 560 should exit reset only if bg_ready is logically true and pmu_done is logically false. In various embodiments, POR enabler 570 may be configured to implement such logic to facilitate the operation, enabling, and disabling of adaptive POR signal generator 500 and / or individual elements of adaptive POR signal generator 500, as illustrated.

[0073] In response to a ramp traversal detector 522 indicating to controller 540 via ramp traversal signal 523 that the supply voltage VCC at input 531 has reached 1.38V, controller 540 initiates the output of oscillator 550 to counter 560 via various clock control signals, including clock enable signal 541. As described herein, controller 540 can also adjust the frequency of oscillator 550 via clock control signals (e.g., slow enable signal 542). Controller 540 can also cause counter 560 to count up or down via various counter control signals (e.g., up / down signal 544), and in this example, when ramp voltage selector 530 indicates that the supply voltage VCC at input 531 is 1.38V, counter 560 begins counting up at the frequency of clock signal 552 output from oscillator 550 to counter 560. When the ramp traversal detector 522 indicates to the controller 540 that the supply voltage VCC at input 531 has reached 1.58V, the controller 540 disables the oscillator 550 from providing a clock signal 552 to the counter 560 (e.g., via a clock enable signal 541). Note that the oscillator may still be active, but it simply does not output the clock signal 552. The counter 560 therefore stops incrementing.

[0074] Various aspects of this disclosure provide for delaying the release of the POR signal by a certain amount, which depends on the rate at which the supply voltage VCC ramps between two ramp threshold voltages, referred to herein as the ramp time. In some aspects, the POR signal delay is also determined based on how far Vh is from the expected final value for VCC and / or the nominal operating voltage. In the example of Vl = 1.38 and Vh = 1.58 (a difference of 0.2V) and a final VCC value of 1.98, there is approximately 0.4V that can be added for VCC, so the release time should be approximately twice the time required to ramp from Vl = 1.38 to Vh = 1.58.

[0075] While various implementations are possible to provide a POR signal delay, in this example, the POR signal delay is achieved and / or adjusted by reducing the oscillator frequency to approximately half the value used for counting up. The controller 540 then instructs the counter 560 to count down at the now reduced frequency instead of counting up. The current count from the counter 560 can be provided to the controller 540, which can be configured to detect when the count value has reached zero and, in response, generate a POR signal on the POR signal bus 580. This POR signal can be used as the POR signal or to generate other logically strobe POR signals (i.e., clear reset or unreset). For example, the POR signal on the POR signal bus 580 can be used directly for clear reset, or it can be consumed by another circuit that can further strobe or use the POR signal on the POR signal bus 580 before clearing the POR.

[0076] In some implementations, counter 560 also has the capability to indicate an overflow (e.g., via overflow signal 564), meaning that ramp traversal detector 522 ultimately failed to trigger controller 540 ramp voltage 538 to reach a value indicating VCC to reach Vh. Controller 540 can use this overflow signal to take action, which may depend on the intended use of the POR signal. Such actions may include resetting the entire chip or part of the integrated circuit and retrying, or in any case, clearing the POR signal. In various embodiments, POR signal bus 580 may be used to communicate POR signals and / or other communication logic signals between controller 540 and any other circuit elements served by adaptive POR signal generator 500. Other implementations may include counter 560, which itself may trigger another signal at a significant value such as zero, without implying or requiring a precise division of these functions implemented by controller 540 and counter 560.

[0077] Generally, Vl and Vh can be adjusted, and corresponding changes in delay or oscillator frequency can be provided. Furthermore, the number of bits in counter 560 can be provided based on the expected range and desired resolution of oscillator 550. For example, oscillator 550 can operate at values ​​such as 1 MHz or higher. Each transition of the clock from oscillator 550 then represents 1 µs. The maximum number of bits can be determined by the maximum allowed POR signal delay. For example, using 17 bits, the counter can count 2^17 transitions of clock signal 552, or a total time of approximately 130 ms (for ramping). More or fewer bits can be allocated, allowing for greater granularity and / or a larger range. Furthermore, generally, for example, other components of oscillator 550, counter 560, POR enabler 570, controller 540, and / or adaptive POR signal generator 500 can be implemented using hard IP resources or soft IP resources of PLD 410.

[0078] In alternative or supplementary embodiments, the adaptive POR signal generator 500 may be implemented by a controller 540 and various circuit elements configured to sample the supply voltage provided by the power supply 462 before it reaches its nominal operating voltage, wherein the controller 540 is configured to determine an appropriate POR signal delay and generate a POR signal based on a POR signal delay that is approximately consistent with the supply voltage reaching its nominal operating voltage. Figure 5In the embodiment shown, controller 540 uses two samples of the supply voltage acquired at different times and voltage levels (e.g., selected by ramp voltage selector 530) to determine the appropriate POR signal delay. In an alternative embodiment, controller 540 and ramp voltage selector 530 may be configured to sample the supply voltage at more than two different times, e.g., or only once. For example, power supply 462 may be adapted to provide the supply voltage according to a characteristic ramp profile, and controller 540 may be configured to use a single sample to determine the position of the supply voltage on the ramp profile, and then use the ramp profile to infer the appropriate POR signal delay based on the single sample (e.g., ramp voltage 538 traverses a single threshold ramp voltage). Alternatively, where power supply 462 provides a supply voltage with a nonlinear and multivariable / unreliable ramp profile, or where two or more supply voltage samples are favorable for determining a reliable POR signal delay, controller 540 may be configured to determine or characterize a nonlinear ramp profile based on two or more supply voltage samples, and then determine the POR signal delay based on the supply voltage samples and the characterized nonlinear ramp profile.

[0079] although Figure 5 The embodiment of the adaptive POR signal generator 500 shown includes various components; however, other embodiments of the adaptive POR signal generator 500 may omit the reference voltage generator 510 and replace the ramp voltage selector 530 and ramp traversal detector 522 with other analog or digital circuitry configured to sample the supply voltage and provide sampling and / or timing to the controller 540. Furthermore, the oscillator 550 and counter 560 may be omitted and / or replaced with timing and / or clock circuitry configured to enable the operation of the controller 540 and the adaptive POR signal generator 500. More generally, Figure 5 Any individual components of the adaptive POR signal generator 500 shown can be integrated together, and / or their functionality can be achieved using different circuit elements and their arrangements. Figure 5 A particular advantage of the embodiment shown is that the oscillator 550 and counter 560 can be used for both ramp time characterization and POR signal delay, with minimal interconnections between the controller 540, oscillator 550, and counter 560. Furthermore, the reference voltage 520 is allowed to remain stable throughout the ramp characterization and POR signal generation process, while the ramp voltage 538 ramps, thereby ensuring repeatable and accurate sampling of the supply voltage provided to input 531 throughout the ramp process.

[0080] Figure 6 An adaptive POR signal generation process 600 according to an embodiment of the present disclosure is illustrated. In some embodiments, Figure 6The operation can be implemented by and Figures 1 to 5 The software instructions executed by one or more logical devices associated with the corresponding electronic device, module, and / or structure described herein. More generally, Figure 6 The operation can be implemented using any combination of software instructions and / or electronic hardware (e.g., inductors, capacitors, amplifiers, actuators, or other analog and / or digital components). It should be understood that any step, substep, subprocess, or block of process 600 can be implemented in a manner different from... Figure 6 The illustrated embodiments are performed in the order or arrangement shown. For example, in other embodiments, one or more blocks may be omitted from process 600, and other blocks may be included. Furthermore, block inputs, block outputs, various sensor signals, sensor information, calibration parameters, and / or other operating parameters may be stored in one or more memories before moving to subsequent parts of process 600. Although references... Figures 1 to 5 The system, devices, and components described herein define process 600; however, process 600 may be performed by other systems, devices, and components, and includes various choices of electronic systems, devices, components, assemblies, and / or arrangements. Upon startup of process 600, various system parameters may be populated by, for example, previous executions of processes similar to process 600, or may be initialized to zero and / or one or more values ​​corresponding to typical, stored, and / or learned values ​​derived from past operations of process 600, as described herein.

[0081] In block 610, the logic device detects a first supply voltage ramp traversal. For example, controller 540 may be configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage selected via a resistor bypass switch 536 of ramp voltage selector 530. For example, ramp voltage selector 530 may be configured to generate a ramp voltage 538 based on either a first or second threshold ramp voltage, wherein the first or second threshold ramp voltage is based on the monitored supply voltage at input 531 and how the supply voltage is modified by the switching states of resistor bypass switch 536 and linear resistor array / resistor divider 532. In some embodiments, controller 540 may be configured to detect such a traversal by, for example, monitoring a ramp traversal signal generated by ramp traversal detector 522, and to initiate an incrementing count within counter 560 upon detecting a logic signal transition in the ramp traversal signal. The controller 540 can be configured to control the counter 560 to increment by generating a counter control signal and to generate a clock control signal to enable the oscillator 550 and control the oscillator 550 to provide a clock signal 552 to the counter 560 to start the increment counting.

[0082] Generally, the ramp traversal detector 522 can be configured to receive a ramp voltage 538 from the ramp voltage selector 530 and provide a ramp traversal signal 523 to the controller 540. The counter 550 can be configured to receive a counter control signal (e.g., via an up / down signal 544, a POR reset signal 574) from the controller 540 and increment and / or decrement the count based at least in part on the counter control signal provided by the controller 540. The oscillator 550 can be configured to receive a clock control signal from the controller 540 and provide a clock signal 552 to the counter 560 based at least in part on the clock control signals 541, 542 provided by the controller 540. The controller 540 can be configured to detect the first supply voltage ramp traversal by detecting a first logic signal transition in the ramp traversal signal 523 generated by the ramp traversal detector 522 corresponding to the first supply voltage ramp traversal and initiating the increment count of the counter 560.

[0083] In various embodiments, controller 540 may be configured to select a first threshold ramp voltage before detecting a first supply voltage ramp traversal by polling the state of bypass switch 536 of ramp voltage selector 530 and / or turning on resistor bypass switch 536. For example, such selection may occur during controller 540 initialization or at any time before detecting the first supply voltage ramp traversal. More generally, controller 540 may be configured to configure ramp voltage selector 530 according to the first threshold ramp voltage by polling the switching state of resistor bypass switch 536 and / or turning on resistor bypass switch 536 before detecting the first supply voltage ramp traversal. The ramp traversal detector 522 can be configured to generate a ramp traversal signal by determining that the ramp voltage 538 generated by the ramp voltage selector 530 is greater than or equal to the reference voltage 520 generated by the reference voltage generator 510, wherein the reference voltage 530 is lower than the nominal operating voltage associated with the power supply 462 and / or the supply voltage, and by generating a first logic signal transition in the ramp traversal signal 523.

[0084] In block 620, a logic device detects a second supply voltage ramp traversal. For example, controller 540 may be configured to detect a second supply voltage ramp traversal that crosses a second threshold ramp voltage selected via a resistor bypass switch 536 of ramp voltage selector 530. In some embodiments, controller 540 may be configured to detect such a traversal by, for example, monitoring a ramp traversal signal generated by ramp traversal detector 522, and to stop the incrementing count in counter 560 (e.g., initialized in block 610) upon detecting a logic signal transition in the ramp traversal signal. In various embodiments, controller 540 may be configured to select a second threshold ramp voltage after detecting a first supply voltage ramp traversal by closing the resistor bypass switch 536 of ramp voltage selector 530. Such selection can occur at any time before the second supply voltage ramp traversal is detected. More generally, the controller 540 can be configured to configure the ramp voltage selector 530 according to a second threshold ramp voltage after a first supply voltage ramp traversal is detected and / or before a second supply voltage ramp traversal is detected by the closed resistor bypass switch 536.

[0085] In various embodiments, controller 540 may be configured to initiate decrementing counting from ramp time by generating a counter control signal to control the counter to start counting down from ramp time, and to initiate decrementing counting by generating a clock control signal to enable oscillator 550 and control oscillator 550 to provide a modified clock signal 552 to counter 560, wherein the modified clock signal 552 includes a frequency at least partially based on ramp time and nominal operating voltage level. For example, such a frequency may be selected to set the desired duration of counting down to zero to be equal to the desired POR signal delay derived from ramp time and nominal operating voltage level for the supply voltage. Controller 540 may be configured to detect a second supply voltage ramp traversal by detecting a second logic signal transition corresponding to a second supply voltage ramp traversal by ramp traversal signal 523 generated by ramp traversal detector 522, and stopping the incrementing count of counter 560 started in block 610.

[0086] In block 630, the logic generates the POR signal based at least in part on the ramp time associated with the first and second supply voltage ramp epochs. For example, controller 540 may be configured to generate the POR signal based at least in part on such ramp time and the nominal operating voltage of power supply 462, as described herein. In some embodiments, controller 540 may be configured to determine the POR signal delay based at least in part on the ramp time and the nominal operating voltage, and to generate the POR signal after the detected second supply voltage ramp epoch, and to delay the POR signal delay relative to the detected second supply voltage ramp epoch.

[0087] In some embodiments, controller 540 may be configured to determine such POR signal delay based at least in part on a linear supply voltage ramp ergodic rate corresponding to the ramp time between the first and second supply voltage ramp ergodices and the voltage difference between the first and second threshold ramp voltages. In such embodiments, the POR signal delay may be determined by linear interpolation based on the linear supply voltage ramp rate and the voltage difference between the nominal operating voltage and the second threshold ramp voltage, as described herein. In other embodiments, controller 540 may be configured to determine the POR signal delay, for example, based at least in part on a nonlinear ramp profile associated with power supply 462 and / or the supply voltage, in addition to the ramp time and the first and second threshold ramp voltages. In such embodiments, the POR signal delay may be determined by nonlinear interpolation based on such a nonlinear ramp profile. In various embodiments, controller 540 may be configured to adjust such POR signal delay based on the temperature of any component of user equipment 430, based on one or more previously stored POR signal delays, a safety margin delay buffer, and / or other POR signal delay adjustments, as described herein.

[0088] In use such as Figure 5 In an embodiment where the counter 560 and oscillator 550 illustrate an adaptive POR signal generator 500, the controller 540 may be configured to generate a POR signal via a countdown initiated by the counter 560, the countdown starting from a ramp time count identified in block 620 and generating the POR signal when the countdown reaches zero (e.g., transmitted to the controller 540 via a count signal 562). More generally, the controller 540 may be configured to determine the POR signal delay by at least partially based on the ramp time and nominal operating voltage level, and to generate the POR signal after a detected second supply voltage ramp traversal, and to generate the POR signal with a delay relative to the detected second supply voltage ramp traversal, as described herein. In various embodiments, the controller 540 may be configured to determine the POR signal delay by, for example, a linear extrapolation based at least partially on a linear supply voltage ramp rate and the voltage difference between the nominal operating voltage and a second threshold ramp voltage, or a nonlinear extrapolation based at least partially on a nonlinear ramp curve associated with the power supply and / or supply voltage.

[0089] Therefore, by employing the systems and methods described herein, embodiments of this disclosure are able to provide flexible and reliable protection for the PLD and / or other components of the user equipment during all possible power ramp levels and sequences.

[0090] Another embodiment may include an article of manufacture comprising an integrated circuit coupled to receive a POR signal and a power supply having a nominal operating voltage (an expected operating voltage within a bounded variation under normal conditions); an adaptive POR signal generator including logic for detecting that the power supply has become active and measuring the ramp time of the supply voltage of the power supply (or a ramp voltage derived from the supply voltage) from a low first threshold ramp voltage to a higher second threshold ramp voltage, wherein both the low first threshold ramp voltage and the higher second threshold ramp voltage are less than the nominal operating voltage, and the logic is configured to generate a POR signal for reception by the integrated circuit after a ramp time-based POR signal delay. In some embodiments, the POR signal delay may be based on the difference between the higher second threshold ramp voltage and the nominal operating voltage of the power supply.

[0091] Another embodiment may include a method comprising: comparing a ramp voltage derived from a ramp supply voltage using a voltage comparator to detect when the ramp voltage reaches a lower first threshold ramp voltage and a higher second threshold ramp voltage, both of which are less than the nominal operating voltage of the power supply; and using the ramp time between the ramp voltage reaching the lower first threshold ramp voltage and reaching the higher second threshold ramp voltage to adjust the generation of a POR signal, which is provided to a circuit coupled to receive the supply voltage.

[0092] Another embodiment may include an integrated circuit comprising a counter for counting transitions in a signal; an oscillator coupled to output a clock signal to the counter; a voltage comparator coupled to a power supply for comparing a reference voltage and a ramp voltage associated with a momentary supply voltage of the power supply at a first time point and a second time point to detect when the supply voltage (or a ramp voltage derived from the supply voltage) reaches a low first threshold ramp voltage and a high second threshold ramp voltage; control logic coupled to the voltage comparator and the counter, the control logic being configured to start counting in response to outputting a signal to the counter when the power supply or ramp voltage reaches a low first threshold ramp voltage, and to stop counting in response to outputting a signal to the counter when the power supply or ramp voltage reaches a high second threshold ramp voltage; and to use the result value of the counter to delay the release of the POR signal for a period of time, which is the expected elapsed time between the power supply or ramp voltage reaching the high second threshold ramp voltage and the supply voltage reaching the nominal operating voltage.

[0093] Another embodiment may include an integrated circuit performing a method comprising estimating a transition or ramp rate of a supply voltage from an initial voltage ramp to a nominal operating voltage, the estimation being performed before the supply voltage has reached the nominal operating voltage; and generating a POR signal after a time period determined based on the estimated ramp rate and the remainder of the voltage increase required to reach the nominal operating voltage has elapsed. Another embodiment may also include a method performed by an integrated circuit comprising estimating a ramp rate of a supply voltage from an initial voltage ramp to a nominal operating voltage, the estimation being performed before the supply voltage has reached the nominal operating voltage; and providing a POR signal after a time period determined based on the estimated ramp rate and the remainder of the voltage increase required to reach the nominal operating voltage has elapsed.

[0094] Where applicable, the various embodiments provided in this disclosure may be implemented using hardware, software, or a combination of hardware and software. Furthermore, where applicable, the various hardware and / or software components described herein may be combined into composite components including software, hardware, and / or both, without departing from the spirit of this disclosure. Where applicable, the various hardware and / or software components described herein may be divided into sub-components including software, hardware, or both, without departing from the spirit of this disclosure. Furthermore, where applicable, it is contemplated that software components may be implemented as hardware components, and vice versa.

[0095] According to the software disclosed herein, non-transitory instructions, program code, and / or data may be stored on one or more non-transitory machine-readable media. It is also contemplated that the software identified herein may be implemented using one or more networked and / or other general-purpose or special-purpose computers and / or computer systems. Where applicable, the order of the various steps described herein may be changed, combined, or subdivided into composite steps and / or sub-steps to provide the features described herein.

[0096] The above embodiments illustrate, but are not limited, the present invention. It should also be understood that many modifications and variations are possible based on the principles of the present invention. Therefore, the scope of the present invention is defined only by the following claims.

Claims

1. An adaptive power-on reset (POR) signal generator, comprising: A ramp voltage selector is configured to monitor the supply voltage provided by a power source and generate a ramp voltage based at least in part on the monitored supply voltage. as well as The logic device is configured as follows: The first supply voltage ramp traversal across the first threshold ramp voltage is detected, based at least in part on the ramp voltage provided by the ramp voltage selector. Detect a second supply voltage ramp traversal across a second threshold ramp voltage, wherein the second threshold ramp voltage is higher than the first threshold ramp voltage and the first threshold ramp voltage and the second threshold ramp voltage are lower than the nominal operating voltage associated with the power supply and / or the supply voltage; The timing for generating the POR signal is determined at least in part based on the amount of time between the first supply voltage ramp traversal and the second supply voltage ramp traversal. as well as The POR signal is generated based on the stated time.

2. The adaptive POR signal generator according to claim 1, wherein: The ramp voltage selector includes a resistor bypass switch and is configured to generate the ramp voltage based on the switching state of the resistor bypass switch, according to either the first threshold ramp voltage or the second threshold ramp voltage. as well as The logic device is configured as follows: Before detecting the first supply voltage ramp traversal, the ramp voltage selector is configured according to the first threshold ramp voltage by polling the switch state of the resistor bypass switch and / or opening the resistor bypass switch; as well as After the first supply voltage ramp traversal is detected and / or before the second supply voltage ramp traversal is detected, the ramp voltage selector is configured according to the second threshold ramp voltage by closing the resistor bypass switch.

3. The adaptive POR signal generator according to claim 1 further includes: A ramp traversal detector is configured to receive the ramp voltage from the ramp voltage selector and provide a ramp traversal signal to the logic device; as well as A counter is configured to receive a counter control signal from the logic device and to count incrementally and / or decrementally based at least in part on the counter control signal provided by the logic device. The detection of the first supply voltage ramp traversal includes: Detecting a first logic signal transition in the ramp traversal signal generated by the ramp traversal detector that corresponds to the first supply voltage ramp traversal; and The incrementing count is initiated by the counter; and The detection of the second supply voltage ramp traversal includes: Detecting a second logic signal transition in the ramp traversal signal generated by the ramp traversal detector, corresponding to the second supply voltage ramp traversal; and At the ramp time count corresponding to the amount of time between the first supply voltage ramp traversal and the second supply voltage ramp traversal, the incrementing count of the counter is stopped.

4. The adaptive POR signal generator of claim 3, further comprising a reference voltage generator configured to provide a reference voltage to the ramp ergodic detector, wherein generating the ramp ergodic signal by the ramp ergodic detector includes: Determine that the ramp voltage generated by the ramp voltage selector is greater than or equal to the reference voltage generated by the reference voltage generator, wherein the reference voltage is lower than the nominal operating voltage associated with the power supply and / or the supply voltage; and Generate the first logic signal transition in the ramp traversal signal.

5. The adaptive POR signal generator according to claim 3, wherein generating the POR signal comprises: The counter starts counting down from the ramp time; as well as The POR signal is generated when the countdown reaches zero.

6. The adaptive POR signal generator according to claim 5, further comprising: An oscillator is configured to receive a clock control signal from the logic device and to provide a clock signal to the counter based at least in part on the clock control signal provided by the logic device; The incrementing count, initiated by the counter, includes: Generate the counter control signal to control the counter to count incrementally; and Generate the clock control signal to enable the oscillator and control the oscillator to provide the clock signal to the counter; and The decrementing count initiated by the counter includes: Generate the counter control signal to control the counter to count down from the ramp time count; and The clock control signal is generated to enable the oscillator and control the oscillator to provide a modified clock signal to the counter, wherein the modified clock signal includes a frequency based at least in part on the nominal operating voltage and the amount of time between the first supply voltage ramp traversal and the second supply voltage ramp traversal.

7. The adaptive POR signal generator of claim 1, wherein the determination of the time for generating the POR signal is further based on the voltage difference between the second threshold voltage and the nominal operating voltage.

8. The adaptive POR signal generator of claim 1, wherein the time for generating the POR signal is determined when the supply voltage is at a voltage level between the second threshold ramp voltage and the nominal operating voltage, and wherein the logic device is configured to: The timing of generating the POR signal is determined by linear extrapolation based at least in part on the linear supply voltage ramp rate and the voltage difference between the nominal operating voltage and the second threshold ramp voltage, or by nonlinear extrapolation based at least in part on a nonlinear ramp curve associated with the power supply and / or the supply voltage.

9. A programmable logic device (PLD) comprising the adaptive POR signal generator according to claim 1, wherein: The PLD includes a PLD structure, a programmable input / output (I / O) interface, and / or a configuration engine. The programmable input / output (I / O) interface is configured to connect to user equipment and / or a semiconductor device interface separate from the PLD via an external bus coupled to the PLD. The configuration engine is configured to manage the configuration of the configuration engine, the PLD structure, and / or the programmable I / O interface and / or the communication between them. The PLD is configured to receive the supply voltage provided via a power bus coupled between the PLD and the power supply. The adaptive POR signal generator is integrated with the PLD and is configured to receive the supply voltage provided to the PLD via the power bus, provide the generated corresponding POR signal to the PLD structure, the programmable I / O interface and / or the configuration engine of the PLD, and de-reset one or more of the PLD structure, the programmable I / O interface and / or the configuration engine of the PLD.

10. A user equipment comprising the adaptive POR signal generator according to claim 1, wherein: The user equipment includes the power supply, programmable logic device (PLD), communication module, computing element and / or device module configured to implement at least a portion of a user interface, sensor or transducer and / or communication bus for: smartphone, laptop computer, tablet computer, desktop computer, smart environmental sensor, home automation device, network management device, smart display or television and / or automotive user interface. The adaptive POR signal generator is integrated with the user equipment and / or components of the user equipment and is configured to receive the supply voltage provided via a power bus coupled between the adaptive POR signal generator and the power supply, and to provide the generated POR signal to the PLD, the communication module, the computing element and / or the device module, and to release one or more reset states of the PLD, the communication module, the computing element and / or the device module.

11. A semiconductor device comprising the adaptive POR signal generator according to claim 1, wherein: The semiconductor device includes one or more power domains served by the power supply; The one or more power domains are configured to receive the supply voltage provided via a power bus coupled between the semiconductor device and the power supply; The adaptive POR signal generator is integrated with the semiconductor device and configured to receive the supply voltage provided to the semiconductor device via the power bus, provide the generated POR signal to the one or more power domains of the semiconductor device, and release one or more reset states of the one or more power domains of the semiconductor device.

12. A method comprising: Based at least in part on the ramp voltage, a first supply voltage ramp traversal across a first threshold ramp voltage is detected, the ramp voltage being generated by a ramp voltage selector based at least in part on the supply voltage, the supply voltage being provided by a power supply and monitored by the ramp voltage selector; Detect a second supply voltage ramp traversal across a second threshold ramp voltage, wherein the second threshold ramp voltage is higher than the first threshold ramp voltage, and the first threshold ramp voltage and the second threshold ramp voltage are lower than the nominal operating voltage associated with the power supply and / or the supply voltage; as well as The timing for generating the POR signal is determined at least in part based on the amount of time between the first supply voltage ramp traversal and the second supply voltage ramp traversal. as well as The POR signal is generated based on the stated time.

13. The method according to claim 12, wherein: The ramp voltage selector is configured to generate the ramp voltage based on a ramp voltage selection signal provided to the ramp voltage selector, according to a first threshold ramp voltage or a second threshold ramp voltage; as well as The method includes: Before detecting the first supply voltage ramp traversal, the ramp voltage selector is configured according to the first threshold ramp voltage; as well as After the first supply voltage ramp traversal is detected and / or before the second supply voltage ramp traversal is detected, the ramp voltage selector is configured according to the second threshold ramp voltage.

14. The method of claim 12, wherein detecting the first supply voltage ramp traversal comprises: The ramp ergodic detector generates the ramp ergodic signal based at least in part on the ramp voltage generated by the ramp voltage selector; Detect the first logic signal transition in the ramp traversal signal generated by the ramp voltage selector that corresponds to the first supply voltage ramp traversal; as well as The incrementing count is initiated by a counter.

15. The method of claim 14, wherein generating the ramp traversal signal comprises: Determine that the ramp voltage generated by the ramp voltage selector is greater than or equal to a reference voltage generated by a reference voltage generator coupled to the ramp traversal detector, wherein the reference voltage is lower than the nominal operating voltage associated with the power supply and / or the supply voltage; and Generate the first logic signal transition in the ramp traversal signal.

16. The method of claim 14, wherein detecting the second supply voltage ramp traversal comprises: Detect the second logic signal transition in the ramp traversal signal generated by the ramp traversal detector that corresponds to the second supply voltage ramp traversal; as well as At the ramp time count corresponding to the amount of time between the first supply voltage ramp traversal and the second supply voltage ramp traversal, the incrementing count of the counter is stopped.

17. The method of claim 16, wherein generating the POR signal comprises: The counter starts counting from the ramp time and begins decrementing based on the modified clock signal; as well as The POR signal is generated when the countdown reaches zero.

18. The method of claim 12, wherein the time for generating the POR signal is further determined based on the voltage difference between the second threshold voltage and the nominal operating voltage.

19. The method of claim 12, wherein the time for generating the POR signal is determined when the supply voltage is at a voltage level between the second threshold ramp voltage and the nominal operating voltage, and wherein determining the time for generating the POR comprises: The timing of generating the POR signal is determined by linear extrapolation based at least in part on the linear supply voltage ramp rate and the voltage difference between the nominal operating voltage and the second threshold ramp voltage, or by nonlinear extrapolation based at least in part on a nonlinear ramp curve associated with the power supply and / or the supply voltage.

20. The method of claim 12, further comprising: The supplied voltage is received via a power bus coupled between the power supply and the programmable logic device (PLD), communication module, computing element, device module and / or semiconductor device; as well as The generated POR signal is provided to one or more power domains of the PLD, the communication module, the computing element, the device module, and / or the semiconductor device, and one or more reset states of the following are released: one or more power domains of the PLD, the communication module, the computing element, the device module, and / or the semiconductor device.

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