Timing control device and control method thereof

Abstract

A timing control device and a control method thereof, the timing control device for a display panel, comprising a control circuit. The control circuit is configured to generate a plurality of gate scan control signals and data transfer control signals. In response to a display refresh rate changing from a first frequency to a second frequency, the control circuit adjusts the plurality of gate scan control signals to generate a plurality of adjusted gate scan control signals, or adjusts the data transfer control signals to generate an adjusted data transfer control signal, for driving the display panel at the second frequency as the display refresh rate.

Description

Technical Field

[0001] This invention relates to a timing control device and its control method, and more specifically to a timing control device for adjusting data charging time when the display refresh rate changes. Background Technology

[0002] In a display panel, a gate driver can provide multiple gate drive signals to sequentially turn on multiple switches of multiple display lines. A source driver can provide transmission data to be written into pixels of each of the multiple display lines via the switches. After the transmission data is filled into the pixel, the pixel's switch is turned off. In conventional technology, the switch is implemented using a thin-film transistor (TFT). When the TFT is in off mode, leakage current exists between the drain and source of the TFT. When the display panel operates in a variable refresh rate application, the display brightness will vary according to the refresh rate. For example, when the display refresh rate decreases, the display brightness will decrease. Therefore, the performance of the display panel degrades. Summary of the Invention

[0003] This invention provides a timing control device and a control method for providing balanced brightness of a display panel in variable refresh rate (VRR) applications.

[0004] According to an embodiment of the present invention, a timing control device for a display panel includes a control circuit. The control circuit is configured to generate a plurality of gate scan control signals and a data transmission control signal. In response to a change in the display refresh rate from a first frequency to a second frequency, the control circuit adjusts the plurality of gate scan control signals to generate a plurality of adjusted gate scan control signals, or adjusts the data transmission control signals to generate an adjusted data transmission control signal, for driving the display panel at the second frequency, which is the display refresh rate.

[0005] According to an embodiment of the present invention, the control method includes: generating a plurality of gate scan control signals and a data transmission control signal; and adjusting the plurality of gate scan control signals to generate a plurality of adjusted gate scan control signals, or adjusting the data transmission control signals to generate an adjusted data transmission control signal, in response to a change in the display refresh rate from a first frequency to a second frequency, for driving a display panel at the second frequency, which is the display refresh rate.

[0006] In summary, when the display refresh rate changes from a first frequency to a second frequency, the control circuit of the timing control device adjusts the gate scan control signal or the data transmission control signal. In variable refresh rate (VRR) applications, when the display refresh rate changes, the control circuit adjusts the data charging time of the display panel, which can balance the brightness of the display panel and improve the display quality.

[0007] To make the above features and advantages of the present invention easier to understand, the embodiments will be described in detail below with reference to the accompanying drawings. Attached Figure Description

[0008] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0009] Figure 1 A block diagram of a timing control device according to an embodiment of the present disclosure is shown.

[0010] Figure 2 The diagram illustrates waveforms of a timing control device operating at different display refresh rates according to embodiments of the present disclosure.

[0011] Figure 3 A waveform diagram is shown of a timing control device operating at different display refresh rates according to another embodiment of the present disclosure.

[0012] Figure 4 A schematic diagram illustrating a display brightness compensation scheme according to an embodiment of the present disclosure is shown.

[0013] Figure 5 A block diagram of a timing control device according to another embodiment of the present disclosure is shown.

[0014] Figure 6 A block diagram of a timing control device according to another embodiment of the present disclosure is shown.

[0015] Figure 7 A block diagram of a timing control device according to another embodiment of the present disclosure is shown.

[0016] Figure 8 A waveform diagram is shown of a timing control device operating at different display refresh rates according to another embodiment of the present disclosure.

[0017] Figure 9 A waveform diagram is shown of a timing control device operating at different display refresh rates according to another embodiment of the present disclosure.

[0018] Figure 10 A block diagram of a timing control device according to another embodiment of the present disclosure is shown.

[0019] Figure 11A flowchart illustrating a control method for a display device according to an embodiment of the present disclosure is shown.

[0020] [Explanation of Symbols]

[0021] 110: Timing control device

[0022] 111, 511, 611, 711, 1011: Control circuit

[0023] 120: Display panel

[0024] 410, 420: Curves

[0025] 510, 610, 710, 1010: Timing control devices

[0026] 521, 621: Gate Array (GOA)

[0027] 522, 622, 722, 1022: Source Driver (S-IC)

[0028] 612, 1012: Frame rate detection circuit

[0029] 721, 1021: Gate Driver (G-IC)

[0030] CLK1, CLK2, CLK3, CLK4~CLKx, CLKN: Gate scan control signals

[0031] CLK1', CLK2', CLK3', CLK4': Adjusted gate scan control signal

[0032] CT1: Data charging time

[0033] CT2: Data charging time / Adjusted data charging time

[0034] CT3: Adjusted data charging time

[0035] DE: Data enable signal

[0036] DFR1: First display refresh rate

[0037] DFR2: Second display refresh rate

[0038] DRV: Numeric Value

[0039] EG1: Frontier

[0040] EG1': Adjusted frontier

[0041] EG2: trailing edge

[0042] EG2': Adjusted edge

[0043] G1~G1917, G1918, G1919, G1920: Gate drive signals

[0044] KB: Chamfering control signal

[0045] LAVG1, LAVG2: Average display brightness

[0046] OE: Output enable signal

[0047] PS1: Pulse

[0048] PS1': Narrow pulse

[0049] S1110, S1120: Steps

[0050] STV: Start of Frame Signal

[0051] TP: Data transmission control signal

[0052] TP': Adjusted data transmission control signal

[0053] TX_DATA: Transmitted data

[0054] Vsync: Vertical synchronization signal Detailed Implementation

[0055] Throughout this application's description (including the claims), the term "coupled (or connected)" is used extensively and encompasses both direct and indirect connections or coupling methods. For example, if this disclosure describes a first device being coupled (or connected) to a second device, it should be interpreted as the first device being directly connectable to the second device, or the first device being indirectly connected to the second device via other means or through a specific coupling method. Furthermore, terms such as "first" and "second" used throughout this application's description (including the claims) are used only to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor are they intended to limit the order of elements. Additionally, in the drawings and embodiments, elements / components / steps with the same reference numerals represent the same or similar parts. Elements / components / symbols with the same reference numerals in different embodiments can be referred to the relevant descriptions.

[0056] Please refer to Figure 1 , Figure 1 A block diagram of a timing control device according to an embodiment of the present disclosure is shown, and reference is also made to... Figure 2 , Figure 2The diagram illustrates waveforms of a timing control device according to an embodiment of the present disclosure operating at different display refresh rates. The timing control device 110 includes a control circuit 111. The control circuit 111 is coupled to a display panel 120. The control circuit 111 is configured to generate a plurality of gate scan control signals CLK1 to CLKN and a data transmission control signal TP, and transmit the gate scan control signals CLK1 to CLKN and the data transmission control signal TP to the display panel 120 for driving the display panel 120. Specifically, the display panel 120 receives the gate scan control signals CLK1 to CLKN and generates a plurality of gate drive signals, such as gate drive signals G1 to G1920, if the display panel 120 has 1920 gate lines and 1920 display lines (i.e., pixel rows, also called horizontal lines), wherein in Figure 2 The diagram illustrates gate drive signals G1917 to G1920 as an example. Gate scan control signals CLK1 to CLKN are periodic signals with the same period but different phases, and the gate onarray circuit in the display panel 120 can generate gate drive signals G1 to G1920 respectively output to the gate lines of the display panel 120 according to the gate scan control signals CLK1 to CLK4. In each frame period, each gate drive signal has only one enable cycle (or pulse), and the timing of the enable cycle of each gate drive signal is the same as one of the multiple pulses of the gate scan control signals CLK1 to CLK4. The timing control device 110 can be implemented as a timing controller integrated circuit (IC), or the timing control device 110 and the data drive circuit can be implemented as a single-chip display driver IC.

[0057] The data transmission control signal TP is a periodic signal with multiple pulses. Each pulse of the data transmission control signal TP indicates the writing time when display data for a corresponding display line of the display panel 120 is written to that display line. In this embodiment, the data charging time of one of the multiple display lines can be determined by the trailing edge of the pulse of the data transmission control signal TP (e.g., the time when the data is charged to the corresponding display line). Figure 2 The time difference between the falling edge of the gate drive signal and the trailing edge of the gate drive signal pulse (i.e., the enable cycle) is used to determine the signal, wherein the gate drive signal pulse is aligned with one of the multiple pulses of the gate scan control signals CLK1 to CLK4.

[0058] By adjusting the data charging time, the timing control device 110 enables the display panel 120 to operate at a variable refresh rate while maintaining consistent display brightness. It should be noted that when the display refresh rate of the display panel 120 changes from a higher first frequency to a lower second frequency, the vertical blanking time increases and the display brightness decreases. In response, the timing control device 110 can adjust the gate scan control signals CLK1 to CLKN to generate multiple adjusted gate scan control signals, or adjust the data transmission control signal TP to generate an adjusted data transmission control signal, thereby increasing the data charging time of the display panel 120. In this way, the data charging time can be increased accordingly, while the display brightness of the display panel 120 can remain constant.

[0059] Please refer to this together. Figure 1 and Figure 2 The data enable signal DE can be transmitted from the front-end circuitry to the timing control device 110. The data enable signal DE is used to define the display time of one display line of the display panel 120. When the data enable signal DE is held at a low voltage level, the display panel 120 is in the vertical blanking time period. When it is detected that the display panel 120 is operating at a first display refresh rate DFR1, the control circuit 111 can generate multiple gate scan control signals CLK1 to CLK4, a data transmission control signal TP, and transmission data TX_DATA (which represents the display data of a drive channel). The data transmission control signal TP is used to define the time point for accessing the transmission data TX_DATA. In this embodiment, the transmission data TX_DATA is transmitted to the display panel 120 at the trailing edge of the pulse of the data transmission control signal TP.

[0060] Here, multiple pulses of the data transmission control signal TP correspond to multiple transmitted data (denoted as TX_DATA) output from the drive channel. For example, the rightmost data pertains to the 1920th display line, and the pulse of the data transmission control signal TP indicates the write time for the 1920th display line; the second data on the right pertains to the 1919th display line, and another pulse of the data transmission control signal TP indicates the write time for the 1919th display line, and so on. Figure 2 In this context, the data charging time CT1 for the data of the 1917th display line can be determined from the trailing edge of the pulse PS1 (which is the pulse of the data transmission control signal TP indicating the write time of the 1917th display line) to the trailing edge of the pulse of the gate drive signal G1917 (which is generated based on the gate scan control signal CLK1) (i.e., the enable period), such that the pulse of the gate drive signal G1917 (i.e., the enable period) is the same as the corresponding pulse of the gate scan control signal CLK1.

[0061] When it is detected that the display panel 120 changes to operate at the second display refresh rate DFR2, and the second frequency of the second display refresh rate DFR2 is lower than the first frequency of the first display refresh rate DFR1, the control circuit 111 can delay the phase of the gate scan control signals CLK1 to CLK4 to generate the plurality of adjusted gate scan control signals CLK1' to CLK4', and can increase the data charging time of the display panel 120.

[0062] Taking the gate scan control signal CLK1 as an example, the control circuit 111 can change the leading edge EG1 and trailing edge EG2 of the gate scan control signal CLK1 to obtain the adjusted leading edge EG1' and adjusted trailing edge EG2' of the adjusted gate scan control signal CLK1', respectively. By adjusting the adjusted trailing edge EG2' of the adjusted gate scan control signal CLK1', the adjusted data charging time CT2 can be increased. The adjusted data charging time CT2 is determined by the time difference between the trailing edge of the pulse (PS1) of the data transmission control signal TP indicating the write time of the 1917th display line and the adjusted trailing edge of the pulse (i.e., the enable period) of the gate drive signal G1917 (the adjusted trailing edge of the pulse is aligned with the adjusted trailing edge EG2' of the adjusted gate scan control signal CLK1').

[0063] In this disclosure, the duty cycle and frequency of the gate scan control signal CLK1 can be the same as those of the adjusted gate scan control signal CLK1'. Only the phase of each gate scan control signal is changed.

[0064] In this embodiment, if the display panel 120 changes from operating at the second display refresh rate DFR2 to operating at the first display refresh rate DFR1, i.e., the display refresh rate increases, the control circuit 111 can shift the phase of the gate scan control signals CLK1' to CLK4' in advance to generate adjusted gate scan control signals CLK1 to CLK4 to reduce the time difference between the trailing edge of the pulse (e.g., PS1, corresponding to the 1917th display line) of the data transmission control signal TP that indicates the write time of the display line and the adjusted trailing edge (e.g., EG2') of the adjusted gate scan control signal (e.g., CLK1' aligned with the adjusted trailing edge of the gate drive signal G1917).

[0065] In this way, whether the display refresh rate is from a higher to a lower refresh rate or from a lower to a higher refresh rate, the display brightness of the display panel 120 can be balanced between the first display refresh rate DFR1 and the second display refresh rate DFR2.

[0066] It should be noted here that the change in the display refresh rate of the display panel 120 can be detected by the timing control device 110. When the display refresh rate changes from a higher first display refresh rate DFR1 to a lower second display refresh rate DFR2, the timing control device 110 sets the control circuit 111 to generate adjusted gate scan control signals CLK1' to CLK4' by delaying the phase of the gate scan control signals CLK1 to CLK4.

[0067] Please refer to this together. Figure 1 and Figure 3 ,in Figure 3 Waveform graphs showing the timing control device according to another embodiment of the present disclosure operating at different display refresh rates are illustrated. Figure 3 In this embodiment, the data enable signal DE can be transmitted from the front-end circuit to the timing control device 110. The data enable signal DE is used to define the display time of one display line of the display panel 120. When the data enable signal is held at a low voltage level, the display panel 120 is in the vertical blanking time period. When it is detected that the display panel 120 is operating at the first display refresh rate DFR1, the control circuit 111 can generate multiple gate scan control signals CLK1 to CLK4, a data transmission control signal TP, and transmission data TX_DATA. The gate scan control signals CLK1 to CLK4 are enabled sequentially. The display panel 120 can generate multiple gate drive signals according to the gate scan control signals CLK1 to CLK4. The data transmission control signal TP is used to define the time point for accessing the transmission data TX_DATA. In this embodiment, the transmission data TX_DATA is transmitted to the display panel 120 at the trailing edge of the pulse of the data transmission control signal TP.

[0068] Taking the gate scan control signal CLK1 as an example, the data charging time CT1 of the 1917th display line can be determined by the time difference between the trailing edge of the pulse PS1 of the data transmission control signal TP of the 1917th display line and the trailing edge of the pulse (i.e., the enable cycle) of the gate drive signal G1917 (the trailing edge of the pulse is aligned with the trailing edge of the gate scan control signal CLK1).

[0069] When it is detected that the display panel 120 is operating at the second display refresh rate DFR2, and the second frequency of the second display refresh rate DFR2 is lower than the first frequency of the first display refresh rate DFR1, the control circuit 111 can reduce the duty cycle of the data transmission control signal TP to generate an adjusted data transmission control signal TP', thereby increasing the data charging time.

[0070] In this embodiment, the control circuit 111 can narrow the width of each pulse of the data transmission control signal TP (in other words, reduce the duty cycle) to generate an adjusted data transmission control signal TP'. Taking the gate scan control signal CLK1 as an example, the adjusted data charging time CT3 of a display line can be determined by the time difference between the trailing edge of the narrow pulse PS1' of the adjusted data transmission control signal TP' and the trailing edge of the pulse of the gate drive signal G1917 (i.e., the enable cycle) (the trailing edge of the pulse is aligned with the trailing edge of the gate scan control signal CLK1).

[0071] Of course, if the display panel 120 changes from operating at the second display refresh rate DFR2 to operating at the first display refresh rate DFR1, the control circuit 111 can increase the duty cycle of the data transmission control signal TP to generate an adjusted data transmission control signal TP'. In this way, the display brightness of the display panel 120 can be maintained in variable refresh rate (VRR) applications.

[0072] Please refer to Figure 4 , Figure 4 A schematic diagram of a display brightness compensation scheme according to an embodiment of the present disclosure is shown. Curve 410 represents the display brightness when the display panel operates at a first display refresh rate with a higher first frequency. Curve 420 represents the display brightness when the display panel operates at a second display refresh rate with a lower second frequency. In this embodiment, when the display refresh rate of the display panel changes between the first display refresh rate and the second display refresh rate, the timing control device can dynamically adjust the data charging time between the data charging time CT1 and the data charging time CT2. Specifically, when the display refresh rate of the display panel is the higher first frequency, the display panel can have a lower data charging time CT1, and when the display refresh rate of the display panel is the lower first frequency, the display panel can have a higher data charging time CT2. In this way, the average display brightness LAVG1 of the display panel at the first display refresh rate can be the same as the average display brightness LAVG2 of the display panel at the second display refresh rate. This can improve the display performance of the display panel.

[0073] Please refer to Figure 5 , Figure 5 A block diagram of a timing control device according to another embodiment of the present disclosure is shown.

[0074] Timing control device 510 is coupled to gate-on-array (GOA) 521 and source driver (S-IC) 522. GOA 521 and S-IC 522 are used to provide gate drive signals and source drive signals, respectively, to drive the display panel. Timing control device 510 includes control circuitry 511.

[0075] The timing control device 510 receives the data enable signal DE and generates a frame start signal STV, multiple gate scan control signals CLKx, and a data transmission control signal TP. The timing control device 510 transmits the frame start signal STV and the gate scan control signals CLKx to GOA 521 and the data transmission control signal TP to S-IC 522. GOA 521 can generate a gate drive signal based on the frame start signal STV and the gate scan control signals CLKx. S-IC 522 can generate a source drive signal based on the data transmission control signal TP and the transmitted data.

[0076] In this embodiment, GOA 521 can be implemented by any gate array circuit known to those skilled in the art, and S-IC 522 can be implemented by any source drive circuit known to those skilled in the art, and there are no further particular limitations herein.

[0077] In this embodiment, the data enable signal DE can be provided by the front-end circuitry (e.g., a TV chip). The control circuitry 511 can detect the display refresh rate based on the data enable signal DE. Specifically, the data enable signal DE can provide a specific time period for maintaining a low voltage level, and said specific time period is the vertical blanking time period. The control circuitry 511 can detect the display refresh rate by identifying the vertical blanking time period based on the data enable signal DE. If the length of the vertical blanking time period increases, the control circuitry 511 can determine that the display refresh rate is decreasing; and if the length of the vertical blanking time period decreases, the control circuitry 511 can determine that the display refresh rate is increasing.

[0078] Furthermore, the control circuit 511 can generate a frame start signal STV based on the data enable signal DE. The control circuit 511 can also obtain the display refresh rate based on the frame start signal STV. The frame start signal STV provides multiple vertical start pulses, and the control circuit 511 can obtain the display refresh rate by calculating two adjacent start pulses.

[0079] The control circuit 511 can adjust the phase of the gate scan control signals CLK1 to CLKx or the duty cycle of the data transmission control signal TP based on the detected display refresh rate obtained by detecting the frame start signal STV. If the display refresh rate changes from a higher first frequency to a lower second frequency, the control circuit 511 can delay the phase of the gate scan control signals CLK1 to CLKx or decrease the duty cycle of the data transmission control signal TP. Conversely, if the display refresh rate changes from a lower first frequency to a higher second frequency, the control circuit 511 can advance the phase of the gate scan control signals CLK1 to CLKx or increase the duty cycle of the data transmission control signal TP.

[0080] The hardware structure of the control circuit 511 can be implemented using digital circuitry. Alternatively, the control circuit 511 can be implemented using any processor or controller chip known to those skilled in the art that is capable of operation.

[0081] Please refer to Figure 6 , Figure 6 A block diagram of a timing control device according to another embodiment of the present disclosure is shown. The timing control device 610 is coupled to a gate array (GOA) 621 and a source driver (S-IC) 622. The GOA 621 and S-IC 622 are used to provide gate drive signals and source drive signals, respectively, to drive the display panel. The timing control device 610 includes a control circuit 611 and a frame rate detection circuit 612. The control circuit 611 is coupled to the frame rate detection circuit 612. The frame rate detection circuit 612 can receive a vertical synchronization signal Vsync and determine the display refresh rate based on the vertical synchronization signal Vsync. The frame rate detection circuit 612 can generate a digital value DRV based on the detected display refresh rate and transmit the digital value DRV to the control circuit 611.

[0082] Control circuit 611 receives the digital value DRV and obtains the display refresh rate by decoding the digital value DRV. Control circuit 611 can adjust the phase of the gate scan control signals CLK1 to CLKx or adjust the duty cycle of the data transmission control signal TP according to the detected display refresh rate. If the display refresh rate changes from a higher first frequency to a lower second frequency, control circuit 611 can delay the phase of the gate scan control signals CLK1 to CLKx or decrease the duty cycle of the data transmission control signal TP. Conversely, if the display refresh rate changes from a lower first frequency to a higher second frequency, control circuit 611 can advance the phase of the gate scan control signals CLK1 to CLKx or increase the duty cycle of the data transmission control signal TP.

[0083] Please refer to Figure 7 , Figure 7 A block diagram of a timing control device according to another embodiment of the present disclosure is shown. The timing control device 710 is coupled to a gate driver (G-IC) 721 and a source driver (S-IC) 722. Unlike... Figure 5 The timing control device 510 is coupled to the G-IC 721, which is not located on the display panel. Both G-IC 721 and S-IC 722 can be off-panel chips.

[0084] In this embodiment, the timing control device 710 includes a control circuit 711. The control circuit 711 receives a data enable signal DE and generates a frame start signal STV, multiple gate scan control signals CLK1 to CLKx, an output enable signal OE, a chamfer control signal KB, and a data transmission control signal TP based on the data enable signal DE. The control circuit 711 transmits the frame start signal STV, the gate scan control signals CLK1 to CLKx, the output enable signal OE, and the chamfer control signal KB to the G-IC 721, and transmits the data transmission control signal TP to the S-IC 722.

[0085] The control circuit 711 can obtain the display refresh rate based on the data enable signal DE. The control circuit 711 can also adjust the phase of the gate scan control signals CLK1 to CLKx based on the detected display refresh rate.

[0086] In this embodiment, G-IC 721 can be implemented on an integrated circuit, and the hardware structure of G-IC 721 can be implemented by any gate drive circuit known to those skilled in the art. S-IC 722 can also be implemented by any source drive circuit known to those skilled in the art. There are no particular limitations here.

[0087] Figure 8 A waveform diagram showing the timing control device according to another embodiment of the present disclosure operating at different display refresh rates is shown. (Refer to...) Figure 7 and Figure 8 In this embodiment, to adjust the phase of the gate scan control signals CLK1 to CLKx, the control circuit 711 can adjust the duty cycle of the output enable signal OE and the phase of the chamfer control signal KB to adjust the gate scan control signals CLK1 to CLKx. For details, please refer to... Figure 8 , Figure 8 The diagram illustrates waveforms of a timing control device according to another embodiment of the present disclosure operating at different display refresh rates. When the display refresh rate becomes lower (the display refresh rate changes from a first display refresh rate DFR1 to a second display refresh rate DFR2), the control circuit 711 can delay the trailing edge of each of the gate scan control signals CLK1 to CLKx by increasing the duty cycle of the output enable signal OE and delaying the phase of the chamfer control signal KB. This increases the data charging time of the display lines. Conversely, when the display refresh rate becomes higher (the display refresh rate changes from the second display refresh rate DFR2 to the first display refresh rate DFR1), the control circuit 711 can advance the trailing edge of each of the gate scan control signals CLK1 to CLKx by decreasing the duty cycle of the output enable signal OE and advancing the phase of the chamfer control signal KB. This reduces the data charging time of the display lines.

[0088] On the other hand, in another embodiment, in response to a change in the display refresh rate, the control circuit 711 can adjust the duty cycle of the data transmission control signal TP according to the detected display refresh rate. Please refer to... Figure 9 , Figure 9 The diagram illustrates waveforms of a timing control device according to another embodiment of the present disclosure operating at different display refresh rates. When the display refresh rate becomes lower (the display refresh rate changes from a first display refresh rate DFR1 to a second display refresh rate DFR2), the control circuit 711 can reduce the duty cycle of the data transmission control signal TP without changing the frequency of the data transmission control signal TP, thereby increasing the data charging time of the display line. In other words, the control circuit 711 narrows the width of each pulse of the data transmission control signal TP to increase the data charging time of the display line. Conversely, when the display refresh rate becomes higher (the display refresh rate changes from a second display refresh rate DFR2 to a first display refresh rate DFR1), the control circuit 711 can increase the duty cycle of the data transmission control signal TP without changing the frequency of the data transmission control signal TP, thereby reducing the data charging time of the display line. In other words, the control circuit 711 widens the width of each pulse of the data transmission control signal TP to reduce the data charging time of the display line.

[0089] In this way, by adjusting the plurality of gate scan control signals or adjusting the data transmission control signals, the control circuit 711 can adjust the data charging time of the display line according to the display refresh rate and maintain the display brightness of the display panel.

[0090] Please refer to Figure 10 , Figure 10 A block diagram of a timing control device according to another embodiment of the present disclosure is shown. The timing control device 1010 is coupled to a gate driver (G-IC) 1021 and a source driver (S-IC) 1022. The timing control device 1010 is coupled to a G-IC 1021 that is not disposed on the display panel. Both G-IC 1021 and S-IC 1022 may be off-panel chips. The timing control device 1010 includes a control circuit 1011 and a frame rate detection circuit 1012. The control circuit 1011 is coupled to the frame rate detection circuit 1012. The frame rate detection circuit 1012 receives a vertical synchronization signal Vsync and determines the display refresh rate based on the vertical synchronization signal Vsync. The frame rate detection circuit 1012 can generate a digital value DRV based on the detected display refresh rate and transmit the digital value DRV to the control circuit 1011.

[0091] The control circuit 1011 can decode the digital value DRV to obtain the display refresh rate, and generate a frame start signal STV, multiple gate scan control signals CLK1 to CLKx, an output enable signal OE, a chamfer control signal KB, and a data transmission control signal TP according to the display refresh rate. In this embodiment, the control circuit 1011 can also adjust the phase of the gate scan control signals CLK1 to CLKx, or adjust the data transmission control signal TP, according to the detected display refresh rate, to drive the display panel at the currently detected display refresh rate.

[0092] Please refer to Figure 11 , Figure 11 A flowchart illustrating a control method for a display device according to an embodiment of the present disclosure is shown. In step S1110, a plurality of gate scan control signals and a data transmission control signal are generated. In step S1120, in response to a change in the display refresh rate from a first frequency to a second frequency, the plurality of gate scan control signals can be adjusted to generate a plurality of adjusted gate scan control signals, or the data transmission control signals can be adjusted to generate an adjusted data transmission control signal, for driving the display panel at the second frequency, which is the display refresh rate.

[0093] The details of the above steps have been described in the above embodiments and will not be repeated here.

[0094] In summary, in this embodiment, in response to a variable display refresh rate, the timing control device can adjust the gate scan control signal or the data transmission control signal to adjust the data charging time of each display line of the display panel. This allows for maintaining the display brightness of the display panel in variable refresh rate applications and improves the performance of the display panel.

[0095] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the embodiments of this disclosure without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A timing control device for a display panel, comprising: The control circuit is configured to generate multiple gate scan control signals and data transmission control signals; In response to a change in the display refresh rate from a relatively high first frequency to a relatively low second frequency, the control circuit generates a plurality of adjusted gate scan control signals by adjusting the leading and trailing edges of each of the plurality of gate scan control signals to delay the phase of the plurality of gate scan control signals, or by reducing the pulse width of the data transmission control signal to reduce the duty cycle of the data transmission control signal to generate an adjusted data transmission control signal. This signal is used to drive the display panel at the second frequency, which is the display refresh rate, by increasing the time difference between the trailing edge of the data transmission control signal and the trailing edges of the plurality of gate scan control signals. The time difference between the trailing edge of the data transmission control signal and the trailing edge of the gate scan control signal is used to define the data writing time of the display line. The gate scan control signal has the same frequency and duty cycle before and after adjustment.

2. The timing control device according to claim 1, further comprising: In response to the display refresh rate changing from a relatively low first frequency to a relatively high second frequency, the control circuit advances the phase of the plurality of gate scan control signals to generate the plurality of adjusted gate scan control signals.

3. The timing control device according to claim 2, wherein the control circuit adjusts the phase of the plurality of gate scan control signals by changing the leading edge of each of the plurality of gate scan control signals and changing the trailing edge of each of the plurality of gate scan control signals or changing the pulse width of each of the plurality of gate scan control signals.

4. The timing control device according to claim 1, further comprising: In response to the display refresh rate changing from a relatively low first frequency to a relatively high second frequency, the control circuit increases the duty cycle of the data transmission control signal to generate the adjusted data transmission control signal.

5. The timing control device according to claim 4, wherein the control circuit adjusts the duty cycle of the data transmission control signal by changing the trailing edge of the data transmission control signal or changing the pulse width of the data transmission control signal.

6. The timing control device according to claim 1, wherein the control circuit is further configured to receive a data enable signal and determine the display refresh rate based on the data enable signal.

7. The timing control device according to claim 1, further comprising: A frame rate detection circuit, coupled to the control circuit, is configured to receive a vertical synchronization signal and determine the display refresh rate based on the vertical synchronization signal.

8. The timing control device according to claim 1, wherein the control circuit further adjusts the plurality of gate scan control signals by adjusting the duty cycle of the output enable signal and adjusting the phase of the chamfer control signal.

9. The timing control device according to claim 8, wherein the control circuit delays the trailing edge of each of the plurality of gate scan control signals by increasing the duty cycle of the output enable signal and delaying the phase of the chamfering control signal, or the control circuit advances the trailing edge of each of the plurality of gate scan control signals by decreasing the duty cycle of the output enable signal and advancing the phase of the chamfering control signal.

10. The timing control device according to claim 1, wherein the timing control device transmits the plurality of gate scan control signals to the gate drive circuit and transmits the data transmission control signal to the source drive circuit.

11. A control method for a display device, comprising: Generates multiple gate scan control signals and data transmission control signals; as well as In response to a change in display refresh rate from a relatively high first frequency to a relatively low second frequency, a plurality of adjusted gate scan control signals are generated by adjusting the leading and trailing edges of the plurality of gate scan control signals to delay the phase of the plurality of gate scan control signals, or by reducing the pulse width of the data transmission control signal to reduce the duty cycle of the data transmission control signal to generate an adjusted data transmission control signal. These signals are used to drive the display panel at the second frequency, which is the display refresh rate, by increasing the time difference between the trailing edge of the data transmission control signal and the trailing edges of the plurality of gate scan control signals. The time difference between the trailing edge of the data transmission control signal and the trailing edge of the gate scan control signal is used to define the data writing time of the display line. The gate scan control signal has the same frequency and duty cycle before and after adjustment.

12. The control method of claim 11, wherein the step of adjusting the plurality of gate scan control signals to generate the plurality of adjusted gate scan control signals further comprises: In response to the display refresh rate changing from a relatively low first frequency to a relatively high second frequency, the phase of the plurality of gate scan control signals is shifted in advance to generate the plurality of adjusted gate scan control signals.

13. The control method according to claim 12, wherein the step of delaying the phase of the plurality of gate scan control signals or shifting the phase of the plurality of gate scan control signals in advance comprises: The phase of the plurality of gate scan control signals is adjusted by changing the leading edge and the trailing edge or pulse width of each of the plurality of gate scan control signals.

14. The control method of claim 12, wherein the step of adjusting the data transmission control signal to generate the adjusted data transmission control signal further comprises: In response to the display refresh rate changing from a relatively low first frequency to a relatively high second frequency, the duty cycle of the data transmission control signal is increased to generate the adjusted data transmission control signal.

15. The control method according to claim 14, wherein the step of decreasing the duty cycle of the data transmission control signal or increasing the duty cycle of the data transmission control signal comprises: The duty cycle of the data transmission control signal is adjusted by changing the trailing edge of the data transmission control signal or by changing the pulse width of the data transmission control signal.

16. The control method according to claim 14, further comprising: Receive a data enable signal and determine the display refresh rate based on the data enable signal.

17. The control method according to claim 11, further comprising: Receive the vertical synchronization signal and determine the display refresh rate based on the vertical synchronization signal.

18. The control method of claim 11, wherein the step of adjusting the plurality of gate scan control signals to generate the plurality of adjusted gate scan control signals comprises: Adjust the duty cycle of the output enable signal and adjust the phase of the chamfer control signal to adjust the plurality of gate scan control signals.

19. The control method of claim 18, wherein the step of adjusting the duty cycle of the output enable signal and adjusting the phase of the chamfering control signal to adjust the plurality of gate scan control signals comprises: The trailing edges of each of the plurality of gate scan control signals are delayed by increasing the duty cycle of the output enable signal and delaying the phase of the chamfer control signal; or The trailing edge of each of the plurality of gate scan control signals is advanced by reducing the duty cycle of the output enable signal and advancing the phase of the chamfer control signal.

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