Memory interface device
By introducing a DQS input buffer, offset control circuit, and duty cycle adjustment buffer into the memory interface device, self-DQS cleanup is achieved, solving the problem of unwanted pulse generation, improving data transmission efficiency, and reducing circuit complexity and power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ELECTRONICS & TELECOMM RES INST
- Filing Date
- 2022-02-17
- Publication Date
- 2026-06-09
AI Technical Summary
Existing memory interface devices are prone to generating unwanted pulses without gating signals or DQS training, affecting the accuracy and efficiency of data transmission.
By employing a DQS input buffer, offset control circuit, and duty cycle adjustment buffer, and through static and dynamic offset control, self-DQS purification is achieved to avoid the generation of unwanted pulses.
Without a separate gating signal or DQS training, the generation of unwanted pulses is reduced, circuit area and power consumption are decreased, and data transmission efficiency is improved.
Smart Images
Figure CN115083460B_ABST
Abstract
Description
[0001] This application claims priority and benefit to Korean Patent Applications No. 10-2021-0034228 and No. 10-2021-0190915, filed with the Korean Intellectual Property Office on March 16, 2021 and December 29, 2021, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This disclosure relates to a memory interface device. Background Technology
[0003] In many electronic devices such as smartphones, desktop computers, laptops, and servers, various types of memory, such as Double Data Rate (DDR), Graphics Double Data Rate (GDDR), Low Power Double Data Rate (LPDDR), and High Bandwidth Memory (HBM), are used depending on their purpose and characteristics. As memory technology advances, data transfer rates are constantly increasing. For example, when moving to the LPDDR5 standard, the LPDDR memory interface was defined as having a maximum speed of 6.4 Gbps and a minimum signal size of 140 mV. Such a signal standard inevitably becomes more sensitive to noise and channel characteristics.
[0004] To recover high-speed, fine-grained signals into digital signals, analog-based equalizers (such as continuous-time linear equalizers (CTLEs)) and digital-based decision feedback equalizers (DFEs) are required. CTLEs are circuits that amplify high-frequency components. CTLEs are advantageous in recovering data or clock signals by compensating for high-frequency components lost in the channel; however, conversely, they can generate errors, such as unwanted high-frequency signals. Specifically, unwanted pulses may be generated when the data strobe (DQS) clock is recovered and then switched to a high-impedance state.
[0005] The information disclosed in this background section is intended only to enhance the understanding of the background art of this disclosure, and therefore may contain information that does not form prior art known to a person skilled in the art in this country. Summary of the Invention
[0006] The purpose of this disclosure is to provide a memory interface device capable of self-DQS cleanup, which prevents the generation of unwanted pulses in the absence of a gating signal or DQS training.
[0007] An exemplary embodiment of this disclosure provides a memory interface device, including: a DQS input buffer configured to receive an input data strobe signal and output a first intermediate data strobe signal, wherein the DQS input buffer provides a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty cycle adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit uses the clean data strobe signal to provide a dynamic offset.
[0008] According to embodiments of this disclosure, the offset control circuit may include two offset control transistors that are turned on according to a purge data strobe signal to change the dynamic offset.
[0009] According to an embodiment of this disclosure, when the first purification data strobe signal in the purification data strobe signal is at a high level, the second offset control transistor of the two offset control transistors can be turned on.
[0010] According to an embodiment of this disclosure, when the second purification data strobe signal in the purification data strobe signal is at a high level, the first offset control transistor of the two offset control transistors can be turned on.
[0011] According to an embodiment of this disclosure, when the first input data strobe signal in the input data strobe signal is high, the second offset control transistor of the two offset control transistors can be turned on.
[0012] According to embodiments of this disclosure, a second offset control transistor that is turned on can pull down a second node of the DQS input buffer to provide a positive dynamic offset.
[0013] According to an embodiment of this disclosure, when the second input data strobe signal in the input data strobe signal is high, the first offset control transistor of the two offset control transistors can be turned on.
[0014] According to embodiments of this disclosure, a first offset control transistor that is turned on can pull down a first node of the DQS input buffer to provide a negative dynamic offset.
[0015] According to an embodiment of this disclosure, when the first input data strobe signal in the input data strobe signal is at a low level and the second input data strobe signal changes from a high level to a low level, the first offset control transistor of the two offset control transistors can be turned on.
[0016] According to embodiments of this disclosure, the static offset may be a direct current (DC) offset.
[0017] According to embodiments of this disclosure, static offset can be provided by setting different sizes of symmetrical transistors forming a differential structure in the DQS input buffer.
[0018] According to embodiments of this disclosure, the input data strobe signal may be a differential data strobe signal.
[0019] According to embodiments of this disclosure, the duty cycle adjustment buffer can adjust the duty cycle error caused by static offset.
[0020] Another embodiment of this disclosure provides a memory interface device, including: a first input transistor configured to receive a first input data strobe signal; a second input transistor configured to receive a second input data strobe signal, wherein the second input transistor and the first input transistor form a differential structure; a first offset control transistor connected to the second input transistor through a first node, wherein when the second input data strobe signal is high, the first offset control transistor is turned on to pull down the first node; and a second offset control transistor connected to the first input transistor through a second node, wherein when the first input data strobe signal is high, the second offset control transistor is turned on to pull down the second node.
[0021] According to embodiments of the present disclosure, the memory interface device may further include: a duty cycle adjustment buffer configured to receive signals from a first node and a second node and output a clean data strobe signal.
[0022] According to embodiments of this disclosure, a clean data strobe signal may be provided to the gates of a first offset control transistor and a second offset control transistor.
[0023] According to an embodiment of this disclosure, when the second purification data strobe signal in the purification data strobe signal is at a high level, the first offset control transistor can be turned on.
[0024] According to an embodiment of this disclosure, when the first purification data strobe signal in the purification data strobe signal is at a high level, the second offset control transistor can be turned on.
[0025] According to an embodiment of this disclosure, when the first input data strobe signal is low and the second input data strobe signal changes from high to low, the first offset control transistor can be turned on.
[0026] According to embodiments of this disclosure, the dimensions of the first input transistor and the second input transistor may be set to be different.
[0027] According to embodiments of this disclosure, when the DQS signal is high impedance or the DQS_t / DQS_c signal is applied to ground, a self-DQS cleanup circuit is provided that can recover normal DQS pulses on its own, so that unintentional pulses will not occur without a separate gating signal or DQS training. Therefore, it is simpler than existing DQS cleanup circuits and does not require additional calibration and complex circuitry, thus reducing area and power consumption and improving data transmission efficiency. Attached Figure Description
[0028] Figure 1 A memory system according to an embodiment of the present disclosure is shown.
[0029] Figure 2 A memory interface device capable of self-DQS cleanup is shown according to an embodiment of the present disclosure.
[0030] Figure 3 This is a circuit diagram illustrating a memory interface device capable of self-DQS cleanup according to an embodiment of the present disclosure.
[0031] Figure 4 This is a timing diagram illustrating a memory interface device capable of self-DQS cleanup according to an embodiment of the present disclosure.
[0032] Figures 5 to 7 This is a circuit diagram used to explain the operation of a memory interface device capable of self-DQS cleanup according to embodiments of the present disclosure.
[0033] Figures 8 to 10 This is a diagram used to explain a comparative example of performing DQS cleanup using gating signals.
[0034] Figure 11 This illustration shows a memory interface device capable of self-DQS cleanup according to an embodiment of the present disclosure. Figures 8 to 10 The comparison example shows the results of the comparison.
[0035] Figure 12 This is a block diagram illustrating a computing device according to an embodiment of the present disclosure. Detailed Implementation
[0036] The present disclosure will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and description are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements.
[0037] Throughout the specification and claims, unless explicitly stated otherwise, the word “comprising” and its variations shall be understood to imply the inclusion of the stated element but not the exclusion of any other element.
[0038] Figure 1 A memory system according to an embodiment of the present disclosure is shown.
[0039] Reference Figure 1 The memory system 1 according to the example embodiment may include a memory controller 10 and a memory device 20.
[0040] The PHY interface 12 of the memory controller 10 can send the clock CK_t / CK_c and the command address CA / chip select signal CS to the memory device 20. Simultaneously, when writing data to the memory device 20, the PHY interface 12 can send the data to be stored as a data signal DQ along with the write clock signal WCK to the memory device 20. Furthermore, when reading data from the memory device 20, the PHY interface 12 can receive the data signal DQ and the input data strobe signals DQS_t / DQS_c.
[0041] When data is read from memory device 20, since the input data strobe signals DQS_t / DQS_c received from memory device 20 are used as the data capture clock in memory controller 10, these input data strobe signals DQS_t / DQS_c must be accurately recovered. Here, the input data strobe signals DQS_t / DQS_c can be differential data strobe signals, and therefore, the input data strobe signals DQS_t / DQS_c can be provided with opposite phases during the read operation of memory device 20.
[0042] In this embodiment, the memory controller 10 may be implemented as a processor, application processor, system-on-a-chip (SoC), etc., but the scope of this disclosure is not limited thereto. Similarly, the memory device 20 may be an LPDDR5 type DRAM installed in a smartphone, tablet computer, laptop computer, etc., but the scope of this disclosure is not limited thereto.
[0043] Figure 2 A memory interface device capable of self-DQS cleanup is shown according to an embodiment of the present disclosure.
[0044] Reference Figure 2 According to an embodiment of the present disclosure, a memory interface device 100 capable of self-DQS cleanup includes a data input buffer 102, a latch 104, a DQS signal input buffer 106, an offset control block 108, a duty cycle adjustment buffer 110, and a phase control block 112.
[0045] Data input buffer 102 may include multiple single-ended buffers to receive data signal DQ from memory device 20, and data input buffer 102 may buffer read data and output the read data as parallel 8-bit data. Reference voltage signal VREF may be used as a reference signal to determine whether the value of data signal DQ is 0 or 1. When data signal DQ exceeds the value of reference voltage signal VREF, the value of data signal DQ may be set to 1, and when data signal DQ does not exceed the value of reference voltage signal VREF, the value of data signal DQ may be set to 0. As described above, the data signal DQ received through data input buffer 102 may be input to latch 104.
[0046] Latch 104 can store the data signal DQ output from data input buffer 102 according to clock DQS_latch, and output the data signal DQ to memory controller 10. Latch 104 may include, for example, two or more flip-flops. One of the two or more flip-flops can be synchronized with the rising edge of clock DQS_latch to receive double data rate (DDR) data output from data input buffer 102 and output single data rate (SDR) data. Additionally, another of the two or more flip-flops can be synchronized with the falling edge of clock DQS_latch to receive DDR data output from data input buffer 102 and output SDR data.
[0047] The DQS input buffer 106 can receive input data strobe signals DQS_t and DQS_c and output a first intermediate data strobe signal A, and can provide a static offset. Here, the static offset can be a DC offset, and specifically, the DQS input buffer 106 can provide a negative DC offset.
[0048] The offset control circuit 108 can receive a first intermediate data strobe signal A output from the DQS input buffer 106 and output a second intermediate data strobe signal B.
[0049] The duty cycle adjustment buffer 110 can receive the second intermediate data strobe signal B output from the offset control circuit 108, and output the clean data strobe signals DQSO_t and DQSO_c.
[0050] The offset control circuit 108 can provide dynamic offset using the purge data strobe signals DQSO_t and DQSO_c output from the duty cycle adjustment buffer 110. That is, the offset control circuit 108 receives the purge data strobe signals DQSO_t and DQSO_c as feedback and pulls down specific nodes of the DQS input buffer 106 according to these signals to provide negative or positive dynamic offset. Therefore, to prevent unwanted pulses, such as when transitioning to a high-impedance state after DQS clock recovery, the offset control circuit 108 can add a negative dynamic offset to the static offset provided from the DQS input buffer 106.
[0051] Figure 3 This is a circuit diagram illustrating a memory interface device capable of self-DQS cleanup according to an embodiment of the present disclosure.
[0052] Reference Figure 3 The DQS input buffer 106 may include symmetrical transistors forming a differential structure. Additionally, static offset can be provided by setting different sizes of the symmetrical transistors forming the differential structure in the DQS input buffer 106.
[0053] In other words, the DQS input buffer 106 may include a first input transistor that receives a first input data strobe signal DQS_t, and a second input transistor that receives a second input data strobe signal DQS_c and forms a differential structure with the first input transistor, and static offset can be provided by setting different sizes of the first transistor and the second transistor.
[0054] The offset control circuit 108 may include two offset control transistors NM_t and NM_c, which are turned on according to the clean data strobe signals DQSO_t and DQSO_c to change the dynamic offset. That is, the offset control circuit 108 may include a first offset control transistor NM_t connected to the second input transistor via a first node N1_t and a second offset control transistor NM_c connected to the first input transistor via a second node N1_c. When the second input data strobe signal DQSO_c is high, the first offset control transistor NM_t is turned on, pulling down the first node N1_t; when the first input data strobe signal DQSO_t is high, the second offset control transistor NM_c is turned on, pulling down the second node N1_c.
[0055] Since the offset control circuit 108 is implemented using only two transistors, it has almost no impact on the area or power consumption of the memory interface device 100, and the offset adjustment circuit 108 is applicable to receivers implemented using only digital circuits, compared to offset adjustment techniques that are only applicable to analog circuits that manipulate existing current sources.
[0056] The duty cycle adjustment buffer 110 can be implemented by adding PMOS and NMOS to the inverter structure, receiving signals from the first node N1_t and the second node N1_c, and outputting clean data strobe signals DQSO_t and DQSO_c. The duty cycle adjustment buffer 110 can adjust the duty cycle error attributable to the static offset added from the DQS input buffer 106.
[0057] The clean data strobe signals DQSO_t and DQSO_c can be provided to the gates of the first offset control transistor NM_t and the second offset control transistor NM_c. When the second clean data strobe signal DQSO_c is high, the first offset control transistor NM_t is turned on. When the first clean data strobe signal DQSO_t is high, the second offset control transistor NM_c is turned on. When the first input data strobe signal DQS_t is low, the first offset control transistor NM_t is turned on, and the second input data strobe signal DQS_c changes from high to low.
[0058] Figure 4 This is a timing diagram illustrating a memory interface device capable of self-DQS cleanup according to an embodiment of the present disclosure, and Figures 5 to 7 This is a circuit diagram used to explain the operation of a memory interface device capable of self-DQS cleanup according to embodiments of the present disclosure.
[0059] Reference Figures 4 to 7 Time period T0 is the period during which the input data strobe signals DQS_t / DQS_c have the same voltage or high impedance. Initially, unwanted pulses may occur in these intervals due to external noise or glitches, but because the DQS input buffer 106 provides a negative DC offset, the DQS signal, defined as the difference between the cleaned data strobe signals DQS_t and DQS_c, can be configured to output 0. The same description as for interval T0 can be applied to time period T4.
[0060] During time period T1, the input data strobe signal DQS_c goes high, and the DQS signal remains at 0. Since the input data strobe signal DQS_c is high, it also maintains a negative offset.
[0061] During time period T2, when the input data strobe signal DQS_t goes high and the input data strobe signal DQS_c goes low, the DQS signal DQSO_t goes high, and the offset control transistor NM_c applied to the signal turns on to generate a positive offset. Conversely, when the input data strobe signal DQS_t goes low and the input data strobe signal DQS_c goes high, the offset control transistor NM_t turns on, and the positive offset is converted back to a negative offset.
[0062] In other words, such as Figure 5 As shown, when the first clean data strobe signal DQSO_t in the clean data strobe signals DQSO_t and DQSO_c is high, the second offset control transistor NM_c in the offset control transistors NM_t and NM_c can be turned on. Optionally, when the first input data strobe signal DQS_t in the input data strobe signals DQS_t and DQS_c is high, the second offset control transistor NM_c in the offset control transistors NM_t and NM_c can be turned on. In this case, the turned-on second offset control transistor NM_c can pull down the second node N1_c of the DQS input buffer 106 to provide a positive dynamic offset.
[0063] In addition, such as Figure 6 As shown, when the second clean data strobe signal DQSO_c in the clean data strobe signals DQSO_t and DQSO_c is high, the first offset control transistor NM_t in the offset control transistors NM_t and NM_c can be turned on. Optionally, when the second input data strobe signal DQS_c in the input data strobe signals DQS_t and DQS_c is high, the first offset control transistor NM_t in the offset control transistors NM_t and NM_c can be turned on. In this case, the turned-on first offset control transistor NM_t can pull down the first node N1_t of the DQS input buffer 106 to provide a negative dynamic offset.
[0064] The reason for changing the offset according to the output value in this way is to make the duty cycle of the output clock constant and change the threshold voltage (Vth) of "DQS_t-DQS_c" to VDD / 2±α instead of VDD / 2, so as to achieve a circuit that is robust to noise and glitches, such as a Schmitt trigger circuit.
[0065] During time period T3, the input data strobe signal DQS_t is at a low level, and only the input data strobe signal DQS_c changes from a high level to a low level. The differential signal "DQS_t - DQS_c" should change from a negative value to 0, but in the actual circuit, once DQS_c becomes 0, Figure 3The value of “node N1_t - node N1_c” immediately becomes positive due to the glitches, which may generate pulses as error components. However, in the circuit according to this embodiment, no error pulses occur due to the negative offset (static offset) in the DQS input buffer 106 circuit and the negative offset (dynamic offset) caused by the conduction of the offset control transistor Nm_t.
[0066] In other words, such as Figure 7 As shown, when the first input data strobe signal DQS_t in the input data strobe signals DQS_t and DQS_c is at a low level and the second input data strobe signal DQS_c changes from a high level to a low level, the first offset control transistor NM_t in the offset control transistors NM_t and NM_c can be turned on.
[0067] Figures 8 to 10 This is a diagram used to explain a comparative example of performing DQS cleanup using gating signals.
[0068] Reference Figure 8 The diagram illustrates a data input buffer with a single-ended structure, a latch for receiving data, a DQS input buffer with a differential structure for receiving DQS signals, a buffer for converting analog output to digital output, a gating signal generator for generating cleaned DQS, and a phase control block for adjusting the phase of the recovered DQS clock for data capture.
[0069] If in Figure 8 If there is no gate signal generator or calibration function for DQS purification, no gate signal is generated. Therefore, if DQS recovers as before, such as Figure 9 As shown, DQS_t and DQS_c are set to the same voltage or high impedance starting from the end of DQS_c, and unwanted glitches or pulses are generated due to small noise or signal fluctuations (see E1).
[0070] Figure 10 This is achieved by correcting the waveform generated when the gating signal is produced. The desired waveform, such as DQS_latch, can be obtained by first generating the gating signal based on the input DQS_t / DQS_c, and then using this gating signal to filter the DQS signal. However, after a certain period, due to changes in chip temperature or voltage, a delay may occur in the DQS_t / DQS_c waveform (see D), and if the gating signal remains at its initial setting, the recovered DQS_latch will cause a fault (see E2). To prevent this, if the gating signal is frequently corrected, data transmission is impossible during the correction time, thus increasing interrupt time and reducing data transmission efficiency.
[0071] In passing as Figure 8The conventional gating signal generator shown can respond to PVT (process-voltage-temperature) changes in real time, unlike the method of correcting gating signals, when generating gating signals. However, it suffers from increased area and power consumption due to additional circuitry. Furthermore, since the gating signal generator only uses the DQS_t input signal, the load conditions of the DQS_t and DQS_c signals differ, leading to undesirable offsets that may cause changes in the duty cycle.
[0072] Figure 11 This illustration shows a memory interface device capable of self-DQS cleanup according to an embodiment of the present disclosure. Figures 8 to 10 The comparison example shows the results of the comparison.
[0073] Reference Figure 11 In the case on the left, there is a "+ peak" compared to "0 offset" and an "error pulse" is generated, while in the case on the right, there is a "- peak" compared to "0 offset" and it can be confirmed that the "error pulse" does not appear, as shown in "B".
[0074] Figure 12 This is a block diagram illustrating a computing device according to an embodiment of the present disclosure.
[0075] Reference Figure 12 The computing device 50 includes at least one of a processor 510, a memory 530, a user interface input device 540, a user interface output device 550, and a storage device 560, which communicate with each other via a bus 520. The computing device 50 may also include a network interface 570 electrically connected to a network 40. Additionally, the computing device 50 may also include a memory interface 580 electrically connected to an external memory 60. The memory interface device according to the above embodiments of this disclosure can be applied to the memory interface 580.
[0076] The processor 510 can be implemented in various types, such as an application processor (AP), a central processing unit (CPU), a graphics processing unit (GPU), etc., and can be any device that executes instructions stored in memory 530 or storage device 560.
[0077] The memory 530 and storage device 560 may include various types of volatile or non-volatile storage media. For example, the memory may include read-only memory (ROM) 531 and random access memory (RAM) 532. In embodiments of this disclosure, the memory 530 may be located inside or outside the processor 510, and the memory 530 may be connected to the processor 510 by various known means.
[0078] According to embodiments of the present disclosure described so far, a self-DQS cleanup circuit is provided that can recover normal DQS pulses on its own when the DQS signal is high impedance or the DQS_t / DQS_c signal is applied to ground. This prevents unintentional pulses from occurring without a separate gating signal or DQS training. Therefore, it is simpler than existing DQS cleanup circuits and does not require additional calibration and complex circuitry, thus reducing area and power consumption and improving data transmission efficiency.
[0079] While this disclosure has been described in conjunction with exemplary embodiments now considered practical, it should be understood that this disclosure is not limited to the disclosed embodiments. Rather, this disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims
1. A memory interface device, comprising: The DQS input buffer is configured to receive an input data strobe signal and output a first intermediate data strobe signal, wherein the DQS input buffer provides a static offset; The offset control circuit is configured to receive a first intermediate data strobe signal and output a second intermediate data strobe signal; and The duty cycle adjustment buffer is configured to receive the second intermediate data strobe signal and output a clean data strobe signal. The offset control circuit uses a clean data strobe signal to provide dynamic offset. The offset control circuit includes two offset control transistors, which are turned on according to the purification data gating signal to change the dynamic offset. Specifically, the second offset control transistor of the two offset control transistors pulls down the second node of the DQS input buffer to provide a positive dynamic offset or a negative dynamic offset.
2. The memory interface device as claimed in claim 1, wherein, When the first purification data strobe signal in the purification data strobe signal is high, the second offset control transistor of the two offset control transistors is turned on.
3. The memory interface device as claimed in claim 1, wherein, When the second purification data strobe signal in the purification data strobe signal is high, the first offset control transistor of the two offset control transistors is turned on.
4. The memory interface device as claimed in claim 1, wherein, When the first input data strobe signal in the input data strobe signal is high, the second offset control transistor of the two offset control transistors is turned on.
5. The memory interface device as claimed in claim 1, wherein, When the second input data strobe signal in the input data strobe signal is high, the first offset control transistor of the two offset control transistors is turned on.
6. The memory interface device as claimed in claim 5, wherein, The first offset control transistor is turned on to pull down the first node of the DQS input buffer to provide a negative dynamic offset.
7. The memory interface device as claimed in claim 1, wherein, When the first input data strobe signal in the input data strobe signal is at a low level and the second input data strobe signal changes from a high level to a low level, the first offset control transistor of the two offset control transistors is turned on.
8. The memory interface device as claimed in claim 1, wherein, Static offset is DC offset.
9. The memory interface device as claimed in claim 1, wherein, Static offset is provided by setting different sizes of symmetrical transistors that form a differential structure in the DQS input buffer.
10. The memory interface device as claimed in claim 1, wherein, The input data strobe signal is a differential data strobe signal.
11. The memory interface device as claimed in claim 1, wherein, The duty cycle adjustment buffer adjusts the duty cycle error caused by static offset.
12. A memory interface device, comprising: The first input transistor is configured to receive a first input data strobe signal; The second input transistor is configured to receive a second input data strobe signal, wherein the second input transistor and the first input transistor form a differential structure; A first offset control transistor is connected to a second input transistor via a first node. When the second input data strobe signal is high, the first offset control transistor is turned on and pulls down the first node; and The second offset control transistor is connected to the first input transistor through the second node. When the first input data strobe signal is high, the second offset control transistor is turned on and pulls down the second node.
13. The memory interface device of claim 12, further comprising: The duty cycle adjustment buffer is configured to take in signals from the first node and the second node and output a clean data strobe signal.
14. The memory interface device as claimed in claim 13, wherein, The clean data strobe signal is provided to the gates of the first offset control transistor and the second offset control transistor.
15. The memory interface device as claimed in claim 14, wherein, When the second purification data strobe signal in the purification data strobe signal is high, the first offset control transistor is turned on.
16. The memory interface device as claimed in claim 14, wherein, When the first purification data strobe signal in the purification data strobe signal is high, the second offset control transistor is turned on.
17. The memory interface device of claim 12, wherein, When the first input data strobe signal is low and the second input data strobe signal changes from high to low, the first offset control transistor is turned on.
18. The memory interface device of claim 12, wherein, The first input transistor and the second input transistor are set to have different sizes.