A test element group and a test method thereof

Abstract

The present application discloses a test element group and a test method, wherein the circuit structure of a bit line sense amplifier designed in a memory is copied into the test element group, and the terminals for connecting the bit line and the reference bit line in each bit line sense amplifier are respectively used as test terminals, and the terminals for connecting the bit line are combined and connected to a voltage input line, and the terminals for connecting the reference bit line are combined and connected to another voltage input line, so that the current of each bit line sense amplifier under two input conditions is selectively measured by simultaneously inputting a power supply voltage or a ground voltage to the two voltage input lines. Since the bit line sense amplifier is the main circuit that affects the read and write speed of the memory, the measured current distribution can reflect the local difference data of the memory, and the read and write speed of the semiconductor memory device can be evaluated by these local difference data.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a test element group and a test method thereof. Background Art

[0002] For semiconductor memory devices, the core is set as a two-dimensional array composed of memory cells, and the memory cells in each row can be selected by the word line WL, and the memory cells in each column can be selected by the bit line BL and the reference bit line BLB. When a certain memory cell performs a read operation or a write operation, the corresponding bit line sense amplifier (BLSA, Bit Line SenseAmp) senses and amplifies the voltage difference between the bit line and the reference bit line to write information into the memory cell or read it from the memory cell. Therefore, the bit line sense amplifier is the main circuit that affects the read and write speed.

[0003] At present, the test of the read and write speed of memory devices is carried out when the chip is packaged after the product is produced (Fab out). In this way, only the overall read and write speed of the device can be tested, and the local difference data of the device cannot be obtained, such as the local difference data of the bit line sense amplifier in the device that affects the read and write speed. Summary of the invention

[0004] The purpose of the present application is to propose a test element group and a test method thereof in view of the deficiencies of the above-mentioned prior art, and the purpose is achieved through the following technical solutions.

[0005] A first aspect of the present application provides a test element group, the test element group comprising: a bit line sense amplifier array, each bit line sense amplifier in the bit line sense amplifier array comprising a first test terminal, a second test terminal and a selection terminal;

[0006] The first test terminal of each of the bit line sense amplifiers is electrically connected to the first voltage input line, and the second test terminal of each of the bit line sense amplifiers is electrically connected to the second voltage input line;

[0007] The bit line sense amplifier array is consistent with the bit line sense amplifier circuit structure in the semiconductor memory device, and the first test terminal and the second test terminal of each bit line sense amplifier are respectively used to connect to the bit line and the reference bit line in the semiconductor memory device, and the selection terminal is used to connect to the bit line selection terminal.

[0008] The second aspect of the present application provides a method for testing the test element group described in the first aspect, the method comprising:

[0009] Applying a preset power supply voltage signal to the first voltage input line and the second voltage input line respectively, applying the preset power supply voltage signal to a selection terminal of each bit line sense amplifier, and measuring a first current output from a first test terminal and a second current output from a second test terminal of the bit line sense amplifier;

[0010] A preset ground voltage signal is applied to the first voltage input line and the second voltage input line respectively, and for each bit line sensing amplifier, the preset power supply voltage signal is applied to the selection end of the bit line sensing amplifier, and a third current output from the first test end and a fourth current output from the second test end of the bit line sensing amplifier are measured.

[0011] Based on the test element group and the test method thereof described in the first and second aspects above, the present application has the following beneficial effects:

[0012] In the TEG (test element group) stage, the present application copies the circuit structure of the bit line sense amplifier designed in the semiconductor memory device into the test element group module, and uses the terminals for connecting the bit line and the reference bit line in each bit line sense amplifier as test terminals, while merging the terminals for connecting the bit line and connecting to a voltage input line, and merging the terminals for connecting the reference bit line and connecting to another voltage input line, thereby selectively measuring the current of each bit line sense amplifier under two input conditions by simultaneously inputting the power supply voltage or the ground voltage to the two voltage input lines. Since the bit line sense amplifier is the main circuit that affects the read and write speed of the semiconductor memory device, the current distribution measured by the present solution can reflect the local difference data of the semiconductor memory device, and the read and write speed of the semiconductor memory device can be evaluated by these local difference data. Since the present application solution can detect the read and write speed problem of the device very early in the TEG stage, it can save testing costs and time and improve product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0014] Figure 1 This is a schematic structural diagram of a test element group according to an exemplary embodiment of the present application;

[0015] Figure 2 This is a flow chart of an embodiment of a method for testing a test element group according to an exemplary embodiment of the present application;

[0016] Figure 3This application is based on Figure 1 A schematic diagram of the testing principle of a test element group shown in the illustrated embodiment;

[0017] Figure 4 This application is based on Figure 1 The illustrated embodiment shows a schematic diagram of the testing principle of another test element group. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0019] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0020] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0021] At present, the test of the read and write speed of the memory device is performed when the chip is packaged after the product is produced (Fab out). However, this can only test the overall read and write speed of the device, and cannot obtain the local difference data of the device, such as the local difference data of the bit line sense amplifier in the device that affects the read and write speed. Moreover, if you want to obtain the local difference data of the bit line sense amplifier when packaging the chip, you need to design a very complex test module to obtain it, which will also increase the test overhead.

[0022] To solve the above technical problems, the present application proposes a test element group to obtain local difference data of a memory device in the TEG stage at the early stage of the test, such as Figure 1 As shown, the test element group includes a bit line sense amplifier array, and each bit line sense amplifier BLSA in the bit line sense amplifier array includes a first test terminal BL, a second test terminal BLB and a selection terminal C ( Figure 1In the figure, the specific circuit structure of one of the BLSAs is given. In order to facilitate the measurement of a unified input signal, the first test terminal BL of each bit line sense amplifier is electrically connected to the first voltage input line, and the second test terminal BLB of each bit line sense amplifier is electrically connected to the second voltage input line.

[0023] It should be noted that the bit line sense amplifier array is consistent with the circuit structure of the bit line sense amplifier in the semiconductor memory device, and the first test terminal and the second test terminal of each bit line sense amplifier are respectively used to connect to the bit line and the reference bit line in the semiconductor memory device, and the selection terminal of each bit line sense amplifier is used to connect to the bit line selection terminal in the semiconductor memory device.

[0024] Based on the above description, it can be known that in the TEG stage, by copying the circuit structure of the bit line sense amplifier designed in the semiconductor memory device into the test element group module, and using the terminals for connecting the bit line and the reference bit line in each bit line sense amplifier as test terminals, the terminals for connecting the bit line are combined and connected to a voltage input line, and the terminals for connecting the reference bit line are combined and connected to another voltage input line, so that the power supply voltage or the ground voltage is simultaneously input to the two voltage input lines to selectively measure the current of each bit line sense amplifier under two input conditions, so that the local difference data of the memory device can be obtained in the TEG stage, so as to detect the read and write speed problems of the device in the early development stage, save the later testing costs and time, and improve the product yield.

[0025] In some embodiments, Figure 1 As shown, each bit line sense amplifier further includes a first node A, a second node B, a first inverter 10 and a second inverter 20 .

[0026] Furthermore, the first inverter 10 includes a first transistor T1 and a second transistor T2 , wherein the drains of the first transistor T1 and the second transistor T2 are connected to the first node A, and the gates of the first transistor T1 and the second transistor T2 are connected to the second node B.

[0027] The second inverter 20 includes a third transistor T3 and a fourth transistor T4, the drains of the third transistor T3 and the fourth transistor T4 are connected and are both connected to the second node B, and the gates of the third transistor T3 and the fourth transistor T4 are connected and are both connected to the first node A; the sources of the first transistor T1 and the third transistor T3 are both connected to the first node A, and the sources of the second transistor T2 and the fourth transistor T4 are both connected to the second node B.

[0028] It should be noted that, in this embodiment, the first node A is used to connect the power supply voltage VDD terminal of the test component group, and the second node B is used to connect the ground VSS terminal of the test component group.

[0029] That is to say, the present application further processes the first node A and the second node B of each bit line sensing amplifier in the semiconductor storage, that is, the first node A is always provided with the power supply voltage VDD, and the second node B is always provided with the ground voltage VSS.

[0030] Preferably, the first transistor T1 and the third transistor T3 mentioned above are both P-type transistors, and the second transistor T2 and the fourth transistor T4 are both N-type transistors.

[0031] In some embodiments, see Figure 1 As shown, each bit line sense amplifier further includes a fifth transistor T5 and a sixth transistor T6.

[0032] Among them, the gates of the fifth transistor T5 and the sixth transistor T6 are connected and are both connected to the selection terminal C; the first end of the channel of the fifth transistor T5 is connected to the first test terminal BL, and the second end of the channel of the fifth transistor T5 is connected to the first node A, that is, the drains of the first transistor T1 and the second transistor T2 connected to each other, the gates of the third transistor T3 and the fourth transistor T4 connected to each other, and the second end of the channel of the fifth transistor T5, all three are formed at the first node A.

[0033] The first end of the channel of the sixth transistor T6 is connected to the second test end BLB, and the second end of the channel of the sixth transistor T6 is connected to the second node B, that is, the gates of the first transistor T1 and the second transistor T2 connected to each other, the drains of the third transistor T3 and the fourth transistor T4 connected to each other, and the second end of the channel of the sixth transistor T6 are all formed at the second node B.

[0034] It should be noted that, in this embodiment, the first channel end and the second channel end of the fifth transistor T5 and the sixth transistor T6 are the source or drain of the transistor, that is, if the first channel end is the source, then the second channel end is the drain.

[0035] In a preferred embodiment, the fifth transistor T5 and the sixth transistor T6 may both be N-type transistors.

[0036] In some embodiments, see Figure 1 As shown, each bit line sense amplifier further includes a seventh transistor T7 and an eighth transistor T8.

[0037] The first channel end of the seventh transistor T7 is connected to the first node A, the second channel end and the gate of the seventh transistor T7 are connected to the second node B, and the first channel end, the second channel end and the gate of the eighth transistor T8 are connected to the second node B.

[0038] Corresponding to the aforementioned test element group embodiment, the present application also provides an embodiment of a test method for a test element group.

[0039] Figure 2 This is a flowchart of an embodiment of a test method for a test element group according to an exemplary embodiment of the present application. This embodiment is based on the above Figure 1 The test element group structure shown in the figure is tested, and the test method of the test element group includes the following steps:

[0040] Step 201: Apply a preset power supply voltage signal to the first voltage input line and the second voltage input line respectively, apply a preset power supply voltage signal to the selection end of each bit line sense amplifier, and measure a first current output from the first test end and a second current output from the second test end of the bit line sense amplifier.

[0041] In this embodiment, see Figure 1 As shown, when a preset power supply voltage signal (VDD) is applied to the first voltage input line and the second voltage input line respectively, it is equivalent to applying the preset power supply voltage signal to the first end of the channel of the fifth transistor T5 and the sixth transistor T6 respectively. When measuring, it is necessary to select the bit line sense amplifiers in sequence for measurement, that is, by applying VDD to the selection end C of one of the bit line sense amplifiers to select the bit line sense amplifier.

[0042] See also Figure 3 As shown, it is a schematic diagram of the measurement principle of the selected bit line sense amplifier. In this case, the fourth transistor T4 and the sixth transistor T6 in the bit line sense amplifier are both turned on, and a saturation current flows ( Figure 3 The remaining first transistor T1, second transistor T2, third transistor T3, and fifth transistor T5 are all in the off state, with a small leakage current flowing through ( Figure 3 By measuring the first current at the first test terminal, the saturation current of the fourth transistor T4 can be obtained, and by measuring the second current at the second test terminal, the leakage current of the second transistor T2 can be obtained.

[0043] Step 202: Apply a preset ground voltage signal to the first voltage input line and the second voltage input line respectively, apply a preset power supply voltage signal to the selection end of each bit line sensing amplifier, and measure a third current output from the first test end and a fourth current output from the second test end of the bit line sensing amplifier.

[0044] In this embodiment, see Figure 1 As shown, when a preset ground voltage signal (VSS) is applied to the first voltage input line and the second voltage input line respectively, it is equivalent to applying a preset ground voltage signal to the first end of the channel of the fifth transistor T5 and the sixth transistor T6 respectively. When measuring, it is also necessary to select the bit line sense amplifiers in sequence for measurement, that is, by applying VDD to the selection end C of one of the bit line sense amplifiers to select the bit line sense amplifier.

[0045] See also Figure 4 As shown, it is a schematic diagram of the measurement principle of the selected bit line sense amplifier. In this case, the first transistor T1 and the fifth transistor T5 in the bit line sense amplifier are both turned on, and a saturation current flows ( Figure 4 The remaining second transistor T2, third transistor T3, fourth transistor T4, and sixth transistor T6 are all in the off state, with a small leakage current flowing through ( Figure 4 By measuring the third current at the first test end, the saturation current of the first transistor T1 can be obtained, and by measuring the fourth current at the second test end, the leakage current of the third transistor T3 can be obtained.

[0046] It is understandable that the present invention does not specifically limit the execution order of the above steps 201 and 202.

[0047] It should be noted that after the measurement is completed, four current values ​​can be obtained for each bit line sense amplifier in the bit line sense amplifier array: a first current, a second current, a third current and a fourth current.

[0048] Furthermore, the first current, the second current, the third current and the fourth current of each bit line sensing amplifier can be statistically analyzed to obtain the error value of the first current, the error value of the second current, the error value of the third current and the error value of the fourth current, so that the error value of the first current, the error value of the second current, the error value of the third current and the error value of the fourth current can be used as local difference data of the semiconductor memory device to evaluate the read and write speed of the semiconductor memory device.

[0049] The error value of the first current, the error value of the second current, the error value of the third current and the error value of the fourth current may all be sigma values.

[0050] At this point, the above Figure 2The test process shown, by simultaneously inputting the power supply voltage or the ground voltage to the two voltage input lines, selectively measures the current of each bit line sense amplifier under two input conditions. Since the bit line sense amplifier is the main circuit that affects the read and write speed of the semiconductor memory device, the current distribution measured by this solution can reflect the local difference data of the semiconductor memory device, and the read and write speed of the semiconductor memory device can be evaluated by these local difference data. Since the application solution can detect the read and write speed problem of the device very early in the TEG stage, it can save testing costs and time and improve product yield.

[0051] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0052] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A test element group, characterized in that: The test element group includes: a bit line sense amplifier array, each bit line sense amplifier in the bit line sense amplifier array includes a first test terminal, a second test terminal and a selection terminal; The first test terminal of each of the bit line sense amplifiers is electrically connected to the first voltage input line, and the second test terminal of each of the bit line sense amplifiers is electrically connected to the second voltage input line; The bit line sense amplifier array has the same structure as the bit line sense amplifier circuit in the semiconductor memory device, and the first test terminal and the second test terminal of each bit line sense amplifier are respectively used to connect to the bit line and the reference bit line in the semiconductor memory device, and the selection terminal is used to connect to the bit line selection terminal; Each of the bit line sense amplifiers further comprises a first node, a second node, a first inverter and a second inverter; the first inverter comprises a first transistor and a second transistor, the drain of the first transistor and the second transistor are connected and both are connected to the first node, and the gate of the first transistor and the second transistor are connected and both are connected to the second node; the second inverter comprises a third transistor and a fourth transistor, the drain of the third transistor and the fourth transistor are connected and both are connected to the second node, and the gate of the third transistor and the fourth transistor are connected and both are connected to the first node; the sources of the first transistor and the third transistor are connected to the first node, and the sources of the second transistor and the fourth transistor are connected to the second node; wherein the first node is used to connect to the power supply voltage VDD terminal, and the second node is used to connect to the ground VSS terminal; The bit line sensing amplifier also includes a fifth transistor and a sixth transistor; the gates of the fifth transistor and the sixth transistor are connected and are both connected to the selection end; the first end of the channel of the fifth transistor is connected to the first test end, and the second end of the channel of the fifth transistor is connected to the first node; the first end of the channel of the sixth transistor is connected to the second test end, and the second end of the channel of the sixth transistor is connected to the second node.

2. The test element set according to claim 1, characterized in that: The first transistor and the third transistor are both P-type transistors; The second transistor and the fourth transistor are both N-type transistors.

3. The test element set according to claim 1, characterized in that: The fifth transistor and the sixth transistor are both N-type transistors.

4. A method for testing a test element group according to any one of claims 1 to 3, characterized in that: The method comprises: Applying a preset power supply voltage signal to the first voltage input line and the second voltage input line respectively, applying the preset power supply voltage signal to a selection terminal of each bit line sense amplifier, and measuring a first current output from a first test terminal and a second current output from a second test terminal of the bit line sense amplifier; A preset ground voltage signal is applied to the first voltage input line and the second voltage input line respectively, and for each bit line sensing amplifier, the preset power supply voltage signal is applied to the selection end of the bit line sensing amplifier, and a third current output from the first test end and a fourth current output from the second test end of the bit line sensing amplifier are measured.

5. The method according to claim 4, characterized in that When a preset power supply voltage signal is applied to the first voltage input line and the second voltage input line respectively, and the preset power supply voltage signal is applied to the selection terminal of one of the bit line sensing amplifiers, the fourth transistor and the sixth transistor in the bit line sensing amplifier are turned on, the measured first current is the saturation current of the fourth transistor, and the measured second current is the leakage current of the second transistor.

6. The method according to claim 4, characterized in that When a preset ground voltage signal is applied to the first voltage input line and the second voltage input line respectively, and the preset power supply voltage signal is applied to the selection terminal of one of the bit line sensing amplifiers, the first transistor and the fifth transistor in the bit line sensing amplifier are turned on, the measured third current is the saturation current of the first transistor, and the measured fourth current is the leakage current of the third transistor.

7. The method according to claim 4, characterized in that The method further comprises: According to the first current, the second current, the third current and the fourth current of each bit line sensing amplifier, respectively, an error value of the first current, an error value of the second current, an error value of the third current and an error value of the fourth current are counted; The error value of the first current, the error value of the second current, the error value of the third current and the error value of the fourth current are used as local difference data of the semiconductor memory device to evaluate the read and write speed of the semiconductor memory device.

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