A method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method, which comprises the following steps: providing a substrate; forming a convex structure pattern on the surface of the substrate, wherein the convex structure pattern comprises a plurality of interval distributed convex structures; depositing an insulating film on the convex structure pattern and the surface of the substrate, and the lowest part of the insulating film is higher than the highest part of the convex structure pattern; depositing a barrier layer on the surface of the insulating film; depositing a metal layer on the surface of the barrier layer, and the upper surface of the metal layer is a plane; sequentially grinding the metal layer, the barrier layer and the insulating film from top to bottom by using a chemical mechanical grinding process until the upper surface of the convex structure pattern is exposed. The metal material is filled in the recessed part on the upper surface of the insulating film, and the relatively hard characteristics of the metal material in the recessed part can prevent the insulating film between the convex structure patterns from being excessively ground when the chemical mechanical grinding process is used to grind until the upper surface of the convex structure pattern is exposed, so that the recessed phenomenon of the CMP process is avoided, and the electrical performance of the semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] In memory devices such as DRAM (Dynamic Random Access Memory), gate patterning is a necessary step in forming transistor patterns; that is, gate patterning is an indispensable process in the development and mass production of semiconductor devices. Gate patterns are typically formed on a substrate. After forming the gate pattern, an insulating film needs to be formed between adjacent gates to isolate them and prevent interference. In existing technology, when forming the insulating film between two gates, the insulating film is first deposited on the gate pattern and the substrate surface, filling the space between the two gates. Then, a CMP (chemical mechanical polishing) process is directly used to polish the insulating film above the gate pattern, exposing the upper surface of the gate pattern. However, after forming the gate pattern, a step difference (height difference) is created between the gate pattern and the substrate surface; this step difference is difficult to eliminate even after depositing the insulating film. The subsequent CMP process removes the step difference and exposes the upper surface of the gate pattern. During the CMP process, areas with lower gate pattern density will experience downward depressions, resulting in a depression phenomenon in the CMP process that affects the electrical performance of the gate pattern. Summary of the Invention

[0003] This invention provides a method for manufacturing a semiconductor device to prevent the occurrence of depressions in the CMP process and improve the electrical performance of the semiconductor device.

[0004] This invention provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate; forming a raised structure pattern on the surface of the substrate, wherein the raised structure pattern includes a plurality of spaced-apart raised structures; depositing an insulating film on the raised structure pattern and the substrate surface, wherein the lowest point of the insulating film is higher than the highest point of the raised structure pattern; depositing a barrier layer on the surface of the insulating film; depositing a metal layer on the surface of the barrier layer, wherein the upper surface of the metal layer is planar; and sequentially grinding the metal layer, the barrier layer and the insulating film from top to bottom using a chemical mechanical polishing process until the upper surface of the raised structure pattern is exposed.

[0005] In the above-described scheme, after depositing an insulating film on the raised structure pattern and the substrate surface, a barrier layer and a metal layer are deposited on the insulating film, and the upper surface of the metal layer forms a plane, allowing the metal material to fill the depressions on the upper surface of the insulating film. Then, a chemical mechanical polishing (CMP) process is used to polish the metal layer, barrier layer, and insulating film sequentially from top to bottom. Compared with the prior art method of directly polishing after insulating film deposition, the scheme of this application has a plane surface at the start of the CMP process, and the depressions on the upper surface of the insulating film are filled with metal material. Utilizing the relatively hard properties of the metal material in the depressions, the metal material removal rate is slower than that of the insulating film, preventing depressions from forming after CMP and achieving the purpose of controlling depressions. This ensures that when the upper surface of the raised structure pattern is exposed during CMP, the insulating film located between the raised structure patterns is not over-polished, thus avoiding the depression phenomenon of the CMP process and improving the electrical performance of the semiconductor device. Furthermore, a barrier layer is placed between the metal layer and the insulating film to prevent particles in the metal layer from penetrating into the insulating film and affecting its insulating performance.

[0006] In one specific embodiment, the chemical mechanical polishing (CMP) process, which sequentially polishes the metal layer, barrier layer, and insulating film from top to bottom, includes the following: the difference in the removal rates of the polishing slurry used in the CMP process for the metal layer, barrier layer, and insulating film is within 10%. The method of adjusting the polishing slurry is used to ensure that the removal rates of the metal layer, barrier layer, and insulating film during CMP are relatively consistent.

[0007] In one specific embodiment, the polishing fluid particles are in the form of colloidal silica or fumed silica.

[0008] In one specific embodiment, the raised structure pattern is a gate pattern, which includes multiple spaced gates to prevent CMP process depressions between the gate patterns and improve the electrical performance of the gate pattern.

[0009] In one specific embodiment, each gate includes a conductor formed on the substrate surface and spacer structures formed on the sidewalls and top surface of the conductor. Specifically, the lowest point of the insulating film is higher than the highest point of the raised structure pattern. A chemical mechanical polishing process is used to sequentially polish the metal layer, barrier layer, and insulating film from top to bottom until the upper surface of the raised structure pattern is exposed. The spacer structures distributed on both sides and the top surface of the conductor improve the protection of the conductor.

[0010] In one specific embodiment, the raised structure pattern is a fin pattern comprising multiple spaced fins to prevent CMP process depressions between the fin patterns and improve the electrical performance of the fin pattern.

[0011] In one specific embodiment, the wire is made of a combination of a metallic material and polycrystalline silicon, and the spacer structure is made of silicon nitride.

[0012] In one specific implementation, the metal layer is made of tungsten, which utilizes the high hardness of tungsten to further improve the depression phenomenon in the CMP process.

[0013] In one specific embodiment, the barrier layer is made of titanium, titanium nitride, or a mixture of titanium and titanium nitride to improve the barrier layer's effectiveness in preventing particles from the metal layer from penetrating into the insulating film.

[0014] In one specific embodiment, the insulating film is made of silica-based materials, low-k materials, SOD (spin-coated hard mask material), TOSZ (Tonen Silazane, abbreviated as TOSZ), or SOH (Silicon-Organic Hybrid, abbreviated as SOH).

[0015] In one specific embodiment, the step difference between the lowest and highest points of the insulating film is no greater than [value missing]. By forming an insulating film with a small step difference, the depression phenomenon in the CMP process can be improved by subsequently depositing a barrier layer and a metal layer, thereby enhancing the electrical performance of the semiconductor device.

[0016] In one specific embodiment, the thickness of the portion of the insulating film located on the upper surface of the raised structural pattern is [missing information]. By depositing an insulating film of a certain thickness on the surface of the raised structure pattern, the depression phenomenon in the CMP process can be improved by subsequently depositing a barrier layer and a metal layer, thereby enhancing the electrical performance of the semiconductor device.

[0017] In one specific implementation, the thickness of the barrier layer is The blocking effect can be improved by setting a blocking layer of a certain thickness.

[0018] In one specific implementation, the thickness of the metal layer is By setting a metal layer with a wide range of thicknesses, the unevenness of the upper surface of the insulating film can be compensated for, thereby improving the depression phenomenon in the CMP process and enhancing the electrical performance of semiconductor devices. Attached Figure Description

[0019] Figure 1This is a cross-sectional structural schematic diagram of one step of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0020] Figure 2 A cross-sectional structural schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0021] Figure 3 A cross-sectional view of a semiconductor device manufactured by a semiconductor device manufacturing method according to an embodiment of the present invention;

[0022] Figure 4 This is a cross-sectional structural schematic diagram of one step in a semiconductor device manufacturing method shown in the prior art;

[0023] Figure 5 A cross-sectional view of a semiconductor device manufactured by a method for manufacturing semiconductor devices as shown in the prior art.

[0024] Figure label:

[0025] Figures 1-3 Figure labels

[0026] 10-Base; 20-Protruding structure; 21-Wire; 22-Spacer structure

[0027] 30 - Insulating film; 40 - Barrier layer; 50 - Metal layer

[0028] Figures 4-5 Figure labels

[0029] 1-Substrate 2-Gate 3-Insulating film Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] To facilitate understanding of the semiconductor device manufacturing method provided in the embodiments of the present invention, the application scenario of the manufacturing method provided in the embodiments of the present invention will be described first. This manufacturing method is applied to manufacturing a semiconductor device having a raised structural pattern and filling the spaces between the raised structural patterns for insulating and isolating the raised structural patterns. The manufacturing method of the semiconductor device will now be described in detail with reference to the accompanying drawings.

[0032] Referring to Reference 1, the method for manufacturing a semiconductor device provided in this embodiment of the invention includes: providing a substrate 10. When setting the substrate 10, the substrate 10 can be a structure comprising a single semiconductor material, such as a single-crystal silicon substrate, a polycrystalline silicon substrate, etc. The substrate 10 can also be a stacked structure in which a partial semiconductor structure has already been formed.

[0033] Next, continue to refer to Figure 1 A pattern of raised structures 20 is formed on the surface of the substrate 10, wherein the pattern of raised structures 20 includes a plurality of spaced-apart raised structures 20. During configuration, this pattern of raised structures 20 can be a gate pattern; correspondingly, each raised structure 20 is a gate, and the gate pattern includes a plurality of spaced-apart gates. When configuring each gate, reference is made to... Figure 1 Each gate includes a wire 21 formed on the surface of the substrate 10, and a spacer structure 22 formed on the sidewalls and top surface of the wire 21. Figure 1 In the diagram, the structure containing the letter "a" represents the conductor 21, and the structure containing the letter "b" represents the spacer structure 22. The conductor 21 is conductive, and the spacer structures 22, disposed on the sidewalls and top surface of the conductor 21, serve as protective structures for the conductor 21. The conductor 21 can be made of a combination of a metallic material and polysilicon, and the spacer structure 22 can be made of silicon nitride. It should be understood that the arrangement of the raised structure 20 pattern is not limited to the arrangement shown above; other structures are also possible. For example, the raised structure 20 pattern can also be a bit line pattern, and correspondingly, the bit line pattern contains multiple bit lines.

[0034] Next, continue to refer to Figure 1 An insulating film 30 is deposited on the pattern of the raised structure 20 and the surface of the substrate 10, with the lowest point of the insulating film 30 being higher than the highest point of the pattern of the raised structure 20. For example... Figure 1 The structure containing the letter "c" is the insulating film 30. This insulating film 30 serves as the medium separating two adjacent raised structures 20. It needs to fill the space between the two adjacent raised structures 20, and also ensure that the lowest point of the insulating film 30 is higher than the highest point of the raised structure 20 pattern. This is to prevent any depressions in the insulating film 30 between the two adjacent raised structures 20 when separating it using chemical mechanical polishing. The material of the insulating film 30 can be silicon dioxide, low-k material, SOD, TOSZ, or SOH. When the raised structure 20 pattern is a gate pattern, the lowest point of the insulating film 30 being higher than the highest point of the raised structure 20 pattern specifically means that the lowest point of the insulating film 30 is higher than the highest point of the spacer structure 22.

[0035] Specifically, when depositing the insulating film 30 on the pattern of the raised structure 20 and the surface of the substrate 10, the insulating film 30 can be formed by methods such as growth. This ensures that the step difference between the lowest and highest points of the insulating film 30 is no greater than [value missing]. Specifically, the step difference between the lowest and highest points in the insulating film 30 can be made as follows: Not greater than Any value of . Due to the poor fluidity of the insulating film 30 material, the height between the two protruding structures 20 is relatively low, while the upper surface of the protruding structure 20 is relatively high. Therefore, the position of the insulating film 30 between the two protruding structures 20 is the lowest point of the insulating film 30, and the portion of the insulating film 30 on the upper surface of the protruding structure 20 has the highest height. It is necessary to ensure that the height difference between the insulating film 30 located on the upper surface of the protruding structure 20 and the insulating film 30 located between the protruding structures 20 is no greater than . By forming an insulating film 30 with a small step difference, the subsequent deposition of a barrier layer 40 and a metal layer 50 can improve the depression phenomenon of the CMP process and enhance the electrical performance of the semiconductor device.

[0036] When specifically depositing the insulating film 30, the thickness of the portion of the insulating film 30 located on the upper surface of the pattern of the raised structure 20 can be made as follows: Specifically, the thickness of the portion of the insulating film 30 located on the upper surface of the pattern of the raised structure 20 can be made as follows: Equal to Any value between these values. Due to the poor fluidity of the insulating film 30 material, a thicker insulating film 30 needs to be deposited to reduce the step difference between the lowest and highest points of the insulating film 30. By depositing an insulating film 30 of a certain thickness on the surface of the raised structure 20 pattern, the step difference between the lowest and highest points of the insulating film 30 can be reduced. This also facilitates the subsequent deposition of the barrier layer 40 and the metal layer 50 to improve the depression phenomenon of the CMP process and enhance the electrical performance of the semiconductor device.

[0037] Next, refer to Figure 2 A barrier layer 40 is deposited on the surface of the insulating film 30 to prevent particles from the subsequently deposited metal layer 50 from penetrating into the insulating film 30. Figure 2 The structure containing the letter "d" represents the barrier layer 40. When specifically determining the material of the barrier layer 40, the material can be titanium, titanium nitride, or a mixture of titanium and titanium nitride to improve the effectiveness of the barrier layer 40 in preventing particles from the metal layer 50 from penetrating into the insulating film 30. The mixing ratio of the titanium and titanium nitride mixture is a ratio conventionally used in the prior art for barrier structures. When determining the thickness of the barrier layer 40, the thickness can be... Equal to Any value between these ranges. The blocking effect is improved by setting a blocking layer 40 of a certain thickness.

[0038] Next, continue to refer to Figure 2 A metal layer 50 is deposited on the surface of the barrier layer 40, and the upper surface of the metal layer 50 is planar. For example... Figure 2 The letter "e" indicates metal layer 50. Metal layer 50 is deposited on the surface of barrier layer 40, and its upper surface is made planar. This ensures that the surface contacted by the grinding head during subsequent chemical mechanical polishing (CMP) is planar. The depressions on the upper surface of insulating film 30 are filled with metal material. Utilizing the relatively hard nature of the metal material in these depressions, the removal rate of the metal material is slower than that of the insulating film 30, preventing depressions from forming after CMP and thus controlling the formation of depressions, which helps prevent depressions during the CMP process. The material of metal layer 50 can be tungsten, which, due to its high hardness, further improves the depression phenomenon during CMP. It should be noted that the material of metal layer 50 is not limited to tungsten as shown above; other metal materials can also be used. For example, aluminum, copper, or metal mixtures can also be used as raw materials for metal layer 50.

[0039] When determining the thickness of the metal layer 50, the thickness of the metal layer 50 can be... Specifically, the thickness of the metal layer 50 can be Equal to Any value between these values. By setting a metal layer 50 with a wide thickness range, the thickness of the metal layer 50 at different positions can be adjusted to compensate for the unevenness of the upper surface of the insulating film 30, thereby improving the depression phenomenon in the CMP process and enhancing the electrical performance of the semiconductor device.

[0040] Next, refer to Figure 3The metal layer 50, barrier layer 40, and insulating film 30 are sequentially ground from top to bottom using a chemical mechanical polishing process until the upper surface of the raised structure 20 pattern is exposed. This facilitates the subsequent placement of contact holes, contact plugs, and other structures above the raised structure 20 pattern. After depositing the insulating film 30 on the raised structure 20 pattern and the substrate 10, a barrier layer 40 and a metal layer 50 are deposited on the insulating film 30. This allows the metal material to fill the depressions on the upper surface of the insulating film 30. Utilizing the relatively hard nature of the metal material in the depressions, the metal material removal rate is slower than that of the insulating film 30, preventing depressions from forming after chemical mechanical polishing and achieving the goal of controlling depressions. At this time, when the metal layer 50, the barrier layer 40 and the insulating film 30 are ground sequentially from top to bottom using the chemical mechanical polishing process, the surface at the beginning of the chemical mechanical polishing process is a plane. By adjusting the chemical mechanical polishing process, the grinding removal rate of the metal layer 50, the barrier layer 40 and the insulating film 30 is made more consistent, so that when the upper surface of the raised structure 20 pattern is exposed, the insulating film 30 located between the raised structure 20 patterns is not over-ground.

[0041] Existing manufacturing methods such as Figure 4 and Figure 5 As shown: First refer to Figure 4 First, a gate 2 pattern is formed on the substrate 1. The gate 2 pattern contains multiple gates 2. Figure 4 The structure formed by the letters "a" and "b" represents gate 2. An insulating film 3 is then deposited on the patterned surface of gate 2 and the surface of substrate 1. Figure 4 The letter "c" in the text indicates insulating film 3. (Refer to the following...) Figure 5 The insulating film 3 is directly ground using chemical mechanical polishing (CMP) to separate the insulating films 3 located between different gates. Because the surface of the gate 2 pattern is uneven, the upper surface of the insulating film 3 also has a large step difference, resulting in an uneven upper surface as well. In areas with lower density of the gate 2 pattern, over-polishing can occur during CMP, leading to a depression in the insulating film 3 between the two gates 2. This phenomenon is called CMP depression.

[0042] Compared to the existing method of directly grinding after depositing the insulating film 3, the solution in this application has a planar surface at the start of the chemical mechanical polishing (CMP) process. The depressions on the upper surface of the insulating film 30 are filled with metal material. Utilizing the relatively hard nature of the metal material in the depressions, the removal rate of the metal material is slower than that of the insulating film 30, thus preventing depressions from forming after CMP and achieving the goal of controlling depressions. This ensures that when the upper surface of the raised structure 20 pattern is exposed during CMP, the insulating film 30 located between the raised structure 20 patterns is not over-polished, thereby avoiding the depression phenomenon of the CMP process and improving the electrical performance of the semiconductor device. Furthermore, a barrier layer 40 is provided between the metal layer 50 and the insulating film 30 to prevent particles in the metal layer 50 from penetrating into the insulating film 30 and affecting its insulation performance.

[0043] When the aforementioned raised structure 20 pattern is a gate pattern, a chemical mechanical polishing (CMP) process is used to grind the metal layer 50, barrier layer 40, and insulating film 30 sequentially from top to bottom until the upper surface of the raised structure 20 pattern is exposed. Specifically, this involves using a CMP process to grind the metal layer 50, barrier layer 40, and insulating film 30 sequentially from top to bottom until the upper surface of the spacer structure 22 in the gate pattern is exposed. The spacer structure 22 is distributed on both sides and the top surface of the conductor 21 to improve the protection of the conductor 21. This prevents the occurrence of CMP process depressions between the gate patterns and improves the electrical performance of the gate pattern.

[0044] When using a chemical mechanical polishing (CMP) process to grind the metal layer 50, barrier layer 40, and insulating film 30 sequentially from top to bottom, the removal rates of these layers can be made more consistent by adjusting the CMP process. Specifically, the type, size, or morphology of particles in the polishing slurry, or the type and concentration of the dispersion, can be adjusted. For example, the difference in removal rates of the polishing slurry for the metal layer 50, barrier layer 40, and insulating film 30 can be kept within 10%. For instance, the particles in the polishing slurry can be colloidal silica or fumed silica to ensure a more consistent removal rate for the metal layer 50, barrier layer 40, and insulating film 30.

[0045] The grinding slurry used in the chemical mechanical polishing (CMP) process can also ensure that the removal rates of the metal layer 50, the barrier layer 40, and the insulating film 30 are equal, or that the difference in the removal rates of the metal layer 50, the barrier layer 40, and the insulating film 30 is within 10%. By adjusting the grinding slurry, the removal rates of the metal layer 50, the barrier layer 40, and the insulating film 30 in CMP are kept relatively consistent. Here, the difference in the removal rates of the metal layer 50, the barrier layer 40, and the insulating film 30 being within 10% can mean that: the removal rate of the metal layer 50 is V1, the removal rate of the barrier layer 40 is V2, and the removal rate of the insulating film 30 is V3; the average removal rate of the three is V0 = (V1 + V2 + V3) / 3. Therefore, V0*90% ≤ V1 ≤ V0*110%, V0*90% ≤ V2 ≤ V0*110%, and V0*90% ≤ V3 ≤ V0*110%. Of course, the difference in the grinding removal rate of the metal layer 50, the barrier layer 40 and the insulating film 30 within 10% can also refer to V3*90%≤V1≤V3*110% and V3*90%≤V2≤V3*110%, so as to limit the grinding removal rate of the metal layer 50 and the barrier layer 40 by the grinding removal rate of the insulating film 30.

[0046] Of course, embodiments of the present invention can also be used for fin manufacturing. Shallow grooves can be formed between fins in the manner described above. In this case, the pattern of the protrusion structure 20 is a fin pattern, which includes multiple spaced fins to prevent the CMP process from causing depressions between the fin patterns and to improve the electrical performance of the fin patterns.

[0047] After depositing an insulating film 30 on the surface of the raised structure 20 pattern and the substrate 10, a barrier layer 40 and a metal layer 50 are deposited on the insulating film 30, with the upper surface of the metal layer 50 forming a plane, allowing the metal material to fill the depressions on the upper surface of the insulating film 30. Then, a chemical mechanical polishing (CMP) process is used to polish the metal layer 50, the barrier layer 40, and the insulating film 30 sequentially from top to bottom. Compared to the prior art method of directly polishing after depositing the insulating film 3, the solution in this application has a plane surface at the start of the CMP process, and the depressions on the upper surface of the insulating film 30 are filled with metal material. Utilizing the relatively hard properties of the metal material in the depressions, the metal material removal rate is slower than that of the insulating film 30, preventing depressions from forming after CMP and achieving the purpose of controlling depressions. Therefore, when the upper surface of the raised structure 20 pattern is exposed during CMP, the insulating film 30 located between the raised structure 20 patterns is not over-polished, thus avoiding the depression phenomenon of the CMP process and improving the electrical performance of the semiconductor device. Furthermore, a barrier layer 40 is provided between the metal layer 50 and the insulating film 30 to prevent particles in the metal layer 50 from penetrating into the insulating film 30 and thus affecting the insulation performance of the insulating film 30.

[0048] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; A raised structure pattern is formed on the surface of the substrate, wherein the raised structure pattern comprises a plurality of spaced raised structures; An insulating film is deposited on the raised structural pattern and the substrate surface, wherein the lowest point of the insulating film is higher than the highest point of the raised structural pattern; A barrier layer is deposited on the surface of the insulating film; A metal layer is deposited on the surface of the barrier layer, and the upper surface of the metal layer is planar; The metal layer, barrier layer and insulating film are ground sequentially from top to bottom using a chemical mechanical polishing process until the upper surface of the raised structure pattern is exposed; The step of using a chemical mechanical polishing process to grind the metal layer, barrier layer, and insulating film sequentially from top to bottom includes: The difference in the removal rates of the metal layer, barrier layer, and insulating film by the grinding slurry used in the chemical mechanical polishing process is within 10%.

2. The manufacturing method as described in claim 1, characterized in that, The grinding fluid particles are in the form of colloidal silica or fumed silica.

3. The manufacturing method as described in claim 1, characterized in that, The raised structure pattern is a gate pattern, which includes a plurality of spaced gates.

4. The manufacturing method as described in claim 3, characterized in that, Each gate includes a wire formed on the surface of the substrate, and a spacer structure formed on the sidewalls and top surface of the wire; Specifically, the lowest point of the insulating film is higher than the highest point of the raised structure pattern. The step of using chemical mechanical polishing (CMP) to grind the metal layer, barrier layer, and insulating film sequentially from top to bottom until the upper surface of the raised structure pattern is exposed specifically involves using CMP to grind the metal layer, barrier layer, and insulating film sequentially from top to bottom until the upper surface of the spacer structure in the gate pattern is exposed.

5. The manufacturing method as described in claim 1, characterized in that, The raised structure pattern is a fin pattern, which includes multiple spaced fins.

6. The manufacturing method as described in claim 1, characterized in that, The material of the metal layer is tungsten.

7. The manufacturing method as described in claim 1, characterized in that, The barrier layer is made of titanium, titanium nitride, or a mixture of titanium and titanium nitride.

8. The manufacturing method as described in claim 1, characterized in that, The thickness of the portion of the insulating film located on the upper surface of the raised structural pattern is 500 Å to 1000 Å.

9. The manufacturing method as described in claim 8, characterized in that, The thickness of the barrier layer is 10 Å to 300 Å.

10. The manufacturing method as described in claim 9, characterized in that, The thickness of the metal layer is 100 Å to 5000 Å.

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