Microwave integrated circuit package assembly and packaging process thereof

Abstract

The embodiment of the present application provides a microwave integrated circuit packaging assembly and a packaging process thereof. First, the surface of the microwave integrated circuit bare chip without pads is packaged by using a heat-conducting material to obtain a restructured wafer. The heat-conducting material conducts away heat, which can effectively reduce the temperature of the microwave integrated circuit. A first dielectric layer is formed in a target area of the restructured wafer. Since the target area does not include the active circuit area of the microwave integrated circuit bare chip, the radio frequency performance caused by the influence of the surrounding medium on the active circuit area is reduced. The pads of the microwave integrated circuit bare chip are avoided, and a first conductive layer and a second dielectric layer are sequentially formed on the first dielectric layer. The pads of the microwave integrated circuit bare chip are exposed, so that a second conductive layer is formed on the second dielectric layer, and a radio frequency transmission line and a power line are etched on the second conductive layer. Then, a third dielectric layer is formed on the second conductive layer, which increases the thickness of the packaged chip and makes it not easy to be damaged by thermal stress and mechanical stress.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit packaging technology, and in particular to a microwave integrated circuit packaging assembly and its packaging process. Background Technology

[0002] Standard RF chips typically use microstrip lines as RF transmission lines to connect active devices. This facilitates the external packaging of the RF chip's I / O pins via wire bonding. Chip bump interconnects are a common packaging method, offering low performance loss for RF devices and reducing chip package area. However, when frequencies rise to the millimeter-wave band, wire bonding with gold wires can cause a shift in the amplitude-frequency characteristics of the circuitry formed by the active devices. Furthermore, the inductance generated by the gold wires can also shift the phase-frequency characteristics of the active devices, potentially leading to self-oscillation and burnout.

[0003] In microwave and millimeter-wave packaging, the use of coplanar waveguide flip-chip bump interconnect structures has become a popular application, promising higher performance and lower-cost packaging methods. For flip-chip structures using coplanar waveguide microwave integrated circuit chips, two main issues arise: first, the line impedance of the bare chip is affected by its proximity to the substrate; second, performance is affected by the backfill material.

[0004] In summary, when packaging chips for millimeter-wave applications, it is necessary to comprehensively consider smaller package size, millimeter-wave characteristics, and ideally, chip heat dissipation. Summary of the Invention

[0005] This invention provides a microwave integrated circuit packaging assembly and its packaging process, which solves the technical problems of low radio frequency performance and poor heat dissipation in existing microwave integrated circuit packaging.

[0006] In a first aspect, the present invention provides a microwave integrated circuit packaging process through an embodiment of the present invention, comprising: assembling a padless surface of a microwave integrated circuit die using a thermally conductive material to obtain a reconstructed wafer; forming a first dielectric layer in a target region of the reconstructed wafer, the target region excluding the active circuit region of the microwave integrated circuit die, the target region being located on the pad-containing side of the reconstructed wafer; avoiding the pads of the microwave integrated circuit die, sequentially forming a first conductive layer and a second dielectric layer on the first dielectric layer to expose the pads of the microwave integrated circuit die; forming a second conductive layer on the second dielectric layer, and etching radio frequency transmission lines and power lines on the second conductive layer; forming a third dielectric layer on the second conductive layer, and planting solder balls on the output ends of the radio frequency transmission lines and the output ends of the power lines exposed on the third dielectric layer to complete the packaging of the microwave integrated circuit.

[0007] Preferably, the method of using thermally conductive material to assemble the padless surface of a microwave integrated circuit die to obtain a reconstructed wafer includes: placing the microwave integrated circuit die on a temporary carrier, with the pad surface of the microwave integrated circuit die in contact with the temporary carrier; compressing the thermally conductive material onto the padless surface of the microwave integrated circuit die; and removing the temporary carrier to obtain the reconstructed wafer.

[0008] Preferably, forming a first dielectric layer within the target area of ​​the reconstructed wafer includes: flipping the reconstructed wafer and placing it on a chip pad, with the padless surface of the reconstructed wafer in contact with the chip pad, and forming the first dielectric layer within the target area.

[0009] Preferably, etching the radio frequency transmission line and the power line on the second conductive layer includes: determining the width of the radio frequency transmission line, the width of the power line, the clearing distance of the radio frequency transmission line, and the clearing distance of the power line; and etching the radio frequency transmission line and the power line on the second conductive layer based on the width of the radio frequency transmission line, the width of the power line, the clearing distance of the radio frequency transmission line, and the clearing distance of the power line.

[0010] Preferably, determining the width of the RF transmission line, the width of the power line, the clearing distance of the RF transmission line, and the clearing distance of the power line includes: establishing a corresponding digital simulation model based on the packaged microwave integrated circuit; performing electromagnetic performance simulation using the digital simulation model; determining the width of the RF transmission line and the width of the power line, as well as the clearing distance of the RF transmission line and the clearing distance of the power line, based on the electromagnetic simulation results.

[0011] Preferably, before completing the packaging of the microwave integrated circuit, the method further includes: forming an electrical connection between the first conductive layer and the microwave integrated circuit die, and grounding the first conductive layer; and forming an electrical connection between the second conductive layer and the microwave integrated circuit die through a rewiring process.

[0012] Secondly, the present invention provides a microwave integrated circuit packaging assembly through an embodiment of the present invention, comprising: a reconstructed wafer layer, a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer, and a third dielectric layer stacked sequentially; wherein, the reconstructed wafer layer includes a microwave integrated circuit die and a thermally conductive material covering the padless surface of the microwave integrated circuit die; the first dielectric layer is located within a target area of ​​the reconstructed wafer layer, the target area excluding the active circuit area of ​​the microwave integrated circuit die; the pads of the microwave integrated circuit die are exposed relative to the first conductive layer and the second dielectric layer; the second conductive layer includes a radio frequency transmission line and a power line; the output terminals of the radio frequency transmission line and the power line are exposed relative to the third dielectric layer, and solder balls are implanted at the output terminals of the radio frequency transmission line and the power line.

[0013] Preferably, the width of the radio frequency transmission line, the width of the power line, the clearing distance of the radio frequency transmission line, and the clearing distance of the power line are determined based on the electromagnetic simulation results; wherein, the electromagnetic simulation results are obtained by performing electromagnetic performance simulation based on a digital simulation model; the digital simulation model is established based on the packaged microwave integrated circuit.

[0014] Preferably, the radio frequency transmission line and the power line are etched on the second conductive layer based on the width of the radio frequency transmission line, the width of the power line, the clearing distance of the radio frequency transmission line, and the clearing distance of the power line.

[0015] Preferably, the thermally conductive material is silicone grease or epoxy resin mixed with silicone grease; the first dielectric layer, the second dielectric layer and the third dielectric layer are made of polyimide; the first conductive layer and the second conductive layer are made of copper; the width of the radio frequency transmission line and the width of the power line are in the range of 16 to 22 micrometers; and the spacing between the solder balls is in the range of 0.01 to 0.15 millimeters.

[0016] One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0017] A reconstructed wafer is obtained by packaging the padless surface of a microwave integrated circuit die using a thermally conductive material. By dissipating heat through the material, the temperature of the microwave integrated circuit is effectively reduced, improving the heat dissipation performance of the reconstructed wafer. A first dielectric layer is formed within the target area of ​​the reconstructed wafer. Since the target area does not include the active circuit area of ​​the microwave integrated circuit die, the RF performance degradation caused by the surrounding dielectric is reduced. Avoiding the pads of the microwave integrated circuit die, a first conductive layer and a second dielectric layer are sequentially formed on the first dielectric layer. By exposing the pads of the microwave integrated circuit die, a second conductive layer is formed on the second dielectric layer, and RF transmission lines and power lines are etched on the second conductive layer. Next, a third dielectric layer is formed on the second conductive layer to increase the thickness of the packaged chip, making it less susceptible to damage from thermal and mechanical stress. Solder balls are implanted on the output ends of the RF transmission lines and power lines exposed on the third dielectric layer, completing the packaging of the microwave integrated circuit. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of the microwave integrated circuit packaging process in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the reconstructed wafer structure in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the structure in which the first dielectric layer is formed on the reconstructed wafer in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the structure in which the first conductive layer is formed on the first dielectric layer in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the structure in which the second dielectric layer is formed on the first conductive layer in an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure in which the second conductive layer is formed on the second dielectric layer in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of the structure in an embodiment of the present invention where the third dielectric layer is formed on the second conductive layer;

[0026] Figure 8This is a schematic diagram of the microwave integrated circuit packaging assembly in an embodiment of the present invention. Detailed Implementation

[0027] This invention provides a microwave integrated circuit packaging assembly and its packaging process, which solves the technical problems of low radio frequency performance and poor heat dissipation in existing microwave integrated circuit packaging.

[0028] The technical solution provided by the embodiments of the present invention is to solve the above-mentioned technical problems, and the general idea is as follows:

[0029] By using thermally conductive materials to mount the padless surface of a microwave integrated circuit die, a reconstructed wafer is obtained. This allows the thermally conductive material to dissipate heat from the microwave integrated circuit, improving the heat dissipation performance of the reconstructed wafer. A first dielectric layer is formed outside the active circuit region of the microwave integrated circuit die, reducing the RF performance degradation caused by the surrounding dielectric in the active circuit region.

[0030] By avoiding the pads of the microwave integrated circuit die, a first conductive layer and a second dielectric layer are sequentially formed on the first dielectric layer, exposing the pads of the microwave integrated circuit die. This facilitates the formation of a second conductive layer on the second dielectric layer, where radio frequency transmission lines and power lines are etched. Next, a third dielectric layer is formed on the second conductive layer, increasing the thickness of the packaged chip and making it less susceptible to damage from thermal and mechanical stress. Solder balls are then implanted on the output ends of the exposed radio frequency transmission lines and power lines on the third dielectric layer, completing the packaging of the microwave integrated circuit.

[0031] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0032] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0033] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0034] In a first aspect, the present invention provides a microwave integrated circuit packaging process through an embodiment thereof, which can be used to package microwave integrated circuits, and can also be used to package millimeter-wave integrated circuits. Please see below. Figure 1 As shown, the packaging process includes the following steps S101 to S105:

[0035] Step S101: The surface of the microwave integrated circuit die without pads is assembled using a thermally conductive material to obtain a reconstructed wafer.

[0036] Specifically, microwave integrated circuit (IC) dies can be placed on a temporary carrier, with the pads of the IC dies in contact with the temporary carrier. In practice, the microwave IC wafer can be diced into IC dies, and then the pads of the IC dies can be placed on the temporary carrier.

[0037] The temporary carrier can be equipped with double-sided thermal adhesive tape to facilitate bonding of the microwave integrated circuit die and prevent relative displacement between the microwave integrated circuit die and the temporary carrier, which would hinder subsequent processes. The temporary carrier can be circular or rectangular, and there is no limitation on its shape.

[0038] Next, a thermally conductive material is compressed and molded onto the padless surface of the microwave integrated circuit die, and the temporary carrier is removed to obtain a reconstructed wafer. The thermally conductive material can be an epoxy molding compound (EMC) with added thermally conductive silicone, or it can be thermally conductive silicone or thermal grease. The compression molding can be performed using a one-piece compression molding process. In some embodiments, the structure of the reconstructed wafer can be seen as follows: Figure 2 As shown, the reconstructed wafer may include a microwave integrated circuit die 201 and a thermally conductive material 202.

[0039] Step S102: Form a first dielectric layer in the target area of ​​the reconstructed wafer. The target area does not include the active circuit area of ​​the microwave integrated circuit die. The target area is located on the side of the reconstructed wafer with pads.

[0040] Specifically, to form a first dielectric layer in the target area of ​​the reconstructed wafer, the reconstructed wafer can be flipped and placed on a chip pad so that the padless surface of the reconstructed wafer contacts the chip pad, and a first dielectric layer is formed in the target area.

[0041] In the specific implementation process, after flipping, the pad surface of the reconstructed wafer can be placed on the chip pad through an opening in a passivation layer (PSV). This allows the passivation layer to cover the active circuit area of ​​the microwave integrated circuit die 201. Consequently, when the first dielectric layer is formed on the pad surface of the reconstructed wafer, the first dielectric layer will not cover the active circuit area, thus affecting the RF performance of the reconstructed wafer.

[0042] In one alternative implementation, the material forming the first dielectric layer may be polyimide (PI) or other insulating materials, such as epoxy resin. In some implementations, the first dielectric layer formed in the reconstructed wafer target region may refer to... Figure 3 As shown, the first dielectric layer 203 is formed on the microwave integrated circuit die 201.

[0043] Step S103: Avoiding the pads of the microwave integrated circuit die, a first conductive layer and a second dielectric layer are sequentially formed on the first dielectric layer to expose the pads of the microwave integrated circuit die.

[0044] Specifically, the first conductive layer cannot cover the pads of the microwave integrated circuit die 201 to avoid short-circuit failure of the microwave integrated circuit die 201; understandably, the first conductive layer also cannot cover the active circuit area of ​​the microwave integrated circuit die 201 to reduce radio frequency performance.

[0045] In one alternative implementation, the material forming the first conductive layer can be copper, or other conductive materials, such as silver or gold. The structure of the first conductive layer formed on the first dielectric layer 203 can be seen in... Figure 4 As shown, the first conductive layer 204 is formed on the first dielectric layer 203.

[0046] In the specific implementation process, a first conductive layer 204 can be formed on the first dielectric layer 203, and then the pads can be exposed by etching to facilitate subsequent redistribution processes. Next, a second dielectric layer is formed on the first conductive layer 204. Similarly, the second dielectric layer can be etched to expose the pads and active circuit areas of the microwave integrated circuit die 201.

[0047] The material forming the second dielectric layer can be polyimide (PI) or other insulating materials, such as epoxy resin. In some embodiments, the structure of the second dielectric layer formed on the first conductive layer 204 can be seen as follows: Figure 5 As shown, the second dielectric layer 205 is formed on the first conductive layer 204.

[0048] Step S104: Form a second conductive layer on the second dielectric layer, and etch radio frequency transmission lines and power lines on the second conductive layer.

[0049] To determine how to etch RF transmission lines and power lines onto the second conductive layer, the widths of the RF transmission lines and power lines, as well as their clearance distances, can be determined first. Then, based on these dimensions, the RF transmission lines and power lines are etched onto the second conductive layer.

[0050] In the specific implementation process, a corresponding digital simulation model can be established based on the packaged microwave integrated circuit. Then, electromagnetic performance simulation is performed using the digital simulation model. Based on the electromagnetic simulation results, the width of the RF transmission line and the width of the power line are determined, as well as the clearing distance of the RF transmission line and the clearing distance of the power line are determined.

[0051] The packaged microwave integrated circuit needs to be mounted on a PCB (Printed Circuit Board) to distribute signals. Therefore, the corresponding digital simulation model can include a radio frequency (RF) transition model. This model includes the connection between the second conductive layer and the pads, the electrical connection between the second conductive layer and the solder balls in the package, and the electrical connection between the second conductive layer and the PCB, to ensure the accuracy of the electromagnetic simulation. Optionally, the RF transition model can be built using three-dimensional electromagnetic simulation software, such as the High Frequency Structure Simulator (HFSS) in ANSYS.

[0052] It should be noted that the first conductive layer 204 is grounded; the second dielectric layer 205 and the second conductive layer 206 constitute a coplanar waveguide. The first conductive layer 204, the second dielectric layer 205, and the second conductive layer 206 together constitute a back-grounded coplanar waveguide transmission line, and also constitute a radio frequency transmission line.

[0053] In one implementation, a second conductive layer can be formed by a rewiring process. The width of the radio frequency transmission line can be any value from 16 micrometers to 22 micrometers; the width of the power line can be any value from 16 micrometers to 22 micrometers; the clear distance of the radio frequency transmission line can be any value from 11 micrometers to 100 micrometers; and the clear distance of the power line can be any value from 11 micrometers to 100 micrometers.

[0054] The material forming the second conductive layer can be copper, or other conductive materials, such as silver or gold. The structure of the second conductive layer formed on the second dielectric layer 205 can be seen in... Figure 6 As shown, the second conductive layer 206 is formed on the second dielectric layer 205.

[0055] Step S105: A third dielectric layer is formed on the second conductive layer, and solder balls are planted on the output ends of the radio frequency transmission lines and the power lines exposed on the third dielectric layer to complete the packaging of the microwave integrated circuit.

[0056] like Figure 7 As shown, after forming the third dielectric layer 207, an under bump metallurgy (UBM) can be generated on the output end of the RF transmission line and the output end of the power line, and solder balls can be planted on the under bump metallurgy.

[0057] Before completing the packaging of the microwave integrated circuit, it is necessary to form an electrical connection between the first conductive layer 204 and the microwave integrated circuit die 201, and to ground the first conductive layer 204; and through a redistribution process, to form an electrical connection between the second conductive layer 206 and the microwave integrated circuit die 201, so that the second conductive layer 206 establishes electrical connections with the pads and solder balls respectively.

[0058] Because the second conductive layer 206 is formed using a rewiring process in this embodiment of the invention, the length of the RF transmission line is shorter. The shorter signal path results in lower parasitic effects, leading to superior electrical performance at millimeter-wave frequencies. Furthermore, since the first dielectric layer 203, the second dielectric layer 205, and the third dielectric layer 207 do not cover the active circuit area, RF losses are reduced.

[0059] The area of ​​the first conductive layer 204 can be set according to heat dissipation requirements. For example, the first conductive layer 204 can be formed in any area other than the active circuit area and the pads to achieve higher heat dissipation performance.

[0060] Secondly, through one embodiment of the present invention, the present invention provides a microwave integrated circuit packaging assembly, please refer to [link to relevant documentation]. Figure 8 As shown, the microwave integrated circuit package assembly includes: a reconfigurable wafer layer 301, a first dielectric layer 302, a first conductive layer 303, a second dielectric layer 304, a second conductive layer 305, and a third dielectric layer 306 stacked sequentially.

[0061] The reconstructed wafer layer 301 includes a microwave integrated circuit die 3011 and a thermally conductive material 3012 covering the padless surface of the microwave integrated circuit die 3011. A first dielectric layer 302 is located within a target area of ​​the reconstructed wafer layer 301, excluding the active circuit area of ​​the microwave integrated circuit die 3011. The pads of the microwave integrated circuit die 3011 are exposed relative to the first conductive layer 303 and the second dielectric layer 304. The second conductive layer 305 includes radio frequency transmission lines and power lines. The output terminals of the radio frequency transmission lines and the power lines are exposed relative to the third dielectric layer 306, and solder balls 307 are planted at the output terminals of the radio frequency transmission lines and the power lines.

[0062] As an optional implementation, the width of the RF transmission line, the width of the power line, the clearing distance of the RF transmission line, and the clearing distance of the power line can be determined based on the electromagnetic simulation results; wherein, the electromagnetic simulation results are obtained by performing electromagnetic performance simulation based on a digital simulation model. The digital simulation model can be established based on the packaged microwave integrated circuit.

[0063] As an alternative implementation, the radio frequency transmission line and the power line are etched on the second conductive layer 305 based on the width of the radio frequency transmission line, the width of the power line, the clearing distance of the radio frequency transmission line, and the clearing distance of the power line.

[0064] As an optional implementation, the thermally conductive material 3012 is silicone grease or epoxy resin mixed with silicone grease; the first dielectric layer 302, the second dielectric layer 304 and the third dielectric layer 306 are made of polyimide; the first conductive layer 303 and the second conductive layer 305 are made of copper; the width of the radio frequency transmission line and the width of the power line are in the range of 16 to 22 micrometers; and the spacing between the solder balls is in the range of 0.01 to 0.15 millimeters.

[0065] The technical solutions in the above embodiments of the present invention have at least the following technical effects or advantages:

[0066] A first dielectric layer is formed outside the active circuit region of the microwave integrated circuit die, reducing the RF performance degradation caused by the surrounding dielectric in the active circuit region. A first conductive layer and a second dielectric layer are sequentially formed on the first dielectric layer, avoiding the pads of the microwave integrated circuit die, thus exposing the pads of the microwave integrated circuit die. This facilitates the formation of a second conductive layer on the second dielectric layer, where RF transmission lines and power lines are etched. Next, a third dielectric layer is formed on the second conductive layer, increasing the thickness of the packaged chip and making it less susceptible to damage from thermal and mechanical stresses.

[0067] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable code.

[0068] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer instructions. These computer instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0069] These computer instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0070] These computer instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0071] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0072] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A microwave integrated circuit packaging process, characterized in that, include: By using thermally conductive materials to assemble the padless surface of microwave integrated circuit dies, a reconstructed wafer is obtained. An open passivation layer is provided on the pad surface of the reconstructed wafer, such that the passivation layer covers the active circuit area of ​​the microwave integrated circuit die. A first dielectric layer is formed in the target area of ​​the reconstructed wafer. The target area does not include the active circuit area of ​​the microwave integrated circuit die. The target area is located on the side of the reconstructed wafer with pads. A first conductive layer and a second dielectric layer are formed sequentially on the first dielectric layer, avoiding the pads of the microwave integrated circuit die, so that the pads are not covered by the first conductive layer and the second dielectric layer. A second conductive layer is formed on the second dielectric layer, and radio frequency transmission lines and power lines are etched on the second conductive layer; A third dielectric layer is formed on the second conductive layer, and solder balls are planted on the output ends of the radio frequency transmission line and the output ends of the power line exposed on the third dielectric layer to complete the packaging of the microwave integrated circuit.

2. The process as described in claim 1, characterized in that, The method of assembling the surface of a microwave integrated circuit die without solder pads using thermally conductive materials to obtain a reconstructed wafer includes: The microwave integrated circuit die is placed on a temporary carrier, with the pads of the microwave integrated circuit die in contact with the temporary carrier. The thermally conductive material is compressed and shaped on the padless surface of the microwave integrated circuit die, and the temporary carrier is removed to obtain the reconstructed wafer.

3. The process as described in claim 2, characterized in that, A first dielectric layer is formed within the target region of the reconstructed wafer, including: The reconstructed wafer is flipped and placed on a chip pad, with the padless side of the reconstructed wafer in contact with the chip pad, and the first dielectric layer is formed in the target area.

4. The process as described in claim 1, characterized in that, The etching of the radio frequency transmission line and power line on the second conductive layer includes: Determine the width of the radio frequency transmission line, the width of the power line, the clearing distance of the radio frequency transmission line, and the clearing distance of the power line; Based on the width of the RF transmission line, the width of the power line, the clearing distance of the RF transmission line, and the clearing distance of the power line, the RF transmission line and the power line are etched on the second conductive layer.

5. The process as described in claim 4, characterized in that, Determining the width of the RF transmission line, the width of the power line, the clearing distance of the RF transmission line, and the clearing distance of the power line includes: A corresponding digital simulation model is established based on the packaged microwave integrated circuit. Electromagnetic performance simulation was performed using the aforementioned digital simulation model; The widths of the radio frequency transmission line and the power line are determined based on the electromagnetic simulation results, as are the clearing distances of the radio frequency transmission line and the power line.

6. The process as described in claim 1, characterized in that, Before completing the packaging of the microwave integrated circuit, the following steps are also included: The first conductive layer is electrically connected to the microwave integrated circuit die, and the first conductive layer is grounded; The second conductive layer is electrically connected to the microwave integrated circuit die through a rewiring process.

7. A microwave integrated circuit packaging assembly, characterized in that, include: The reconstructed wafer layer, the first dielectric layer, the first conductive layer, the second dielectric layer, the second conductive layer, and the third dielectric layer are stacked sequentially. The reconstructed wafer layer includes a microwave integrated circuit die and a thermally conductive material covering the padless surface of the microwave integrated circuit die; the pad surface of the reconstructed wafer is provided with an open passivation layer, such that the passivation layer covers the active circuit area of ​​the microwave integrated circuit die. The first dielectric layer is located within the target area of ​​the reconstructed wafer layer, and the target area does not include the active circuit area of ​​the microwave integrated circuit die; the target area is located on the side of the reconstructed wafer with pads; The pads are not covered by the first conductive layer and the second dielectric layer; The second conductive layer includes radio frequency transmission lines and power lines; The output terminals of the radio frequency transmission line and the power supply line are exposed relative to the third dielectric layer, and solder balls are implanted on the output terminals of the radio frequency transmission line and the power supply line.

8. The microwave integrated circuit packaging assembly as described in claim 7, characterized in that, The width of the radio frequency transmission line, the width of the power line, the clearing distance of the radio frequency transmission line, and the clearing distance of the power line are determined based on the electromagnetic simulation results. The electromagnetic simulation results are obtained by performing electromagnetic performance simulation based on a digital simulation model; the digital simulation model is established based on the packaged microwave integrated circuit.

9. The microwave integrated circuit packaging assembly as described in claim 8, characterized in that, The radio frequency transmission line and the power line are etched on the second conductive layer based on the width of the radio frequency transmission line, the width of the power line, the clearing distance of the radio frequency transmission line, and the clearing distance of the power line.

10. The microwave integrated circuit packaging assembly as described in claim 7, characterized in that, The thermally conductive material is silicone grease or epoxy resin mixed with silicone grease; The first dielectric layer, the second dielectric layer, and the third dielectric layer are made of polyimide; the first conductive layer and the second conductive layer are made of copper. The width of the radio frequency transmission line and the width of the power line are in the range of 16 to 22 micrometers; The spacing between the solder balls is in the range of 0.01 to 0.15 mm.

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