semiconductor devices

Abstract

A semiconductor device includes a plurality of p-type surface voltage-resistant regions and a plurality of p-type deep voltage-resistant regions disposed below the plurality of surface voltage-resistant regions in an outer peripheral region. The width of the interval between the inner peripheral surface voltage-resistant region and the outer peripheral surface voltage-resistant region is set to Ws (m), and the n-type impurity concentration in the surface interval region between the inner peripheral surface voltage-resistant region and the outer peripheral surface voltage-resistant region is set to Ns (m －3 ), the n-type impurity concentration of the drift region within the depth range between the surface withstand voltage region and the deep withstand voltage region is set to Nv(m －3 ), when the width of the interval between the inner circumference surface pressure-resistant region and the specific deep pressure-resistant region is set to Wv1(m), and the width of the interval between the outer circumference surface pressure-resistant region and the specific deep pressure-resistant region is set to Wv2(m), Nv(Wv1+Wv2) is satisfied. 2 <Ns·Ws 2 relationship.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Japanese Patent Publication No. 2019-140138 discloses a semiconductor device having multiple guard rings. In this semiconductor device, multiple guard rings are provided in the peripheral area of ​​the semiconductor substrate. Furthermore, the peripheral area of ​​the semiconductor substrate is covered with a protective film. Typically, an oxide film is used for the protective film. Multiple guard rings are in contact with the protective film. Multiple guard rings are arranged in a state where there is a gap between each other from the inner peripheral side (the side closer to the element area) toward the outer peripheral side (the side closer to the peripheral end face of the semiconductor substrate). When the semiconductor device is cut off, the depletion layer expands to the drift region in the peripheral area. In the state where the depletion layer expands to the drift region in the peripheral area, the electric field concentration in the peripheral area is alleviated by the multiple guard rings. Thus, the withstand voltage of the semiconductor device can be improved. Hereinafter, the p-type region provided in the peripheral area like the guard ring is referred to as the withstand voltage region. Summary of the Invention

[0003] Summary of the Invention

[0004] Technical problem to be solved by the invention

[0005] If the intervals between the voltage-resistant regions are wide, a high electric field is generated in the interval when the drift region is depleted. If a high electric field is generated in the intervals between the voltage-resistant regions, hot carriers accelerated by the electric field are injected into the oxide film covering the peripheral voltage-resistant region. As a result, the electric field distribution in the peripheral region is disordered, and the voltage resistance of the semiconductor device decreases. By narrowing the intervals between the voltage-resistant regions, the electric field generated in the intervals can be reduced. However, due to problems with processing accuracy, there are limits to narrowing the intervals between the voltage-resistant regions. Therefore, this specification proposes a technology that can effectively improve the voltage resistance of a semiconductor device through a voltage-resistant region.

[0006] Means for solving technical problems

[0007] The semiconductor device disclosed in this specification comprises a semiconductor substrate, an upper electrode in contact with the upper surface of the semiconductor substrate, a lower electrode in contact with the lower surface of the semiconductor substrate, and an oxide film in contact with the upper surface of the semiconductor substrate. The semiconductor substrate comprises an element region and a peripheral region, wherein the upper electrode is in contact with the upper surface of the semiconductor substrate in the element region, and the oxide film is in contact with the upper surface of the semiconductor substrate in the peripheral region. The peripheral region is located between the element region and the peripheral end surface of the semiconductor substrate. The element region comprises a semiconductor element connected between the upper electrode and the lower electrode. The peripheral region comprises a plurality of p-type surface withstand voltage regions, a plurality of p-type deep withstand voltage regions, and an n-type drift region. The plurality of surface withstand voltage regions are in contact with the oxide film. The plurality of surface withstand voltage regions are arranged at intervals from the inner peripheral side toward the outer peripheral side. The plurality of deep withstand voltage regions are arranged below the plurality of surface withstand voltage regions. The above-mentioned multiple deep pressure-resistant regions are arranged at intervals from the inner circumference to the outer circumference. The above-mentioned drift region separates the above-mentioned multiple surface pressure-resistant regions from the above-mentioned multiple deep pressure-resistant regions, separates the above-mentioned surface pressure-resistant regions from each other, and separates the above-mentioned deep pressure-resistant regions from each other. When the above-mentioned drift region located in the interval between the above-mentioned surface pressure-resistant regions is set as the surface interval region, and the above-mentioned drift region located in the interval between the above-mentioned deep pressure-resistant regions is set as the deep interval region, the above-mentioned deep pressure-resistant region is located directly below the above-mentioned surface interval region, and the above-mentioned deep interval region is located directly below the above-mentioned surface pressure-resistant region. Each deep pressure-resistant region extends from a position directly below the above-mentioned surface pressure-resistant region adjacent to itself on the inner circumference to a position directly below the above-mentioned surface pressure-resistant region adjacent to itself on the outer circumference. One of the plurality of deep pressure-resistant regions is set as a specific deep pressure-resistant region, the surface pressure-resistant region adjacent to the specific deep pressure-resistant region on the inner circumference is set as an inner circumference surface pressure-resistant region, the surface pressure-resistant region adjacent to the specific deep pressure-resistant region on the outer circumference is set as an outer circumference surface pressure-resistant region, the width of the interval between the inner circumference surface pressure-resistant region and the outer circumference surface pressure-resistant region is set as Ws (m), the n-type impurity concentration of the surface interval region between the inner circumference surface pressure-resistant region and the outer circumference surface pressure-resistant region is set as Ns (m －3 ), the n-type impurity concentration of the drift region within the depth range between the plurality of surface withstand voltage regions and the plurality of deep withstand voltage regions is set to Nv(m －3 ), when the width of the interval between the inner circumference surface pressure-resistant region and the specific deep pressure-resistant region is set to Wv1(m), and the width of the interval between the outer circumference surface pressure-resistant region and the specific deep pressure-resistant region is set to Wv2(m), Nv(Wv1+Wv2) is satisfied. 2 <Ns·Ws2 ···(Mathematical formula 1).

[0008] In addition, in this specification, "inner peripheral side" refers to the direction close to the element area, and "outer peripheral side" refers to the direction close to the outer peripheral end surface of the semiconductor substrate. Furthermore, in this specification, "adjacent on the inner peripheral side" refers to the area located on the inner peripheral side and closest to the object area relative to the object area. For example, "surface pressure-resistant area adjacent to a specific deep pressure-resistant area on the inner peripheral side" refers to the surface pressure-resistant area closest to the specific deep pressure-resistant area among one or more surface pressure-resistant areas located on the inner peripheral side relative to the specific deep pressure-resistant area. Furthermore, in this specification, "adjacent on the outer peripheral side" refers to the area located on the outer peripheral side and closest to the object area relative to the object area. For example, "surface pressure-resistant area adjacent to a specific deep pressure-resistant area on the outer peripheral side" refers to the surface pressure-resistant area closest to the specific deep pressure-resistant area among one or more surface pressure-resistant areas located on the outer peripheral side relative to the specific deep pressure-resistant area.

[0009] In this semiconductor device, when the depletion layer extends from the element region into the drift region within the outer peripheral region, the depletion layer progresses via the surface voltage-resistant region and the deep voltage-resistant region. When the depletion layer reaches the inner peripheral side surface voltage-resistant region, the depletion layer extends from the inner peripheral side surface voltage-resistant region to its surroundings. If the relationship of the above-mentioned mathematical formula 1 is satisfied, the depletion layer extending from the inner peripheral side surface voltage-resistant region reaches the outer peripheral side surface voltage-resistant region via a specific deep voltage-resistant region before directly reaching the outer peripheral side surface voltage-resistant region. Therefore, the potential of the specific deep voltage-resistant region is higher than the potential of the inner peripheral side surface voltage-resistant region and lower than the potential of the outer peripheral side surface voltage-resistant region. If the potential is distributed in this way, the electric field is dispersed in the surface spacing region between the inner peripheral side surface voltage-resistant region and the outer peripheral side surface voltage-resistant region (i.e., the drift region near the oxide film). Thus, according to this semiconductor device, the injection of hot carriers into the oxide film can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a top view of a semiconductor device.

[0011] Figure 2 yes Figure 1 Cross-sectional view of line II-II.

[0012] Figure 3 It is an enlarged cross-sectional view of the outer peripheral area.

[0013] Figure 4 It is an enlarged cross-sectional view of the outer peripheral area.

[0014] Figure 5 It is an enlarged cross-sectional view of the outer peripheral region of a semiconductor device according to a comparative example.

[0015] Figure 6 It is a diagram showing the electric field distribution in the surface gap region. DETAILED DESCRIPTION

[0016] The following are additional features of the film forming method disclosed in this specification. In addition, each of the features listed below is useful independently.

[0017] In the semiconductor device of one example disclosed in this specification, the width Wv1 may be smaller than the width Ws, and the width Wv2 may be smaller than the width Ws.

[0018] According to this structure, the relationship of the above-mentioned mathematical formula 1 can be obtained while ensuring that the width Ws of the interval between the inner side surface pressure-resistant region and the outer side surface pressure-resistant region is wider. Since the interval between the inner side surface pressure-resistant region and the outer side surface pressure-resistant region (the interval of width Ws) is a horizontal interval (along the direction of the upper surface of the semiconductor substrate), there is a limit to narrowing the width Ws due to processing accuracy issues. On the other hand, since the interval between the specific deep pressure-resistant region and the inner side surface pressure-resistant region (the interval of width Wv1) and the interval between the specific deep pressure-resistant region and the outer side surface pressure-resistant region (the interval of width Wv2) are vertical intervals (in the thickness direction of the semiconductor substrate), it is relatively easy to narrow the widths Wv1 and Wv2 by controlling the thickness of the epitaxial film and controlling the ion implantation depth. Therefore, according to this structure, the relationship of the above-mentioned mathematical formula 1 can be obtained relatively easily.

[0019] In the semiconductor device of one example disclosed in this specification, the n-type impurity concentration of each of the deep spacer regions may be higher than the n-type impurity concentration of each of the surface spacer regions.

[0020] According to this structure, a high electric field is easily generated in the deep spacer region, while a high electric field is less likely to be generated in the surface spacer region. Therefore, hot carriers are less likely to be generated in the surface spacer region, and injection of hot carriers into the oxide film is suppressed.

[0021] In an example of the semiconductor device disclosed in this specification, the width of the interval between the deep voltage-resistant regions may be Wd(m), and the n-type impurity concentration of each deep interval region may be Nd(m). －3 ), satisfying Nd·Wd 2 >Ns·Ws 2 relationship.

[0022] According to this structure, a high electric field is easily generated in the deep spacer region, while a high electric field is less likely to be generated in the surface spacer region. Therefore, hot carriers are less likely to be generated in the surface spacer region, and injection of hot carriers into the oxide film is suppressed.

[0023] (Example 1)

[0024] Figure 1 、 Figure 2 FIG. 1 shows a semiconductor device 10 according to the first embodiment. Figure 1 、 Figure 2 As shown, the semiconductor device 10 includes a semiconductor substrate 12. Figure 2 As shown, an upper electrode 14 and an oxide film 16 are provided on the upper surface 12a of the semiconductor substrate 12. The oxide film 16 is an insulating protective film made of silicon oxide. Figure 1 The upper electrode 14 and the oxide film 16 are omitted in the figure. The semiconductor substrate 12 has a device region 20 and a peripheral region 22. The device region 20 is a region where the upper electrode 14 is in contact with the upper surface 12a of the semiconductor substrate 12. The peripheral region 22 is a region where the oxide film 16 is in contact with the upper surface 12a of the semiconductor substrate 12. Figure 1 As shown, the device region 20 is provided in the central portion of the semiconductor substrate 12. The peripheral region 22 is provided between the device region 20 and the peripheral end surface 12c of the semiconductor substrate 12. The peripheral region 22 surrounds the device region 20. The lower electrode 18 is provided on the lower surface 12b of the semiconductor substrate 12. The lower electrode 18 is in contact with substantially the entire area of ​​the lower surface 12b.

[0025] In the element region 20, a MOSFET (metal oxide semiconductor field effect transistor) is formed. Figure 2 As shown, the MOSFET has a gate electrode 30, a source region 32, a body region 34, a drift region 36, and a drain region 38. Trenches are provided on the upper surface 12a within the element region 20, and gate electrodes 30 are arranged in each trench. The gate electrode 30 is insulated from the semiconductor substrate 12 by a gate insulating film. The source region 32 is an n-type region and is in contact with the upper electrode 14 and the gate insulating film. The body region 34 is a p-type region and is in contact with the upper electrode 14. Furthermore, the body region 34 is in contact with the gate insulating film below the source region 32. The body region 34 has a surface protrusion 34a protruding toward the outer periphery within a range including the upper surface 12a of the semiconductor substrate 12. The surface protrusion 34a is arranged within the peripheral region 22. Furthermore, the body region 34 has a deep protrusion 34b protruding toward the outer periphery below the surface protrusion 34a. The deep protrusion 34b is arranged within the peripheral region 22. The deep protrusion 34b protrudes less than the surface protrusion 34a. The drift region 36 is a low-concentration n-type region and is located below the body region 34. The drift region 36 is in contact with the gate insulating film below the body region 34. The drain region 38 is a high-concentration n-type region and is located below the drift region 36. The drain region 38 is in contact with the lower electrode 18.

[0026] The drift region 36 and the drain region 38 are distributed from the element region 20 to the peripheral region 22 . The drift region 36 and the drain region 38 are exposed at the peripheral end surface 12 c of the semiconductor substrate 12 .

[0027] The outer peripheral region 22 is provided with a plurality of surface protection rings 40 a to 40 d and a plurality of deep protection rings 42 a to 42 d.

[0028] The plurality of surface protection rings 40a to 40d are p-type regions and are arranged in a range exposed on the upper surface 12a of the semiconductor substrate 12. Each of the surface protection rings 40a to 40d is in contact with the oxide film 16. Figure 1 As shown, the plurality of surface protection rings 40a to 40d extend in a ring shape so as to multiplexly surround the device region 20. Figure 2 As shown, multiple surface protection rings 40a-40d are spaced apart from each other from the inner circumference toward the outer circumference. Drift regions 36 are distributed in the spaces between the surface protection rings 40a-40d. In these spaces, the drift regions 36 are exposed on the upper surface 12a of the semiconductor substrate 12. The surface protection rings 40a-40d are separated from each other by the drift regions 36.

[0029] A gap is provided between the innermost surface guard ring 40a and the surface protrusion 34a of the body region 34. A drift region 36 is distributed in this gap, and in this gap, the drift region 36 is exposed on the upper surface 12a of the semiconductor substrate 12. The surface guard rings 40a to 40d are separated from the body region 34 by the drift region 36. Hereinafter, a portion of the drift region 36 located in the gap between the surface guard ring 40a and the surface protrusion 34a will be referred to as a surface gap region 50a. Furthermore, a portion of the drift region 36 located in the gap between the surface guard ring 40a and the surface guard ring 40b, the gap between the surface guard ring 40b and the surface guard ring 40c, and the gap between the surface guard ring 40c and the surface guard ring 40d will be referred to as surface gap regions 50b, 50c, and 50d, respectively.

[0030] The multiple deep guard rings 42a to 42d are p-type regions and are arranged below (deeper than) the surface guard rings 40a to 40d. That is, the deep guard rings 42a to 42d are arranged below the lower ends of the surface guard rings 40a to 40d. The deep guard rings 42a to 42d are set at approximately the same depth as the deep protrusion 34b of the body region 34. The drift region 36 is distributed in the range between the lower ends of the surface guard rings 40a to 40d and the upper ends of the deep guard rings 42a to 42d. Hereinafter, the drift region 36 located between the lower ends of the surface guard rings 40a to 40d and the upper ends of the deep guard rings 42a to 42d is referred to as the intermediate region 54. The multiple deep guard rings 42a to 42d are separated from the multiple surface guard rings 40a to 40d by the drift region 36 (intermediate region 54). A plurality of deep protection rings 42a to 42d are arranged at intervals from the inner peripheral side toward the outer peripheral side. The deep protection rings 42a to 42d are arranged directly below the surface spacing regions 50a to 50d. That is, when looking down at the semiconductor substrate 12 from above, the deep protection ring 42a is arranged at a position overlapping with the surface spacing region 50a, the deep protection ring 42b is arranged at a position overlapping with the surface spacing region 50b, the deep protection ring 42c is arranged at a position overlapping with the surface spacing region 50c, and the deep protection ring 42d is arranged at a position overlapping with the surface spacing region 50d. A plurality of deep protection rings 42a to 42d are arranged as follows. Figure 1 As shown, the spacer regions 50 a to 50 d extending in a ring shape extend along the surface so as to multiplexly surround the device region 20 .

[0031] like Figure 2As shown, a gap is provided between the innermost deep guard ring 42a and the deep protrusion 34b of the body region 34. A drift region 36 is located in this gap. The deep guard rings 42a to 42d are separated from the body region 34 by the drift region 36. Hereinafter, a portion of the drift region 36 located in the gap between the deep guard ring 42a and the deep protrusion 34b will be referred to as the deep gap region 52a. A drift region 36 is located in the gap between the deep guard rings 42a to 42d. The deep guard rings 42a to 42d are separated from each other by the drift region 36. Hereinafter, a portion of the drift region 36 located in the gap between the deep guard ring 42a and the deep guard ring 42b, the gap between the deep guard ring 42b and the deep guard ring 42c, and the gap between the deep guard ring 42c and the deep guard ring 42d will be referred to as the deep gap regions 52b, 52c, and 52d, respectively. The deep spacing region 52a is located directly below the surface protrusion 34a. The deep spacing regions 52b to 52d are located directly below the surface protection rings 40a to 40c. Specifically, when viewing the semiconductor substrate 12 from above, the deep spacing region 52a is located so as to overlap with the surface protrusion 34a, the deep spacing region 52b is located so as to overlap with the surface protection ring 40a, the deep spacing region 52c is located so as to overlap with the surface protection ring 40b, and the deep spacing region 52d is located so as to overlap with the surface protection ring 40c.

[0032] Hereinafter, the surface protrusion 34a of the body region 34 and the surface guard rings 40a to 40d may be collectively referred to as a surface withstand voltage region, and the deep protrusion 34b of the body region 34 and the deep guard rings 42a to 42d may be collectively referred to as a deep withstand voltage region.

[0033] Hereinafter, the surface pressure-resistant region adjacent to the inner circumference of the target deep protection ring (any of deep protection rings 42a to 42d) may be referred to as the inner circumference surface pressure-resistant region, and the surface pressure-resistant region adjacent to the outer circumference of the target deep protection ring may be referred to as the outer circumference surface pressure-resistant region. For example, for deep protection ring 42a, surface protrusion 34a is the inner circumference surface pressure-resistant region, and surface protection ring 40a is the outer circumference surface pressure-resistant region. Furthermore, for example, for deep protection ring 42b, surface protection ring 40a is the inner circumference surface pressure-resistant region, and surface protection ring 40b is the outer circumference surface pressure-resistant region.

[0034] Each deep protection ring 42a to 42d extends from a position directly below the inner surface pressure-resistant region to a position directly below the outer surface pressure-resistant region. For example, deep protection ring 42a extends from a position directly below surface protrusion 34a to a position directly below surface protection ring 40a. In other words, the inner end of deep protection ring 42a is located directly below surface protrusion 34a, and the outer end of deep protection ring 42a is located directly below surface protection ring 40a. Furthermore, for example, deep protection ring 42b extends from a position directly below surface protection ring 40a to a position directly below surface protection ring 40b. In other words, the inner end of deep protection ring 42b is located directly below surface protection ring 40a, and the outer end of deep protection ring 42b is located directly below surface protection ring 40b.

[0035] exist Figure 2 In the symbol Nv(m －3 ) represents the n-type impurity concentration in the middle region 54. Also, symbol Ns(m －3 ) represents the n-type impurity concentration in the drift region 36 above the intermediate region 54. That is, symbol Ns represents the n-type impurity concentration in each surface spacing region 50a to 50d. Symbol Nd (m －3 ) represents the n-type impurity concentration within the drift region 36 below the intermediate region 54. Specifically, the symbol Nd represents the n-type impurity concentration within each of the deep spacing regions 52a to 52d. In Example 1, the n-type impurity concentration is constant throughout the drift region 36. That is, in Example 1, Ns = Nv = Nd.

[0036] The deep guard rings 42 a to 42 d are arranged so as to satisfy the relationship of the following mathematical formula 2.

[0037] Nv(Wv1+Wv2) 2 <Ns·Ws 2 ···(Mathematical formula 2)

[0038] In Equation 2, Wv1(m) represents the width of the gap between the target deep guard ring and the inner surface pressure-resistant region. Wv2(m) represents the width of the gap between the target deep guard ring and the outer surface pressure-resistant region. Ws(m) represents the width of the gap between the inner and outer surface pressure-resistant regions of the target deep guard ring. Widths Wv1 and Wv2 represent the dimensions in the thickness direction of the semiconductor substrate 12, while width Ws represents the dimension in the lateral direction (from the inner circumference toward the outer circumference) of the semiconductor substrate 12.

[0039] For example, in the case where the target deep guard ring is the deep guard ring 42a, the width Wv1 is the width of the interval between the deep guard ring 42a and the surface protrusion 34a ( Figure 3The width Wv2 is the width of the gap between the deep protection ring 42a and the surface protection ring 40a ( Figure 3 The width Wvb is the width of the gap between the surface protrusion 34a and the surface protection ring 40a ( Figure 3 And, for example, in the case where the target deep guard ring is the deep guard ring 42b, the width Wv1 is the width of the interval between the deep guard ring 42b and the surface guard ring 40a ( Figure 3 The width Wvc is the width of the gap between the deep protection ring 42b and the surface protection ring 40b ( Figure 3 The width Wvd is the width of the gap between the surface protection ring 40a and the surface protection ring 40b ( Figure 3 width Wsb).

[0040] As described above, in Example 1, the n-type impurity concentration in the entire drift region 36 is constant, Nv=Ns. Furthermore, in Example 1, the widths Wv1 and Wv2 are equal to the thickness Wv of the intermediate region 54. Therefore, in Example 1, Equation 2 is equal to Equation 3 below.

[0041] 2Wv<Ws···(Mathematical formula 3)

[0042] The deep guard rings 42 a to 42 d are respectively arranged so as to satisfy Mathematical Formula 3.

[0043] and, Figure 3 The width Wd shown represents the width of the interval between the deep pressure-resistant regions (ie, the width of the deep interval regions 52a to 52d). In Example 1, the surface protection rings 40a to 40d and the deep protection rings 42a to 42d are arranged to satisfy the relationship of the following equation 4.

[0044] Nd·Wd 2 >Ns·Ws 2 ···(Mathematical formula 4)

[0045] As described above, in Example 1, the n-type impurity concentration is constant throughout the drift region 36 , and Nd=Ns. Therefore, in Example 1, Mathematical Formula 4 is equal to the following Mathematical Formula 5.

[0046] Wd>Ws···(Formula 5)

[0047] That is, in Example 1, the width Wd is larger than the width Ws (for example, Figure 3 The width Wsa, Wsb) is wide.

[0048] Next, the development of the depletion layer within the peripheral region 22 when the MOSFET within the element region 20 is turned off will be described. When the MOSFET is turned off, the potential of the lower electrode 18 becomes higher than the potential of the upper electrode 14. Consequently, the depletion layer extends from the body region 34 into the drift region 36. Within the peripheral region 22, the depletion layer extends from the surface protrusion 34a of the body region 34 toward its periphery. At this time, because the width Wva of the gap between the surface protrusion 34a and the deep guard ring 42a is narrower than the width Wsa of the surface gap region 50a, the depletion layer extending from the surface protrusion 34a reaches the deep guard ring 42a before reaching the surface guard ring 40a. Thus, the depletion layer expands from the deep guard ring 42a into the surrounding drift region 36. At this time, because the deep guard ring 42a satisfies the aforementioned equations 2 and 3, the depletion layer extending from the deep guard ring 42a reaches the surface guard ring 40a before directly reaching the surface guard ring 40a. Thus, the depletion layer extending from the surface protrusion 34a first reaches the surface guard ring 40a via the deep guard ring 42a before directly reaching the surface guard ring 40a. Once the depletion layer reaches the surface guard ring 40a, it extends from the surface guard ring 40a toward its periphery. In this case, since the deep guard ring 42b also satisfies the above-mentioned equations 2 and 3, the depletion layer extending from the surface guard ring 40a first reaches the surface guard ring 40b via the deep guard ring 42b before directly reaching the surface guard ring 40b. Similarly, the depletion layer extending from the surface guard ring 40b first reaches the surface guard ring 40c via the deep guard ring 42c before directly reaching the surface guard ring 40c. Similarly, the depletion layer extending from the surface guard ring 40c first reaches the surface guard ring 40d via the deep guard ring 42d before directly reaching the surface guard ring 40d. Thus, the depletion layer extending from the surface protrusion 34a spreads outward through each of the guard rings in the order of guard rings 42a, 40a, 42b, 40b, 42c, 40c, 42d, and 40d. Therefore, when the depletion layer has fully developed in the peripheral region 22, the potential of guard ring 42a is the lowest, and the potentials of the guard rings gradually increase in the order of guard rings 42a, 40a, 42b, 40b, 42c, 40c, 42d, and 40d.

[0049] Figure 4 It represents the potential distribution (equipotential lines) in the peripheral region 22 when the MOSFET is turned off. Figure 4As shown, each equipotential line is distributed so as to pass through the depleted drift region 36 and is distributed so as to hardly enter the guard ring. The equipotential line 100a represents the distribution of a potential higher than the body region 34 and lower than the deep guard ring 42a. The equipotential line 100a extends through the deep spacing region 52a and the surface spacing region 50a to the upper surface 12a of the semiconductor substrate 12. The equipotential line 100a extends in an obliquely upward direction toward the outer periphery of the peripheral region 22 as a whole. The equipotential line 100b represents the distribution of a potential higher than the deep guard ring 42a and lower than the surface guard ring 40a. The equipotential line 100b extends in an obliquely upward direction toward the outer periphery and enters the deep spacing region 52b. Since the potential of the equipotential line 100b is lower than that of the surface guard ring 40a, the equipotential line 100b cannot enter the outer periphery of the surface guard ring 40a (i.e., the surface spacing region 50b). Thus, equipotential lines 100b bend within deep spacing region 52b, extend obliquely upward toward the inner periphery, and reach upper surface 12a of semiconductor substrate 12 within surface spacing region 50a. Thus, within outer peripheral region 22, the potential distribution is such that equipotential lines extending obliquely upward toward the outer periphery as a whole, like equipotential lines 100a, and equipotential lines that bend within the deep spacing region, like equipotential lines 100b, are alternately arranged.

[0050] Figure 5 Figure 2 shows the potential distribution within the peripheral region 22 of the semiconductor device of the comparative example. In the semiconductor device of the comparative example, the spacing between the surface guard rings 40a-40d and the deep guard rings 42a-42d (i.e., the thickness Wv of the intermediate region 54) is thicker than that of the semiconductor device of Example 1. The semiconductor device of the comparative example does not satisfy the relationship of Mathematical Formulas 2 and 3. Therefore, in the semiconductor device of the comparative example, the depletion layer extending from the surface protrusion 34a reaches the surface guard ring 40a before reaching the deep guard ring 42a. In other words, the depletion layer extends toward the outer periphery via the surface guard rings 40a, 40b, 40c, and 40d, and the deep guard rings 42a-42d do not contribute to the development of the depletion layer in the surface portion of the semiconductor substrate 12. The deep guard rings 42a-42d merely promote the extension of the depletion layer in the thickness direction of the semiconductor substrate 12. In this case, the potential of the deep guard ring 42a is higher than that of the surface guard ring 40a. Similarly, the potential of the deep guard ring 42b is higher than that of the surface guard ring 40b, the potential of the deep guard ring 42c is higher than that of the surface guard ring 40c, and the potential of the deep guard ring 42d is higher than that of the surface guard ring 40d. Figure 5 As shown in FIG, all equipotential lines extend obliquely upward toward the outer periphery. That is, in the comparative example, the equipotential lines ( Figure 4Thus, the potential distribution in the outer peripheral region is different between Example 1 and the comparative example.

[0051] like Figure 5 As shown, in the semiconductor device of the comparative example, the equipotential lines are densely distributed at the lower end portion (e.g., within range A) of the outer periphery of each surface guard ring 40a to 40d, and the electric field is concentrated in this portion. If the electric field is concentrated near the surface guard ring 40a, hot carriers are generated, and the generated hot carriers are easily injected into the oxide film 16. On the other hand, Figure 4 As shown, in the semiconductor device of Example 1, the equipotential lines are not dense near the surface guard rings 40a to 40d, and the electric field concentration is suppressed. Therefore, hot carriers are difficult to generate near the surface guard rings 40a to 40d. In addition, in the semiconductor device of Example 1, the equipotential lines are dense at the lower end of the deep guard rings 42a to 42d (for example, within the range B), and the electric field is concentrated in this part. Therefore, hot carriers are easily generated near the deep guard rings 42a to 42d. However, since the deep guard rings 42a to 42d are arranged at a position away from the oxide film 16, even if hot carriers are generated near the deep guard rings 42a to 42d, the injection of hot carriers into the oxide film 16 is suppressed. In this way, according to the semiconductor device of Example 1, the injection of hot carriers into the oxide film 16 can be suppressed. Therefore, the situation in which the electric field distribution in the peripheral region 22 is disturbed due to the hot carriers injected into the oxide film 16 can be suppressed. Therefore, the semiconductor device 10 of Example 1 has a high withstand voltage.

[0052] and, Figure 6 The electric field distribution in the surface spacing region 50a is compared in Example 1 and the comparative example. Figure 6In the diagram, the electric field is shown as being positive in the direction from the outer circumference toward the inner circumference. In the comparative example, the entire surface gap region 50a is depleted due to the depletion layer extending from the surface protrusion 34a. Therefore, an electric field is generated in the positive direction throughout the surface gap region 50a. In contrast, in Example 1, the depletion layer extending from the deep guard ring 42a reaches the surface guard ring 40a before the depletion layer extending from the surface protrusion 34a reaches the surface guard ring 40a. Consequently, region 34x near the surface protrusion 34a in the surface gap region 50a is depleted by the surface protrusion 34a, while region 34y near the surface guard ring 40a is depleted by the surface guard ring 40a. Consequently, an electric field is generated in the positive direction in region 34x, while an electric field is generated in the negative direction in region 34y. Due to this generation of electric fields, the maximum value E of the electric field generated in the surface gap region 50a is lower in Example 1 than in the comparative example. Similarly, the maximum value E of the electric field in the surface spacing regions 50b to 50d is also reduced. Thus, according to the structure of Example 1, even if the width of the surface spacing regions 50a to 50d is relatively wide, the electric field generated in the surface spacing regions 50a to 50d can be suppressed. Consequently, the injection of hot carriers into the oxide film 16 is also suppressed.

[0053] Furthermore, as described above, in Example 1, the width Wd of the deep spacing regions 52a-52d is wider than the width Ws of the surface spacing regions 50a-50d. Consequently, a higher electric field is more likely to be generated in the deep spacing regions 52a-52d than in the surface spacing regions 50a-50d. Therefore, hot carriers are more likely to be generated in the deep spacing regions 52a-52d before they are generated in the surface spacing regions 50a-50d. This further suppresses the generation of hot carriers in the surface spacing regions 50a-50d. Consequently, the injection of hot carriers into the oxide film 16 is also suppressed.

[0054] Furthermore, the semiconductor device 10 of Example 1 satisfies the relationship Wv < Ws. As described above, width Ws is the lateral width, and width Wv is the longitudinal width. The minimum processing value of width Ws is determined by the processing accuracy of the manufacturing process for forming the surface guard rings 40a to 40d. The surface guard rings 40a to 40d are formed by ion implantation or selective epitaxial growth. Regardless of the method, width Ws is determined by the mask used in the ion implantation or selective epitaxial growth. Neither method can make width Ws that small. On the other hand, when the surface guard rings 40a to 40d and the deep guard rings 42a to 42d are formed by ion implantation, the minimum processing value of width Wv is determined by the implantation depth. When they are formed by selective epitaxial growth, the minimum processing value of width Wv is determined by the thickness of the intermediate region 54 during epitaxial growth. Regardless of the method, it is easy to make width Wv smaller than width Ws. By making the width Wv smaller than the width Ws in this manner, the semiconductor device 10 satisfying the above-mentioned mathematical expressions 2 and 3 can be easily manufactured.

[0055] (Example 2)

[0056] In Example 2, the n-type impurity concentration Nd in each of the deep spacing regions 52a to 52d is higher than the n-type impurity concentration Ns in each of the surface spacing regions 50a to 50d. The n-type impurity concentration Nv in the intermediate region 54 may be equal to the n-type impurity concentration Nd, equal to the n-type impurity concentration Ns, or have other values. The other structures of the semiconductor device of Example 2 are the same as those of the semiconductor device 10 of Example 1. By satisfying the above-mentioned mathematical formulas 2 and 4, the semiconductor device of Example 2 also suppresses the generation of hot carriers in the surface spacing regions 50a to 50d, similarly to the semiconductor device of Example 1. Furthermore, in the semiconductor device of Example 2, the n-type impurity concentration Nd in each of the deep spacing regions 52a to 52d is higher than the n-type impurity concentration Ns in each of the surface spacing regions 50a to 50d, thereby making it easier to generate a high electric field in the deep spacing regions 52a to 52d. Therefore, hot carriers are more likely to be generated in the deep spacing regions 52a to 52d before they are generated in the surface spacing regions 50a to 50d. This further suppresses the generation of hot carriers in the surface spacing regions 50a to 50d. This also suppresses the injection of hot carriers into the oxide film 16. Consequently, the semiconductor device of Example 2 has a higher withstand voltage.

[0057] As described above, the structures of Examples 1 and 2 can improve the breakdown voltage of the semiconductor device. Furthermore, in the structures of Examples 1 and 2, by increasing the n-type impurity concentration in the drift region 36 compared to conventional ones, the on-resistance of the MOSFET can be reduced while maintaining the same breakdown voltage as conventional ones.

[0058] In the above-described first and second embodiments, a MOSFET is formed in the element region 20. However, other semiconductor devices may be formed in the element region 20. For example, an IGBT (insulated gate bipolar transistor), a pn diode, a Schottky barrier diode, etc. may be formed in the element region 20.

[0059] Furthermore, in the above-described first and second embodiments, all of the deep space regions 52a to 52d satisfy the above-described mathematical formula 2. However, some of the deep space regions 52a to 52d may not satisfy the above-described mathematical formula 2. In other words, it is sufficient that at least one of the deep space regions 52a to 52d satisfies the above-described mathematical formula 2.

[0060] While the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technologies described in the claims include various variations and modifications of the specific examples illustrated above. The technical elements described in this specification or the drawings may exhibit technical utility individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or the drawings may achieve multiple objectives simultaneously, and achieving any one of these objectives may itself be technically useful.

Claims

1. A semiconductor device, characterized in that: have: semiconductor substrates; an upper electrode in contact with the upper surface of the semiconductor substrate; a lower electrode in contact with the lower surface of the semiconductor substrate; and an oxide film in contact with the upper surface of the semiconductor substrate, The semiconductor substrate includes a device region and a peripheral region, wherein the upper electrode is in contact with the upper surface of the semiconductor substrate in the device region, and the oxide film is in contact with the upper surface of the semiconductor substrate in the peripheral region. The peripheral region is located between the element region and the peripheral end surface of the semiconductor substrate. The device region has a semiconductor device connected between the upper electrode and the lower electrode. The outer peripheral region includes a plurality of p-type surface withstand voltage regions, a plurality of p-type deep withstand voltage regions, and an n-type drift region. The plurality of surface pressure-resistant regions are in contact with the oxide film. The plurality of surface pressure-resistant regions are arranged at intervals from the inner circumference toward the outer circumference. The plurality of deep pressure-resistant regions are arranged below the plurality of surface pressure-resistant regions. The plurality of deep pressure-resistant regions are arranged at intervals from the inner circumference toward the outer circumference. The drift region separates the plurality of surface pressure-resistant regions from the plurality of deep pressure-resistant regions, separates the surface pressure-resistant regions from each other, and separates the deep pressure-resistant regions from each other. When the drift region located in the gap between the surface pressure-resistant regions is defined as the surface gap region, and the drift region located in the gap between the deep pressure-resistant regions is defined as the deep gap region, the deep pressure-resistant regions are located directly below the surface gap regions, and the deep gap regions are located directly below the surface pressure-resistant regions. Each of the deep pressure-resistant regions extends from a position directly below the surface pressure-resistant region adjacent to the region on the inner circumference to a position directly below the surface pressure-resistant region adjacent to the region on the outer circumference. One of the plurality of deep pressure-resistant regions is set as a specific deep pressure-resistant region, the surface pressure-resistant region adjacent to the specific deep pressure-resistant region on the inner circumference is set as an inner circumference surface pressure-resistant region, the surface pressure-resistant region adjacent to the specific deep pressure-resistant region on the outer circumference is set as an outer circumference surface pressure-resistant region, the width of the interval between the inner circumference surface pressure-resistant region and the outer circumference surface pressure-resistant region is set as Ws (m), the n-type impurity concentration of the surface interval region between the inner circumference surface pressure-resistant region and the outer circumference surface pressure-resistant region is set as Ns (m －3 ), the n-type impurity concentration of the drift region within the depth range between the plurality of surface withstand voltage regions and the plurality of deep withstand voltage regions is set to Nv(m －3 ), the width of the interval between the inner circumference side surface pressure-resistant region and the specific deep pressure-resistant region is set as Wv1(m), and the width of the interval between the outer circumference side surface pressure-resistant region and the specific deep pressure-resistant region is set as Wv2(m), Satisfy Nv(Wv1+Wv2) 2 <Ns·Ws 2 relationship.

2. The semiconductor device according to claim 1, wherein The width Wv1 is smaller than the width Ws. The width Wv2 is smaller than the width Ws.

3. The semiconductor device according to claim 1, wherein The n-type impurity concentration of each of the deep spacer regions is higher than the n-type impurity concentration of each of the surface spacer regions.

4. The semiconductor device according to any one of claims 1 to 3, wherein The width of the interval between the deep voltage-resistant regions is denoted as Wd(m), and the n-type impurity concentration of each deep interval region is denoted as Nd(m －3 ), satisfying Nd·Wd 2 >Ns·Ws 2 relationship.

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