Array substrate, display panel and display device

Abstract

The present invention provides an array substrate, a display panel, and a display device. A shift register includes multiple thin-film transistors, including a setting thin-film transistor. The setting thin-film transistor includes a semiconductor layer, a gate, a source, a drain, and a shielding metal layer. The shielding metal layer overlaps the semiconductor layer in a direction perpendicular to the substrate. A first constant voltage line provides a first constant voltage with a voltage value less than 0V, and a second constant voltage line provides a second constant voltage with a voltage value greater than 0V. The thin-film transistor is set as an N-type transistor, and the shielding metal layer is electrically connected to the first constant voltage line; alternatively, the thin-film transistor is set as a P-type transistor, and the shielding metal layer is electrically connected to the second constant voltage line. The present invention provides an array substrate, a display panel, and a display device. The shielding metal layer corrects a shifted threshold voltage to a normal range, thereby preventing abnormal activation of the setting thin-film transistor, thereby improving the operational stability of the array substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of science and technology and the progress of society, people's dependence on the exchange and transmission of information is increasing. Display devices, as the main carrier and material basis for information exchange and transmission, have now become a hot topic of research for many scientists.

[0003] Thin film transistors (TFTs) are widely used as switching elements in display panels (eg, liquid crystal panels or organic light emitting display panels). Therefore, an array substrate formed with thin film transistors is a basic element of a display panel constructed for a display device.

[0004] However, there is a risk that the thin film transistors in the display driving circuit of the array substrate may be abnormally turned on. Summary of the Invention

[0005] The present invention provides an array substrate, a display panel and a display device, which correct a shifted threshold voltage to a normal range through a shielding metal layer, avoid abnormal opening of a set thin film transistor, and thus improve the working stability of the array substrate.

[0006] In a first aspect, an embodiment of the present invention provides an array substrate, comprising a display area and a non-display area, wherein the non-display area is located outside the display area;

[0007] substrate;

[0008] A display driving circuit is located in a non-display area on one side of the substrate, and includes a plurality of cascaded shift registers, a first constant voltage line, and a second constant voltage line;

[0009] The shift register includes a plurality of thin film transistors, wherein the thin film transistors include a setting thin film transistor, and the setting thin film transistor includes a semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a shielding metal layer; in a direction perpendicular to the substrate, the shielding metal layer overlaps the semiconductor layer;

[0010] The first constant voltage line provides a first constant voltage with a voltage value less than 0V, and the second constant voltage line provides a second constant voltage with a voltage value greater than 0V;

[0011] The thin film transistor is set to be an N-type transistor, and the shielding metal layer is electrically connected to the first constant voltage line; or the thin film transistor is set to be a P-type transistor, and the shielding metal layer is electrically connected to the second constant voltage line.

[0012] In a second aspect, an embodiment of the present invention provides a display panel, comprising the array substrate described in the first aspect.

[0013] In a third aspect, an embodiment of the present invention provides a display device comprising the display panel described in the second aspect.

[0014] An embodiment of the present invention provides an array substrate, comprising a display driver circuit, the display driver circuit including a shift register, a first constant voltage line, and a second constant voltage line. At least some of the thin-film transistors in the shift register are set thin-film transistors. The set thin-film transistors include a shielding metal layer overlapping a semiconductor layer. For N-type transistors, the shielding metal layer overlaps with the first constant voltage line, and for P-type transistors, the shielding metal layer overlaps with the second constant voltage line. The shielding metal layer corrects a shifted threshold voltage to a normal range, preventing abnormal activation of the set thin-film transistors and thereby improving the operational stability of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic top view of an array substrate provided by an embodiment of the present invention;

[0016] Figure 2 A schematic structural diagram of a display driving circuit provided by an embodiment of the present invention;

[0017] Figure 3 A schematic cross-sectional view of a shift register provided by an embodiment of the present invention;

[0018] Figure 4 A schematic structural diagram of another display driving circuit provided by an embodiment of the present invention;

[0019] Figure 5 A schematic diagram of the circuit structure of a shift register provided by an embodiment of the present invention;

[0020] Figure 6 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0021] Figure 7 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0022] Figure 8 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0023] Figure 9 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided.

[0024] Figure 10 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0025] Figure 11 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0026] Figure 12 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention;

[0027] Figure 13 A schematic cross-sectional view of another shift register provided by an embodiment of the present invention;

[0028] Figure 14 A schematic cross-sectional view of a display panel provided by an embodiment of the present invention;

[0029] Figure 15 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0031] Research has found that for thin-film transistors that remain in the off state for a long time, their threshold voltage will deviate, causing abnormal turn-on. For N-type transistors, the threshold voltage will shift to a negative bias, for example, changing the original 2V threshold voltage to 1.5V, making it easier for abnormal turn-on. For P-type transistors, the threshold voltage will shift to a positive bias, for example, changing the original -2V threshold voltage to -1.5V, making it easier for abnormal turn-on.

[0032] Figure 1 A schematic top view of an array substrate provided in an embodiment of the present invention is shown. Figure 2 A schematic structural diagram of a display driving circuit provided by an embodiment of the present invention is shown. Figure 3 A schematic cross-sectional view of a shift register provided by an embodiment of the present invention is provided. Figure 4 A schematic diagram of another display driving circuit according to an embodiment of the present invention is provided. Figures 1-4 The array substrate includes a display area 01 and a non-display area 02 , and the non-display area 02 is located outside the display area 01 .

[0033] The array substrate includes a substrate 43 and a display driver circuit 10. The display driver circuit 10 is located in a non-display area 02 on one side of the substrate 43. The display driver circuit 10 is used to provide a switch control signal to the pixel unit 20 in the display area 01. The pixel unit 20 may include a pixel driver circuit and a light-emitting unit. The display driver circuit 10 is used to provide a switch control signal to the pixel driver circuit so that the pixel driver circuit drives the light-emitting unit to emit light under preset timing control. The switch control signal may include, for example, a scan signal (i.e., a scan signal) and a light-emitting control signal (i.e., an emit signal).

[0034] The display driving circuit 10 includes a plurality of cascaded shift registers 40, a first constant voltage line 11, and a second constant voltage line 12. The shift register 40 includes a plurality of thin film transistors 41 ( Figure 2 and Figure 3 , each of the thin film transistors 41 in the shift register 40 is schematically shown. The thin film transistors 41 include setting thin film transistors 410. That is, at least a portion of the thin film transistors 41 in the shift register 40 are setting thin film transistors 410. In one embodiment, all thin film transistors 41 in the shift register 40 are setting thin film transistors 410. In another embodiment, a portion of the thin film transistors 41 in the shift register 40 are setting thin film transistors 410, while another portion of the thin film transistors 41 in the shift register 40 are not setting thin film transistors 410.

[0035] The setting thin film transistor 410 includes a semiconductor layer 411, a gate 412, a source 413, a drain 414, and a shielding metal layer 415. The shielding metal layer 415 overlaps the semiconductor layer 411 perpendicular to the substrate 43. The voltage on the shielding metal layer 415 affects the width of the conductive channel in the semiconductor layer 411, thereby affecting the threshold voltage of the setting thin film transistor 410. The threshold voltage is the voltage that turns the thin film transistor 41 (including the setting thin film transistor 410) on or off.

[0036] like Figure 2 As shown, thin-film transistor 410 is configured as an N-type transistor, and shielding metal layer 415 is electrically connected to first constant voltage line 11. First constant voltage line 11 provides a first constant voltage less than 0V. Shielding metal layer 415, which provides the first constant voltage, pulls the threshold voltage of thin-film transistor 410 to a positive level. For example, if the threshold voltage of thin-film transistor 410 is negatively shifted, the original threshold voltage of 2V will shift negatively to 1.5V. Because shielding metal layer 415 is less than the first constant voltage of 0V, the 1.5V threshold voltage is pulled positive to 2V, correcting it to the normal threshold voltage, thereby preventing the thin-film transistor 410 from turning on abnormally.

[0037] like Figure 4 As shown, thin-film transistor 410 is configured as a P-type transistor, and shielding metal layer 415 is electrically connected to second constant voltage line 12. Second constant voltage line 12 provides a second constant voltage greater than 0V. Shielding metal layer 415, which provides the second constant voltage, pulls the threshold voltage of thin-film transistor 410 negative. For example, if the threshold voltage of thin-film transistor 410 undergoes a positive shift, the original -2V threshold voltage will shift positively to -1.5V. Because shielding metal layer 415 is greater than the second constant voltage of 0V, the -1.5V threshold voltage is pulled negative to -2V, correcting it to the normal threshold voltage, thereby preventing abnormal activation of thin-film transistor 410.

[0038] An embodiment of the present invention provides an array substrate, comprising a display driver circuit 10, wherein the display driver circuit 10 includes a shift register 40, a first constant voltage line 11, and a second constant voltage line 12. At least some of the thin film transistors 41 in the shift register 40 are setting thin film transistors 410. The setting thin film transistors 410 include a shielding metal layer 415 overlapping with a semiconductor layer 411. For N-type transistors, the shielding metal layer 415 overlaps with the first constant voltage line 11, and for P-type transistors, the shielding metal layer 415 overlaps with the second constant voltage line 12. Thus, the shielding metal layer 415 corrects a shifted threshold voltage to a normal range, preventing abnormal activation of the setting thin film transistors 410, thereby improving the operational stability of the array substrate.

[0039] It should be further explained that because the display driver circuit 10 in the non-display area 02 is used to provide the switch control signal, the off-time of the display driver circuit 10 in the off state for a long period of time must be much longer than the enable level time of the switch control signal. For example, it is much longer than the on-time of the scan signal. In this embodiment of the present invention, the method of providing a shielding metal layer 415 and providing a voltage to the shielding metal layer 415 is applicable to the display driver circuit 10 in the non-display area 02.

[0040] It should be further explained that when the shielding metal layer 415 is electrically connected to the first constant voltage line 11 or the second constant voltage line 12, the shielding metal layer 415 receives the first constant voltage or the second constant voltage, and the voltage value on the shielding metal layer 415 does not change, and will not cause the threshold voltage of the thin film transistor 410 to change, which is beneficial to improving the circuit stability of the shift register 40, improving the circuit stability of the display driving circuit 10, and improving the working stability of the array substrate.

[0041] The present invention further describes the configuration of the setting thin film transistor 410 in the shift register 40 using a P-type transistor as an example. However, the present invention is not limited to this. At least one setting thin film transistor 410 in the shift register 40 may also be an N-type transistor. For a P-type transistor, its off-voltage is a high voltage and its on-voltage is a low voltage. For an N-type transistor, its off-voltage is a low voltage and its on-voltage is a high voltage.

[0042] Figure 5 A schematic diagram of a circuit structure of a shift register provided by an embodiment of the present invention is provided. Figure 5 , the shift register 40 includes a pull-down unit 51. The pull-down unit 51 is electrically connected to the first voltage terminal VGL, the first node N1 and the cascade signal output terminal OUT. The pull-down unit 51 is used to transmit the signal input from the first voltage terminal VGL to the cascade signal output terminal OUT under the control of the first node N1. The first voltage terminal VGL provides a low-level constant voltage. The first node N1 serves as a control node of the pull-down unit 51, controlling the pull-down unit 51 to be in an off state for a long time. The time the pull-down unit 51 is on is shorter than the time the pull-down unit 51 is off. The time the pull-down unit 51 is on is shorter, and the time the pull-down unit 51 is off is longer. The thin film transistor 41 in the pull-down unit 51 is in an off state for a long time. Therefore, at least one thin film transistor 41 in the pull-down unit 51 is set as a setting thin film transistor 410.

[0043] Figure 6 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 6 The pull-down unit 51 includes a tenth transistor M10. A first terminal of the tenth transistor M10 is electrically connected to the first voltage terminal CGL, a second terminal of the tenth transistor M10 is electrically connected to the cascade signal output terminal OUT, and a gate of the tenth transistor M10 is electrically connected to the first node N1. The first node N1 controls the tenth transistor M10 to be in an off state for a long period of time, thereby configuring the tenth transistor M10 as the setting thin film transistor 410.

[0044] Figure 7 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 7The shift register includes a pull-up unit 52 and a pull-up control unit 53. The pull-up unit 52 is electrically connected to the second voltage terminal VGH, the second node N2, and the cascade signal output terminal OUT. The pull-up unit 52 is configured to transmit a signal input from the second voltage terminal VGH to the cascade signal output terminal OUT under the control of the second node N2. The second voltage terminal VGH provides a high-level constant voltage. The pull-up control unit 53 is electrically connected to the second voltage terminal VGH, the first clock signal input terminal CK, the second clock signal input terminal XCK, the first node N1, and the second node N2. The pull-up control unit 53 is configured to transmit a signal from the second voltage terminal VGH or the second clock signal input terminal XCK to the second node N2 under the control of the first node N1 and the second clock signal input terminal XCK. Since the first node N1 serves as the control node of the pull-up control unit 53, the thin film transistors in the pull-up control unit 53 are in the off state for a long time. Therefore, at least one thin film transistor 41 in the pull-up control unit 53 is configured as a setting thin film transistor 410.

[0045] Optionally, refer to Figure 7 The pull-up control unit 53 includes a sixth transistor M6. A first terminal of the sixth transistor M6 is electrically connected to the second voltage terminal VGH, a second terminal of the sixth transistor M6 is electrically connected to the second node N2, and a gate of the sixth transistor M6 is electrically connected to the first node N1. The first node N1 controls the sixth transistor M6 to be in an off state for a long time, thereby setting the sixth transistor M6 to be the setting thin film transistor 410.

[0046] Figure 8 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 8 The pull-up control unit 53 includes a second transistor M2, a third transistor M3, and a seventh transistor M7. The first end of the second transistor M2 is electrically connected to the first clock signal input terminal CK, the second end of the second transistor M2 is electrically connected to the gate of the third transistor M3, and the gate of the second transistor M2 is electrically connected to the third node N3. The third node N3 has the same voltage timing as the first node N1, that is, the third node N3 and the first node N1 generate rising and falling edges at the same time and produce the same voltage change trend at the same time. In other embodiments, the gate of the second transistor M2 can also be connected to the first node N1. The first end of the third transistor M3 is electrically connected to the first end of the seventh transistor M7, and the second end of the third transistor M3 is electrically connected to the second clock signal input terminal XCK. The gate of the seventh transistor M7 is electrically connected to the second clock signal input terminal XCK, and the second end of the seventh transistor M7 is electrically connected to the second node N2. The first node N1 or the third node N3 controls the second transistor M2 to remain in the off state for a long time, thereby setting the second transistor M2 as the setting thin film transistor 410.

[0047] For example, refer to Figure 8 The gate of the third transistor M3 and the second end of the second transistor M2 are both electrically connected to the fourth node N4. The pull-up control unit 53 includes a third capacitor C3 and a fourth capacitor C4. The first plate of the third capacitor C3 is electrically connected to the fourth node N4, and the second plate of the third capacitor C3 is electrically connected to the first end of the third transistor M3. The first plate of the fourth capacitor C4 is electrically connected to the third node N3, and the second plate of the fourth capacitor C4 is electrically connected to the second voltage terminal VGH.

[0048] Figure 9 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 9 The pull-up control unit 53 further includes a thirteenth transistor M13. A first terminal of the thirteenth transistor M13 is electrically connected to the second voltage terminal VGH, a second terminal of the thirteenth transistor M13 is electrically connected to the first node N1, and a gate of the thirteenth transistor M13 is electrically connected to the power-on signal control terminal Control. The power-on signal control terminal Control turns on the thirteenth transistor M13 during the power-on phase, transmitting the high-level constant voltage provided by the second voltage terminal VGH to the first node N1 to turn off the tenth transistor M10, thereby preventing the tenth transistor M10 from being accidentally turned on during the power-on phase and preventing power-on flickering. The thirteenth transistor M13 is only turned on during the power-on phase and is in the off state during normal operation of the display device, thereby configuring the thirteenth transistor M13 as the setting thin-film transistor 410.

[0049] Figure 10 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 10 The shift register 40 includes a pull-down control unit 54. The pull-down control unit 54 is electrically connected to the first voltage terminal VGL, the second voltage terminal VGH, the first clock signal input terminal CK, the second clock signal input terminal XCK, the cascade signal input terminal IN, and the first node N1. The pull-down control unit 54 is configured to transmit a signal from the second voltage terminal VGH or the cascade signal input terminal IN to the first node N1 under the control of the first clock signal input terminal CK and the second clock signal input terminal XCK. The second voltage terminal VGH provides a high-level constant voltage.

[0050] For example, refer to Figure 10 The pull-up unit 52 includes a ninth transistor M9 and a first capacitor C1. A first terminal of the ninth transistor M9 is electrically connected to the second voltage terminal VGH, a second terminal of the ninth transistor M9 is electrically connected to the cascade signal output terminal OUT, and a gate of the ninth transistor M9 is electrically connected to the second node N2. A first plate of the first capacitor C1 is electrically connected to the second voltage terminal VGH, and a second plate of the first capacitor C1 is electrically connected to the second node N2.

[0051] For example, refer to Figure 10 The pull-down control unit 54 includes a first transistor M1, a fourth transistor M4, a fifth transistor M5, an eighth transistor M8, an eleventh transistor M11, and a second capacitor C2. A first terminal of the eighth transistor M8 is electrically connected to the second voltage terminal VGH, a second terminal of the eighth transistor M8 is electrically connected to the first terminal of the first transistor M1, and a gate of the eighth transistor M8 is electrically connected to the fourth node N4. A second terminal of the first transistor M1 is electrically connected to the first node N1, and a gate of the first transistor M1 is electrically connected to the second clock signal input terminal XCK. A first terminal of the eleventh transistor M11 is electrically connected to the third node N3, a second terminal of the eleventh transistor M11 is electrically connected to the cascade signal input terminal IN, and a gate of the eleventh transistor M11 is electrically connected to the first clock signal input terminal CK. A first terminal of the fifth transistor M5 is electrically connected to the first voltage terminal VGL, a second terminal of the fifth transistor M5 is electrically connected to the fourth node N4, and a control terminal of the fifth transistor M5 is electrically connected to the first clock signal input terminal CK. A first terminal of the fourth transistor M4 is electrically connected to the first node N1, a second terminal of the fourth transistor M4 is electrically connected to the cascade signal input terminal IN, and a gate of the fourth transistor M4 is electrically connected to the first clock signal input terminal CK. A first plate of the second capacitor C2 is electrically connected to the second clock signal input terminal XCK, and a second plate of the second capacitor C2 is electrically connected to the first node N1.

[0052] For example, refer to Figure 10 The gate of the fourth transistor M4 and the gate of the eleventh transistor M11 are both electrically connected to the first clock signal input terminal CK and are simultaneously turned on or off under the control of the first clock signal input terminal CK. Furthermore, when the fourth transistor M4 and the eleventh transistor M11 are turned on, they transmit the signal from the cascade signal input terminal IN to the first node N1 and the third node N3, respectively. As a result, the first node N1 and the third node N3 have the same voltage timing.

[0053] Figure 11 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 11 The pull-down control unit 54 is electrically connected to the first voltage terminal VGL, the second voltage terminal VGH, the first clock signal input terminal CK, the second clock signal input terminal XCK, the cascade signal input terminal IN, and the first node N1. The pull-down control unit 54 is configured to transmit a signal from the second voltage terminal VGH or the cascade signal input terminal IN to the first node N1 under the control of the first clock signal input terminal CK and the second clock signal input terminal XCK. The second voltage terminal VGH provides a high-level constant voltage. The pull-down control unit 54 is electrically connected to the first node N1, thereby configuring at least one thin-film transistor 41 in the pull-down control unit 54 as a setting thin-film transistor 410.

[0054] Figure 12 A schematic diagram of the circuit structure of another shift register provided by an embodiment of the present invention is provided. Figure 12 The pull-down control unit 54 includes a first transistor M1, a fourth transistor M4, a fifth transistor M5, an eighth transistor M8, and a second capacitor C2. A first terminal of the first transistor M1 is electrically connected to the first plate of the second capacitor C2, a second terminal of the first transistor M1 is electrically connected to the second clock signal input terminal XCK, and a gate of the first transistor M1 is electrically connected to the first node N1. A first terminal of the fourth transistor M4 is electrically connected to the first node N1, a second terminal of the fourth transistor M4 is electrically connected to the cascade signal input terminal IN, and a gate of the fourth transistor M4 is electrically connected to the first clock signal input terminal CK. A first terminal of the fifth transistor M5 is electrically connected to the first voltage terminal VGL, a second terminal of the fifth transistor M5 is electrically connected to the fourth node N4, and a control terminal of the fifth transistor M5 is electrically connected to the first clock signal input terminal CK. A first terminal of the eighth transistor M8 is electrically connected to the second voltage terminal VGH, and a second terminal of the eighth transistor M8 is electrically connected to the first terminal of the first transistor M1. A second plate of the second capacitor C2 is electrically connected to the first node N1. The first node N1 controls the first transistor M1 to be in the off state for a long time, thereby setting the first transistor M1 to be the setting thin film transistor 410 .

[0055] For example, refer to Figure 12 The pull-up control unit 53 includes an eleventh transistor M11 and a twelfth transistor M12. The eleventh transistor M11 and the twelfth transistor M12 are both electrically connected to the first voltage terminal VGL. Since the eleventh transistor M11 and the twelfth transistor M12 are both P-type transistors, they are always turned on under the control of the first voltage terminal VGL. Therefore, the voltage of the first node N1 is equal to the voltage of the fifth node N5, and the voltage of the fourth node N4 is equal to the voltage of the sixth node N6.

[0056] Optionally, refer to Figure 2 The first voltage terminal VGL is electrically connected to the first constant voltage line 11, and the low-level constant voltage is equal to the first constant voltage. In other words, the first constant voltage line 11 is used to provide voltage to the first voltage terminal VGL and the shielding metal layer 415. The shielding metal layer 415 is provided with voltage using existing wiring in the display driver circuit 10, reducing the number of signal lines.

[0057] Optionally, refer to Figure 4 The second voltage terminal VGH is electrically connected to the second constant voltage line 12, and the high-level constant voltage is equal to the second constant voltage. In other words, the second constant voltage line 12 is used to provide voltage to the second voltage terminal VGH and the shielding metal layer 415. The existing wiring in the display driver circuit 10 is used to provide voltage to the shielding metal layer 415, reducing the number of signal lines.

[0058] Optionally, refer to Figure 3 In the thin film transistor 410, the semiconductor layer 411 is located between the gate 412 and the shielding metal layer 415. The shielding metal layer 415 is used to reduce the threshold voltage deviation caused by applying a voltage to the gate 412 for a long time.

[0059] For example, refer to Figure 3 The shift register 40 further includes at least one capacitor 42, which may be, for example, a first capacitor C1, a second capacitor C2, a third capacitor C3, or a fourth capacitor C4. A first plate 421 of the capacitor 42 is located on the same layer as the gate 412, and a second plate 422 of the capacitor 42 is located on a side of the first plate 421 away from the substrate 43.

[0060] Figure 13 A cross-sectional view of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 13 The gate 412 is located between the semiconductor layer 411 and the substrate 43, and the shielding metal layer 415 is formed on the same layer as the second plate 422 of the capacitor 42. Thus, the shielding metal layer 415 and the second plate 422 of the capacitor 42 can be formed simultaneously using the same material and in the same process, saving process steps. In other embodiments, the shielding metal layer 415 can also be formed on the same layer as the source 413 and the drain 414, and can be formed simultaneously using the same material and in the same process.

[0061] Optionally, the first constant voltage line 11 and / or the second constant voltage line 12 are co-layered with the shielding metal layer 415, so that the same material can be used and the first constant voltage line 11 and / or the second constant voltage line 12 and the shielding metal layer 415 can be formed simultaneously in the same process, thereby saving process steps. On the other hand, placing the first constant voltage line 11 and the shielding metal layer 415 in the same layer facilitates electrical connection between the first constant voltage line 11 and the shielding metal layer 415. Placing the second constant voltage line 12 in the same layer as the shielding metal layer 415 facilitates electrical connection between the second constant voltage line 12 and the shielding metal layer 415.

[0062] Figure 14 A schematic cross-sectional view of a display panel according to an embodiment of the present invention is provided. Figure 14 The display panel includes the array substrate in the above embodiment. The display panel can be an organic light emitting display panel, a liquid crystal display panel, a quantum dot display panel or a micro light emitting diode display panel.

[0063] Optionally, refer to Figure 14The display panel also includes a pixel driving circuit 61, an anode 621 and a transfer metal layer 63 located in the display area 01. The transfer metal layer 63 is located between the pixel driving circuit 61 and the anode 621, one end of the transfer metal layer 63 is electrically connected to the pixel driving circuit 61, and the other end of the transfer metal layer 63 is electrically connected to the anode 621. The gate 412 is located between the semiconductor layer 411 and the substrate 43, and the shielding metal layer 415 is in the same layer as the transfer metal layer 63, so that the same material can be used and the shielding metal layer 415 and the transfer metal layer 63 can be formed at the same time in the same process, thereby saving process steps. In other embodiments, the shielding metal layer 415 is in the same layer as the anode 621, so that the same material can be used and the shielding metal layer 415 and the anode 621 can be formed at the same time in the same process.

[0064] For example, refer to Figure 14 The display panel may be an organic light-emitting display panel, which includes a light-emitting unit 62. The light-emitting unit 62 includes an anode 621, a light-emitting functional layer 622, and a cathode 623. The light-emitting functional layer 622 is located between the anode 621 and the cathode 623. Electrons and holes are injected from the cathode 623 and the anode 621 into the light-emitting functional layer 622 and recombine to generate excitons. The energy is transferred to the light-emitting molecules in the light-emitting functional layer 622, and the electrons are excited to transition from the ground state to the excited state. The excited state energy is released through radiative transition, thereby generating light.

[0065] Figure 15 A schematic diagram of a display device provided by an embodiment of the present invention, with reference to Figure 15 The display device includes the display panel in the above embodiment. The display device can be one of a mobile phone, a computer, an electronic paper, a car display, a wearable device, etc.

[0066] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that: comprising a display area and a non-display area, wherein the non-display area is located outside the display area; substrate; A display driving circuit is located in a non-display area on one side of the substrate, and includes a plurality of cascaded shift registers, a first constant voltage line, and a second constant voltage line; The shift register includes a plurality of thin film transistors, wherein the thin film transistors include a setting thin film transistor, and the setting thin film transistor includes a semiconductor layer, a gate, a source electrode, a drain electrode, and a shielding metal layer; The shielding metal layer overlaps the semiconductor layer in a direction perpendicular to the substrate; The first constant voltage line provides a first constant voltage with a voltage value less than 0V, and the second constant voltage line provides a second constant voltage with a voltage value greater than 0V; The thin film transistor is set to be an N-type transistor, and the shielding metal layer is electrically connected to the first constant voltage line; Alternatively, the thin film transistor is set to be a P-type transistor, and the shielding metal layer is electrically connected to the second constant voltage line; The shielding metal layer is configured to correct the shifted threshold voltage to a normal range by receiving the first constant voltage or the second constant voltage.

2. The array substrate according to claim 1, wherein: The shift register comprises: a pull-down unit electrically connected to the first voltage terminal, the first node, and the cascade signal output terminal, and configured to transmit a signal input from the first voltage terminal to the cascade signal output terminal under the control of the first node; the first voltage terminal provides a low-level constant voltage; At least one of the thin film transistors in the pull-down unit is the setting thin film transistor.

3. The array substrate according to claim 2, wherein: The pull-down unit includes a tenth transistor, a first terminal of the tenth transistor is electrically connected to the first voltage terminal, a second terminal of the tenth transistor is electrically connected to the cascade signal output terminal, and a gate of the tenth transistor is electrically connected to the first node; The tenth transistor is the setting thin film transistor.

4. The array substrate according to claim 1, wherein: The shift register comprises: a pull-up unit electrically connected to the second voltage terminal, the second node, and the cascade signal output terminal, and configured to transmit a signal input from the second voltage terminal to the cascade signal output terminal under the control of the second node; the second voltage terminal provides a high-level constant voltage; a pull-up control unit, electrically connected to the second voltage terminal, the first clock signal input terminal, the second clock signal input terminal, the first node, and the second node, and configured to transmit a signal from the second voltage terminal or the second clock signal input terminal to the second node under the control of the first node and the second clock signal input terminal; At least one of the thin film transistors in the pull-up control unit is the setting thin film transistor.

5. The array substrate according to claim 4, wherein: The pull-up control unit includes a sixth transistor, a first terminal of the sixth transistor is electrically connected to the second voltage terminal, a second terminal of the sixth transistor is electrically connected to the second node, and a gate of the sixth transistor is electrically connected to the first node; The sixth transistor is the setting thin film transistor.

6. The array substrate according to claim 4, wherein: The pull-up control unit includes a second transistor, a third transistor and a seventh transistor; The first terminal of the second transistor is electrically connected to the first clock signal input terminal, the second terminal of the second transistor is electrically connected to the gate of the third transistor, and the gate of the second transistor is electrically connected to the first node or the third node; the third node and the first node have the same voltage timing; The first end of the third transistor is electrically connected to the first end of the seventh transistor, and the second end of the third transistor is electrically connected to the second clock signal input end; The gate of the seventh transistor is electrically connected to the second clock signal input terminal, and the second terminal of the seventh transistor is electrically connected to the second node; The second transistor is the setting thin film transistor.

7. The array substrate according to claim 6, wherein: The pull-up control unit further includes a thirteenth transistor, a first end of the thirteenth transistor is electrically connected to the second voltage end, a second end of the thirteenth transistor is electrically connected to the first node, and a gate of the thirteenth transistor is electrically connected to a power-on signal control end, and the power-on signal control end turns on the thirteenth transistor in a power-on phase; The thirteenth transistor is the setting thin film transistor.

8. The array substrate according to claim 2, wherein: The shift register comprises: a pull-down control unit, electrically connected to the first voltage terminal, the second voltage terminal, the first clock signal input terminal, the second clock signal input terminal, the cascade signal input terminal, and the first node, and configured to transmit a signal from the second voltage terminal or the cascade signal input terminal to the first node under the control of the first clock signal input terminal and the second clock signal input terminal; the second voltage terminal provides a high-level constant voltage; At least one of the thin film transistors in the pull-down control unit is the setting thin film transistor.

9. The array substrate according to claim 8, wherein: The pull-down control unit includes a first transistor, a fourth transistor, a fifth transistor, an eighth transistor, and a second capacitor, wherein a first terminal of the first transistor is electrically connected to a first plate of the second capacitor, a second terminal of the first transistor is electrically connected to the second clock signal input terminal, and a gate of the first transistor is electrically connected to the first node; A first terminal of the fourth transistor is electrically connected to the first node, a second terminal of the fourth transistor is electrically connected to the cascade signal input terminal, and a gate of the fourth transistor is electrically connected to the first clock signal input terminal; A first terminal of the fifth transistor is electrically connected to the first voltage terminal, a second terminal of the fifth transistor is electrically connected to the gate of the eighth transistor, and a control terminal of the fifth transistor is electrically connected to the first clock signal input terminal; A first terminal of the eighth transistor is electrically connected to the second voltage terminal, and a second terminal of the eighth transistor is electrically connected to the first terminal of the first transistor; The second plate of the second capacitor is electrically connected to the first node; The first transistor is the setting thin film transistor.

10. The array substrate according to claim 2, wherein: The low-level constant voltage is equal to the first constant voltage.

11. The array substrate according to claim 4 or 8, characterized in that: The high-level constant voltage is equal to the second constant voltage.

12. The array substrate according to claim 1, wherein: In the set thin film transistor, the semiconductor layer is located between the gate and the shielding metal layer.

13. The array substrate according to claim 1, wherein: The shift register further comprises at least one capacitor, wherein a first plate of the capacitor is in the same layer as the gate, and a second plate of the capacitor is located on a side of the first plate away from the substrate; The gate is located between the semiconductor layer and the substrate, the shielding metal layer is in the same layer as the source and the drain, or the shielding metal layer is in the same layer as the second electrode.

14. The array substrate according to claim 1, wherein: The first constant voltage line and / or the second constant voltage line is / are in the same layer as the shielding metal layer.

15. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 14.

16. The display panel according to claim 15, wherein: It also includes a pixel driving circuit, an anode and a transfer metal layer located in the display area; The transfer metal layer is located between the pixel driving circuit and the anode, one end of the transfer metal layer is electrically connected to the pixel driving circuit, and the other end of the transfer metal layer is electrically connected to the anode; The gate is located between the semiconductor layer and the substrate, and the shielding metal layer is in the same layer as the transfer metal layer, or the shielding metal layer is in the same layer as the anode.

17. A display device, characterized in that: Including the display panel according to claim 15 or 16.

Images