A fast power control system and method for new energy power plants based on FPGA implementation

Abstract

This invention discloses a fast power control system and method for new energy power plants based on FPGA, belonging to the field of power control technology for energy power plants. The fast power control system for new energy power plants based on FPGA of this invention includes an ARM0 circuit, an ARM1 circuit, an FPGA circuit, an Ethernet module, a MAC circuit, an AD sampling circuit, a power supply circuit, a clock circuit, and a reset circuit, resulting in fast communication speed and high control efficiency. Simultaneously, the ARM0 circuit of this invention can deploy control schemes in real time, and performs communication message packaging and unpacking based on the FPGA circuit, followed by network reading and writing through the MAC circuit. This effectively reduces network latency in control command transmission, improves frequency and voltage regulation effects, and maximizes the power control effect of new energy power plants. Furthermore, the FPGA circuit of this invention can perform fast data packaging and unpacking of control messages according to the GOOSE message specification, thereby effectively improving the stability and reliability of the power plant system operation.

Description

TECHNICAL FIELD

[0001] The application relates to a new energy station power fast control system and method based on FPGA implementation, and belongs to the technical field of energy station power control. BACKGROUND

[0002] At present, the power grid new energy develops rapidly, the installed capacity is larger and larger, and the starting proportion of conventional water and fire power units with rotational inertia is gradually reduced, but the new energy does not have the ability of fast frequency response, and the structural difficulties of the power grid frequency control characteristics are increasingly obvious. Based on this, the frequency and voltage response popularization and application work of the new energy station is a major measure to ensure the safe and stable operation of the large power grid under the condition of high proportion of new energy, and has important significance for promoting the sustainable and healthy development of new energy.

[0003] A new energy station fast power control method and system are disclosed in a Chinese patent (publication number: CN 112803490 A), which includes five steps of station setting, system networking, station system prefabrication, power management and power adjustment. The system includes a network interface, a memory and a processor. The network interface is used for receiving and sending signals in the process of transmitting information with other external network elements. The memory is used for storing computer programs that can run on the processor. The processor is used to execute the steps of the method of new energy station fast power control when running the computer programs.

[0004] However, the frequency and voltage adjustment of the above-mentioned scheme and the existing scheme is completed by transmitting control instructions through a relatively complex network topology, and the network delay occupies a large part in the transmission of the control command, resulting in unsatisfactory frequency and voltage adjustment effect. SUMMARY

[0005] In view of the defects of the prior art, the purpose of the application is to provide a new energy station power fast control system based on FPGA implementation, which sets ARM0 circuit, ARM1 circuit, FPGA circuit, Ethernet module and MAC circuit, effectively improves communication speed and control efficiency, and utilizes the ARM0 circuit to deploy the control scheme in real time, and performs communication message packaging and unpacking based on the FPGA circuit, and then performs network reading and writing through the MAC circuit, so that the network delay in the transmission of the control command is effectively reduced, the frequency and voltage adjustment effect is improved, and the power control effect of the new energy station is maximized.

[0006] The second objective of this invention is to provide a fast power control system for new energy power plants based on FPGA, which includes an ARM0 circuit, an ARM1 circuit, an FPGA circuit, an Ethernet module, a MAC circuit, an AD sampling circuit, a power supply circuit, a clock circuit, and a reset circuit. This system features fast sampling and communication speeds, high control efficiency, and the ability to deploy control schemes instantly via the ARM0 circuit. Furthermore, it utilizes the FPGA circuit to perform grid connection point signal sampling and calculation, communication message packaging and unpacking, and network reading and writing via the MAC circuit, thereby maximizing the power control effect of new energy power plants.

[0007] The third objective of this invention is to provide a fast power control method for new energy power plants based on FPGA, which can deploy control schemes in real time according to power control commands, and realize the packaging and unpacking of communication messages based on FPGA circuits, effectively reducing network latency in the transmission of control commands, improving frequency and voltage regulation effects, and maximizing the power control effect of new energy power plants.

[0008] To achieve one of the above objectives, the first technical solution of the present invention is as follows:

[0009] A fast power control system for new energy power plants based on FPGA implementation.

[0010] This includes ARM0 circuits, ARM1 circuits, FPGA circuits, Ethernet modules, and MAC circuits.

[0011] The ARM0 circuit is used to deploy the control scheme of the power fast control system, and to obtain the control algorithm and control logic.

[0012] The ARM1 circuit is used to execute control algorithms and control logic, and generate control data;

[0013] The FPGA circuit is used to package and / or unpack control data according to the message specification to obtain packaged data and / or unpacked data.

[0014] The MAC circuit is used to read and write packaged data and / or unpack data;

[0015] The Ethernet module is used to connect with the dispatch master station and / or AGC / AVC master station, receive power control commands from the dispatch master station and / or AGC / AVC master station to the new energy power station in real time, and report the power station voltage and / or frequency and / or active power and / or reactive power and / or power station execution status information to the dispatch master station and / or AGC / AVC master station.

[0016] The ARM0 circuit is connected to the Ethernet module circuit;

[0017] The ARM1 is connected to the ARM0 circuit and the FPGA circuit respectively;

[0018] The FPGA circuit is connected to the MAC circuit.

[0019] Through continuous exploration and experimentation, this invention incorporates an ARM0 circuit, an ARM1 circuit, an FPGA circuit, an Ethernet module, and a MAC circuit, resulting in high communication speed and control efficiency. Furthermore, the ARM0 circuit allows for real-time deployment of control schemes, and the FPGA circuit handles message packaging and unpacking, while the MAC circuit enables network read / write operations. This effectively reduces network latency in control command transmission, improves frequency and voltage regulation, and ultimately maximizes the power control performance of new energy power plants.

[0020] Furthermore, the FPGA circuit of this invention can quickly pack and unpack control messages according to the GOOSE message specification, reducing the processing burden of ARM1 on reading and parsing control messages, and reducing the waiting time of process scheduling during ARM1 task scheduling. This allows the processing delay of message parsing and reading / writing to be controlled within 1 millisecond, thereby effectively improving the stability and reliability of the field system operation.

[0021] Furthermore, the FPGA circuit of this invention relies on hardware to implement its functions, and its speed is comparable to that of dedicated chips, resulting in better control speed and thus effectively improving the power control effect of new energy power plants.

[0022] As a preferred technical measure:

[0023] The ARM0 circuit uses a trimmed Linux operating system and is modularly configured based on a distributed real-time data bus. It is equipped with a communication protocol stack and a management strategy module.

[0024] The ARM1 circuit is configured using the lightweight embedded real-time operating system FreeOS, and it is woken up by the policy management service unit of the ARM0 circuit.

[0025] The FPGA circuit performs Fourier transform calculations on the control data and manages the reading and writing of the MAC circuit.

[0026] As a preferred technical measure:

[0027] The communication protocol stack and management strategy module adopt a plug-and-play component-based structure, which includes a process management service unit, a data bus service unit, a remote communication service unit, a setpoint management service unit, a test management service unit, a strategy management service unit, and a human-computer interaction unit.

[0028] As a preferred technical measure:

[0029] The process management service unit is used to manage all processes running on the ARM0 circuit, including determining the activity status of processes, running daemons, calculating process resource usage, and optimizing the allocation of process running resources.

[0030] The data bus service unit is used to provide real-time data and interaction interfaces based on a unified information model for the remote communication service unit, the setting management service unit, the test management service unit, and the policy management service unit.

[0031] The remote communication service unit is used to read and write remote communication data from the Ethernet module, call the communication protocol stack and management strategy module to unpack or encapsulate the protocol data, perform bidirectional mapping processing on the communication protocol stack data to the unified information model, and call the data bus service unit interface to read and write the data bus.

[0032] The setpoint management service unit is used to manage all setpoint information of the power fast control system and to detect and verify the pressure plate status corresponding to the setpoint.

[0033] The test management service unit is used to provide the system with test plan loading, execution, statistics and reporting functions, which facilitates the system to conduct simulation tests and online tests;

[0034] The strategy management service unit provides strategy selection, loading, execution, and deployment / deployment functions. The strategies are implemented in a dynamic library, supporting online dynamic loading of strategies, thereby improving the scalability and adaptability of system strategy execution and greatly reducing the workload of code refactoring.

[0035] The human-computer interaction unit provides a human-computer interaction interface for each service unit module.

[0036] As a preferred technical measure:

[0037] It also includes an AD sampling circuit, a power supply circuit, a clock circuit, and a reset circuit;

[0038] The AD sampling circuit is used to quickly acquire the voltage and frequency signals of the grid connection point;

[0039] The power supply circuit is used to provide electrical energy;

[0040] The clock reset circuit is used for time control and circuit recovery.

[0041] To achieve one of the above objectives, the second technical solution of the present invention is as follows:

[0042] A fast power control system for new energy power plants based on FPGA includes an ARM0 circuit, an ARM1 circuit, an FPGA circuit, an Ethernet module, a MAC circuit, an AD sampling circuit, a power supply circuit, a clock circuit, and a reset circuit.

[0043] The ARM0 circuit is used to deploy the control scheme of the power fast control system, and to obtain the control algorithm and control logic.

[0044] The ARM1 circuit is used to execute control algorithms and control logic, and generate control data;

[0045] The FPGA circuit is used to package and / or unpack control data according to the message specification to obtain packaged data and / or unpacked data.

[0046] The MAC circuit is used to read and write packaged data and / or unpack data;

[0047] The AD sampling circuit is used to quickly acquire the voltage and frequency signals of the grid connection point;

[0048] The Ethernet module is used to connect with the dispatch master station and / or AGC / AVC master station, receive power control commands from the dispatch master station and / or AGC / AVC master station to the new energy power station in real time, and report the power station voltage and / or frequency and / or active power and / or reactive power and / or power station execution status information to the dispatch master station and / or AGC / AVC master station.

[0049] The power supply circuit is used to provide electrical energy;

[0050] The clock reset circuit is used for time control and circuit recovery;

[0051] The ARM0 circuit is connected to the Ethernet module circuit;

[0052] ARM1 connects the ARM0 circuit and the FPGA circuit;

[0053] The clock reset circuit connects the ARM0 circuit, the ARM1 circuit, and the FPGA circuit.

[0054] The FPGA circuit connects to the MAC circuit and the AD sampling circuit;

[0055] The ARM0 circuit, ARM1 circuit, FPGA circuit, Ethernet module, MAC circuit, AD sampling circuit, power supply circuit, clock circuit, and reset circuit are all connected to the power supply circuit.

[0056] Through continuous exploration and experimentation, this invention incorporates an ARM0 circuit, an ARM1 circuit, an FPGA circuit, an Ethernet module, a MAC circuit, an AD sampling circuit, a power supply circuit, a clock circuit, and a reset circuit. This results in advantages such as fast sampling and communication speeds, high control efficiency, and the ability to deploy control schemes in real-time via the ARM0 circuit. Furthermore, this invention utilizes the FPGA circuit for packet packaging and unpacking, and the MAC circuit for network reading and writing, effectively reducing network latency in control command transmission, improving frequency and voltage regulation, and ultimately maximizing the power control performance of new energy power plants.

[0057] Furthermore, the FPGA circuit of this invention can quickly pack and unpack control messages according to the GOOSE message specification, reducing the processing burden of ARM1 on reading and parsing control messages, and reducing the waiting time of process scheduling during ARM1 task scheduling. This allows the processing delay of message parsing and reading / writing to be controlled within 1 millisecond, thereby effectively improving the stability and reliability of the field system operation.

[0058] Furthermore, the FPGA circuit of this invention relies on hardware to implement its functions, and its speed is comparable to that of dedicated chips, resulting in better control speed and thus effectively improving the power control effect of new energy power plants.

[0059] To achieve one of the above objectives, the third technical solution of the present invention is as follows:

[0060] A method for rapid power control of new energy power plants based on FPGA is provided, which applies the aforementioned rapid power control system for new energy power plants based on FPGA.

[0061] Includes the following steps:

[0062] The first step is to obtain power control commands from the dispatch master station and / or AGC / AVC master station to the new energy power plant;

[0063] The second step is to deploy a control scheme based on the power control instructions from the first step, and obtain the control algorithm and control logic.

[0064] The third step is to execute the control algorithm and control logic from the second step to generate control data.

[0065] The fourth step is to use the FPGA circuit to pack and / or unpack the control data from the third step according to the message specification, so as to obtain the packed data and / or unpacked data.

[0066] The fifth step is to send the packaged data and / or unpacked data from the fourth step to the device to be controlled in the new energy power station, so as to realize the rapid control of the power of the new energy power station.

[0067] This invention can deploy control schemes in real time according to power control commands, and realize the packaging and unpacking of communication messages based on FPGA circuits. It can effectively reduce network latency in the transmission of control commands, improve frequency and voltage regulation effects, and achieve the goal of maximizing the power control effect of new energy power plants.

[0068] As a preferred technical measure:

[0069] The power control commands include active power control commands, reactive power control commands, and interlocking control commands.

[0070] The active power control commands are divided into limit control commands, setpoint control commands, differential control commands, and primary frequency regulation control commands.

[0071] The reactive power control commands are divided into constant reactive power control commands, constant power factor control commands, constant voltage control commands, and reactive voltage droop control commands.

[0072] The constant power factor control command takes the reactive power of the photovoltaic power station as the control target, and its target value is calculated and obtained based on the measured value of the active power of the photovoltaic power station and the set value of the power factor.

[0073] When the grid connection point voltage is lower than the set low voltage blocking threshold, the power control command will be stopped immediately.

[0074] When the grid connection point voltage recovers to above the low voltage blocking threshold and the duration exceeds the set delay, the active power control command and reactive power control command will resume to be sent.

[0075] The lockout recovery delay time can be set according to requirements.

[0076] As a preferred technical measure:

[0077] The primary frequency modulation control command is generated based on the primary frequency modulation contribution power, and the calculation formula for the primary frequency modulation contribution power is as follows:

[0078]

[0079] In the formula:

[0080] H i The primary frequency regulation contribution of unit i;

[0081] t0: The moment when the frequency exceeds one tuning cycle and the cycle ends;

[0082] Frequency value at time t0

[0083] t t The first frequency modulation calculation ends;

[0084] P t: The actual active power output of unit i at time t;

[0085] P0: The end time of the first frequency modulation calculation;

[0086] The speed variation rate of a single frequency modulation is less than 5%, and its calculation formula is as follows:

[0087]

[0088] In the formula:

[0089] P2: Unit output peak value after frequency exceeds dead zone 3 seconds during a large disturbance; P1: Unit output value at the moment frequency exceeds dead zone.

[0090] f2: The frequency value corresponding to the time when P2 occurs;

[0091] f n Rated frequency;

[0092] P n The nameplate output of the generator set.

[0093] As a preferred technical measure:

[0094] The formula for calculating the target value of reactive power of the photovoltaic power station is as follows:

[0095]

[0096] In the formula:

[0097] Q obj Target value for reactive power of photovoltaic power plants;

[0098] Grid-connected voltage power factor reference value;

[0099] P meas Active power measurement value of photovoltaic power station.

[0100] To achieve one of the above objectives, the fourth technical solution of the present invention is as follows:

[0101] A method for rapid power control of new energy power plants based on FPGA is provided, which applies the aforementioned rapid power control system for new energy power plants based on FPGA.

[0102] It includes active power control, reactive power control, and interlocking control;

[0103] When the grid connection point voltage is lower than the set low voltage blocking threshold, the new energy power fast control system immediately stops sending power control commands.

[0104] When the grid connection point voltage recovers to above the low voltage blocking threshold and the duration exceeds the set delay, the new energy power plant power rapid control system resumes normal active power control and reactive power control functions.

[0105] The lockout recovery delay time can be set via the human-machine interface.

[0106] This invention can quickly acquire voltage and frequency signals at grid connection points and ensure signal accuracy through filtering and verification. Simultaneously, it performs rapid analysis and calculation on these signals, combines remote dispatch commands and AGC / AVC control commands to generate control data, and then uses FPGA circuitry to perform network packing and unpacking of the control data, reading and writing it into the MAC circuit for network transmission. The solution is simple, practical, and feasible.

[0107] As a preferred technical measure:

[0108] The data matrix for active power and reactive power control is as follows:

[0109] module memory();

[0110] reg[32:0]p_sepcs_memory[0:32];

[0111] reg[32:0]p_pcs_memory[0:512];

[0112] reg[32:0]q_sepcs_memory[0:32];

[0113] reg[32:0]q_pcs_memory[0:512];

[0114] initial begin

[0115] $readpsepcsmemh("memory.list", p_sepcs_memory);

[0116] $readppcsmemh("memory.list", p_pcs_memory);

[0117] $readqsepcsmemh("memory.list", q_sepcs_memory);

[0118] $readqpcsmemh("memory.list", q_pcs_memory);

[0119] end

[0120] Endmodule.

[0121] Compared with the prior art, the present invention has the following beneficial effects:

[0122] Through continuous exploration and experimentation, this invention incorporates an ARM0 circuit, an ARM1 circuit, an FPGA circuit, an Ethernet module, and a MAC circuit, resulting in high communication speed and control efficiency. Furthermore, the ARM0 circuit allows for real-time deployment of control schemes, and the FPGA circuit handles message packaging and unpacking, while the MAC circuit enables network read / write operations. This effectively reduces network latency in control command transmission, improves frequency and voltage regulation, and ultimately maximizes the power control performance of new energy power plants.

[0123] Furthermore, the FPGA circuit of this invention can quickly pack and unpack control messages according to the GOOSE message specification, reducing the processing burden of ARM1 on reading and parsing control messages, and reducing the waiting time of process scheduling during ARM1 task scheduling. This allows the processing delay of message parsing and reading / writing to be controlled within 1 millisecond, thereby effectively improving the stability and reliability of the field system operation. Attached Figure Description

[0124] Figure 1 This is a structural diagram of the power fast control system of the present invention;

[0125] Figure 2 This is a system block diagram of an ARM0 circuit according to the present invention;

[0126] Figure 3 This is a flowchart of an active power control method according to the present invention;

[0127] Figure 4 This is a flowchart of reactive power control according to the present invention. Detailed Implementation

[0128] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0129] Conversely, this invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the invention as defined in the claims. Furthermore, to provide a better understanding of the invention, certain specific details are described in detail below. However, those skilled in the art will fully understand the invention even without these detailed descriptions.

[0130] The first specific embodiment of the fast power control system for new energy power plants based on FPGA of the present invention:

[0131] A fast power control system for new energy power plants based on FPGA includes an ARM0 circuit, an ARM1 circuit, an FPGA circuit, an Ethernet module, and a MAC circuit.

[0132] The ARM0 circuit is used to deploy the control scheme of the power fast control system, and to obtain the control algorithm and control logic.

[0133] The ARM1 circuit is used to execute control algorithms and control logic, and generate control data;

[0134] The FPGA circuit is used to package and / or unpack control data according to the message specification to obtain packaged data and / or unpacked data.

[0135] The MAC circuit is used to read and write packaged data and / or unpack data;

[0136] The Ethernet module is used to connect with the dispatch master station and / or AGC / AVC master station, receive power control commands from the dispatch master station and / or AGC / AVC master station to the new energy power station in real time, and report the power station voltage and / or frequency and / or active power and / or reactive power and / or power station execution status information to the dispatch master station and / or AGC / AVC master station.

[0137] The ARM0 circuit is connected to the Ethernet module circuit;

[0138] The ARM1 is connected to the ARM0 circuit and the FPGA circuit respectively;

[0139] The FPGA circuit is connected to the MAC circuit.

[0140] The FPGA circuit of this invention completes the data packing and unpacking of control messages according to the GOOSE message specification, which reduces the processing burden of ARM1 on reading and parsing control messages and reduces the waiting time of process scheduling during ARM1 task scheduling, thereby controlling the processing delay of message parsing and reading / writing to within 1 millisecond.

[0141] like Figure 1 As shown, this invention presents a second specific embodiment of the fast power control system for new energy power plants implemented using FPGA:

[0142] A fast power control system for a new energy power station based on FPGA includes an ARM0 circuit, an ARM1 circuit, an FPGA circuit, an Ethernet module, a MAC circuit, an AD sampling circuit, a power supply circuit, a clock circuit, and a reset circuit. The ARM0 circuit is connected to the Ethernet module circuit. The ARM1 circuit is connected to the ARM0 circuit and the FPGA circuit. The clock circuit and the reset circuit are connected to the ARM0 circuit, the ARM1 circuit, and the FPGA circuit. The FPGA circuit is connected to the MAC circuit and the AD sampling circuit. All circuits are connected to the power supply circuit.

[0143] This invention has the advantages of fast sampling and communication speed, high control efficiency, and real-time programmable control via ARM0 circuit. It is based on FPGA chip to realize grid connection point signal sampling and calculation, communication message packing and unpacking, and network reading and writing via MAC, so as to maximize the power control effect of new energy power plants.

[0144] The power fast control system of this invention is connected to the dispatching master station or AGC / AVC master station via an Ethernet network. It receives power control commands from the dispatching master station or AGC / AVC master station for new energy power plants in real time and reports the power plant's voltage, frequency, active power, reactive power, and power plant execution status information to the master station. The Ethernet module is controlled by an ARM0 circuit.

[0145] like Figure 2 As shown, a specific embodiment of the ARM0 circuit of the present invention is as follows:

[0146] To improve the compatibility and deployment flexibility of the power fast control system, the ARM0 uses a trimmed-down Linux operating system, and its application programs adopt a modular design based on a distributed real-time data bus. The communication protocol stack and management strategies adopt a "plug-and-play" component-based design, comprising modules for remote communication service, setting management service, test management service, data bus service, strategy management service, human-machine interaction service, and process management service.

[0147] The process management service manages all processes running on ARM0, including determining process activity status, running daemons, calculating process resource usage, and optimizing the allocation of process resources.

[0148] The data bus service provides real-time data and interaction interfaces based on a unified information model for remote communication services, value management services, test management services, and policy management services.

[0149] The remote communication service reads and writes remote communication data from the Ethernet module, calls the application protocol stack parsing module to unpack or encapsulate the protocol data, performs bidirectional mapping processing on the communication protocol stack data corresponding to the unified information model, and calls the data bus service interface to read and write the data bus.

[0150] The setpoint management service manages all setpoint information of the power rapid control system and detects and verifies the status of the pressure plate corresponding to the setpoint.

[0151] The test management service provides the system with functions for loading, executing, statistically analyzing, and reporting test plans, facilitating system simulation testing and online testing.

[0152] The strategy management service provides functions such as strategy selection, loading, execution, and deployment / rejection. The strategies are implemented in a dynamic library and support online dynamic loading of strategies, thereby improving the scalability and adaptability of system strategy execution and greatly reducing the workload of code refactoring.

[0153] Human-computer interaction provides a human-computer interaction interface for each service module.

[0154] A specific embodiment of the ARM1 circuit of the present invention:

[0155] The ARM1 circuit is the main controller for the control algorithm and logic of the power fast control system. ARM1 is woken up by the policy management service of ARM0. To further improve the efficiency of the control system, ARM1 uses the more lightweight embedded real-time operating system FreeOS. Once a high-priority task in FreeOS is ready, it can preempt the CPU usage of lower-priority tasks, thereby improving the system's real-time responsiveness.

[0156] The first specific embodiment of the fast power control method for new energy power plants based on FPGA of the present invention:

[0157] A method for rapid power control of renewable energy power plants based on FPGA implementation.

[0158] The above-mentioned FPGA-based power rapid control system for new energy power plants is applied.

[0159] Includes the following steps:

[0160] The first step is to obtain power control commands from the dispatch master station and / or AGC / AVC master station to the new energy power plant;

[0161] The second step is to deploy a control scheme based on the power control instructions from the first step, and obtain the control algorithm and control logic.

[0162] The third step is to execute the control algorithm and control logic from the second step to generate control data.

[0163] The fourth step is to use the FPGA circuit to pack and / or unpack the control data from the third step according to the message specification, so as to obtain the packed data and / or unpacked data.

[0164] The fifth step is to send the packaged data and / or unpacked data from the fourth step to the device to be controlled in the new energy power station, so as to realize the rapid control of the power of the new energy power station.

[0165] A second specific embodiment of the FPGA-based method for rapid power control of renewable energy power plants according to the present invention:

[0166] A fast power control method for renewable energy power plants based on FPGA is proposed, which includes active power control, reactive power control, and blocking control. When the grid connection point voltage is lower than the set low voltage blocking threshold, the fast power control system of the renewable energy power plant immediately stops sending power control commands.

[0167] When the grid connection point voltage recovers to above the low voltage blocking threshold and the duration exceeds the set delay, the new energy power plant power rapid control system resumes normal active power control and reactive power control functions.

[0168] The lockout recovery delay time can be set via the human-machine interface.

[0169] like Figure 3 As shown, active power control supports limit control, setpoint control, differential control, and primary frequency regulation control.

[0170] The integral value of the calculated power change should be greater than 0; otherwise, the primary frequency modulation operation is considered incorrect. The calculation formula is as follows:

[0171]

[0172] In the formula:

[0173] H i The primary frequency regulation contribution of unit i;

[0174] t0: The moment when the frequency exceeds one tuning cycle and the cycle ends;

[0175] Frequency value at time t0

[0176] t t The first frequency modulation calculation ends;

[0177] P t : The actual active power output of unit i at time t;

[0178] P0: End time of primary frequency modulation calculation

[0179] The speed variation rate of a single frequency modulation should be less than 5%, calculated using the following formula:

[0180]

[0181] In the formula:

[0182] P2: The unit's maximum output value after the frequency exceeds the dead zone by 3 seconds during a large disturbance;

[0183] P1: The unit output exceeds the dead zone at the frequency;

[0184] f2: The frequency value corresponding to the time when P2 occurs;

[0185] f n Rated frequency;

[0186] P n The nameplate output of the generator set.

[0187] like Figure 4 As shown, reactive power control supports constant reactive power control, constant power factor control, constant voltage control, and reactive voltage droop control.

[0188] In constant power factor control mode, the power control system takes the reactive power of the photovoltaic power station as the control target. The target value is calculated based on the measured active power of the photovoltaic power station and the power factor setpoint, as shown in the following formula:

[0189]

[0190] In the formula:

[0191] Q obj Target value for reactive power of photovoltaic power plants;

[0192] Grid-connected voltage power factor reference value;

[0193] P meas Active power measurement value of photovoltaic power station.

[0194] The power fast control system provides a lockout function to enable / disable. When the grid connection point voltage is lower than the set low voltage lockout threshold, the control system immediately stops sending power control commands.

[0195] When the grid connection point voltage recovers to above the low-voltage blocking threshold and the duration exceeds the set delay, the control system resumes normal active power control and reactive voltage control functions. The blocking recovery delay time can be set via the human-machine interface. The blocking state can also be manually set via the human-machine interface.

[0196] The FPGA implements AD sampling and performs Fourier transform calculations on the sampled data. Simultaneously, it manages the read and write operations of the MAC circuit. The FPGA handles the fast packing and unpacking of control messages according to the GOOSE message specification, reducing the processing burden of control message reading and parsing on the ARM1 and lowering the process scheduling wait time during ARM1 task scheduling. This keeps the processing latency for message parsing and reading / writing within 1 millisecond.

[0197] To further improve module interaction efficiency, the FPGA maps a shared memory block for the exchange of measurement and control data with the ARM1. To improve addressing efficiency and simultaneously support the differentiated control of energy storage converters and photovoltaic (or wind turbine) converters in new energy power plants, separate active and reactive power control data matrices are designed, as follows:

[0198] module memory();

[0199] reg[32:0]p_sepcs_memory[0:32];

[0200] reg[32:0]p_pcs_memory[0:512];

[0201] reg[32:0]q_sepcs_memory[0:32];

[0202] reg[32:0]q_pcs_memory[0:512];

[0203] initial begin

[0204] $readpsepcsmemh("memory.list",p_sepcs_memory);

[0205] $readppcsmemh("memory.list",p_pcs_memory);

[0206] $readqsepcsmemh("memory.list",q_sepcs_memory);

[0207] $readqpcsmemh("memory.list",q_pcs_memory);

[0208] end

[0209] Endmodule.

[0210] Verification has shown that this invention can support power control for up to 32 energy storage converters and 512 photovoltaic (or wind turbine) converters.

[0211] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0212] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0213] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A new energy station power fast control system based on FPGA implementation, characterized in that, comprising ARM0 circuit, ARM1 circuit, FPGA circuit, Ethernet module, MAC circuit; the ARM0 circuit adopts a trimmed linux operating system and is set up based on a distributed real-time data bus, is provided with a communication protocol stack and a management strategy module, is used for control scheme deployment of the power fast control system, and obtains control algorithm and control logic; the ARM1 circuit is set up by a lightweight embedded real-time operating system FreeOS, is awakened by a strategy management service unit of the ARM0 circuit, is used for executing the control algorithm and the control logic, and generates control data; the FPGA circuit performs Fourier transform calculation on the control data, simultaneously manages reading and writing of the MAC circuit, is used for data packing or / and unpacking of the control data according to a message specification, and obtains packed data or / and unpacked data; the MAC circuit is used for reading and writing the packed data or / and the unpacked data; the Ethernet module is used for connecting a dispatching master station or / and an AGC / AVC master station, receiving power control instructions of the new energy station from the dispatching master station or / and the AGC / AVC master station in real time, and reporting voltage or / and frequency or / and active power or / and reactive power or / and station execution state information of the station end to the dispatching master station or / and the AGC / AVC master station; the ARM0 circuit is connected with the Ethernet module circuit; the ARM1 is connected with the ARM0 circuit and the FPGA circuit respectively; the FPGA circuit is connected with the MAC circuit.

2. The new energy station power fast control system based on FPGA implementation according to claim 1, characterized in that, the communication protocol stack and the management strategy module adopt a plug-and-play componentized structure, which comprises a process management service unit, a data bus service unit, a remote communication service unit, a constant value management service unit, a test management service unit, a strategy management service unit, and a man-machine interaction unit.

3. The new energy station power fast control system based on FPGA implementation according to claim 2, characterized in that, the process management service unit is used for managing all processes running on the ARM0 circuit, including judging process active state, running a daemon process, counting process resource occupation, and optimizing allocation of process running resources; the data bus service unit is used for providing real-time data and interactive interfaces based on a unified information model for the remote communication service unit, the constant value management service unit, the test management service unit, and the strategy management service unit; the remote communication service unit is used for reading and writing remote communication data from the Ethernet module, unpacking or encapsulating protocol data by calling the communication protocol stack and the management strategy module, performing bidirectional mapping processing of the communication protocol stack data to the unified information model, and calling the data bus service unit interface to read and write the data bus; the constant value management service unit is used for managing all constant value information of the power fast control system, and detecting and checking a pressure plate state corresponding to the constant value. The test management service unit is used for providing test scheme loading, execution, statistics and reporting functions for the test of the system, and facilitating the system to perform simulation test and online test. The policy management service unit is used for providing policy selection, loading, execution and switching functions. The policy is programmed in the form of dynamic library, and supports online dynamic loading of the policy. The man-machine interaction unit is used for providing man-machine interaction interfaces for the service unit modules.

4. The new energy station power fast control system based on FPGA according to any one of claims 1-3, further comprising an AD sampling circuit, a power supply circuit, a clock circuit and a reset circuit. The AD sampling circuit is used for fast acquisition of voltage and frequency signals of a grid-connected point. The power supply circuit is used for providing electric energy. The clock reset circuit is used for time control and circuit recovery.

5. The new energy station power fast control system based on FPGA, comprising an ARM0 circuit, an ARM1 circuit, an FPGA circuit, an Ethernet module, a MAC circuit, an AD sampling circuit, a power supply circuit, a clock circuit and a reset circuit. The ARM0 circuit adopts a trimmed Linux operating system and is set in a modularized manner based on a distributed real-time data bus. The ARM0 circuit is provided with a communication protocol stack and a management strategy module, and is used for control scheme deployment of the power fast control system to obtain a control algorithm and a control logic. The ARM1 circuit is set by a lightweight embedded real-time operating system FreeOS. The ARM1 circuit is awakened by a strategy management service unit of the ARM0 circuit, and is used for executing the control algorithm and the control logic to generate control data. The FPGA circuit performs Fourier transform calculation on the control data, and manages reading and writing of the MAC circuit. The FPGA circuit is used for data packing or / and unpacking of the control data according to a message specification to obtain packed data or / and unpacked data. The MAC circuit is used for reading and writing of the packed data or / and unpacked data. The AD sampling circuit is used for fast acquisition of voltage and frequency signals of a grid-connected point. The Ethernet module is used for connection with a dispatching master station or / and an AGC / AVC master station, real-time reception of power control instructions of the new energy station from the dispatching master station or / and the AGC / AVC master station, and reporting of station end voltage or / and frequency or / and active power or / and reactive power or / and station execution state information to the dispatching master station or / and the AGC / AVC master station. The power supply circuit is used for providing electric energy. The clock reset circuit is used for time control and circuit recovery. The ARM0 circuit is connected with the Ethernet module circuit. The ARM1 is connected with the ARM0 circuit and the FPGA circuit. The clock reset circuit is connected with the ARM0 circuit, the ARM1 circuit and the FPGA circuit. The FPGA circuit is connected with the MAC circuit and the AD sampling circuit. The ARM0 circuit, the ARM1 circuit, the FPGA circuit, the Ethernet module, the MAC circuit, the AD sampling circuit, the power supply circuit, the clock circuit and the reset circuit are all connected with the power supply circuit.

6. A new energy station power fast control method based on FPGA, comprising the following steps of ​ ​ The application discloses a new energy station power fast control system based on FPGA. The method comprises the following steps: In the first step, the power control instruction of the dispatching master station or / and the AGC / AVC master station to the new energy station is acquired; In the second step, the control scheme is deployed according to the power control instruction in the first step, and the control algorithm and the control logic are obtained; In the third step, the control algorithm and the control logic in the second step are executed, and the control data is generated; In the fourth step, the control data in the third step is packed or / and unpacked by using the FPGA circuit according to the message specification, and the packed data or / and the unpacked data is obtained; In the fifth step, the packed data or / and the unpacked data in the fourth step is sent to the to-be-controlled equipment in the new energy station, and the fast control of the new energy station power is realized.

7. The new energy station power fast control method based on FPGA according to claim 6, wherein the power control instruction comprises active power control instruction, reactive power control instruction and blocking control instruction; the active power control instruction is divided into limit value control instruction, fixed value control instruction, difference value control instruction and primary frequency modulation control instruction; the reactive power control instruction is divided into fixed reactive power control instruction, fixed power factor control instruction, fixed voltage control instruction and reactive power voltage droop control instruction; the fixed power factor control instruction takes the reactive power of the photovoltaic power station as the control target, and the target value is calculated according to the active power measurement value of the photovoltaic power station and the power factor setting value; when the grid-connected point voltage is lower than the set low voltage blocking threshold value, the sending of the power control instruction is immediately stopped; when the grid-connected point voltage is restored to above the low voltage blocking threshold value and the duration exceeds the set delay time, the sending of the active power control instruction and the reactive power control instruction is restored; and the blocking recovery delay time is set by demand.

8. The new energy station power fast control method based on FPGA according to claim 7, wherein the primary frequency modulation control instruction is generated according to the primary frequency modulation contribution electric quantity, and the calculation formula of the primary frequency modulation contribution electric quantity is as follows: wherein the speed variation rate of the primary frequency modulation is less than 5%, and the calculation formula is as follows: wherein 9. The new energy station power fast control method based on FPGA according to claim 7, wherein the target value calculation formula of the reactive power of the photovoltaic power station is as follows: wherein ​ ​ ​ ​ ​ ​ ​ ​ : the primary frequency modulation contribution of the unit i; : the time at which the frequency exceeds the FM action dies : time corresponding to the frequency value : end of the once frequency modulation calculation time : actual active power output of unit i at time t; : end time of the one-time frequency adjustment calculation ​ ​ : the maximum unit output after the frequency exceeds the dead band 3s during a large disturbance : unit output when frequency exceeds dead band; : the frequency value corresponding to the occurrence instant; : rated frequency; : Rated output of the unit. ​ ​ ​ : photovoltaic power station reactive power target value; : grid voltage power factor reference value; : Photovoltaic power plant active power measurement value.

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