Storage system, memory device and method for reading reference voltage management

Abstract

Storage systems, memory devices, and methods for read reference voltage management are provided. A storage system can include a memory device and a memory controller. The memory device can include one or more storage units associated with one or more physical addresses. The memory controller can be coupled to the memory device and configured to obtain one or more parameters stored in an address mapping table corresponding to one of the one or more physical addresses and determine a read reference voltage for a read operation to a physical address of the memory device based on the one or more parameters.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a storage system, a storage device, and a management method thereof. BACKGROUND

[0002] The stability of an amorphous phase in a phase-change memory (PCM) device can be affected by temperature-activated crystallization and resistance drift due to structural relaxation. As a result, threshold voltage drift can occur, thus affecting the lifetime and reliability of the PCM device. SUMMARY

[0003] Some embodiments of a storage system, a storage device, and a method for read reference voltage management are disclosed herein.

[0004] In an aspect of the disclosure, a storage system is provided. The storage system can include a storage device and a memory controller. The storage device can include one or more storage units associated with one or more physical addresses. The memory controller can be coupled to the storage device and configured to obtain one or more parameters corresponding to one of the one or more physical addresses stored in an address mapping table and determine a read reference voltage for a read operation of the physical address of the storage device based on the one or more parameters.

[0005] In some embodiments, the one or more parameters can include a timestamp and a durability bit. The timestamp can include a time at which a write operation is performed on the physical address. The durability bit can include information on whether a cycle count of read / write operations on the physical address is greater than a threshold cycle.

[0006] In some embodiments, the memory controller is further configured to, when a write operation is performed on the physical address, obtain the durability bit and the timestamp corresponding to the physical address from the address mapping table and obtain a current time at which a read operation is to be performed on the physical address; determine a comparison result of a time difference between the timestamp and the current time and a threshold time; and in response to a different combination of the comparison result and the durability bit; provide different read reference voltages for the read operation on the physical address.

[0007] In some embodiments, the one or more parameters can include a durability bit. The durability bit can include information on whether a cycle count of read / write operations on the physical address is greater than a threshold cycle. The durability bit can include a binary value of 1 or 0.

[0008] In some embodiments, the memory controller can be further configured to: obtain, from the address mapping table, a durability bit corresponding to the physical address when the write operation to the physical address is performed; provide a first read reference voltage for the read operation to the physical address in response to the durability bit being equal to 1; and provide a second read reference voltage for the read operation in response to the durability bit being equal to 0. The first read reference voltage can be different from the second read reference voltage.

[0009] In some embodiments, the one or more parameters can include a timestamp of the write operation to the physical address.

[0010] In some embodiments, the memory controller can be further configured to: obtain, from the address mapping table, a timestamp corresponding to the physical address when the write operation to the physical address is performed, and obtain a current time at which the read operation to the physical address is to be performed; provide a third read reference voltage for the read operation in response to a time difference between the current time and the timestamp being greater than a threshold time; and provide a fourth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time. The third read reference voltage can be different from the fourth read reference voltage.

[0011] In some embodiments, the memory controller can be further configured to: obtain, from the address mapping table, a durability bit and a timestamp corresponding to the physical address when the write operation to the physical address is performed, and obtain a current time at which the read operation to the physical address is to be performed; provide a fifth read reference voltage for the read operation in response to a time difference between the current time and the timestamp being greater than a threshold time and the durability bit being equal to 1; provide a sixth read reference voltage for the read operation in response to the time difference being greater than the threshold time and the durability bit being equal to 0; provide a seventh read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1; and provide an eighth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0. At least some of the fifth read reference voltage, the sixth read reference voltage, the seventh read reference voltage, and the eighth read reference voltage can be different.

[0012] In some embodiments, the memory controller can be further configured to: obtain, from the address mapping table, a durability bit and a timestamp corresponding to the physical address when the write operation to the physical address is performed, and obtain a current time at which the read operation to the physical address is to be performed; provide a ninth read reference voltage for the read operation in response to the durability bit being equal to 1; provide a tenth read reference voltage for the read operation in response to the durability bit being equal to 0 and a time difference between the current time and the timestamp being greater than a threshold time; and provide an eleventh read reference voltage for the read operation in response to the durability bit being equal to 0 and the time difference being less than or equal to the threshold time. At least some of the ninth read reference voltage, the tenth read reference voltage, and the eleventh read reference voltage can be different.

[0013] In some embodiments, the memory controller can be further configured to: obtain, when a write operation is performed on the physical address, a durability bit and a timestamp corresponding to the physical address from the address mapping table, and obtain a current time at which a read operation is to be performed on the physical address; provide a twelfth read reference voltage for the read operation in response to a time difference between the current time and the timestamp being greater than a threshold time; provide a thirteenth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1; and provide a fourteenth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0. At least a portion of the twelfth read reference voltage, the thirteenth read reference voltage, and the fourteenth read reference voltage can be different.

[0014] In some embodiments, the memory device can be a phase change memory (PCM) device, and each of the one or more memory cells can include a PCM cell.

[0015] In some embodiments, the memory system can further include a dynamic random access memory (DRAM), wherein the address mapping table is stored in the DRAM.

[0016] In some embodiments, the memory controller can be further configured to: control the memory device to perform a write operation on the physical address, and obtain a current time as the timestamp; obtain, by a wear leveling management mechanism, a cycle count of read / write operations on the physical address; determine, from the cycle count, a durability bit corresponding to the physical address; and store the timestamp and the durability bit corresponding to the physical address in the address mapping table, wherein the one or more parameters include the timestamp and the durability bit.

[0017] In another aspect of the disclosure, a memory controller is provided. The memory controller can be coupled to a memory device that can include one or more memory cells associated with one or more physical addresses. The memory controller can include a processor and a memory. The memory can be coupled to the processor and store instructions that, when executed by the processor, cause the processor to obtain one or more parameters corresponding to one of the one or more physical addresses stored in an address mapping table; and determine, based on the one or more parameters, a read reference voltage for a read operation on the physical address of the memory device.

[0018] In some embodiments, the one or more parameters can include a timestamp and a durability bit. The timestamp can include a time at which a write operation is performed on the physical address. The durability bit can include information about whether a cycle count of read / write operations on the physical address is greater than a threshold cycle.

[0019] In some embodiments, the instructions further cause the processor to: obtain, from the address mapping table, a durability bit and a timestamp corresponding to the physical address when the write operation to the physical address is performed, and obtain a current time at which the read operation to the physical address is to be performed; determine a comparison result of a time difference between the timestamp and the current time and a threshold time; and provide different read reference voltages for the read operation to the physical address in response to different combinations of the comparison result and the durability bit.

[0020] In some embodiments, the one or more parameters can include a durability bit. The durability bit can include information about whether a cycle count of the read / write operation to the physical address is greater than a threshold cycle count. The durability bit can include a binary value of 1 or 0.

[0021] In some embodiments, the instructions can further cause the processor to: obtain, from the address mapping table, a durability bit corresponding to the physical address when the write operation to the physical address is performed; provide a first read reference voltage for the read operation to the physical address in response to the durability bit being equal to 1; and provide a second read reference voltage for the read operation in response to the durability bit being equal to 0. The first read reference voltage can be different from the second read reference voltage.

[0022] In some embodiments, the one or more parameters can include a timestamp at which the write operation to the physical address is performed.

[0023] In some embodiments, the instructions can further cause the processor to: obtain, from the address mapping table, a timestamp corresponding to the physical address when the write operation to the physical address is performed, and obtain a current time at which the read operation to the physical address is to be performed; provide a third read reference voltage for the read operation to the physical address in response to a time difference between the current time and the timestamp being greater than a threshold time; and provide a fourth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time. The third read reference voltage can be different from the fourth read reference voltage.

[0024] In some embodiments, the instructions can further cause the processor to: obtain, from the address mapping table, a durability bit and a timestamp corresponding to the physical address when the write operation to the physical address is performed, and obtain a current time at which the read operation to the physical address is to be performed; provide a fifth read reference voltage for the read operation in response to the time difference between the current time and the timestamp being greater than a threshold time and the durability bit being equal to 1; provide a sixth read reference voltage for the read operation in response to the time difference being greater than the threshold time and the durability bit being equal to 0; provide a seventh read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1; and provide an eighth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0. At least some of the fifth read reference voltage, the sixth read reference voltage, the seventh read reference voltage, and the eighth read reference voltage can be different.

[0025] In some embodiments, the instructions can further cause the processor to: obtain, from the address mapping table, a durability bit and a time stamp corresponding to the physical address when performing the write operation on the physical address, and obtain a current time at which the read operation is to be performed on the physical address; provide, in response to the durability bit being equal to 1, a ninth read reference voltage for the read operation; provide, in response to the durability bit being equal to 0 and a time difference between the current time and the time stamp being greater than a threshold time, a tenth read reference voltage for the read operation; and provide, in response to the durability bit being equal to 0 and the time difference being less than or equal to the threshold time, an eleventh read reference voltage for the read operation. At least some of the ninth read reference voltage, the tenth read reference voltage, and the eleventh read reference voltage can be different.

[0026] In some embodiments, the instructions can further cause the processor to: obtain, from the address mapping table, a durability bit and a time stamp corresponding to the physical address when performing the write operation on the physical address, and obtain a current time at which the read operation is to be performed on the physical address; provide, in response to a time difference between the current time and the time stamp being greater than a threshold time, a twelfth read reference voltage for the read operation; provide, in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1, a thirteenth read reference voltage for the read operation; and provide, in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0, a fourteenth read reference voltage for the read operation. At least some of the twelfth read reference voltage, the thirteenth read reference voltage, and the fourteenth read reference voltage can be different.

[0027] In some embodiments, the memory device can be a phase change memory (PCM) device, and each of the one or more storage cells can include a PCM cell.

[0028] In some embodiments, the address mapping table can be stored in a dynamic random-access memory (DRAM).

[0029] In some embodiments, the instructions can further cause the processor to: control the memory device to perform a write operation on the physical address, and obtain a current time as the time stamp; obtain, by the wear leveling management mechanism, a cycle count of read / write operations on the physical address; determine, from the cycle count, the durability bit corresponding to the physical address; and store, in the address mapping table, the time stamp and the durability bit corresponding to the physical address, wherein the one or more parameters include the time stamp and the durability bit.

[0030] In yet another aspect of the disclosure, a method for read reference voltage management is provided. The method can be implemented to a memory device that can include one or more storage units associated with one or more physical addresses. The method can include obtaining one or more parameters corresponding to one of the one or more physical addresses stored in an address map table; and determining a read reference voltage for a read operation to the physical address of the memory device based on the one or more parameters.

[0031] In some embodiments, the one or more parameters can include a timestamp and a durability bit. The timestamp can include a timestamp of a write operation performed to the physical address. The durability bit can include information about whether a cycle count of read / write operations to the physical address is greater than a threshold cycle.

[0032] In some embodiments, the method can further include obtaining a current time at which a read operation is to be performed to the physical address when the write operation is performed to the physical address. Obtaining the one or more parameters can include obtaining the durability bit corresponding to the physical address from the address map table when the write operation is performed to the physical address. Determining the read reference voltage based on the one or more parameters can include determining a comparison result of a time difference between the timestamp and the current time and a threshold time; and providing different read reference voltages for the read operation to the physical address in response to different combinations of the comparison result and the durability bit.

[0033] In some embodiments, the one or more parameters can include a durability bit. The durability bit can include information about whether a cycle count of read / write operations to the physical address is greater than a threshold cycle. The durability bit can include a binary value of 1 or 0.

[0034] In some embodiments, the method can further include obtaining a current time at which a read operation is to be performed to the physical address when the write operation is performed to the physical address. Obtaining the one or more parameters can include obtaining the durability bit corresponding to the physical address from the address map table when the write operation is performed to the physical address. Determining the read reference voltage based on the one or more parameters can include providing a first read reference voltage for the read operation to the physical address in response to the durability bit being equal to 1; and providing a second read reference voltage for the read operation in response to the durability bit being equal to 0. The first read reference voltage can be different from the second read reference voltage.

[0035] In some embodiments, the one or more parameters can include a timestamp of a write operation performed to the physical address.

[0036] In some embodiments, the method can further include obtaining, when a write operation is performed on the physical address, a current time at which a read operation is to be performed on the physical address. Obtaining the one or more parameters can include obtaining, when the write operation is performed on the physical address, a timestamp corresponding to the physical address from the address mapping table. Determining the read reference voltage based on the one or more parameters can include providing, in response to a time difference between the current time and the timestamp being greater than a threshold time, a third read reference voltage for the read operation on the physical address; and providing, in response to the time difference being less than or equal to the threshold time, a fourth read reference voltage for the read operation. The third read reference voltage can be different from the fourth read reference voltage.

[0037] In some embodiments, the method can further include obtaining, when a write operation is performed on the physical address, a current time at which a read operation is to be performed on the physical address. Obtaining the one or more parameters can include obtaining, when the write operation is performed on the physical address, a durability bit and a timestamp corresponding to the physical address from the address mapping table. Determining the read reference voltage based on the one or more parameters can include providing, in response to a time difference between the current time and the timestamp being greater than a threshold time and the durability bit being equal to 1, a fifth read reference voltage for the read operation; providing, in response to the time difference being greater than the threshold time and the durability bit being equal to 0, a sixth read reference voltage for the read operation; providing, in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1, a seventh read reference voltage for the read operation; and providing, in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0, an eighth read reference voltage for the read operation. At least some of the fifth read reference voltage, the sixth read reference voltage, the seventh read reference voltage, and the eighth read reference voltage can be different.

[0038] In some embodiments, the method can further include obtaining, when a write operation is performed on the physical address, a current time at which a read operation is to be performed on the physical address. Obtaining the one or more parameters can include obtaining, when the write operation is performed on the physical address, a durability bit and a timestamp corresponding to the physical address from the address mapping table. Determining the read reference voltage based on the one or more parameters can include providing, in response to the durability bit being equal to 1, a ninth read reference voltage for the read operation; providing, in response to the durability bit being equal to 0 and a time difference between the current time and the timestamp being greater than a threshold time, a tenth read reference voltage for the read operation; and providing, in response to the durability bit being equal to 0 and the time difference being less than or equal to the threshold time, an eleventh read reference voltage for the read operation. At least some of the ninth read reference voltage, the tenth read reference voltage, and the eleventh read reference voltage can be different.

[0039] In some embodiments, the method can include obtaining, at the time of the write operation to the physical address, a current time at which the read operation is to be performed to the physical address. Obtaining the one or more parameters can include obtaining, at the time of the write operation to the physical address, the endurance bit and the timestamp corresponding to the physical address from the address mapping table. Determining the read reference voltage based on the one or more parameters can include providing a twelfth read reference voltage for the read operation in response to a time difference between the current time and the timestamp being greater than a threshold time, providing a thirteenth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the endurance bit being equal to 1, and providing a fourteenth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the endurance bit being equal to 0. At least a portion of the twelfth read reference voltage, the thirteenth read reference voltage, and the fourteenth read reference voltage can be different.

[0040] In some embodiments, the memory device can be a phase change memory (PCM) device, and each of the one or more memory cells can include a PCM cell.

[0041] In some embodiments, the address mapping table can be stored in a dynamic random access memory (DRAM).

[0042] In some embodiments, the method can further include controlling the memory device to perform a write operation to the physical address and obtaining the current time as the timestamp, obtaining, by a wear leveling management mechanism, a cycle count of read / write operations to the physical address, determining the endurance bit corresponding to the physical address based on the cycle count, and storing the timestamp and the endurance bit corresponding to the physical address in the address mapping table.

[0043] Reference to these descriptive block embodiments is not intended to limit or restrict the disclosure to such descriptive block embodiments. Additional embodiments will be discussed in the DETAILED DESCRIPTION and further description is provided there. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings, which are incorporated in and form a part of the specification, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable making and using the present disclosure.

[0045] Figure 1 FIG. illustrates a schematic diagram of an exemplary memory device including phase change memory (PCM) cells, in accordance with some aspects of the present disclosure.

[0046] Figure 2A FIG. illustrates an exemplary curve profile showing a threshold voltage of a bidirectional threshold selector as a function of latency of a PCM device.

[0047] Figure 2BAn exemplary curve profile is illustrated showing the threshold voltage variation of set (SET) and reset (RESET) states corresponding to the number of read / write operation cycles.

[0048] Figure 2C A schematic diagram of read reference voltage shift due to threshold voltage drift is illustrated in accordance with some aspects of the present disclosure.

[0049] Figure 3 A schematic diagram of an exemplary address management structure having a mapping table in a storage system is illustrated in accordance with some aspects of the present disclosure.

[0050] Figure 4 A block diagram of an exemplary storage system having memory storage is illustrated in accordance with some aspects of the present disclosure.

[0051] Figure 5 A schematic diagram of an exemplary entry of an address mapping table having a timestamp and a durability bit is illustrated in accordance with some aspects of the present disclosure.

[0052] Figure 6 A flowchart of a first exemplary method of read reference voltage management is illustrated in accordance with some aspects of the present disclosure.

[0053] Figure 7 A flowchart of a second exemplary method of read reference voltage management is illustrated in accordance with some aspects of the present disclosure.

[0054] Figure 8A A flowchart of an exemplary method of read reference voltage management is illustrated in accordance with some aspects of the present disclosure.

[0055] Figure 8B A flowchart of a third exemplary method of read reference voltage management is illustrated in accordance with some aspects of the present disclosure.

[0056] Figure 8C A flowchart of a fourth exemplary method of read reference voltage management is illustrated in accordance with some aspects of the present disclosure.

[0057] Figure 8D A flowchart of a fifth exemplary method of read reference voltage management is illustrated in accordance with some aspects of the present disclosure.

[0058] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0059] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Other configurations and arrangements can be employed without departing from the scope of the disclosure. Moreover, the disclosure is applicable to other applications. The functionality and structures described in this disclosure can be combined in ways not specifically described in the figures, adjusted, modified, and / or adapted to combinations of the features described in the figures without departing from the scope of the present disclosure.

[0060] It should also be noted that the description of the specification uses “one embodiment,” “an embodiment,” “example embodiment,” “some embodiments,” “one example,” “some examples,” and so on to mean that a particular feature, structure, or characteristic described in connection with these phrases can be included in the claimed disclosure. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments, whether or not explicitly described or illustrated.

[0061] In general, terminology can be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, depending at least in part upon context, can be understood either to refer to a singular feature or feature of

[0062] It should be readily understood that the terms “on,” “over,” and “above” in the present disclosure are to be interpreted in the broadest possible way, such that “on” means not only “directly on something,” but also includes the meaning of “on something with intervening feature(s) or layer(s) therebetween,” and “over” or “above” means not only the meaning of something “over” or “above” something, but also can include the meaning of something “over” or “above” something without intervening feature(s) or layer(s) therebetween (i.e., directly on something).

[0063] Moreover, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0064] As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0065] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an extent less than the underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be between or at any pair of horizontal planes between a top surface and a bottom surface of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above and / or below. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0066] As technology advances, such as in cloud storage and autonomous navigation, higher demands are placed on the performance and density of memory devices due to the increasing demand for data size. For this reason, new types of storage devices, such as memory devices having phase change memory (PCM) cells, have been introduced to replace dynamic random access memory (DRAM) and NAND memory. PCM cells are non-volatile memory devices that can store data using a phase change material. Based on electro-thermal heating and quenching the phase change material, PCM devices exploit the difference in resistivity between an amorphous phase and a crystalline phase in a phase change material, such as a chalcogenide alloy. By changing the structure of the phase change material and exploiting the difference in resistivity, PCM cells can store binary information, where a "SET" state = 1 and a "RESET" state = 0.

[0067] Figure 1A cross-sectional side view of a memory device 100 having a PCM element in series with a selector is illustrated. The memory device 100 can include one or more parallel bit lines 104 over a substrate 102 and one or more parallel word lines 116 over the bit lines 104. The memory device 100 can also include one or more PCM cells 101, each PCM cell disposed at an intersection of a respective pair of bit lines 104 and word lines 116. Adjacent PCM cells 101 are separated by an insulating structure 122. Each PCM cell 101 can include a selector 108 and a PCM element 112 over the selector 108. In some embodiments, each PCM cell 101 can also include a plurality of electrodes 106, 110, and 114 vertically positioned between the respective bit line 104, selector 108, PCM element 112, and respective word line 116.

[0068] As described above, the PCM element 112 can be based on electro-thermal heating and quenching phase change material, exploiting the difference in resistivity between amorphous and crystalline phases in a phase change material, such as a chalcogenide alloy. More specifically, the phase change material in each PCM cell can be arranged between two electrodes, and an electrical current can be applied to the electrodes to repeatedly switch the material (or at least a portion of the material blocking the current path) between two phases storing data. The “SET” state (=1) is a low resistance state of the PCM cell, which can be obtained by creating crystalline regions in its chalcogenide material. Crystallization occurs when the chalcogenide material is heated at the crystallization temperature for a sufficient amount of time. Conversely, the “RESET” state (=0) is a high resistance state of the PCM cell, which can be obtained by creating amorphous regions in the chalcogenide material. The amorphous regions can be created when the chalcogenide material is heated above its melting temperature and then rapidly quenched to create an amorphous composition. As used herein, the “SET” state can also be referred to as an “on” state, while the “RESET” state can be referred to as an “off’ state.

[0069] Figure 1 The selector 108 in the PCM cell 101 can include an ovonic threshold switch (OTS) selector having an OTS material, such as zinc telluride (ZnTe), which exhibits a field-dependent, volatile resistance switching behavior (referred to as “OTS phenomenon”) when an external bias voltage (Va) above a threshold voltage (Vt) is applied. At lower voltages (i.e., |Va| < Vt), the high resistance of the OTS selector in its off state can keep the off current (Ioff) low. On the other hand, at higher voltages (|Va| ≥ Vt), the OTS selector can experience the OTS phenomenon and switch to an on state at a low resistance. As a result, the current (Ion) through the OTS selector in the on state can increase. Once the high voltage is provided, the volatile on state can be maintained.

[0070] One key challenge for PCM devices is the time evolution of the resistance level, referred to as "resistance drift", which is a result of spontaneous structural relaxation of the PCM material. The amorphous phase of chalcogenide materials in PCM devices can be susceptible to structural relaxation. Thus, in PCM devices, the amorphous phase relaxes after the RESET state and the threshold voltage (Vt) changes accordingly due to structural relaxation. This process is referred to as "threshold voltage drift".

[0071] Figure 2A An exemplary curve profile is illustrated showing the threshold voltage of a bidirectional threshold switch (OTS) selector (e.g., in the SET state) as a function of latency for a PCM device. Figure 2A The latency in the PCM device can indicate the duration between the programming time point and the read time point for the PCM device. As shown in Figure 2A with the increase of latency, the threshold voltage of the OTS selector can gradually increase over a certain period of time (in terms of comparison with the reference threshold voltage Vo), and reach a saturation state after the period of time. In addition, Figure 2B An exemplary curve profile is illustrated showing the threshold voltage change of the SET state and the RESET state corresponding to the number of read / write operation cycles (or referred to as "cycle count") for a PCM device. As shown in Figure 2B with the increase of the number of read / write operation cycles and reaching a certain number, the threshold voltage associated with the SET state and the RESET state changes accordingly. In view of Figure 2A and 2B The threshold voltage of a PCM device can drift due to various reasons. Thus, the PCM device can require a scheme related to read reference voltage (Vread) management in response to the threshold voltage drift.

[0072] Figure 2C A schematic diagram is shown illustrating the read reference voltage shift due to threshold voltage drift in accordance with some aspects of the present disclosure. The threshold voltage drift can be caused by temperature change, increased read / write operation cycles, longer latency, and other factors. As shown in Figure 2C The read reference voltage can depend on the threshold voltage associated with the SET state and the RESET state. In response to the threshold voltage drift, the read reference voltage (Vread) can need to be modified so that the SET state can be distinguished from the RESET state at the read time point after the write operation on the PCM device.

[0073] In some other methods in the related art, a read retry scheme is proposed to provide dynamic adaptation of read reference voltage. In the read retry technique, when the number of error rates in, for example, a page exceeds the correction capability at the time of read operation, the operation can be repeated to modify the read parameters, so that the number of read errors can be reduced. However, in these methods, the read retry algorithm is very complex. Therefore, the read bandwidth of the system can be occupied, and the power consumption can be increased accordingly, thereby greatly affecting the system performance.

[0074] To solve the above problems and other problems, the present disclosure provides an inventive scheme in which a corresponding Vread option can be determined according to one or more PCM parameters. The one or more PCM parameters can include a timestamp for determining a latency, a lifetime of a PCM device, an operating temperature of a PCM device, and the like. Therefore, the scheme provided by the present disclosure can effectively reduce the error rate of the read operation to ensure the performance of the system. A storage system according to some embodiments of the present disclosure can include a memory controller configured to determine a Vread option according to one or more PCM parameters. Therefore, compared to using a complex read retry algorithm in other methods, the process according to the present disclosure is simplified, thereby reducing read latency.

[0075] As a non-volatile memory, a PCM device faces the same challenges as a NAND device. That is, a PCM device can have limited lifetime and reliability problems like a NAND device. Even though a PCM device can have higher endurance than a NAND device, a PCM device still needs wear leveling management. A flash translation layer (FTL) software layer can be introduced to a PCM storage system for the purpose of wear leveling management, in which an address mapping table is a necessary part. In the address mapping table, a read / write operation cycle number (i.e., cycle count) corresponding to each physical address can be stored.

[0076] Since the address mapping table is easy to implement in a storage system, one or more PCM parameters can also be stored in the address mapping table. In some embodiments of the present disclosure, one or more PCM parameters (e.g., endurance bits and timestamps) can also be stored in the address mapping table corresponding to the physical address without incurring additional overhead. This embodiment effectively utilizes the free space of the address mapping table and can reduce the frequency of accessing the storage system. That is, whenever the address mapping table is accessed, the corresponding information of one or more PCM parameters corresponding to the physical address can be easily retrieved.

[0077] Figure 3FIG. illustrates a schematic diagram showing an exemplary address management structure with an address mapping table 302, where a logical address space can be mapped to a physical address space of a storage system 301, in accordance with some aspects of the present disclosure. The address mapping table can be responsible for translating logical addresses used by upper layers in a system that interacts with the storage system to physical addresses where data is stored in the storage system, and vice versa. As Figure 3 As shown, in some embodiments, the storage system 301 can include a PCM device 304 with a physical address space to which a logical address space is mapped. The address mapping table can include arrays, each of which is allocated to a logical address and where the logical address is mapped to a physical address of the PCM device 304. In some embodiments of the present disclosure, one or more PCM parameters, including, for example, a durability bit and a time stamp, can be stored in the address mapping table.

[0078] While Figure 3 The address mapping table is shown as a one-level mapping relationship for translating a logical address space to a physical address space and vice versa. It can also be understood that, Figure 3 This is provided by way of illustration and not of limitation. In other embodiments, a multi-level address mapping table can be employed, and one or more PCM parameters can be stored in a suitable level of the multiple levels (e.g., in the last level), depending on the particular application and design constraints imposed on the overall system.

[0079] Figure 4 FIG. illustrates a block diagram of an exemplary storage system 400 with a memory storage 401, in accordance with some aspects of the present disclosure. The storage system 400 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device with storage. As Figure 4 As shown, the storage system 400 can include a host 402, a memory controller 404, and a memory storage 401 including one or more memory devices. In some embodiments, the memory storage 401 can include a DRAM 406, a PCM device 408, and other suitable memory devices controlled by the memory controller 404.

[0080] As Figure 4 shown, the host 402 can be configured to generate instructions and send them to the memory controller 404. Based on the instructions or by its initiative, the memory controller 404 can generate command signals to control the memory storage 401. Although it is not shown in the figure, the memory controller 404 can also be configured to generate command signals to control the memory storage 401 based on its initiative. Figure 4As shown in FIG. 4, in some embodiments, the host 402 can be directly connected with the memory storage 401 and can access the memory storage 401 bypassing the memory controller 404. The present disclosure is not limited thereto.

[0081] The host 402 can be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). In some implementations, the host 402 can be configured to send or receive data regarding the memory storage 401. In some implementations, the host 402 can include a user logic or a user interface such that a user can give an instruction to the host 402 and send the instruction to the memory storage 401.

[0082] The one or more memory devices can include the PCM device 408, the DRAM 406, and other suitable memory devices, such as a NAND flash device. Each of the one or more memory devices can include a clock input, a command bus, a data bus, control logic, an address register, a row decoder / word line driver, a memory cell array with memory cells, a voltage generator, a page buffer / sense amplifier, a column decoder / bit line driver, a data input / output (I / O). In some embodiments, one physical address can be configured to point to and provide access to one or more memory cells.

[0083] The memory controller 404 can be electrically connected or coupled with the memory storage 401 and the host 402, and can be configured to control the memory storage 401. The memory controller 404 can manage data stored in the memory storage 401 and communicate with the host 402. In some embodiments, the memory controller 404 can be designed for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used for electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 404 can be designed for operation in a high duty cycle environment, such as a solid-state drive (SSD) or an embedded multi-media-card (eMMC) used as data storage for mobile devices (e.g., smartphones, tablet computers, laptop computers, etc.) and enterprise storage arrays. The memory controller 404 can be configured to control the operation of one or more memory devices, such as read operations, erase operations, and write operations. The memory controller 404 can also be configured to manage various functions related to data stored or to be stored in the memory storage 401, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 404 is also configured to process error correction codes (ECC) related to data read from or written to one or more memory devices. The memory controller 404 can also perform any other suitable functions, such as formatting one or more memory devices.

[0084] The memory controller 404 can communicate with external devices (e.g., the host 402) in accordance with a particular communication protocol. For example, the memory controller 404 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0085] In addition, the memory controller 404 can also be configured to control the operation of one or more memory devices to perform methods in accordance with some embodiments of the present disclosure. For example, in some embodiments, the memory controller 404 can determine whether a time difference between a timestamp of a write operation and a current time of a read operation is greater than or less than a threshold time. In some embodiments, the memory controller 404 can determine whether a durability bit indicates that a cycle count of read / write operations to a physical address is greater than or less than a threshold cycle. In some embodiments, the threshold cycle can be on the order of 10 5 to about 10 8 The current time can be a system time measured by a system clock.

[0086] In some embodiments, instead of being shown as separate from Figure 4 the host 402, the memory controller 404 can be integrated into the host 402 as a whole. In addition, as an example, Figure 4 DRAM 406 and the PCM device 408 are shown as communicating with the memory controller 404 in a parallel manner. However, in some embodiments, the DRAM 406 and the PCM device 408 can communicate with each other and have internal data transfer within the memory storage 401.

[0087] In some embodiments, a wear leveling algorithm can be implemented for the storage system 400. The purpose of the wear leveling algorithm is to make the distribution of programming locations uniform, thereby increasing the lifetime of the memory storage 401.

[0088] In some embodiments, the wear leveling algorithm may be stored in the memory storage device 401 and executed by the memory controller 404 to perform wear leveling management, such as... Figure 4 As shown. In some embodiments, the wear leveling mechanism may be a source for providing cycle counts of read / write operations (read operations and write operations) associated with the PCM device 408. This disclosure may utilize cycle counting. It is understood that... Figure 4 This is just an example; in other implementations, wear leveling management may be stored and performed by other devices inside or outside the storage system 400.

[0089] In some embodiments, the address mapping table 500 may be stored in DRAM 406, but this disclosure is not limited thereto. In other embodiments, the address mapping table 500 may be stored locally in PCM device 408, or alternatively in any suitable memory device in memory storage device 401. In one case, the PCM device 408 may be used as a buffer or cache when the system retrieves data from the address mapping table 500 from DRAM 406. In response to the memory controller 404 generating and sending control signals to the memory device storing the address mapping table 500 (in... Figure 4 In the case of DRAM 406, the information stored in the address mapping table 500 can be retrieved by the memory controller 404. The memory controller 404 can evaluate and determine decisions based on the information provided by the address mapping table 500.

[0090] Figure 5 A schematic diagram of exemplary entries of an address mapping table 500 having timestamps and durability bits according to some aspects of this disclosure is shown. The address mapping table 500 is an abstract data structure that implements a key-to-value associative data mapping to organize data. As described above, the address mapping table 500 may include links (i.e., relationships) between logical addresses 502 and their corresponding physical addresses 504 to translate logical space used by upper layers (e.g., host 402) in the system into physical space, and vice versa. The physical address may be represented in binary bit form and provides access to one or more memory cells of the PCM device 408.

[0091] In some embodiments of this disclosure, address mapping table 500 may include one or more PCM parameters. As used herein, the term "one or more PCM parameters" can describe one or more parameters associated with a PCM device configured to provide information for supporting read reference voltage management. For example, address mapping table 500 may include a timestamp 506 and a durability bit 508. Timestamp 506 and durability bit 508 can be stored based on physical address 504. Timestamp 506 can be updated based on the time of a write operation (to determine the associated latency), while durability bit 508 can be updated based on the number of read / write operations. The number of read / write operations can be recorded by the wear leveling mechanism of storage system 400, which is necessary information for wear leveling management. Some embodiments of this disclosure can readily utilize the number of read / write operations to determine read reference voltage options.

[0092] like Figure 5 As shown, logical address 502 can be a key in address mapping table 500. That is, logical address 502 can be used to locate the corresponding physical address 504. In some embodiments, timestamp 506 and durability bit 508 can be stored according to the corresponding physical address 504. Therefore, by using logical address 502 as a search index (i.e., database key), physical address 504 and its corresponding timestamp 506 and durability bit 508 can be located. Although Figure 5 Only two fields of one or more PCM parameters (timestamp 506 and durability bit 508) in address mapping table 500 are shown. It is understood that other data fields may also be applicable, such as temperature coefficient and / or read error rate.

[0093] In some implementations, timestamp 506 may include data bits and check bits. The data bits may store a numerical value, such as time data. For each write operation to a physical address, the current time of the write operation can be encoded and stored in the data bits according to the algorithm's conversion format, and the address mapping table 500 can be updated. The check bits of timestamp 506 can be configured to verify the correctness of the time conversion and / or indicate the conversion format or accuracy of timestamp 506. In one example, the size of timestamp 506 may not exceed 8 bits.

[0094] In some implementations, durability bit 508 may include a bit of a binary value ("1" or "0"), while in other implementations, durability bit 508 may include additional bits for storing other information about the lifespan of PCM device 408.

[0095] Figure 6A flow diagram illustrating a first exemplary method of read reference voltage management in accordance with some aspects of the present disclosure is shown. In some embodiments, the memory controller 404 can be configured to execute instructions stored in a memory device (e.g., DRAM 406) for performing the method 600 to determine a read reference voltage for a read operation based on a time stamp 506. Figure 6 The read reference voltage is determined based on the time stamp 506.

[0096] The method 600 proceeds to 602, where the memory controller 404 can perform a write operation to a physical address of the PCM device 408. The physical address can be represented in a digital form and provides access to one or more storage cells of the PCM device 408. At the time of the write operation, the memory controller 404 can obtain a current time as a time stamp ti at 604, and store the time stamp ti to the field of time stamps 506 of the address mapping table 500 at 606. Further, at 608, the memory controller 404 can prepare to perform a read operation to the same physical address. At 610, the memory controller 404 can obtain a current time as a time stamp t2 and retrieve the time stamp ti stored in the address mapping table 500 to determine a read reference voltage for the read operation.

[0097] The method proceeds to 612 in Figure 6 , where the memory controller 404 can calculate a time difference between the time stamp t2 and the time stamp ti and compare the time difference to a threshold time. In response to the time difference being greater than the threshold time, the memory controller 404 can apply option A for the read operation at 614, where a read reference voltage Va is supplied for the read operation. When the time difference (t2-ti) is large, it can mean that the associated latency is relatively long. As is known, as the latency increases, the threshold voltage of the OTS selector also changes, as shown in Figure 2A .

[0098] On the other hand, in response to the time difference being less than or equal to the threshold time, the memory controller 404 can apply option B at 616, where a read reference voltage Vb is supplied for the read operation. The read reference voltage Va and the read reference voltage Vb can be different. In this way, the threshold voltage drift can be properly compensated in terms of the read reference voltage, thereby reducing the read error rate, and thus increasing the performance and lifetime of the PCM device 408.

[0099] In some implementations, the threshold time can be obtained based on a modeling of the threshold voltage versus latency, as shown in Figure 2A The threshold time can depend on, for example, the PCM product type and its operating temperature. In some implementations, the threshold time can be in the order of milliseconds, for example, 1 millisecond.

[0100] Figure 7A flowchart illustrating a second exemplary method of read reference voltage management in accordance with some aspects of the present disclosure is shown. In some implementations, the memory controller 404 can be configured to execute instructions stored in a memory device (e.g., DRAM 406) to perform the method 700 of read reference voltage management based on a durability bit 508. Figure 7 The method 700 of performing read reference voltage management based on a durability bit 508.

[0101] According to the method 700 in Figure 7 The memory controller 404 can perform a write operation to a physical address of the PCM device 408 at 702 and obtain a cycle count at the time of the write operation. As described above, the cycle count can be provided by a wear leveling mechanism of the storage system 400. For each write operation to the physical address, the cycle count is updated by increasing, for example, by 1 (one). In response to the memory controller 404 determining that the cycle count is greater than a threshold cycle count (C Figure 7 The memory controller 404 can set the durability bit 508 in the address map table 500 to "1" at 706 in response to the memory controller 404 determining that the cycle count is greater than the threshold cycle count (C threshold ), and the memory controller can set the durability bit 508 to "0" at 708 in response to the memory controller 404 determining that the cycle count is less than or equal to the threshold cycle count. Accordingly, the memory controller 404 can store a binary value of "1" or "0" to the field of the durability bit 508 in the address map table 500 at 710. Further, the memory controller 404 can prepare to perform a read operation to the same physical address at 712. The memory controller 404 can retrieve the durability bit 508 from the address map table 500 at 714. The memory controller 404 can evaluate the value of the durability bit 508 at 716. Depending on the value of the durability bit 508 (e.g., "1" or "0") stored earlier in the address map table 500, the memory controller 404 can determine to apply a differential read reference voltage option at 718 and 720, in which either a read reference voltage Vc or Vd is used for the read operation. The read reference voltage Vc and the read reference voltage Vd can be different.

[0102] The durability bit 508 can indicate whether a particular number of read / write operations to a physical address of the PCM device 408 has been exceeded. At each write operation, a system (e.g., a wear leveling mechanism) can update a number of read / write operations (or referred to as a "cycle count") that some embodiments of the present disclosure can readily use. In explanation, the larger the cycle count of a physical address, the shorter the life of the remaining physical address. In some implementations, a default value of the durability bit 508 can be set to "0," and the durability bit 508 can be modified to "1" only when the cycle count exceeds a threshold cycle count to reduce processing overhead. According to Figure 7 Upon evaluating the durability bit 508, a read reference voltage (Vread) can be determined for the read operation.

[0103] For simplicity of description, Figure 7 only one example is depicted in which the cycle count is updated based on write operations only. Given that both write and read operations can affect the lifetime of the PCM device 408, in some embodiments, the cycle count can also be updated based on read operations. For example, in one case, the impact of four read operations can be considered equivalent to the impact of one write operation, and the system can be configured to update the cycle count once for every four read operations. It can be appreciated that the number "four" is given as an example for simplicity of description, and can depend on the actual application case, the type of PCM device, etc. The present disclosure is not limited as such. Thus, the term "read / write" operation can be used to indicate either write operations only or a combination of read and write operations.

[0104] Furthermore, given that both latency and cycle count can affect the threshold voltage associated with the SET and RESET states, in other implementations, the memory controller 404 can evaluate both latency and cycle count to determine the read reference voltage for read operations.

[0105] Figure 8A A flowchart of an exemplary method of read reference voltage management according to some aspects of the present disclosure is partially illustrated. Similar to Figure 6 and Figure 7 , the memory controller 404 can perform a write operation to a physical address of the PCM device 408 at 802. The memory controller 404 can obtain the current time as a timestamp ti at 804, and set the endurance bit 508 according to a comparison of the threshold cycles to the cycle count of read / write operations to the physical address at 806, 808, and 810. As mentioned above, the term "read / write operation" can be used to indicate either write operations only or a combination of read and write operations, depending on the system application constraints. Figure 8A The threshold cycles (C threshold ) used in Figure 7 may be the same or different from the threshold cycles used in . These values of the timestamp ti and the endurance bit 508 can be stored in the corresponding fields of the address mapping table 500. The method proceeds to 814, where the memory controller 404 can prepare to perform a read operation to the same physical address. At 816, the memory controller 404 can obtain the current time as a timestamp t2. At the same time, the timestamp ti and the endurance bit 508 stored earlier in the address mapping table 500 can be retrieved at 818. In some implementations, the memory controller 404 can process operations 816 and 818 in parallel, as shown in Figure 8A , while in other implementations, these operations can be performed serially, e.g., obtaining the current time before retrieving the timestamp ti and the endurance bit.

[0106] Figure 8B A flow diagram illustrating a third exemplary method of read reference voltage management is shown in accordance with some aspects of the present disclosure. From Figure 8A Continuing, at 820 in Figure 8B The memory controller 404 can compare the threshold time to the difference between the timestamp t2 and the timestamp ti at 820 in Figure 8B The threshold time (t drift ) used in Figure 6 may be the same or different from the threshold time used in Meanwhile, the endurance bit 508 stored earlier can be evaluated at 822. Depending on the evaluation results of the endurance bit 508 and the time difference between the timestamp t2 and the timestamp ti, various read reference voltage options can be provided for the read operation at 824, where at least a portion of the read reference voltages provided by the read reference voltage options can be different.

[0107] Figure 8B An exemplary method is provided where the timestamp 506 and the endurance bit 508 are equally considered and weighted to determine the read reference voltage. Thus, the evaluation sequence of the operations 820 and 822 can be interchanged in Figure 8B However, in other implementations, different weights can be given between the timestamp 506 and the endurance bit 508, respectively. Thus, the timestamp 506 and the endurance bit 508 can be evaluated in a certain order for determining the read reference voltage.

[0108] For example, Figure 8C A flow diagram illustrating a fourth exemplary method of read reference voltage management is shown in accordance with some aspects of the present disclosure, where the endurance bit 508 can be evaluated before the timestamp 506 at 830 and given a greater weight. Once the value of the endurance bit 508 is equal to “1”, the memory controller 404 can determine to apply a certain read reference voltage at 832, because according to the determination, the lifetime of the physical address of the PCM device can be close to the lifetime limit. On the other hand, when the value of the endurance bit 508 is equal to “0”, the memory controller 404 can further evaluate the timestamp 506 at 834 and thus determine the read reference voltage by one of the read reference voltage options at 836. At least a portion of the read reference voltages provided by the read reference voltage options can be different. In this way, the endurance bit 508 can be assigned a greater weight before the timestamp 506.

[0109] However, in other implementations, the timestamp 506 can be assigned a greater weight than the endurance bit 508. Figure 8D A flow diagram illustrating a fifth exemplary method of read reference voltage management is shown in accordance with some aspects of the present disclosure. With reference to Figure 8CIn contrast to the method provided in FIG. 8, at 840, the timestamp 506 can be evaluated before the endurance bit 508. Once the value of the time difference between the timestamp t2 and the timestamp t1 is greater than a threshold time (which can be the same or different from those in Figure 6 and Figure 8C ), the memory controller 404 can determine to apply a certain read reference voltage at 842, because at that determination, the latency can be relatively long and thus close to the time limit. On the other hand, when the value of the time difference is less than the threshold time at 840, the memory controller 404 can further evaluate the endurance bit 508 at 844 and thus determine the read reference voltage option by one of the read reference voltage options at 846. At least a portion of the read reference voltages provided by the read reference voltage options can be different. In this way, a greater weight can be assigned to the timestamp 506 in the address mapping table 500 according to Figure 8D .

[0110] In view of the above, the present disclosure provides an inventive solution in which the corresponding Vread option can be determined according to one or more PCM parameters. The one or more PCM parameters can include the timestamp 506 and the endurance bit 508. Thus, the solution provided by the present disclosure can effectively reduce the error rate of read / write operations to guarantee system performance. Moreover, in contrast to using a complex read retry algorithm in other methods, the procedure according to the present disclosure is simplified, and thus the read latency can be reduced.

[0111] Furthermore, since the address mapping table is easy to implement in a storage system, the one or more PCM parameters can also be stored in the address mapping table. In some embodiments of the present disclosure, the one or more PCM parameters (e.g., the endurance bit and the timestamp can) are also stored in the address mapping table corresponding to the physical address without incurring additional overhead. Such embodiments effectively utilize the free space of the address mapping table, and can reduce the frequency of accessing the storage system. That is, every time when the address mapping table is accessed, the corresponding information of the one or more PCM parameters can be easily obtained.

[0112] The foregoing description of certain implementations can be readily modified and / or adapted by those skilled in the art without departing from the scope and spirit of this disclosure. The foregoing description teaches those skilled in the art in the art sufficient to enable them to adopt and / or modify the teachings of the present disclosure to their use. The appended claims are intended to cover all such adaptations and modifications as they can fall within the equivalent of the scope of the disclosed implementations.

[0113] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A storage system comprising: a storage device including one or more storage units associated with one or more physical addresses; and a memory controller coupled to the storage device and configured to: obtain one or more parameters corresponding to a physical address of the one or more physical addresses stored in an address mapping table; and determine a read reference voltage for a read operation to the physical address of the storage device based on the one or more parameters, wherein the one or more parameters include a timestamp including a time at which a write operation to the physical address is performed.

2. The storage system of claim 1, wherein: the one or more parameters further include a durability bit; and the durability bit includes information about whether a cycle count of read / write operations to the physical address is greater than a threshold cycle. the memory controller is further configured to:

3. The storage system of claim 2, wherein, obtain the durability bit and the timestamp corresponding to the physical address from the address mapping table when the write operation to the physical address is performed, and obtain a current time at which the read operation to the physical address is to be performed; determine a comparison result of a time difference between the timestamp and the current time and a threshold time; and provide different read reference voltages for the read operation to the physical address in response to different combinations of the comparison result and the durability bit.

4. The storage system of claim 2, wherein: the durability bit includes a binary value of 1 or 0. the memory controller is further configured to: obtain the durability bit corresponding to the physical address from the address mapping table when the write operation to the physical address is performed; 5. The storage system of claim 4, wherein, provide a first read reference voltage for the read operation to the physical address in response to the durability bit being equal to 1; and provide a second read reference voltage for the read operation in response to the durability bit being equal to 0, the first read reference voltage being different from the second read reference voltage. the memory controller is further configured to: obtain the timestamp corresponding to the physical address from the address mapping table when the write operation to the physical address is performed, and obtain a current time at which the read operation to the physical address is to be performed; provide a third read reference voltage for the read operation to the physical address in response to a time difference between the current time and the timestamp being greater than a threshold time; and 6. The storage system of claim 4, wherein, provide a fourth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time, the third read reference voltage being different from the fourth read reference voltage. the memory controller is further configured to: obtain the durability bit and the timestamp corresponding to the physical address from the address mapping table when the write operation to the physical address is performed, and obtain a current time at which the read operation to the physical address is to be performed; provide a fifth read reference voltage for the read operation in response to a time difference between the current time and the timestamp being greater than a threshold time and the durability bit being equal to 1; and provide a sixth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0, the fifth read reference voltage being different from the sixth read reference voltage.

7. The storage system of claim 4, wherein, ​ ​ ​ in response to the time difference being greater than the threshold time and the durability bit being equal to 0, providing a sixth read reference voltage for the read operation; in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1, providing a seventh read reference voltage for the read operation; and in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0, providing an eighth read reference voltage for the read operation, at least a portion of the fifth read reference voltage, the sixth read reference voltage, the seventh read reference voltage, and the eighth read reference voltage being different.

8. The storage system of claim 4, wherein, The memory controller is further configured to: obtain, from the address mapping table, the durability bit and the timestamp corresponding to the physical address when the write operation is performed on the physical address, and obtain a current time at which the read operation is to be performed on the physical address; in response to the durability bit being equal to 1, provide a ninth read reference voltage for the read operation; in response to the durability bit being equal to 0 and a time difference between the current time and the timestamp being greater than a threshold time, provide a tenth read reference voltage for the read operation; and in response to the durability bit being equal to 0 and the time difference being less than or equal to the threshold time, provide an eleventh read reference voltage for the read operation, at least a portion of the ninth read reference voltage, the tenth read reference voltage, and the eleventh read reference voltage being different.

9. The storage system of claim 4, wherein, The memory controller is further configured to: obtain, from the address mapping table, the durability bit and the timestamp corresponding to the physical address when the write operation is performed on the physical address, and obtain a current time at which the read operation is to be performed on the physical address; in response to a time difference between the current time and the timestamp being greater than a threshold time, provide a twelfth read reference voltage for the read operation; in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1, provide a thirteenth read reference voltage for the read operation; and in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0, provide a fourteenth read reference voltage for the read operation, at least a portion of the twelfth read reference voltage, the thirteenth read reference voltage, and the fourteenth read reference voltage being different.

10. The storage system of any one of claims 1-9, wherein, The memory device is a phase change memory (PCM) device, and each of the one or more memory cells comprises a PCM cell.

11. The storage system of any of claims 1-9, further comprising a dynamic random access memory (DRAM), wherein, The address mapping table is stored in the DRAM.

12. The storage system of any one of claims 1-9, wherein, The memory controller is further configured to: control the memory device to perform a write operation on the physical address, and obtain a current time as a timestamp; obtain, by a wear leveling management mechanism, a cycle count of read / write operations on the physical address; determine, from the cycle count, a durability bit corresponding to the physical address; and store, in the address mapping table, the timestamp and the durability bit corresponding to the physical address, the one or more parameters comprising the timestamp and the durability bit. The memory controller is further configured to: obtain, from the address mapping table, the durability bit and the timestamp corresponding to the physical address when the write operation is performed on the physical address, and obtain a current time at which the read operation is to be performed on the physical address; in response to a time difference between the current time and the timestamp being greater than a threshold time, provide a twelfth read reference voltage for the read operation; in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1, provide a thirteenth read reference voltage for the read operation; and in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0, provide a fourteenth read reference voltage for the read operation, at least a portion of the twelfth read reference voltage, the thirteenth read reference voltage, and the fourteenth read reference voltage being different. The memory device is a phase change memory (PCM) device, and each of the one or more memory cells comprises a PCM cell. The address mapping table is stored in the DRAM. The memory controller is further configured to: control the memory device to perform a write operation on the physical address, and obtain a current time as a timestamp; obtain, by a wear leveling management mechanism, a cycle count of read / write operations on the physical address; determine, from the cycle count, a durability bit corresponding to the physical address; and store, in the address mapping table, the timestamp and the durability bit corresponding to the physical address, the one or more parameters comprising the timestamp and the durability bit.

13. A memory controller coupled to a memory device comprising one or more storage units associated with one or more physical addresses, the memory controller comprising: a processor; and a memory coupled to the processor and storing instructions that, when executed by the processor, cause the processor to: obtain one or more parameters corresponding to a physical address of the one or more physical addresses stored in an address mapping table; and determine, based on the one or more parameters, a read reference voltage for a read operation to the physical address of the memory device, wherein the one or more parameters comprise a timestamp comprising a time at which a write operation to the physical address was performed.

14. The memory controller of claim 13, wherein: the one or more parameters further comprise a durability bit; and the durability bit comprises information about whether a cycle count of read / write operations to the physical address is greater than a threshold cycle. the instructions further cause the processor to:

15. The memory controller of claim 14, wherein, obtain, from the address mapping table, the durability bit and the timestamp corresponding to the physical address at the time of the write operation to the physical address, and obtain a current time at which the read operation is to be performed to the physical address; determine a comparison result of a time difference between the timestamp and the current time to a threshold time; and provide different read reference voltages for the read operation to the physical address in response to different combinations of the comparison result and the durability bit.

16. The memory controller of claim 14, wherein: the durability bit comprises a binary value of 1 or 0. the instructions further cause the processor to: obtain, from the address mapping table, the durability bit corresponding to the physical address at the time of the write operation to the physical address; 17. The memory controller of claim 16, wherein, provide a first read reference voltage for the read operation to the physical address in response to the durability bit being equal to 1; and provide a second read reference voltage for the read operation in response to the durability bit being equal to 0, the first read reference voltage being different from the second read reference voltage. the instructions further cause the processor to: obtain, from the address mapping table, the timestamp corresponding to the physical address at the time of the write operation to the physical address, and obtain a current time at which the read operation is to be performed to the physical address; provide a third read reference voltage for the read operation to the physical address in response to a time difference between the current time and the timestamp being greater than a threshold time; and 18. The memory controller of claim 16, wherein, provide a fourth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time, the third read reference voltage being different from the fourth read reference voltage. the instructions further cause the processor to: obtain, from the address mapping table, the durability bit and the timestamp corresponding to the physical address at the time of the write operation to the physical address, and obtain a current time at which the read operation is to be performed to the physical address; ​ ​ 19. The memory controller of claim 16, wherein, ​ ​ in response to a time difference between the current time and the timestamp being greater than a threshold time and the durability bit being equal to 1, providing a fifth read reference voltage for the read operation; in response to the time difference being greater than the threshold time and the durability bit being equal to 0, providing a sixth read reference voltage for the read operation; in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1, providing a seventh read reference voltage for the read operation; and in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0, providing an eighth read reference voltage for the read operation, at least a portion of the fifth read reference voltage, the sixth read reference voltage, the seventh read reference voltage, and the eighth read reference voltage being different.

20. The memory controller of claim 16, wherein, The instructions further cause the processor to: obtain, from the address mapping table, the durability bit and the timestamp corresponding to the physical address when the write operation is performed on the physical address, and obtain a current time at which the read operation is to be performed on the physical address; in response to the durability bit being equal to 1, provide a ninth read reference voltage for the read operation; in response to the durability bit being equal to 0 and a time difference between the current time and the timestamp being greater than a threshold time, provide a tenth read reference voltage for the read operation; and in response to the durability bit being equal to 0 and the time difference being less than or equal to the threshold time, provide an eleventh read reference voltage for the read operation, at least a portion of the ninth read reference voltage, the tenth read reference voltage, and the eleventh read reference voltage being different.

21. The memory controller of claim 16, wherein, The instructions further cause the processor to: obtain, from the address mapping table, the durability bit and the timestamp corresponding to the physical address when the write operation is performed on the physical address, and obtain a current time at which the read operation is to be performed on the physical address; in response to a time difference between the current time and the timestamp being greater than a threshold time, provide a twelfth read reference voltage for the read operation; in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1, provide a thirteenth read reference voltage for the read operation; and in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0, provide a fourteenth read reference voltage for the read operation, at least a portion of the twelfth read reference voltage, the thirteenth read reference voltage, and the fourteenth read reference voltage being different.

22. The memory controller of any of claims 13-21, wherein, The memory device is a phase change memory (PCM) device, and each of the one or more memory cells comprises a PCM cell.

23. The memory controller of any of claims 13-21, wherein, The address mapping table is stored in a dynamic random access memory (DRAM).

24. The memory controller of any of claims 13-21, wherein, The instructions further cause the processor to: control the memory device to perform a write operation on the physical address, and obtain a current time as a timestamp; obtain, by a wear leveling management mechanism, a cycle count of read / write operations on the physical address; determine, according to the cycle count, a durability bit corresponding to the physical address; and storing the timestamp and the durability bit corresponding to the physical address in the address map table, the one or more parameters including the timestamp and the durability bit.

25. A method for read reference voltage management implemented to a memory device including one or more storage units associated with one or more physical addresses, the method comprising: obtaining one or more parameters corresponding to one of the one or more physical addresses stored in an address map table; and determining a read reference voltage for a read operation to the physical address of the memory device based on the one or more parameters, wherein the one or more parameters include a timestamp including a time at which a write operation to the physical address is performed.

26. The method of claim 25, wherein: the one or more parameters further include a durability bit; and the durability bit includes information on whether a cycle count of read / write operations to the physical address is greater than a threshold cycle.

27. The method of claim 26, further comprising obtaining a current time at which the read operation to the physical address is to be performed when the write operation to the physical address is performed, wherein: obtaining the one or more parameters includes: obtaining the durability bit corresponding to the physical address from the address map table when the write operation to the physical address is performed; and determining the read reference voltage based on the one or more parameters includes: determining a comparison result of a time difference between the timestamp and the current time and a threshold time; and providing different read reference voltages for the read operation to the physical address in response to different combinations of the comparison result and the durability bit.

28. The method of claim 26, wherein: the durability bit includes a binary value of 1 or 0.

29. The method of claim 28, further comprising: obtaining a current time at which the read operation to the physical address is to be performed when the write operation to the physical address is performed, wherein: obtaining the one or more parameters includes: obtaining the durability bit corresponding to the physical address from the address map table when the write operation to the physical address is performed; and determining the read reference voltage based on the one or more parameters includes: providing a first read reference voltage for the read operation to the physical address in response to the durability bit being equal to 1; and providing a second read reference voltage for the read operation in response to the durability bit being equal to 0, the first read reference voltage being different from the second read reference voltage.

30. The method of claim 28, further comprising: obtaining a current time at which the read operation to the physical address is to be performed when the write operation to the physical address is performed, wherein: obtaining the one or more parameters includes: obtaining the timestamp corresponding to the physical address from the address map table when the write operation to the physical address is performed; and determining the read reference voltage based on the one or more parameters includes: providing a third read reference voltage for the read operation to the physical address in response to a time difference between the current time and the timestamp being greater than a threshold time; and providing a fourth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time, the third read reference voltage being different from the fourth read reference voltage.

31. The method of claim 28, further comprising: obtaining a current time at which the read operation will be performed on the physical address when the write operation is performed on the physical address, wherein: obtaining the one or more parameters comprises: obtaining the durability bit and the timestamp corresponding to the physical address from the address mapping table when the write operation is performed on the physical address; and determining the read reference voltage based on the one or more parameters comprises: providing a fifth read reference voltage for the read operation in response to the time difference being greater than the threshold time and the durability bit being equal to 0; providing a sixth read reference voltage for the read operation in response to the time difference being greater than the threshold time and the durability bit being equal to 0; providing a seventh read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 1; and providing an eighth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the durability bit being equal to 0, at least a portion of the fifth read reference voltage, the sixth read reference voltage, the seventh read reference voltage, and the eighth read reference voltage being different.

32. The method of claim 28, further comprising obtaining a current time at which the read operation will be performed on the physical address when the write operation is performed on the physical address, wherein: obtaining the one or more parameters comprises: obtaining the durability bit and the timestamp corresponding to the physical address from the address mapping table when the write operation is performed on the physical address; and determining the read reference voltage based on the one or more parameters comprises: providing a ninth read reference voltage for the read operation in response to the durability bit being equal to 1; providing a tenth read reference voltage for the read operation in response to the durability bit being equal to 0 and a time difference between the current time and the timestamp being greater than a threshold time; and providing an eleventh read reference voltage for the read operation in response to the durability bit being equal to 0 and the time difference being less than or equal to the threshold time, at least a portion of the ninth read reference voltage, the tenth read reference voltage, and the eleventh read reference voltage being different.

33. The method of claim 28, further comprising: obtaining a current time at which the read operation will be performed on the physical address when the write operation is performed on the physical address, wherein: obtaining the one or more parameters comprises: obtaining the durability bit and the timestamp corresponding to the physical address from the address mapping table when the write operation is performed on the physical address; and determining the read reference voltage based on the one or more parameters comprises: providing a twelfth read reference voltage for the read operation in response to the time difference being greater than the threshold time, providing a thirteenth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the endurance bit being equal to one; and providing a fourteenth read reference voltage for the read operation in response to the time difference being less than or equal to the threshold time and the endurance bit being equal to zero, at least some of the twelfth read reference voltage, the thirteenth read reference voltage, and the fourteenth read reference voltage being different.

34. The method of any one of claims 25-33, wherein, The memory device is a phase change memory (PCM) device, and each of the one or more memory cells comprises a PCM cell.

35. The method of any one of claims 25-33, wherein, The address mapping table is stored in a dynamic random access memory (DRAM).

36. The method of any one of claims 25-33, further comprising: controlling the memory device to perform a write operation on the physical address and obtain a current time as a time stamp; obtaining, by a wear leveling management mechanism, a cycle count of read / write operations on the physical address; determining an endurance bit corresponding to the physical address according to the cycle count; and storing the time stamp and the endurance bit corresponding to the physical address in the address mapping table.

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