Storage system, information processing system and host device

Abstract

According to one embodiment, a storage system, an information processing system, and a host device capable of controlling power consumption of the storage system are provided. A storage system of one embodiment can be connected to a host device. The storage system includes a nonvolatile memory and a controller for controlling the nonvolatile memory. The controller suppresses power consumption of the storage system according to a first instruction from the host device.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2021-47518 (filing date: March 22, 2021). This application incorporates all the contents of the basic application by reference. Technical Field

[0002] The present embodiment relates to a storage system, an information processing system, and a host device. Background Art

[0003] Storage systems such as SSD (Solid State Drive) have a controller and a non-volatile memory. The controller controls the processing of sending data read from the non-volatile memory to the host device and the processing of writing data received from the host device to the non-volatile memory according to the request from the host device. Furthermore, the controller performs a transcription process to move data within the non-volatile memory. In the storage system, power is consumed not only in the transmission and reception of data between the host device and the non-volatile memory, but also in the transcription process. Summary of the invention

[0004] According to one embodiment, an object is to provide a storage system and an information processing system in which a host device can control power consumption, and a host device in which the power consumption of the storage system can be controlled.

[0005] According to one embodiment, a storage system is connectable to a host device. The storage system includes a nonvolatile memory and a controller that controls the nonvolatile memory. The controller suppresses power consumption of the storage system according to a first instruction from the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a schematic diagram showing an example of the configuration of the information processing system according to the first embodiment.

[0007] Figure 2 This is a schematic diagram showing an example of the configuration of a memory chip according to the first embodiment.

[0008] Figure 3 It is a schematic diagram showing the circuit configuration of blocks according to the first embodiment.

[0009] Figure 4 This is a diagram for explaining each partition in each storage mode according to the first embodiment.

[0010] Figure 5 This is a diagram showing an example of state transition of blocks in the first embodiment.

[0011] Figure 6 This is a diagram for explaining an example of information transferred between the host device and the storage system according to the first embodiment.

[0012] Figure 7 This is a flowchart for explaining an example of the operation of garbage collection as an example of the dump processing according to the first embodiment.

[0013] Figure 8 This is a flowchart for explaining an example of the operation of ejection which is another example of the transfer processing according to the first embodiment.

[0014] Fig. 9 This is a flowchart for explaining an example of the operation related to the transition of the operation mode in the first embodiment.

[0015] Fig.10 This is a diagram for explaining an example of a method of selecting a block BLK as a transfer source in garbage collection according to the second embodiment.

[0016] Fig.11 This is a flowchart for explaining an example of the operation related to the transition of the operation mode in the second embodiment.

[0017] Fig.12 This is a schematic diagram showing an example of a power consumption plan generated by the controller according to the third embodiment.

[0018] Fig.13 This is a flowchart for explaining an example of the operation related to the transition of the operation mode in the third embodiment.

[0019] Fig.14 This is a schematic diagram showing an example of the configuration of a storage system according to the third embodiment.

[0020] Fig.15 This is a diagram for explaining an example of a method for the storage system according to the third embodiment to receive information related to power consumption.

[0021] Fig.16 16 (A) and 16 (B) are diagrams for explaining a modification example of the power consumption plan according to the third embodiment.

[0022] Fig.17 This is a schematic diagram showing an example of a power consumption plan generated by the controller according to the fourth embodiment.

[0023] Fig.18 This is a flowchart for explaining an example of the operation related to the transition of the operation mode in the fourth embodiment.

[0024] Fig.19 This is a flowchart for explaining an example of operations related to transition of the operation mode in the fifth embodiment.

[0025] Fig. 20 This is a flowchart showing an example of the operation of the storage system according to the sixth embodiment in the power amount limitation mode.

[0026] Fig.21 This is a flowchart showing an example of the operation of the storage system according to the seventh embodiment in the power amount limitation mode.

[0027] Fig. 22 This is a flowchart showing an example of the operation of the storage system according to the eighth embodiment in the power amount limitation mode.

[0028] Fig.23 This is a diagram for explaining an example of a method in which the storage system according to the ninth embodiment sends operating status information to a host device.

[0029] Description of symbols

[0030] 1 storage system, 2 host device, 3 communication interface, 4 partition, 5 power supply device, 6 power supply line, 10 information processing system, 100 controller, 101 processor, 102 host interface, 103 RAM, 104 buffer memory, 105 memory interface, 106 internal bus, 200 NAND memory, 201 memory chip, 210 peripheral circuit, 211 storage cell array, 212 NAND string, 300 memory bus, 400 power supply circuit, 401 measurement circuit. DETAILED DESCRIPTION

[0031] Hereinafter, a storage system, an information processing system, and a host device according to the embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to these embodiments.

[0032] (First embodiment)

[0033] Figure 1 This is a schematic diagram showing an example of the configuration of the information processing system 10 according to the first embodiment.

[0034] The information processing system 10 is, for example, various computers, servers, etc. Among the various computers, portable computers are laptop personal computers, mobile phones, smart phones, portable music players, camera devices, etc. The host device 2 is, for example, a processor provided in the information processing system 10. The storage system 1 is, for example, an SSD. The storage system 1 can also be externally connected to various computers, servers, etc.

[0035] The storage system 1 is connected to the host device 2 via the communication interface 3. The host device 2 can use the storage system 1 as a data storage. The standard of the communication interface 3 is not limited to a specific standard. For example, SAS (Serial Attached SCSI), SATA (Serial ATA), PCI express (PCIe, registered trademark) or NVM express (NVMe, registered trademark) can be adopted as the standard of the communication interface 3.

[0036] The storage system 1 receives an access command (eg, a write command or a read command) from the host device 2. The storage system 1 stores the user data requested to be written in accordance with the write command. The storage system 1 sends the user data requested to be read to the host device 2 in accordance with the read command.

[0037] In addition, the access command includes a logical address. The storage system 1 provides a logical address space to the host device 2. The logical address indicates a location in the address space. The host device 2 specifies a location to write user data or a location to read user data by using the logical address. That is, the logical address is location information specified by the host device 2.

[0038] The storage system 1 includes a controller 100 and a NAND memory 200. The controller 100 is connected to the NAND memory 200 via a memory bus 300. The NAND memory 200 is an example of a nonvolatile memory.

[0039] The controller 100 performs control of the NAND memory 200 .

[0040] The controller 100 writes data requested to be written by the host device 2 to the NAND memory 200, and reads data requested to be read by the host device 2 from the NAND memory 200 and sends it to the host device 2. That is, the controller 100 performs data transfer between the host device 2 and the NAND memory 200. The data transfer between the host device 2 and the NAND memory 200 is described as a host access process.

[0041] Furthermore, the controller 100 performs a transfer process of transferring data in the NAND memory 200. The transfer process includes garbage collection or eviction, etc. The details of the transfer process will be described later.

[0042] The controller 100 includes a processor 101, a host interface (host I / F) 102, a RAM (Random Access Memory) 103, a buffer memory 104, a memory interface (memory I / F) 105, and an internal bus 106. The processor 101, the host I / F 102, the RAM 103, the buffer memory 104, and the memory I / F 105 are electrically connected to the internal bus 106.

[0043] In addition, the controller 100 may be configured as a system-on-a-chip (SoC). Alternatively, the controller 100 may be configured by a plurality of chips. The RAM 103 or the buffer memory 104 may also be arranged outside the controller 100 .

[0044] The host I / F 102 outputs the access command and user data received from the host device 2 to the internal bus 106 . The user data is sent to the buffer memory 104 via the internal bus 106 .

[0045] In addition, the host I / F 102 transmits user data read from the NAND memory 200 , a response from the processor 101 , and the like to the host device 2 .

[0046] The buffer memory 104 is a memory that functions as a cache for data transmission between the host device 2 and the NAND memory 200. The buffer memory 104 is composed of a volatile memory such as SRAM (Static Random Access Memory) or SDRAM (Synchronous Dynamic Random Access Memory). In addition, the type of memory constituting the buffer memory 104 is not limited to these. The buffer memory 104 can also be composed of any type of non-volatile memory.

[0047] The memory I / F 105 controls a process such as writing user data to the NAND memory 200 and a process such as reading user data from the NAND memory 200 based on an instruction from the processor 101 .

[0048] The processor 101 is a circuit capable of executing a computer program. The processor 101 is, for example, a CPU (Central Processing Unit). The processor 101 controls the components of the controller 100 in general based on a firmware program pre-stored in a predetermined location (e.g., NAND memory 200), thereby implementing various processes including host access processing and transfer processing.

[0049] In addition, part or all of the processing performed by the processor 101 may also be performed by a hardware circuit. Part or all of the processing performed by the processor 101 may also be performed by an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0050] The RAM 103 provides a function as a buffer, a cache memory, or a working memory for the processor 101. The RAM 103 is composed of a DRAM (Dynamic Random Access Memory), an SRAM, or a combination of these. The types of memories constituting the RAM 103 are not limited to these.

[0051] In addition, the controller 100 may include any components instead of or in addition to these components. For example, the controller 100 may include a circuit that performs predetermined processing (for example, encoding or decoding) on ​​user data.

[0052] The NAND memory 200 can store user data and the like in a nonvolatile manner. The NAND memory 200 is composed of one or more memory chips 201. Here, as an example, the NAND memory 200 is composed of four memory chips 201-0, 201-1, 201-2, and 201-3. The memory chip 201 is a memory chip of a NAND flash memory.

[0053] Figure 2 2 is a schematic diagram showing an example of the configuration of a memory chip 201 according to Embodiment 1. The memory chip 201 includes a peripheral circuit 210 and a memory cell array 211 .

[0054] The memory cell array 211 includes a plurality of blocks BLK (BLK0, BLK1, BLK2, ...), each of which is a collection of a plurality of nonvolatile memory cell transistors. Each block BLK includes a plurality of string units SU (SU0, SU1, SU2, ...), each of which is a collection of memory cell transistors associated with a word line and a bit line. Each string unit SU includes a plurality of NAND strings 212 in which a plurality of memory cell transistors are connected in series. In addition, the number of NAND strings 212 in the string unit SU is arbitrary.

[0055] The peripheral circuit 210 includes, for example, a row decoder, a column decoder, a sense amplifier, a latch circuit, and a voltage generating circuit. The peripheral circuit 210 performs operations corresponding to the instructions on the memory cell array 211 according to the instructions from the controller 100. The instructions from the controller 100 include writing, reading, and erasing.

[0056] Figure 3 2 is a schematic diagram showing a circuit configuration of a block BLK according to the first embodiment. Each block BLK has the same configuration. The block BLK includes, for example, four string units SU0 to SU3 . Each string unit SU includes a plurality of NAND strings 212 .

[0057] Each NAND string 212 includes, for example, 64 memory cell transistors MT (MT0 to MT63) and selection transistors ST1 and ST2. The memory cell transistor MT has a control gate and a charge storage layer to store data in a non-volatile manner. Furthermore, the 64 memory cell transistors MT (MT0 to MT63) are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. In addition, the memory cell transistor MT can be either a MONOS type using an insulating film for the charge storage layer or an FG type using a conductive film for the charge storage layer. Furthermore, the number of memory cell transistors MT in the NAND string 212 is not limited to 64.

[0058] The gate of the selection transistor ST1 in each of the string units SU0 to SU3 is connected to each selection gate line SGD0 to SGD3. In contrast, the gate of the selection transistor ST2 in each of the string units SU0 to SU3 is commonly connected to the selection gate line SGS, for example. The gate of the selection transistor ST2 in each of the string units SU0 to SU3 may also be connected to different selection gate lines SGS0 to SGS3 (not shown) for each string unit SU. The control gates of the memory cell transistors MT0 to MT63 in the same block BLK are commonly connected to each word line WL0 to WL63.

[0059] The drains of the selection transistors ST1 of each NAND string 212 in the string unit SU are connected to different bit lines BL (BL0 to BL (L-1), where L is a natural number greater than 2). In addition, the bit line BL connects one NAND string 212 in each string unit SU in common between multiple blocks BLK. Furthermore, the sources of the selection transistors ST2 are connected in common to the source line SL.

[0060] That is, the string unit SU is a collection of multiple NAND strings 212 connected to different bit lines BL and connected to the same selection gate line SGD. In addition, the block BLK is a collection of multiple string units SU that share a word line WL. And the memory cell array 211 is a collection of multiple blocks BLK that share at least one bit line BL.

[0061] Writing and reading by the peripheral circuit 210 can be performed together for the memory cell transistors MT connected to one word line WL in one string unit SU. The group of memory cell transistors MT selected together during writing and reading is recorded as a memory cell group MCG. Furthermore, the unit of a collection of 1-bit data written or read in one memory cell group MCG is recorded as a page.

[0062] Erasing by the peripheral circuit 210 is performed in units of blocks BLK. That is, all data stored in one block BLK is erased at once.

[0063] In addition, the configuration of the memory cell array 211 is not limited to Figure 2 and Figure 3 For example, the memory cell array 211 may have a structure in which NAND strings 212 are arranged in two or three dimensions.

[0064] In writing to the memory cell array 211, the peripheral circuit 210 injects an amount of charge corresponding to the data into the charge storage layer of each memory cell transistor MT constituting the page of the writing destination. And, in reading from the memory cell array 211, the peripheral circuit 210 reads data corresponding to the amount of charge accumulated in the charge storage layer from each memory cell transistor MT constituting the page of the reading destination.

[0065] Each memory cell transistor MT is capable of maintaining a value of n (n ≥ 1) bits. The mode in which n is 1 is called SLC (Single Level Cell). When each memory cell transistor MT maintains a value of n bits, the storage capacity of each memory cell group MCG is equal to the size of n pages. The mode in which n is 2 is called MLC. The mode in which n is 3 is called TLC. The mode in which n is 4 is called QLC (Quad Level Cell). These modes in which n-bit values ​​are maintained in one memory cell are recorded as storage modes.

[0066] The threshold voltage of each memory cell transistor MT is controlled within a certain range by the peripheral circuit 210. The controllable range of the threshold voltage is divided into 2n-power partitions, and a different n-bit value is assigned to each partition.

[0067] Figure 4 1 is a diagram for explaining each partition in each storage mode of the first embodiment. Figure 4 As shown, the range of threshold voltage (controllable range) is divided into multiple partitions 4. For example, in the case of SLC, the range of threshold voltage is divided into 2 partitions 4. In the case of MLC, the range of threshold voltage is divided into 4 partitions 4. In the case of TLC, the range of threshold voltage is divided into 8 partitions 4. In the case of QLC, the range of threshold voltage is divided into 16 partitions 4. The more bits of the value held in one storage cell, the narrower the range of each partition 4. A value is assigned to each partition 4. In the case of SLC, the value "1" is assigned to the partition 4 on the low voltage side, and the value "0" is assigned to the partition 4 on the high voltage side. In the case of MLC, the value "11" is assigned to the partition 4 on the lowest voltage side, and the other three partitions 4 are assigned "01", "00", and "10" in order of voltage. In addition, the method of assigning values ​​to each partition 4 is not limited to the above example. In addition, n, that is, the number of bits of the value held in a storage cell transistor MT, is sometimes recorded as the number of levels in the future.

[0068] In writing to the memory cell array 211, the peripheral circuit 210 injects an amount of charge corresponding to the partition 4 to which the data of the write object is allocated into the charge accumulation layer of each memory cell transistor MT constituting the page of the write destination. In reading from the memory cell array 211, the peripheral circuit 210 determines the partition 4 to which the threshold voltage of each memory cell transistor MT constituting the page of the read destination belongs, and outputs the data allocated to the partition 4 obtained by the determination as read data.

[0069] In erasing the memory cell array 211, the peripheral circuit 210 applies an erase voltage to the substrate side of the memory cell array 211. In addition, the peripheral circuit 210 conducts all word lines WL of the block BLK to be erased to the ground potential. As a result, the charge previously accumulated in the charge accumulation layer of each memory cell transistor MT in the selected block BLK is discharged. As a result, the state of each memory cell transistor MT in the selected block BLK changes to a state in which the data can be regarded as erased (i.e., the partition 4 on the lowest voltage side).

[0070] The storage system 1 may be configured to be capable of reading and writing only in a single storage mode. Alternatively, the storage system 1 may be configured to be capable of switching the storage mode during operation. When the storage mode can be switched, the range of the storage area of ​​the switching unit is arbitrary. For example, the storage system 1 may also be capable of switching the storage mode in units of blocks BLK.

[0071] When the storage system 1 is configured to be able to switch the storage mode during operation, the storage mode of a portion of the storage area (e.g., a portion of the blocks BLK) of the storage system 1 is fixed to the first storage mode, and the storage mode of the other portion (e.g., another portion of the blocks BLK) is fixed to the second storage mode different from the first storage mode, and the storage system 1 may select the block BLK of the write destination according to the storage mode to be used. Alternatively, the storage system 1 may be configured to be able to change the storage mode of the storage area (e.g., each block BLK) between multiple storage modes during operation.

[0072] In the following description, it is assumed that the storage system 1 is configured to be able to switch the storage mode between SLC and TLC as an example.

[0073] Next, the state transition of the block BLK will be described. Figure 5 1 is a diagram showing an example of state transition of the block BLK according to the first embodiment. The hatched arrows indicate state transition of the block BLK, and the solid arrows indicate movement of data.

[0074] The states of the block BLK include at least an open block, an active block, and a free block. One or more active blocks constitute an active block pool, and one or more free blocks constitute a free block pool.

[0075] An open block is a block in the process of writing data. In other words, an open block is a block in which there is a remaining area where data can be written.

[0076] An active block is a block that cannot be reused among blocks to which data has been written. A block that stores valid user data among blocks to which data has been written is managed as an active block. Reuse means converting it into an open block.

[0077] A free block is a block that does not store valid user data and can be reused.

[0078] For example, after data of one BLK block is written to an open block, the open block is changed to an active block. The data stored in the active block is either valid or invalid.

[0079] When certain data (recorded as first data) is stored in the active block, and second data is sent by specifying the same logical address value as the logical address value specified when the first data is sent from the host device 2, the controller 100 writes the second data to an empty page of the open block and manages the first data stored in the active block as invalid data. As a result, valid user data and invalid user data may be mixed in the data stored in the active block.

[0080] Furthermore, designating the same logical address value as the logical address value designated when the host device 2 sent the old data to the storage system 1 and sending the new data is described as rewriting.

[0081] The active block is transformed into a free block through garbage collection. Garbage collection refers to the following process: the valid data stored in the block BLK as the active block is transcribed to the block BLK as the open block, so that all the data stored in the block BLK of the transcribe source is invalidated. Thus, the block BLK of the transcribe source is transformed from the active block to the free block. In addition, transcribe can be expressed alternatively as transfer or move.

[0082] A free block is converted into an open block after the stored data is erased.

[0083] In addition, data is valid means that the location where the data is stored is associated with a certain logical address value. Data is invalid means that the location where the data is stored is not associated with any logical address value. In addition, the "empty" state here refers to a state in which no data among invalid data and valid data is stored. That is, an empty page is an idle area where data can be written. In addition, the controller 100 maintains and updates the correspondence between the location in the block BLK and the logical address value.

[0084] Alternatively, open blocks may be prepared separately for each of the host access process and the transfer process. Alternatively, open blocks for the host access process and open blocks for the transfer process may be prepared. If the storage mode can be switched in units of blocks BLK, open blocks may be prepared for each storage mode.

[0085] In addition to garbage collection, the dump process also includes eviction, which is performed when the storage system 1 is configured to be able to use two or more different storage modes.

[0086] For example, consider a storage system configured to be able to switch the storage mode when writing between a first storage mode and a second storage mode having a smaller number of layers than the first storage mode. In such a storage system, when writing in the second storage mode, a storage area with a larger capacity is required compared to when writing in the first storage mode. Therefore, when writing in the second storage mode, the amount of free blocks consumed increases compared to when writing in the first storage mode, and the total amount of data that can be written to the storage system decreases. Therefore, when writing of data in the second storage mode is completed, the controller then reads the data and writes the read data back in the first storage mode. As a result, the number of free blocks is restored, and the total amount of data that can be written to the storage system is restored. Eviction is a process in which, after writing of data in the second storage mode is completed, the data is read and the read data is written back in the first storage mode.

[0087] In the eviction, for example, an active block to which data is written in the second storage mode is selected as a transfer source, and valid data is read from the selected transfer source. Furthermore, the read valid data is written to another block BLK (open block) in the first storage mode. When the movement of all valid data in the block BLK of the transfer source is completed, the block BLK of the transfer source is changed from an active block to a free block. Thus, a free block is also generated by eviction.

[0088] The host device 2 may wish to control the power consumption of the storage system 1. For example, if the information processing system 10 is a portable computer equipped with a battery, the power consumption of the storage system 1 may be controlled according to whether the information processing system 10 is connected to a power source or the like. When the information processing system 10 is connected to a power source, the information processing system 10 can use abundant power from the power source, and thus can fully supply the power required by the storage system 1 to the storage system 1. When the information processing system 10 is not connected to a power source and operates using the energy stored in the battery, the information processing system 10 reduces the amount of power supplied to the storage system 1 compared to when the information processing system 10 is connected to a power source.

[0089] In an embodiment, the storage system 1 is configured to be able to receive information related to the amount of electric power from the host device 2. In the first embodiment, the storage system 1 is able to receive an indication of electric power limitation as an example of information related to the amount of electric power. When receiving the indication of electric power limitation, the operation mode of the storage system 1 is changed to an operation mode in which the power consumption is suppressed. In addition, the operation mode in which the power consumption is not suppressed is recorded as a normal mode. The operation mode in which the power consumption is suppressed is recorded as a power limit mode.

[0090] In the power limit mode, the controller 100 reduces the amount of processing of the transfer process compared to the case of the normal mode. The method of reducing the amount of processing of the transfer process is not limited to a specific method.

[0091] In one example, the controller 100 makes the execution frequency of the transfer process different between the normal mode and the power limit mode. That is, the controller 100 makes the execution frequency of the transfer process in the power limit mode lower than the execution frequency of the transfer process in the normal mode. In the power limit mode, the processing amount of the transfer process is reduced as the execution frequency of the transfer process is reduced compared to the normal mode. In the power limit mode, the power consumption of the storage system 1 is suppressed as the processing amount of the transfer process is reduced as compared to the normal mode.

[0092] In other examples, the controller 100 makes the start condition of the transfer processing different in the normal mode and the power limit mode. For example, in the case where the number of free blocks is lower than the determination threshold as the start condition of garbage collection (or expulsion), different values ​​are used as the determination threshold in the normal mode and the power limit mode. Specifically, the controller 100 uses the first set value as the determination threshold in the normal mode, and uses the second set value that is smaller than the first set value as the determination threshold in the power limit mode. As a result, in the power limit mode, it becomes difficult to perform garbage collection (or expulsion) compared to the normal mode, and the processing volume of garbage collection (or expulsion) is reduced. In the power limit mode, the power consumption of the storage system 1 is suppressed in accordance with the reduction in the processing volume of garbage collection (or expulsion) compared to the normal mode.

[0093] The processes whose processing volume is reduced in the power limit mode may be all dump processes or only some dump processes. For example, only garbage collection, only eviction, or both may be the targets.

[0094] In this way, the controller 100 performs an operation corresponding to the operation mode. That is, the operation mode of the storage system 1 can be regarded as the operation mode of the controller 100. Hereinafter, the operation mode of the controller 100 is assumed to mean the operation mode of the storage system 1.

[0095] Next, the operation of the information processing system 10 according to the first embodiment will be described.

[0096] Figure 6 FIG. 1 is a diagram for explaining an example of information transmitted between the host device 2 and the storage system 1 in the first embodiment. Figure 6 In the description of , it is assumed that in the initial state, the operation mode of the storage system 1 is the normal mode.

[0097] The host device 2 can read and write data from the storage system 1 in the normal mode (S101). When the host device 2 wishes to change the operation mode of the storage system 1 to the power limit mode, it sends a power limit instruction to the storage system 1 (S102).

[0098] For example, in NVMe (registered trademark) and the like, actual operations are not defined for all command values. Manufacturers can assign command values ​​for undefined operations to arbitrary operations. Such command values ​​that manufacturers can assign to arbitrary operations are called vendor specific. Manufacturers can assign vendor specific command values ​​prepared according to the standard of communication interface 3 to power limit indications. For the power limit release indication described later, other vendor specific command values ​​can also be assigned.

[0099] Alternatively, the power amount limitation instruction (and the power amount limitation release instruction) may be added to the standard of the communication interface 3 .

[0100] Alternatively, the host device 2 and the storage system 1 may be connected via a dedicated signal line for transmitting a power limitation indication (and a power limitation release indication), and the host device 2 may send a power limitation indication (and a power limitation release indication) to the storage system 1 via the dedicated signal line.

[0101] When receiving the power limit instruction, the storage system 1 changes from the normal mode to the power limit mode. The host device 2 can read and write data from the storage system 1 in the power limit mode (S103).

[0102] When the host device 2 wishes to return the operation mode of the storage system 1 from the power limit mode to the normal mode, it sends a power limit release instruction to the storage system 1 (S104). When the storage system 1 receives the power limit release instruction, it changes from the power limit mode to the normal mode. The host device 2 can read data from the storage system 1 in the normal mode and write data (S105).

[0103] Thereafter, the host device 2 and the storage system 1 can repeatedly perform the same operations as S101 to S105 .

[0104] Figure 7 This is a flowchart for explaining an example of the operation of garbage collection as an example of the dump processing according to the first embodiment.

[0105] The controller 100 determines whether to execute garbage collection (S201). The method for determining whether to execute garbage collection is not limited to a specific method. For example, as described above, the controller 100 can determine whether to execute garbage collection based on a comparison between the number of free blocks and a determination threshold. Alternatively, the controller 100 can determine whether to execute garbage collection in such a way that the execution frequency of garbage collection reaches a predetermined frequency.

[0106] When it is determined that garbage collection is not to be performed ( S201 : No), the controller 100 performs the determination process of S201 again.

[0107] When it is determined that garbage collection is to be performed ( S201 : Yes), the controller 100 selects an active block as a block BLK of a dump source ( S202 ).

[0108] Then, the controller 100 transfers all valid data stored in the block BLK of the transfer source to the block BLK of the transfer destination (S203). That is, the controller 100 copies all valid data stored in the block BLK of the transfer source to the block BLK of the transfer destination, and invalidates all data stored in the transfer source. Thus, the valid data previously stored in the block BLK of the transfer source is transferred to the block BLK of the transfer destination. In addition, the block BLK of the transfer destination is a block BLK set as an open block.

[0109] Then, the controller 100 sets the block BLK of the transfer source as a free block ( S204 ).

[0110] Then, control is transferred to S201.

[0111] Figure 8 This is a flowchart for explaining an example of the operation of ejection which is another example of the transfer processing according to the first embodiment.

[0112] The controller 100 determines whether to execute eviction (S301). The method for determining whether to execute eviction is not limited to a specific method. For example, as described above, the controller 100 can determine whether to execute eviction based on a comparison between the number of free blocks and a determination threshold. Alternatively, the controller 100 can determine whether to execute garbage collection in such a way that the execution frequency of eviction reaches a predetermined frequency.

[0113] When it is determined that the ejection is not to be performed ( S301 : No), the controller 100 performs the determination process of S301 again.

[0114] When it is determined that the eviction is to be performed ( S301 : Yes), the controller 100 selects an active block to which data is written in the SLC mode as a block BLK of the transfer source ( S302 ).

[0115] Then, the controller 100 transfers all valid data stored in the block BLK of the transfer source to the block BLK of the transfer destination in the TLC mode (S303). That is, the controller 100 writes all valid data stored in the block BLK of the transfer source to the block BLK of the transfer destination in the TLC mode, invalidating all data stored in the transfer source. Thus, the valid data stored in the block BLK of the transfer source is transferred to the block BLK of the transfer destination. In addition, the block BLK of the transfer destination is a block BLK set as an open block and a block BLK to which data is written in the TLC mode.

[0116] Then, the controller 100 sets the block BLK of the transfer source as a free block ( S304 ).

[0117] Then, control is transferred to S301.

[0118] Fig. 9 is a flowchart for explaining an example of the operation involved in the transition of the operation mode of the first embodiment. Fig. 9 In the description of , it is assumed that the operation mode of the storage system 1 in the initial state is the normal mode.

[0119] The controller 100 determines whether or not a power limit instruction is received from the host device 2 (S401). When it is determined that no power limit instruction is received (S401: No), the controller 100 executes the determination process of S401 again.

[0120] When it is determined that the power limit instruction is received (S401: Yes), the controller 100 changes from the normal mode to the power limit mode (S402). That is, the controller 100 reduces the processing amount of the transfer process.

[0121] After S402, the controller 100 determines whether or not a power limit release instruction has been received from the host device 2 (S403). If it is determined that the power limit release instruction has not been received (S403: No), the controller 100 executes the determination process of S403 again.

[0122] If it is determined that the power limit release instruction has been received (S403: Yes), the controller 100 changes from the power limit mode to the normal mode (S404). That is, the controller 100 releases the reduction in the processing amount of the dump process.

[0123] Then, control is transferred to S401.

[0124] Furthermore, in the above description, the storage system 1 changes from the power limitation mode to the normal mode according to the power limitation release instruction. The trigger for changing from the power limitation mode to the normal mode is not limited to the reception of the power limitation release instruction alone. The controller 100 may also autonomously change the operation mode of the storage system 1 from the power limitation mode to the normal mode. For example, when the elapsed time since the operation mode of the storage system 1 was changed to the power limitation mode reaches a predetermined time, the controller 100 may also change the operation mode of the storage system 1 from the power limitation mode to the normal mode. Alternatively, the controller 100 may also change the operation mode of the storage system 1 from the power limitation mode to the normal mode when it becomes difficult to continuously reduce the processing volume of the transfer processing.

[0125] As described above, according to the first embodiment, the controller 100 can perform data transfer processing for transferring data between the host device 2 and the NAND memory 200 and transfer processing for transferring data within the NAND memory 200. In addition, the controller 100 reduces the processing amount of the transfer processing according to the power limit instruction from the host device 2.

[0126] Since the storage system 1 is configured as described above, the power consumption of the storage system 1 can be controlled by the host device 2 .

[0127] (Second embodiment)

[0128] In the second embodiment, the garbage collection operation in the transfer process is different in the normal mode and the power consumption limited mode. More specifically, the strategy for selecting the block BLK of the transfer source in the garbage collection is different in the normal mode and the power consumption limited mode. In the second embodiment, the differences from the first embodiment are described, and the description of the same points as the first embodiment is omitted or briefly described. In addition, the second embodiment can be used together with the first embodiment.

[0129] Fig.10 This is a diagram for explaining an example of a method of selecting a block BLK as a dump source in garbage collection according to the second embodiment.

[0130] exist Fig.10 , a plurality of (here, six as an example) blocks BLK are depicted. Assume that the six blocks BLK are active blocks, and the active blocks of the storage system 1 are all of the six blocks BLK. Fig.10In the figure, the six blocks BLK are arranged in the order of the time when they are transformed into active blocks (in other words, the time when the data is last written). The six blocks BLK are recorded as blocks BLKa~BLKf. Here, the time when block BLKa is transformed into an active block is the latest, and the time when they are transformed into active blocks is from late to early in the order of block BLKa, block BLKb, block BLKc, block BLKd, and block BLKe. In each block of blocks BLKa~BLKf, the area of ​​the oblique line corresponds to the amount of valid data stored.

[0131] The controller 100 (eg, the processor 101 ) records the order of when each block BLK becomes an active block and the amount of valid data stored in each block BLK, and updates the recorded content at any time.

[0132] In the power amount limitation mode, the controller 100 selects the block BLK storing the least amount of valid data as the block BLK to be transferred in garbage collection. Fig.10 In the example of FIG. 1 , the controller 100 selects, for example, a block BLKc among six blocks BLKa to BLKf, each of which is an active block, as a block BLK of a transfer source.

[0133] In garbage collection, by moving valid data from the block BLK of the transfer source to the block BLK of the transfer destination, the block BLK of the transfer source can be set as a free block. The less the amount of valid data stored in the block BLK of the transfer source, the less the amount of data moved to generate one free block, and therefore, the less power is required to generate one free block. In the power limit mode, the block BLK with the least amount of valid data is selected as the block BLK of the transfer source in garbage collection, and the power required for garbage collection is suppressed.

[0134] Furthermore, in the power amount limitation mode, there is a case where the block BLK storing the smallest amount of valid data is not necessarily selected as the block BLK of the transfer source.

[0135] For example, the controller 100 may record the amount of valid data stored in each block BLK as inaccurate coarse-grained numerical information. In such a case, a block BLK storing a small amount of valid data can be found.

[0136] In other examples, there may be a time lag between the update timing of the amount of valid data stored in each block BLK and the change timing of the amount of valid data stored in each block BLK recorded by the controller 100. In such a case, a block BLK storing a small amount of valid data can be found.

[0137] In these examples, a block BLK storing less valid data can be preferentially selected as a transfer source block BLK. In the power limit mode, the method of selecting the transfer source block BLK can be variously changed as long as a block BLK storing less valid data is preferentially selected as a transfer source block BLK.

[0138] In another example of another method of preferentially selecting a block BLK with a small amount of valid data stored as a block BLK of a transfer source, the following method can be considered: the controller 100 stores an amount that is sufficiently small relative to the capacity of a block BLK as a threshold, and selects a block BLK of a transfer source in garbage collection based on a comparison between the amount of valid data stored and the threshold. The controller 100 can also search for a block BLK with an amount of valid data stored that is less than the threshold, and select the first block BLK found as the block BLK of a transfer source in garbage collection.

[0139] In the normal mode, the controller 100 (eg, the processor 101) selects the earliest block BLK to be turned into an active block, in other words, the earliest block BLK to which data was last written, as the block BLK to be transferred in garbage collection. Fig.10 In the example of FIG. 1 , the controller 100 selects the block BLKf as the block BLK of the transfer source.

[0140] The fact that data remains in a valid state in a block BLK that becomes an active block earlier means that the data has not been rewritten for a long period of time. The state of data that tends to remain valid over such a long period of time is recorded as cold. In contrast, the state of data that tends to become invalid after being rewritten in a short period of time is recorded as hot.

[0141] There is a high possibility that the rewriting of cold data will not be executed temporarily in the future. Therefore, when the block BLK that is the earliest to be transformed into an active block is selected as the block BLK of the dump source in garbage collection, the cold data can be gathered in several blocks BLK. When the cold data is gathered in several blocks BLK, the utilization efficiency of all blocks BLK is improved, thereby improving the efficiency of garbage collection in the future.

[0142] Furthermore, in the normal mode, the block BLK to which data was last written the earliest may not necessarily be selected as the block BLK of the transfer source in garbage collection.

[0143] For example, in the normal mode, the controller 100 may preferentially select a block BLK to which data was last written earlier as a block BLK to be the source of data in garbage collection.

[0144] Alternatively, in the normal mode, the controller 100 may select the block BLK as the source of transfer in garbage collection based on a complex determination in which an arbitrary condition is added to the condition related to the time when the data was last written. For example, the controller 100 may select a block BLK with the least amount of valid data stored among several blocks BLKs to which the data was last written earlier as the block BLK as the source of transfer in garbage collection.

[0145] Fig.11 This is a flowchart for explaining an example of the operation related to the transition of the operation mode in the second embodiment.

[0146] exist Fig.11 In the description of , it is assumed that: As an example, the controller 100 selects the block BLK with the least amount of valid data stored as the block BLK of the garbage collection in the power consumption limit mode. In addition, it is assumed that: As an example, the controller 100 selects the block BLK with the earliest time of data being written as the block BLK of the garbage collection in the normal mode. In addition, it is assumed that: Fig.11 In the initial state, the working mode of the storage system 1 is the normal mode.

[0147] The controller 100 (eg, the processor 101) determines whether the storage system 1 has received a power limit instruction from the host device 2 (S501). If it is determined that the storage system 1 has not received a power limit instruction (S501: No), the controller 100 executes the determination process of S501 again.

[0148] If the controller 100 determines that the storage system 1 has received a power limit instruction (S501: Yes), the controller 100 switches to the power limit mode (S502). In the power limit mode, the controller 100 uses a strategy of selecting the block BLK storing the least amount of valid data as the dump source in garbage collection.

[0149] After S502, the controller 100 determines whether or not a power limit release instruction is received from the host device 2 (S503). If it is determined that the power limit release instruction is not received (S503: No), the controller 100 executes the determination process of S503 again.

[0150] If it is determined that the power limit release instruction has been received (S503: Yes), the controller 100 changes to the normal mode (S504). In the normal mode, the controller 100 uses a strategy of selecting the block BLK to which data was last written the earliest as the dump source in garbage collection.

[0151] Then, control is transferred to S501.

[0152] Thus, in the second embodiment, the controller 100 selects the block BLK as the source of transfer in garbage collection according to a strategy based only on the amount of valid data stored in the power consumption limited mode. In addition, the controller 100 selects the block BLK as the source of transfer in garbage collection according to a strategy different from that in the power consumption limited mode in the normal mode.

[0153] More specifically, in the power amount limitation mode, the controller 100 preferentially selects a block BLK storing less valid data as a block to be transferred.

[0154] Thus, in the power limit mode, the amount of data to be moved to generate one free block can be reduced, thereby suppressing the amount of power required for garbage collection. As a result, the power consumption of the storage system 1 can be suppressed in the power limit mode.

[0155] Furthermore, the controller 100 may select the block BLK that is the source of data to be transferred in garbage collection based on the time at which data was last written in the normal mode.

[0156] In such a case, for example, cold data can be gathered in advance in several blocks BLK, so the efficiency of garbage collection will be improved in the future. In addition, as described above, the strategy of selecting the block BLK of the transfer source in the normal mode is not limited to this example.

[0157] (Third embodiment)

[0158] In the third embodiment, the controller 100 generates a plan related to power consumption (referred to as a power consumption plan) based on instructions from the host device 2. The controller 100 switches the operation mode of the storage system 1 between the power limit mode and the normal mode so that the transition of power consumption satisfies the power consumption plan.

[0159] Hereinafter, a third embodiment will be described. In the third embodiment, differences from the first embodiment will be described, and descriptions of similarities to the first embodiment will be omitted or briefly described.

[0160] Specifically, in addition to the power limit instruction, the controller 100 can also receive a scheduled power consumption and a planned period from the host device 2. The scheduled power consumption received by the storage system 1 from the host device 2 is an example of a first value. The planned period received by the storage system 1 from the host device 2 is an example of a second value.

[0161] The planned period specifies the period during which the operation in the power consumption limit mode can be performed. For example, if the planned period is "30 minutes", the operation mode of the storage system 1 is switched between the power consumption limit mode and the normal mode based on the power consumption plan from the start time of the planned period to the elapse of 30 minutes.

[0162] In addition, the planned period received from the host device 2 may be numerical information directly indicating the length of the planned period. The planned period received from the host device 2 may be a pair of numerical information indicating the start time of the planned period and numerical information indicating the end time. The planned period received from the host device 2 may be numerical information indicating the end time. In the case where the planned period received from the host device 2 is numerical information indicating the end time, the method of determining the start time of the planned period is arbitrary. For example, the controller 100 may be configured to interpret the power consumption restriction indication as an indication of the start of the planned period.

[0163] Alternatively, the controller 100 may pre-set a plurality of numerical information, each of which is numerical information that can be set as the planned period and is associated with an identifier. Furthermore, the host device 2 may select the numerical information to be set as the planned period from the plurality of numerical information by sending the identifier.

[0164] The planned power consumption specifies the amount of power that can be consumed during the planned period.

[0165] Furthermore, the estimated power consumption received from the host device 2 may be numerical information directly indicating the estimated power consumption.

[0166] Alternatively, the controller 100 may pre-set a plurality of numerical information, each of which is numerical information that can be set as a predetermined power consumption and is associated with an identifier. Furthermore, the host device 2 may select numerical information to be set as the predetermined power consumption from the plurality of numerical information by sending the identifier.

[0167] The controller 100 creates a power consumption plan based on the scheduled power consumption and the planned period.

[0168] Fig.12 1 is a schematic diagram showing an example of a power consumption plan generated by the controller 100 according to the third embodiment. The horizontal axis represents the elapsed time from the start of the plan period. The vertical axis represents the power consumption from the start of the plan period. Fig.12 In the example, the scheduled power consumption is 1000mWh and the planned period is 30 minutes.

[0169] The dotted line represents the power consumption plan. In this example, the power consumption plan is generated in a manner that the power consumption increases linearly with respect to time within the range of 0mWh to 1000mWh. In addition, the power consumption gradient is determined in a manner that the power consumption from the beginning of the plan period becomes 1000mWh at the end of the plan period, that is, 30 minutes have passed since the beginning of the plan period.

[0170] The controller 100 starts controlling the power consumption based on the power consumption plan in accordance with the power consumption limitation instruction. More specifically, the controller 100 controls the power consumption of the storage system 1 by changing the operation mode of the storage system 1 to the power consumption limitation mode as needed, so that the actual power consumption does not exceed the change indicated by the power consumption plan as much as possible. That is, the power consumption plan specifies the change of the upper limit value of the power consumption.

[0171] The controller 100 switches the operation mode so that the change in power consumption does not exceed the change in the upper limit value specified in the power consumption plan, thereby suppressing the power consumption of the storage system 1 so that the power consumption does not exceed the predetermined power consumption during the plan period.

[0172] exist Fig.12 : shows an example of the transition of the actual power consumption in the storage system 1 (see the solid line). It can be read that the above-mentioned control is performed so that the transition of the actual power consumption does not exceed the transition of the upper limit value specified by the power consumption plan.

[0173] Fig.13 This is a flowchart for explaining an example of the operation related to the transition of the operation mode in the third embodiment.

[0174] The controller 100 determines whether the storage system 1 has received a scheduled power consumption, a planned period, and a power limitation instruction from the host device 2 ( S601 ).

[0175] When the storage system 1 has not received the scheduled power consumption, the planned period, and the power limitation instruction from the host device 2 ( S601 : No), the controller 100 executes the process of S601 again.

[0176] When the storage system 1 receives the scheduled power consumption, the planned period, and the power limitation instruction from the host device 2 ( S601 : Yes), the controller 100 generates a power consumption plan based on the scheduled power consumption and the planned period ( S602 ).

[0177] Next, the controller 100 starts controlling the amount of electric power according to the received power limitation instruction. That is, the controller 100 starts the planned period (S603).

[0178] During the planned period, the controller 100 determines the operation mode based on a comparison between the power consumption since the start of the planned period and the upper limit value specified by the power consumption plan.

[0179] More specifically, the controller 100 calculates the upper limit value E(t) of the power consumption specified in the power consumption plan at a time point when the elapsed time (recorded as time t) from the start of the plan period to the present has passed (S604).

[0180] E(t) is calculated, for example, using the following formula (1). Fig.12 Generate using the method described above.

[0181] E(t)=Ep*t / tp……(1)

[0182] Here, Ep is the planned power consumption, and tp is the length of the planned period. In the formula (1), it is assumed that t takes a value greater than or equal to 0 and less than or equal to tp.

[0183] Next, the controller 100 determines whether the power consumption (represented as Ec) from the start of the planned period is less than E(t) ( S605 ).

[0184] When Ec is less than E(t) (S605: Yes), the controller 100 operates in the normal mode (S606). When Ec is not less than E(t) (S605: No), the controller 100 operates in the power limit mode (S607).

[0185] After S606 or S607, the controller 100 determines whether the end timing of the planned period has arrived (S608). When the end timing of the planned period has not arrived (S608: No), the controller 100 executes the processing of S604 again. When the end timing of the planned period has arrived (S608: Yes), the controller 100 ends the planned period (S609). That is, when the working mode of the controller 100 was previously the power limit mode, the controller 100 changes to the normal mode. When the working mode of the controller 100 was previously the normal mode, the controller 100 continues to work in the normal mode. Through S609, a series of operations are completed.

[0186] In addition, the operation in the normal mode of the controller 100 of the third embodiment may be the same as the operation in the normal mode of the controller 100 of the first embodiment or the operation in the normal mode of the controller 100 of the second embodiment.

[0187] The operation of the controller 100 in the power amount limitation mode of the third embodiment may be the same as the operation of the controller 100 in the power amount limitation mode of the first embodiment or the operation of the controller 100 in the power amount limitation mode of the second embodiment.

[0188] The loop processing of S604 to S608 is repeated at time intervals that are sufficiently short relative to the planned period. Thus, by repeating this loop processing, the operation mode is switched so that the change in power consumption does not exceed the change determined as the power consumption plan as much as possible. As a result, the power consumption is suppressed so that the power consumption during the planned period does not exceed the predetermined power consumption.

[0189] In addition, the above description assumes that the controller 100 operates in the power limit mode when Ec and E(t) are equal. The processing when Ec and E(t) are equal is not limited to this. When Ec and E(t) are equal, the controller 100 may also operate in the normal mode.

[0190] In addition, the method by which the controller 100 acquires its own power consumption is not limited to a specific method.

[0191] In one example, it is considered that a circuit for monitoring power consumption is provided in the storage system 1 . Fig.14 1 is a schematic diagram showing an example of the configuration of the storage system 1 according to the third embodiment. Fig.14 In the drawings, illustration of the same configuration as that included in the first embodiment is omitted.

[0192] like Fig.14 As shown, the information processing system 10 includes a power supply device 5. In addition to the controller 100 and the NAND memory 200, the storage system 1 further includes a power supply circuit 400. The power supply circuit 400 is connected to the power supply device 5 via a power supply line 6. The power supply circuit 400 generates power for operating the controller 100 and the NAND memory 200 based on the power supplied from the power supply device 5 via the power supply line 6, and supplies the generated power to the controller 100 and the NAND memory 200.

[0193] Furthermore, the power supply circuit 400 includes a measuring circuit 401. The measuring circuit 401 measures the power consumption of the storage system 1. The measurement result of the measuring circuit 401 is transmitted to the controller 100. The controller 100 calculates the power consumption based on the obtained measurement result.

[0194] The measurement circuit 401 may be provided on a substrate (not shown) of the storage system 1. In such a case, the measurement circuit 401 measures, for example, the amount of current flowing in the substrate. The measurement result of the measurement circuit 401 is sent to the controller 100. The controller 100 calculates the power consumption based on the obtained measurement result and the rated voltage.

[0195] In another example, parameters such as the amount of power consumed for each write to the NAND memory 200, the amount of power consumed for each read from the NAND memory 200, the amount of power consumed for data transfer per unit size in the communication interface 3, and the amount of power consumed by each component in a steady state are stored in advance in a predetermined location (for example, the NAND memory 200). Then, the controller 100 calculates the power consumption in the storage system 1 based on these parameters, the number of reads actually performed by each memory chip 201, the number of writes actually performed by each memory chip 201, and the amount of data transferred via the communication interface 3.

[0196] In still another example, the storage system 1 may be configured such that information on power consumption of the storage system 1 is input from the host device 2 .

[0197] Fig.15 This is a diagram for explaining an example of a method in which the storage system 1 according to the third embodiment receives information related to power consumption.

[0198] like Fig.15 As shown, the host device 2 first sends the scheduled power consumption, the planned period, and the power limit instruction (S701). Then, in the storage system 1, the controller 100 starts the planned period (S702). During the planned period, while data is being sent and received between the host device 2 and the storage system 1, the host device 2 sends power consumption information to the storage system 1 (S703).

[0199] The power consumption information may also be the power consumption of the storage system 1 at the timing when the power consumption information is sent. The power consumption information may also be the amount of power consumed by the storage system 1 after a predetermined timing. The predetermined timing may be, for example, the start timing of the planned period, the timing when the power consumption information was sent last time, or a timing other than these. The power consumption information may also be the amount of current flowing in the storage system 1. That is, the power consumption information is any physical quantity related to power consumption that the storage system 1 can provide for the calculation of power consumption.

[0200] The power consumption information may be sent by using any command. For example, a manufacturer-specific command may be assigned as a command for sending the power consumption information. The command for sending the power consumption information may also be added to the standard of the communication interface 3. The host device 2 and the storage system 1 may also be connected via a dedicated signal line for transmitting the power consumption information, and the host device 2 may also send the power consumption information to the storage system 1 via the dedicated signal line.

[0201] The transmission of the power consumption information from the host device 2 to the storage system 1 is performed once or more periodically or at an arbitrary timing. The controller 100 can calculate the power consumption based on the power consumption information received from the host device 2 .

[0202] When the planned period ends ( S704 ), the host device 2 can end the transmission of the power consumption information.

[0203] In addition, the host device 2 may also send power consumption information during a period other than the planned period. In addition, the storage system 1 may send a request for power consumption information to the host device 2, and the host device 2 may send power consumption information based on the request. The method for the host device 2 to send power consumption information to the storage system 1 may be modified in various ways.

[0204] The host device 2 may not transmit the scheduled power consumption, the planned period, and the power limit instruction at the same time. The storage system 1 may be configured to receive the scheduled power consumption, the planned period, or both at a timing different from the power limit instruction.

[0205] For example, the storage system 1 receives the scheduled power consumption and the planned period from the host device 2. Then, when receiving the power limit instruction, the storage system 1 may start the planned period in accordance with the power limit instruction.

[0206] The above is an example of a power consumption plan. Fig.12 The power consumption plan is not limited to Fig.12 The example given. Furthermore, the storage system 1 may be configured such that the power consumption plan can be changed during the planning period. For example, the controller 100 may also generate a new power consumption plan at any timing during the planning period, such as a power consumption plan in which the upper limit of power consumption increases linearly with respect to time within the range of the amount of power already consumed to the predetermined power consumption, and start working based on the newly generated power consumption plan. That is, the controller 100 may also regenerate the power consumption plan during the planning period. The controller 100 may also regenerate the power consumption plan at a plurality of different timings during the planning period. The host device 2 may also instruct the storage system 1 to regenerate the power consumption plan.

[0207] Furthermore, the host device 2 may appropriately instruct a change in the power consumption plan during the planned period.

[0208] Furthermore, when it is estimated that power consumption is high in the first half of the planned period because reading or writing is concentrated in the first half of the planned period, the controller 100 may set a margin for the upper limit of power consumption in the first half of the planned period.

[0209] Fig.16 3 is a diagram for explaining an example of changing the power consumption plan according to the third embodiment. For example, sometimes the number of accesses from the host device 2 is heavy during the first half of the plan period, such as Fig.16 As shown in (A), the actual power consumption changes approach or exceed the upper limit value specified by the initially generated power consumption plan. In such a case, the upper limit value specified by the power consumption plan becomes a bottleneck, and the access performance between the host device 2 and the storage system 1 is suppressed.

[0210] So, if Fig.16 As shown by the dotted line in (B), the controller 100 changes the power consumption plan to the upper limit of the power consumption, which has a positive value other than zero as the intercept of a linear function. Fig.16 As shown by the solid line of (B), even if the power consumption increases in the first half of the planned period due to heavy access from the host device 2, the power consumption can be prevented from being suppressed by the upper limit value. In other words, the access performance between the host device 2 and the storage system 1 can be prevented from being suppressed in the first half of the planned period.

[0211] The trigger for changing the power consumption plan is arbitrary. Alternatively, the host device 2 may send an instruction to use a function that provides a margin for the upper limit of power consumption in the first half of the plan period, and the controller 100 may change the power consumption plan according to the instruction. Alternatively, the controller 100 may autonomously change the power consumption plan when it detects that the actual power consumption is approaching or exceeding the upper limit specified in the power consumption plan that was originally generated.

[0212] In addition, the controller 100 may also generate the following at the beginning of the planning period: Fig.16 The power consumption plan is not changed as shown by the dotted line in (B).

[0213] in addition, Fig.16 The function of the power consumption plan shown in (B) is an example of a function for providing a margin for the upper limit value of power consumption in the first half of the plan period. A power function may be used as a function for providing a margin for the upper limit value of power consumption in the first half of the plan period.

[0214] Thus, according to the third embodiment, the controller 100 receives the scheduled power consumption and the planned period from the host device 2. Then, the controller 100 controls the power consumption of the storage system 1 according to the power limit instruction so that the power consumption during the planned period does not exceed the scheduled power consumption.

[0215] Thus, the host device 2 can operate the storage system 1 during a limited period of time and with a limited amount of electric power.

[0216] For example, sometimes the information processing system 10 is a portable computer having a storage system 1, a volatile memory, and a battery. When the host device 2 is driven by the power stored in the battery and the remaining power of the battery becomes insufficient, the host device 2 uses the remaining power to save the contents of the volatile memory to the non-volatile memory, that is, in this case, to the storage system 1. This operation is called PLP (Power Loss Protection). In PLP, since the remaining power of the battery is insufficient, it is desired to suppress the power consumption of the storage system 1 to a power amount corresponding to the remaining power of the battery.

[0217] The storage system 1 according to the third embodiment can operate so that the power consumption during the planned period does not exceed the predetermined power consumption. Thus, the host device 2 determines the predetermined power consumption and the planned period based on the remaining power of the battery. If the predetermined power consumption and the planned period are sent to the storage system 1 together with the power limit indication, the insufficient power can be used to implement the operation of the PLP.

[0218] According to the third embodiment, the controller 100 generates a power consumption plan that defines transitions in the upper limit of power consumption based on the scheduled power consumption and the planned period, and suppresses power consumption of the storage system 1 based on the power consumption plan in response to the power limit instruction.

[0219] This makes it possible to control the power consumption of the storage system 1 so that the power consumption during the planned period does not exceed the predetermined power consumption.

[0220] According to the third embodiment, the controller 100 can operate in the normal mode and the power limit mode which consumes less power than the normal mode. The controller 100 switches between the normal mode and the power limit mode based on the power consumption plan.

[0221] This makes it possible to control the power consumption of the storage system 1 so that the power consumption during the planned period does not exceed the predetermined power consumption.

[0222] According to the third embodiment, as an example, the controller 100 may be configured to receive power consumption information from the host device 2 and acquire the power consumption of the storage system 1 based on the power consumption information.

[0223] In such a case, it is not necessary to provide a circuit for measuring a physical quantity related to power consumption in the storage system 1 .

[0224] In addition, the condition for ending the planned period is not limited to the elapse of the length specified as the second value by the host device 2. For example, the controller 100 may end the planned period when receiving an instruction to release the power limit during the planned period.

[0225] (Fourth embodiment)

[0226] In the power consumption plan according to the third embodiment, the change of the upper limit value of power consumption is specified as a function of time. In the power consumption plan according to the fourth embodiment, the change of the upper limit value of power consumption is specified as a function of the amount of data transferred from the host device 2 to the NAND memory 200. The amount of data transferred from the host device 2 to the NAND memory 200 is recorded as the host write amount.

[0227] Hereinafter, the differences from the third embodiment will be described. The description of the same points as the third embodiment will be omitted or briefly described.

[0228] In the fourth embodiment, the storage system 1 can receive the planned power consumption and the planned host write amount from the host device 2. The planned host write amount is another example of the second value. The controller 100 generates a power consumption plan based on the planned power consumption and the planned host write amount.

[0229] Fig.17 : is a schematic diagram showing an example of a power consumption plan generated by the controller 100 according to the fourth embodiment. Fig.17 In the table, the horizontal axis represents the host write volume from the start of the planned period. The vertical axis represents the power consumption from the start of the planned period. Fig.17 In the example, the scheduled power consumption is set to 1000mWh and the scheduled host write volume is set to 50GB.

[0230] The dotted line represents the power consumption plan. In this example, the power consumption plan is generated in a manner that the power consumption increases linearly with respect to the host write amount in the range of 0mWh to 1000mWh. In addition, the power consumption gradient is determined so that at the end of the plan period, that is, when the host write amount from the beginning of the plan period reaches 50GB, the power consumption from the beginning of the plan period becomes 1000mWh.

[0231] The controller 100 starts controlling the power consumption based on the power consumption plan according to the power consumption limitation instruction. More specifically, the controller 100 controls the power consumption of the storage system 1 by changing the operation mode of the storage system 1 to the power consumption limitation mode as needed, so that the actual power consumption does not exceed the upper limit value specified by the power consumption plan as much as possible.

[0232] exist Fig.17 : shows an example of the transition of the actual power consumption in the storage system 1 (see the solid line). It can be read that the above-mentioned control is performed so that the transition of the actual power consumption does not exceed the transition of the upper limit value specified by the power consumption plan.

[0233] Fig.18 This is a flowchart for explaining an example of the operation related to the transition of the operation mode in the fourth embodiment.

[0234] The controller 100 determines whether the storage system 1 has received a predetermined power consumption, a predetermined host write amount, and a power limit instruction from the host device 2 ( S801 ).

[0235] When the storage system 1 has not received the scheduled power consumption, the scheduled host write amount, and the power limit instruction from the host device 2 ( S801 : No), the controller 100 executes the process of S801 again.

[0236] When the storage system 1 receives the planned power consumption, the planned host write amount, and the power limit instruction from the host device 2 ( S801 : Yes), the controller 100 generates a power consumption plan based on the planned power consumption and the planned host write amount ( S802 ).

[0237] Next, the controller 100 starts controlling the amount of electric power according to the received power limitation instruction, that is, starts the planned period (S803).

[0238] During the planned period, the controller 100 determines the operation mode based on a comparison between the power consumption since the start of the planned period and the power consumption plan.

[0239] More specifically, the controller 100 first calculates the upper limit value E(W) of the power consumption specified by the power consumption plan ( S804 ).

[0240] E(W) is calculated using, for example, the following formula (2). Fig.17 Generate using the method described above.

[0241] E(W)=Ep*W / Wp……(2)

[0242] Here, W is the host write amount from the start of the planned period to the present. Ep is the planned power consumption, and Wp is the planned host write amount. In equation (2), it is assumed that W takes a value greater than or equal to 0 and less than or equal to Wp.

[0243] Next, the controller 100 determines whether the power consumption Ec from the start of the planned period to the present is smaller than E(W) (S805). The method of obtaining Ec is not limited to a specific method. Ec is obtained by the same method as the third embodiment.

[0244] When Ec is smaller than E(W) (S805: Yes), the controller 100 operates in the normal mode (S806). When Ec is not smaller than E(W) (S805: No), the controller 100 operates in the power limit mode (S807).

[0245] After S806 or S807, the controller 100 determines whether W has reached Wp (S808). When W has not reached Wp (S808: No), the controller 100 executes the process of S804 again. When W has reached Wp (S808: Yes), the controller 100 ends the planned period (S809). That is, when the working mode of the controller 100 was previously the power limit mode, the controller 100 changes to the normal mode. When the working mode of the controller 100 was previously the normal mode, the controller 100 continues to work in the normal mode. Through S809, a series of operations are completed.

[0246] In addition, the operation in the normal mode of the controller 100 of the fourth embodiment may be the same as the operation in the normal mode of the controller 100 of the first embodiment or the operation in the normal mode of the controller 100 of the second embodiment.

[0247] The operation of the controller 100 in the fourth embodiment in the power amount limitation mode may be the same as the operation of the controller 100 in the first embodiment in the power amount limitation mode or the operation of the controller 100 in the second embodiment in the power amount limitation mode.

[0248] The loop processing of S804 to S808 is repeated, for example, at a predetermined time interval. The predetermined time interval is sufficiently shorter than the length of the planned period. Thus, by repeatedly performing the loop processing of S804 to S808, the operation mode is switched so that the power consumption does not exceed the upper limit value determined as the power consumption plan as much as possible. As a result, it is possible to suppress the power consumption so that the power consumption does not exceed the predetermined power consumption while writing the amount of data set as the predetermined host write amount.

[0249] In addition, the above description assumes that when Ec and E(W) are equal, the controller 100 operates in the power limit mode. The processing when Ec and E(W) are equal is not limited to this. When Ec and E(W) are equal, the controller 100 may also operate in the normal mode.

[0250] In addition, the power consumption plan is not limited to Fig.17 As the function representing the power consumption plan, any function can be used.

[0251] Furthermore, the storage system 1 may be configured so that the power consumption plan can be changed during the plan period. For example, the controller 100 may regenerate the power consumption plan so that the upper limit of power consumption increases linearly with respect to the host write amount within the range of power consumed to a predetermined power consumption during the plan period.

[0252] Furthermore, the host device 2 may appropriately instruct a change in the power consumption plan during the planned period.

[0253] Furthermore, when the controller 100 receives an electric energy restriction release instruction during the planned period, the controller 100 may end the planned period in accordance with the electric energy restriction release instruction.

[0254] The host device 2 may not transmit the planned power consumption, planned host write amount, and power limit instruction at the same time. The storage system 1 may be configured to receive the planned power consumption, planned host write amount, or both at a timing different from the power limit instruction.

[0255] Thus, according to the fourth embodiment, the controller 100 receives the planned power consumption and the planned host write amount from the host device 2. Then, the controller 100 transmits data of the amount designated as the planned host write amount so that the power consumption does not exceed the planned power consumption.

[0256] Thus, the host device 2 can transmit a limited amount of data within a limited period of time.

[0257] The technology of the fourth embodiment can be used for PLP in the same manner as the third embodiment. For example, the host device 2 determines the predetermined power consumption and the predetermined host write amount based on the remaining power of the battery, and if the predetermined power consumption and the predetermined host write amount are sent to the storage system 1 together with the power limit indication, the insufficient power can be used to implement the operation of PLP.

[0258] In the above example, the storage system 1 is configured to control power consumption based on the host write amount. The storage system 1 may also be configured to control power consumption based on the amount of data transferred from the NAND memory 200 to the host device 2 (referred to as the host read amount).

[0259] For example, the storage system 1 can receive a predetermined power consumption and a predetermined host read amount from the host device 2. The controller 100 can also generate a power consumption plan in which an upper limit of power consumption is defined as a function of the host read amount based on the predetermined power consumption and the predetermined host read amount, and control power consumption based on the host read amount and the power consumption plan.

[0260] Alternatively, the storage system 1 may control power consumption based on both the host write amount and the host read amount. The controller 100 may also generate a power consumption plan in which the upper limit of power consumption is defined as a function of the host read amount and the host write amount based on the predetermined power consumption, the predetermined host read amount, and the predetermined host write amount, and control power consumption based on the host read amount, the host write amount, and the power consumption plan.

[0261] Hereinafter, host write volume, host read volume, or both are sometimes referred to as host access volume.

[0262] (Fifth embodiment)

[0263] In the third and fourth embodiments, when the power consumption is less than the upper limit value specified by the power consumption plan, the controller 100 sets the operation mode of the storage system 1 to the normal mode. In the fifth embodiment, when the power consumption is significantly less than the upper limit value, the controller 100 sets the operation mode of the storage system 1 to a mode in which the processing amount of the transfer processing is increased compared to the normal mode. That is, the controller 100 increases the processing amount of the transfer processing by using the abundant amount of electric power available. The mode in which the processing amount of the transfer processing is increased compared to the normal mode is recorded as a high power mode.

[0264] The method of increasing the processing amount of the transfer process is not limited to a specific method. For example, the controller 100 may increase the execution frequency of the transfer process in the high power mode than the execution frequency of the transfer process in the normal mode.

[0265] Alternatively, the controller 100 makes the start condition of the dump processing different in the high power mode and the normal mode. For example, when the number of free blocks is lower than the determination threshold as the start condition of garbage collection (or eviction), different values ​​are used as the determination threshold in the high power mode and the normal mode. Specifically, the controller 100 uses the first setting value as the determination threshold in the normal mode, and uses the third setting value larger than the first setting value as the determination threshold in the high power mode. As a result, the processing amount of garbage collection (or eviction) increases in the high power mode.

[0266] The fifth embodiment will be described later. Here, it is assumed as an example that the power consumption plan is similar to the third embodiment, and the upper limit value of the power consumption is defined as a function of time.

[0267] Fig.19 This is a flowchart for explaining an example of the operation related to the transition of the operation mode of the fifth embodiment. In addition, the operation related to the electric energy of the fifth embodiment adds S901 and S902 after the processing of S605, which is similar to Fig.13 The operation related to the electric power amount in the third embodiment shown is different. The following describes the differences from the operation related to the electric power amount in the third embodiment.

[0268] When it is determined in the determination process of S605 that Ec is smaller than E(t) (S605: Yes), the controller 100 determines whether the difference between the upper limit value E(t) of the power consumption specified by the power consumption plan and the actual power consumption Ec, that is, (E(t)-Ec) is greater than a threshold value Eth related to the power amount (S901). Eth is a pre-set positive real number.

[0269] When (E(t)-Ec) is greater than Eth (S901: Yes), the controller 100 operates in the high power mode (S902). When (E(t)-Ec) is not greater than Eth (S901: No), the controller 100 operates in the normal mode (S606).

[0270] After S902 , S606 or S607 , the controller 100 executes the determination process of S608 .

[0271] In addition, the above description assumes that when (E(t)-Ec) is equal to Eth, the controller 100 operates in the normal mode. The processing when (E(t)-Ec) is equal to Eth is not limited to this. When (E(t)-Ec) is equal to Eth, the controller 100 can also operate in the high power mode.

[0272] In the fifth embodiment, the host device 2 may not transmit the scheduled power consumption, the planned period, and the power limit instruction at the same time. The storage system 1 may be configured to receive the scheduled power consumption, the planned period, or both at a timing different from the power limit instruction.

[0273] Thus, according to the fifth embodiment, the controller 100 is configured to switch the operation mode among the normal mode, the power limit mode, and the high power mode in which the amount of transfer processing is greater than that in the normal mode. The controller 100 switches the operation mode based on the power consumption plan.

[0274] By increasing the amount of transfer processing when sufficient power is available, the number of free blocks can be increased. When the number of free blocks increases, the operation in the power limit mode can be continued for a longer time.

[0275] In addition, the power consumption plan is set as follows: the upper limit of power consumption is defined as a function of time. The fifth embodiment can also be applied when the power consumption plan is defined as a function of host access (host write amount, host read amount, or both) as in the fourth embodiment.

[0276] (Sixth Implementation Method)

[0277] Generally speaking, in a storage mode in which the number of bits (i.e., the aforementioned number of levels) of the value maintained in a memory cell transistor MT is small, writing and reading can be performed in less time and consumes less power than in a storage mode in which the number of levels is large.

[0278] However, in the storage mode with a small number of layers, the consumption of free blocks is greater than that in the storage mode with a large number of layers. When free blocks are exhausted due to continuous writing in the storage mode with a small number of layers, eviction is required. When eviction is performed, power consumption increases according to the amount of eviction processing.

[0279] Therefore, if writing is performed in a storage mode with a small number of layers when the number of free blocks is sufficient, power consumption can be further suppressed even if the amount of processing of the transfer process including eviction is suppressed, albeit temporarily.

[0280] According to the sixth embodiment, as an example, the storage system 1 can switch the storage mode during writing from the SLC mode to the TLC mode. Furthermore, when there are sufficient free blocks in the power limit mode, the controller 100 writes data in the SLC mode. When the number of free blocks is insufficient in the power limit mode, the controller 100 writes data in the TLC mode.

[0281] The sixth embodiment may be used in combination with any one of the third embodiment, the fourth embodiment, and the fifth embodiment. Here, as an example, an example of using the sixth embodiment in combination with the third embodiment will be described.

[0282] Fig. 20 This is a flowchart showing an example of the operation of the storage system 1 according to the sixth embodiment in the power amount limitation mode.

[0283] In the power amount limitation mode, the controller 100 determines whether the number of free blocks is sufficient with respect to the remaining time of the planning period (S1001).

[0284] The specific method of determination of S1001 is not limited to a specific method. In one example, when the number of free blocks is larger than a threshold value determined according to the remaining time of the planned period, the controller 100 determines that the number of free blocks is sufficient for the remaining time of the planned period. When the number of free blocks is smaller than a threshold value determined according to the remaining time of the planned period, the controller 100 determines that the number of free blocks is insufficient for the remaining time of the planned period. When the number of free blocks is equal to the threshold value determined according to the remaining time of the planned period, the controller 100 may determine that the number of free blocks is sufficient for the remaining time of the planned period, or may determine that the number of free blocks is insufficient for the remaining time of the planned period.

[0285] The threshold value determined based on the remaining time of the planned period is, for example, a threshold value proportional to the remaining time of the planned period. The calculation method of the threshold value determined based on the remaining time of the planned period is not limited thereto. The threshold value determined based on the remaining time of the planned period is an example of the third value.

[0286] When the number of free blocks is sufficient for the remaining time of the planned period (S1001: Yes), the controller 100 sets the operation mode of the storage system 1 to the first power limit mode (S1002). In the first power limit mode, the controller 100 writes data in the SLC mode when writing data to the NAND memory 200, based on the operation in the power limit mode described in the first embodiment or the second embodiment.

[0287] When the number of free blocks is insufficient relative to the remaining time of the planned period (S1001: No), the controller 100 sets the operation mode of the storage system 1 to the second power limit mode (S1003). In the second power limit mode, the controller 100 writes data in the TLC mode when writing data to the NAND memory 200, based on the operation in the power limit mode described in the first embodiment or the second embodiment.

[0288] After S1002 or S1003, the controller 100 determines whether to terminate the operation in the power limit mode (S1004). That is, the controller 100 determines whether to change the operation mode of the storage system 1 from the power limit mode to another mode (e.g., normal mode). The conditions for changing the operation mode are the same as those described in the third embodiment, and therefore, the description thereof is omitted here.

[0289] If the operation in the power limit mode is not to be terminated (S1004: No), the controller 100 executes the process of S1001 again. If the operation in the power limit mode is to be terminated (S1004: Yes), the controller 100 terminates the operation in the power limit mode.

[0290] Thus, in the sixth embodiment, the controller 100 can suppress the power consumption of the storage system 1 by reducing the number of layers, that is, reducing the number of bits of data stored in one memory cell transistor MT, during the power limit mode according to the power consumption plan.

[0291] This can further reduce power consumption compared to a case where the number of layers is not reduced.

[0292] In addition, in the sixth embodiment, when the number of free blocks is smaller than a third value (a threshold value determined according to the remaining time in the above example), the controller 100 writes data in a mode (a TLC mode in the above example) in which the first bit of data is written to each memory cell transistor. When the number of free blocks is larger than a third value (a threshold value determined according to the remaining time in the above example), the controller 100 writes data in a mode (a SLC mode in the above example) in which the second bit of data less than the first bit is written to each memory cell transistor.

[0293] This can further reduce power consumption compared to a case where the number of layers is not reduced.

[0294] In addition, as described above, the sixth embodiment can be used in conjunction with the fourth embodiment instead of the third embodiment. When the sixth embodiment is used in conjunction with the fourth embodiment, the controller 100 determines in S1001 whether the number of free blocks is sufficient relative to the amount obtained by subtracting the host access amount from the start of the planned period from the remaining host write amount, that is, the scheduled host access amount. In addition, the scheduled host access amount is the scheduled host write amount, the scheduled host read amount, or both received as the second value from the host device 2, and is the amount used to generate the power consumption plan. When the number of free blocks is sufficient relative to the remaining host access amount, the controller 100 executes the processing of S1002. When the number of free blocks is insufficient relative to the remaining host access amount, the controller 100 executes the processing of S1003.

[0295] The method for determining whether the number of free blocks is sufficient relative to the remaining host access amount is not limited to a specific method. For example, when the number of free blocks is less than the threshold value obtained by converting the remaining host access amount into the number of blocks BLK, the controller 100 determines that the number of free blocks is insufficient relative to the remaining host access amount. When the number of free blocks is more than the threshold value obtained by converting the remaining host access amount into the number of blocks BLK, the controller 100 determines that the number of free blocks is sufficient relative to the remaining host access amount. When the number of free blocks is equal to the threshold value obtained by converting the remaining host access amount into the number of blocks BLK, the controller 100 can either determine that the number of free blocks is sufficient relative to the remaining host access amount or determine that the number of free blocks is insufficient relative to the remaining host access amount.

[0296] The threshold value obtained by converting the remaining host access amount into the number of blocks BLK is another example of the third value. In addition, the third value is not limited to this.

[0297] In addition, the sixth embodiment can also be used together with the fifth embodiment. That is, the controller 100 can operate in the high power mode according to the power consumption plan.

[0298] In the sixth embodiment, the storage mode used for writing data in the normal mode (and the high power mode) is arbitrary. In the normal mode (and the high power mode), abundant power can be used, so the controller 100 can also write data in the TLC mode.

[0299] (Seventh Implementation Method)

[0300] When the host device 2 requests the storage system 1 to write user data, it can send attribute information of the user data to be written. The attribute information is recorded as data color. In the seventh embodiment, the host device 2 can indicate to the storage system 1 whether the user data to be written is hot or cold based on the data color. Thereafter, the user data to be written sent by the host device 2 to the storage system 1 is recorded as write data.

[0301] When data is written in the SLC mode, the data needs to be ejected later. However, when data written in the SLC mode becomes invalid before the ejection is performed, the data does not need to be ejected, and the amount of power required for the ejection can be reduced.

[0302] In the seventh embodiment, the controller 100 writes the write data indicated as hot by the data color to the memory chip 201 in the SLC mode in the power amount limiting mode. Thus, the power amount required for writing can be suppressed compared to the case where the write data is written to the memory chip 201 in the TLC mode. Furthermore, if the write data written in the SLC mode and indicated as hot by the data color becomes invalid before the eviction is performed and the eviction of the write data is unnecessary, the power amount required for eviction can be reduced, and as a result, the power amount can be further suppressed.

[0303] Furthermore, the seventh embodiment may be used in combination with any one of the third to fifth embodiments.

[0304] Fig.21 FIG. 1 is a flowchart showing an example of the operation in the power limit mode of the storage system 1 according to the seventh embodiment. In the power limit mode of the seventh embodiment, the controller 100 performs the operation in the power limit mode according to the third to fifth embodiments. Fig.21 A series of work described.

[0305] In the power limit mode, the controller 100 determines whether the storage system 1 receives a write command from the host device 2 (S1101). If the storage system 1 does not receive a write command from the host device 2 (S1101: No), the controller 100 executes the process of S1101 again.

[0306] When the storage system 1 receives a write command from the host device 2 ( S1101 : YES), the controller 100 determines whether the storage system 1 receives a data color together with the write command from the host device 2 ( S1102 ).

[0307] When the storage system 1 receives the data color from the host device 2 (S1102: Yes), the controller 100 determines whether the data color indicates "hot" (S1103). When the data color indicates "hot" (S1103: Yes), the controller 100 writes the data requested to be written by the received write command to the storage chip 201 in the SLC mode (S1104).

[0308] When the storage system 1 does not receive a data color together with a write command (S1102: No), or when the storage system 1 receives a data color that does not indicate "hot" together with a write command (S1103: No), the controller 100 writes the data requested to be written by the received write command to the storage chip 201 in TLC mode (S1105).

[0309] After S1104 or S1105, the controller 100 determines whether to terminate the operation in the power limit mode (S1106). That is, the controller 100 determines whether to change the operation mode of the storage system 1 from the power limit mode to another mode (e.g., normal mode). The conditions for the change of the operation mode are as described in other embodiments, and therefore, the description is omitted here.

[0310] If the operation in the power limit mode is not to be terminated (S1106: No), the controller 100 executes the process of S1101 again. If the operation in the power limit mode is to be terminated (S1106: Yes), the controller 100 terminates the operation in the power limit mode.

[0311] As described above, according to the seventh embodiment, the controller 100 writes write data to the NAND memory 200 in the storage pattern corresponding to the data color instructed from the host device 2 in the power amount limit mode.

[0312] Therefore, for example, when the host device 2 sends data that may be rewritten in a short time to the storage system 1, if the storage system 1 is notified that the data is hot, the possibility of reducing the processing amount of eviction in the storage system 1 becomes higher, and the possibility of further suppressing power consumption becomes higher.

[0313] In addition, the host device 2 may notify that the data is hot when sending data from the volatile memory to the storage system 1 in the PLP. In this case, the time required for writing data can be shortened, and the power consumption required for writing data can be reduced.

[0314] In addition, the information processing system 10 can sometimes perform hibernation. Hibernation is a function that completely saves the data in the volatile memory to the non-volatile memory (here, for example, the storage system 1) and turns off the power supply. When the system is started up next, the saved data is restored from the non-volatile memory to the volatile memory without changing. Hibernation can quickly restore the system to the state before the power supply was turned off.

[0315] The data stored in the storage system 1 during hibernation becomes unnecessary after the next startup. Therefore, the data stored in the storage system 1 during hibernation is considered to be hot. The host device 2 may also notify the storage system 1 that the data is hot when sending data to the storage system 1 during hibernation. In this case, the time required for writing data can be shortened, and the power consumption required for writing data can be reduced.

[0316] (Eighth Implementation Method)

[0317] In the seventh embodiment, the controller 100 selects the storage mode based on the data color. The controller 100 may select the storage mode based not only on the data color but also on the number of free blocks.

[0318] The eighth embodiment can be used in combination with any one of the third embodiment to the fifth embodiment. Here, as an example, the operation in the case where the eighth embodiment is used in combination with the third embodiment will be described.

[0319] Fig. 22 This is a flowchart showing an example of the operation of the storage system 1 according to the eighth embodiment in the power amount limitation mode.

[0320] The operation of the storage system 1 in the power consumption limit mode according to the eighth embodiment is similar to the operation of the storage system 1 in the eighth embodiment in that the determination process of S1201 is added after the determination process of S1103. Fig.21 The operations related to the seventh embodiment shown are different. The differences from the seventh embodiment will be described below.

[0321] If the determination in S1103 is "yes", that is, if the color of the data received together with the write command indicates "hot", the controller 100 determines whether the number of free blocks is sufficient for the remaining time of the planned period (S1201).

[0322] The process of S1201 is similar to that used in the sixth embodiment. Fig. 20 The processing of S1001 described above is the same. That is, the controller 100 determines whether the number of free blocks is sufficient for the remaining time of the planned period based on the comparison between the number of free blocks and the third value. When the number of free blocks is less than the third value, the controller 100 determines that the number of free blocks is insufficient for the remaining time of the planned period. When the number of free blocks is more than the third value, the controller 100 determines that the number of free blocks is sufficient for the remaining time of the planned period. When the number of free blocks is equal to the third value, the controller 100 may determine that the number of free blocks is sufficient for the remaining time of the planned period, or may determine that the number of free blocks is insufficient for the remaining time of the planned period.

[0323] When the number of free blocks is sufficient for the remaining time of the planned period (S1201: Yes), the controller 100 writes the data required to be written by the received write command to the storage chip 201 in the SLC mode (S1104). When the number of free blocks is insufficient for the remaining time of the planned period (S1201: No), the controller 100 writes the data required to be written by the received write command to the storage chip 201 in the TLC mode (S1105).

[0324] In addition, as described above, the eighth embodiment may be used in conjunction with the fourth embodiment instead of the third embodiment. When the eighth embodiment is used in conjunction with the fourth embodiment, the controller 100 determines in S1001, for example, whether the number of free blocks is sufficient relative to the remaining host write amount, that is, the amount obtained by subtracting the host access amount from the start of the planned period from the scheduled host access amount.

[0325] The eighth embodiment can also be used in combination with the fifth embodiment. That is, the controller 100 can operate in the high power mode according to the power consumption plan.

[0326] Thus, according to the eighth embodiment, in the power amount limitation mode, the controller 100 operates as follows. That is, when the data color notified from the host device 2 is cold, which is a data color corresponding to the TLC mode, the controller 100 writes the write data to the NAND memory 200 in the TLC mode. When the data color notified from the host device 2 is hot, which is a data color corresponding to the SLC mode, and the number of free blocks is less than the third value, the controller 100 writes the write data to the NAND memory 200 in the TLC mode. When the data color notified from the host device 2 is hot, which is a data color corresponding to the SLC mode, and the number of free blocks is more than the third value, the controller 100 writes the write data to the NAND memory 200 in the SLC mode.

[0327] Even when the controller 100 receives a notification from the host device 2 that the write data is hot, if there are not enough free blocks left, the controller 100 writes the write data to the NAND memory 200 in TLC mode. This prevents free blocks from running out during the planned period and requiring eviction.

[0328] (Ninth Implementation Method)

[0329] In some embodiments, when operating in the power-limited mode, the controller 100 reduces the amount of processing for the transfer process and uses a storage mode with a small number of layers when writing data to the NAND memory 200. However, when reducing the amount of processing for the transfer process and using a storage mode with a small number of layers in the power-limited mode, the number of free blocks decreases faster than in the normal mode. When the free blocks are exhausted, it is difficult for the controller 100 to continue operating in the power-limited mode.

[0330] In the ninth embodiment, the storage system 1 can transmit status information related to whether or not power consumption can be suppressed to the host device 2. The status information is described as related information.

[0331] The host device 2 can use the related information to determine the timing to operate the storage system 1 in the power limit mode, the period to operate the storage system 1 in the power limit mode, the start timing of the planned period, or the planned period.

[0332] The associated information is, for example, numerical information indicating the maximum value of the period during which the operation in the power limit mode can be performed (or the period which can be set as the planned period). The controller 100 calculates the maximum value of the period during which the operation in the power limit mode can be performed (or the period which can be set as the planned period) based on the number of free blocks, etc., and sends the maximum value as the associated information to the host device 2.

[0333] In another example, the associated information is the number of free blocks. The controller 100 sends the number of free blocks as the associated information to the host device 2. The host device 2 calculates the maximum value of the period during which the operation in the power limit mode can be performed (or the period that can be set as the planned period) based on the number of free blocks received as the associated information.

[0334] In another example, the associated information may be binary information indicating whether the operation in the power consumption limit mode (or the start of the planned period) can be performed. Alternatively, the associated information may be numerical information indicating the length of the period during which the operation in the power consumption limit mode (or the start of the planned period) is prohibited. Alternatively, the associated information may be a maximum value that can be set to a predetermined power consumption.

[0335] In this way, the content of the related information can be configured arbitrarily.

[0336] Fig.23 FIG. 1 is a diagram for explaining an example of a method in which the storage system 1 according to the ninth embodiment sends related information to the host device 2. Fig.23 In the description of , it is assumed that it is numerical information indicating the maximum value of the period that can be set as the planned period as an example.

[0337] The host device 2 first sends a related information output instruction to the storage system 1 (S1301).

[0338] The associated information output instruction can be sent by using any command. For example, a manufacturer-specific command value can also be assigned as a command for sending the associated information output instruction. The command for sending the associated information output instruction can also be added to the standard of the communication interface 3. The host device 2 and the storage system 1 are connected by a dedicated signal line for transmitting the associated information output instruction, and the host device 2 can also send the associated information output instruction to the storage system 1 via the dedicated signal line.

[0339] In the storage system 1, the controller 100 calculates the associated information (in this example, the maximum value tmax of the period that can be set as the planned period) according to the associated information output instruction (S1302). For example, the controller 100 obtains the number of free blocks at the current time point, and calculates the maximum value of the period that can be set as the planned period based on the obtained number of free blocks.

[0340] Then, the controller 100 transmits the maximum value obtained by calculation to the host device 2 as associated information (S1303).

[0341] The host device 2 determines a period shorter than tmax as a planned period ( S1304 ), and transmits the estimated power consumption, the determined planned period, and a power amount limitation instruction to the storage system 1 ( S1305 ).

[0342] In addition, as mentioned above, the controller 100 can send the maximum value of the period during which operation in the power limitation mode can be performed, the current number of free blocks, binary information indicating whether the operation in the power limitation mode can be performed, binary information indicating whether the planned period can be set, numerical information indicating the length of the period during which operation in the power limitation mode is prohibited, numerical information indicating the length of the period during which the start of the planned period is prohibited, the maximum value that can be set to a predetermined power consumption, or a combination of all or part of these as associated information.

[0343] In addition, the ninth embodiment can be used in combination with any one of the first embodiment to the eighth embodiment. The content of the related information can be variously changed according to the embodiment used in combination with the ninth embodiment.

[0344] As described above, in the ninth embodiment, the controller 100 transmits the related information, which is information related to whether or not power consumption can be suppressed, to the host device 2 in response to the related information output instruction from the host device 2 .

[0345] Thus, the host device 2 can determine whether the storage system 1 can be switched to the power limitation mode, the period during which the storage system 1 can operate in the power limitation mode, whether the storage system 1 can start the planned period, the period that can be set as the planned period, etc.

[0346] (Variation Example)

[0347] The controller 100 of the storage system 1 may not transmit the associated information to the host device 2 .

[0348] For example, the controller 100 of the storage system 1 may be configured to not perform the work corresponding to the power limit instruction even if the power limit instruction is received during a predetermined period from the timing when the power limit release instruction is received. Alternatively, the controller 100 of the storage system 1 may not start the work corresponding to the power limit instruction even if the power limit instruction is received during a predetermined period from the timing when the power limit release instruction is received, and instead send a message to the host device 2 that the work corresponding to the power limit instruction is not performed.

[0349] Alternatively, the controller 100 of the storage system 1 may be configured to not perform the operation corresponding to the power limit instruction even if the power limit instruction is received during the predetermined period from the end timing of the planned period. The controller 100 of the storage system 1 may not start the operation corresponding to the power limit instruction even if the power limit instruction is received during the predetermined period from the end timing of the planned period, and instead send a message to the host device 2 that the operation corresponding to the power limit instruction is not performed.

[0350] (10th embodiment)

[0351] The host device 2 can send various instructions (power restriction instructions, power restriction release instructions, or related information output instructions, etc.) or various information (planned power consumption, planned period, or planned host access volume, etc.) to the storage system 1 of the first to ninth embodiments based on arbitrary judgments.

[0352] For example, when the information processing system 10 is a portable computer, the host device 2 can transmit a power amount limitation instruction based on whether the information processing system 10 is receiving power supply from a power source.

[0353] Alternatively, the host device 2 learns how the operator uses the information processing system 10 during a predetermined period (e.g., one day or one week). Specifically, the information learned as the operator's usage of the information processing system 10 is a change in workload, a timing of connecting / disconnecting the information processing system 10 to a power source, or a history of changes in battery capacity over time. Based on the information obtained through learning, the host device 2 predicts future conditions related to the power of the information processing system 10. Furthermore, the host device 2 sends various instructions or information to the storage system 1 based on the prediction.

[0354] In one example, even when the power supply from the power supply is interrupted, when the workload is light and it is predicted that the host device 2 will immediately resume the power supply from the power supply, the host device 2 does not send a power limit indication, so that the storage system 1 maintains its normal operation mode.

[0355] In other examples, even when the information processing system 10 receives power from the power supply, when it is predicted that the host device will immediately interrupt the power supply from the power supply, the host device 2 suppresses the power consumption of the storage system 1 by sending a power limit indication to the storage system 1, and uses the suppressed amount of power to charge the battery.

[0356] In this way, the host device 2 can control the power consumption of the storage system 1 based on arbitrary determination.

[0357] According to the first to tenth embodiments, the storage system 1 includes the NAND memory 200 as a nonvolatile memory and the controller 100 that controls the NAND memory 200. The controller 100 suppresses power consumption of the storage system 1 in accordance with a power limit instruction from the host device 2.

[0358] Thereby, the host device 2 can control the power consumption.

[0359] Several embodiments of the present invention have been described above, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the purpose of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A storage system capable of being connected to a host device, comprising: non-volatile memory; and a controller that controls the nonvolatile memory to suppress power consumption of the storage system according to a first instruction from the host device, the controller, transferring data between the host device and the non-volatile memory, receiving a first value and a second value from the host device, Data of an amount corresponding to the second value is transferred between the host device and the nonvolatile memory according to the first instruction so that the power consumption does not exceed an amount corresponding to the first value.

2. A storage system capable of being connected to a host device, comprising: non-volatile memory; and a controller that controls the nonvolatile memory to suppress power consumption of the storage system according to a first instruction from the host device, The nonvolatile memory includes a plurality of memory cell transistors, each of which is configured so that the number of bits of stored data is variable. the controller, receiving a first value and a second value from the host device, the power consumption is controlled according to the first instruction so that the power consumption in the period corresponding to the second value does not exceed the amount corresponding to the first value, generating an electric energy plan that defines a transition of the upper limit value of the electric energy consumption based on the first value and the second value; controlling the power consumption based on the power consumption plan according to the first instruction, capable of operating in a plurality of operating modes including a first operating mode and a second operating mode consuming less power than the first operating mode, performing switching between the plurality of working modes based on the power consumption plan, In the second operation mode, a notification from the host device is received, and data having a number of bits corresponding to the notification is written into a memory cell transistor at a write destination.

3. A storage system capable of being connected to a host device, comprising: non-volatile memory; and a controller that controls the nonvolatile memory to suppress power consumption of the storage system according to a first instruction from the host device, The nonvolatile memory includes a plurality of memory cell transistors, each of which is configured such that the number of bits of data stored therein is variable, and each of which is divided into a plurality of blocks in which the data stored therein are erased together. the controller, receiving a first value and a second value from the host device, the power consumption is controlled according to the first instruction so that the power consumption in the period corresponding to the second value does not exceed the amount corresponding to the first value, generating an electric energy plan that defines a transition of the upper limit value of the electric energy consumption based on the first value and the second value; controlling the power consumption based on the power consumption plan according to the first instruction, capable of operating in a plurality of operating modes including a first operating mode and a second operating mode consuming less power than the first operating mode, performing switching between the plurality of working modes based on the power consumption plan, In the second working mode, receiving a notification from the host device, When the notification corresponds to the first bit, the data of the first bit is written into the memory cell transistor of the writing destination. When the notification corresponds to a second digit smaller than the first digit and the number of free blocks in the plurality of blocks is smaller than a third value, writing the data of the first digit to the storage cell transistor of the write destination, When the notification corresponds to the second bit number and the number of free blocks among the plurality of blocks is larger than a third value, the data of the second bit number is written to the memory cell transistor of the write destination.

4. A storage system capable of being connected to a host device, comprising: non-volatile memory; and a controller that controls the nonvolatile memory to suppress power consumption of the storage system according to a first instruction from the host device, The nonvolatile memory includes a plurality of memory cell transistors, each of which is configured so that the number of bits of stored data is variable. the controller, receiving a first value and a second value from the host device, the power consumption is controlled according to the first instruction so that the power consumption in the period corresponding to the second value does not exceed the amount corresponding to the first value, The power consumption is suppressed by reducing the number of bits of data to be written to the memory cell transistor at the writing destination.

5. A storage system capable of being connected to a host device, comprising: non-volatile memory; and a controller that controls the nonvolatile memory to suppress power consumption of the storage system according to a first instruction from the host device, the controller, receiving a first value and a second value from the host device, the power consumption is controlled according to the first instruction so that the power consumption in the period corresponding to the second value does not exceed the amount corresponding to the first value, generating an electric energy plan that defines a transition of the upper limit value of the electric energy consumption based on the first value and the second value; controlling the power consumption based on the power consumption plan according to the first instruction, executing a first process of transferring data between the host device and the nonvolatile memory and a second process of transferring data into the nonvolatile memory, capable of operating in a plurality of operating modes including a first operating mode, a second operating mode in which power consumption is less than that of the first operating mode, and a third operating mode in which the processing amount of the second process is greater than that of the first operating mode, Switching between the plurality of operating modes is performed based on the power amount plan.

6. The storage system according to any one of claims 1 to 4, The controller executes a first process of transferring data between the host device and the nonvolatile memory and a second process of transferring data into the nonvolatile memory, and reduces a processing amount of the second process according to the first instruction.

7. The storage system according to any one of claims 1 to 5, The nonvolatile memory includes a plurality of blocks in which data stored in each block is erased together. The controller performs garbage collection, When the first instruction is received, a block to be dumped in the garbage collection is selected from the plurality of blocks according to a first policy based only on the amount of valid data stored. When the first instruction is not received, a block to be dumped in the garbage collection is selected from the plurality of blocks according to a second policy different from the first policy.

8. The storage system according to claim 7, The first policy is a policy that, among the plurality of blocks, a block storing a smaller amount of valid data is selected more preferentially as the block to be transferred.

9. The storage system according to claim 7, The second policy is a policy for selecting a block to be transferred to in the garbage collection from among the plurality of blocks based on the time at which data was last written.

10. The storage system according to any one of claims 1 to 5, The controller receives first information related to the power consumption from the host device, and acquires the power consumption based on the first information.

11. The storage system according to claim 4, The plurality of memory cell transistors are divided into a plurality of blocks in which the data stored in the blocks are erased together. the controller, When the number of free blocks in the plurality of blocks is smaller than a third value, data of the first bit is written to the memory cell transistor of the write destination, When the number of free blocks among the plurality of blocks is greater than a third value, data of a second number of bits less than the first number of bits is written to the memory cell transistor of the write destination.

12. The storage system according to any one of claims 1 to 5, The controller transmits information related to whether or not the power consumption can be suppressed to the host device in response to a second instruction from the host device.

13. An information processing system comprising: a host device; and A storage system according to any one of claims 1 to 5 connected to the host device.

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