Adaptive background scanning in memory subsystems

Abstract

This application relates to adaptive background scanning in memory subsystems. A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of a plurality of physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to adaptive background scanning in memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. Memory components may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application provides a system comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: maintaining a log of error events associated with the memory device, each error event contained in the log being associated with one of a plurality of physical locations within the memory device; identifying physical locations within the memory device based on the log of error events for background scanning; and performing background scanning on the physical locations identified based on the log of error events.

[0004] In another aspect, this application provides a method comprising: maintaining a log of error events associated with a memory device, each error event contained in the log being associated with one of a plurality of physical locations within the memory device; identifying physical locations within the memory device based on the log of error events for background scanning; and performing background scanning on the identified physical locations.

[0005] In another aspect, this application provides a computer-readable storage medium including instructions that, when executed by a processing device, configure the processing device to perform operations including: maintaining a log of error events associated with a memory device, each error event contained in the log being associated with one of a plurality of physical locations within the memory device; identifying physical locations within the memory device based on the log of error events for background scanning; and performing background scanning on the identified physical locations. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2This is a data flow diagram illustrating the interactions between components of a memory subsystem during adaptive background scanning, according to some embodiments of the present disclosure.

[0009] Figure 3 and 4 A flowchart illustrating an example method for performing adaptive background scanning in a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 5 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0011] Various aspects of this disclosure relate to performing adaptive background scanning in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem containing one or more memory devices, such as those for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0012] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device. The following section will discuss this further. Figure 1 Other examples of non-volatile memory devices are described. Data operations can be performed by the memory subsystem. Data operations can be initiated by the host. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on the memory device at the memory subsystem and to read data from the memory device at the memory subsystem.

[0013] Some memory devices (e.g., NAND memory devices) include arrays of memory cells (e.g., flash cells) for storing data. Each cell contains a transistor, and within each cell, data is stored as a threshold voltage of the transistor based on the cell's logic value (e.g., 0 or 1). During a read operation, a read reference voltage is applied to the transistor, and if the read reference voltage is higher than the cell's threshold voltage, the transistor is programmed and identified by the memory subsystem as a binary value of 0. Memory cells in these devices can be grouped into pages that refer to logical cells of the memory device used for storing data. For some types of memory devices (e.g., NAND), pages are grouped to form blocks (also referred to herein as "memory blocks").

[0014] Background scan operations can run in the background of the memory subsystem (e.g., during an idle period when the memory subsystem is performing other operations and is not responding to a host-initiated command). A memory device background scan can be initiated by reading a segment of the memory device (e.g., a codeword, block, or portion of a block). The background scan can track the number of bit corrections required to determine the quality of the memory segment. The background scan can also determine whether a segment is uncorrectable. The memory segment can be analyzed to determine metrics (e.g., the amount or type of error correction required, the estimated remaining lifetime, the number of cells operating below a threshold level, and whether the segment is uncorrectable). If the metric is above the threshold, the background scan can proceed to the next memory segment. If the metric is below the threshold, the background scan can attempt correction measures, for example, by performing a refresh relocation event on the memory segment or the memory portion associated with the memory segment. For example, if a portion of a block is read and determined to have a metric below the threshold, a refresh relocation event can be performed on the block containing the read portion after data has been recovered using a system-driven read recovery method.

[0015] Conventionally, background scanning is performed at a specific frequency throughout the lifetime of the memory device. In some conventional implementations, the memory subsystem controller operates a timer, and when the timer reaches a timing threshold (e.g., 3 minutes), a background scan is initiated. The conventional approach to background scanning is to attempt as aggressively as possible and capture as many instances as possible. However, this conventional approach fails to account for the variability in the quality and weaknesses of certain devices, such as NAND flash memory. For example, a given memory device can exhibit significant variability in the physical location where an error event might occur. This means that a background scan might repeatedly target certain locations where an error event is unlikely to occur, while ignoring other areas where an error event is highly probable. Therefore, the conventional approach results in insufficient background scanning, which often reduces the relative performance and reliability of the memory device.

[0016] Various aspects of this disclosure address the problems of conventional background scanning techniques by utilizing an adaptive background scanning method. The adaptive background scanning method uses error data from background scanning and other data integrity checks to identify physical locations within the memory device where error events, such as read errors, error handling events, or block folding events, frequently occur. Components of the memory subsystem controller (e.g., firmware) aggregate and use the error data to increase the rate of background scanning at high-risk locations within the memory device.

[0017] The adaptive background scanning method described herein improves the overall reliability of the memory subsystem by adapting to and compensating for variability in the memory device and workload. For example, the background scanning component targets the worst-case segment of the memory device more frequently by scanning it more often. The adaptive background scanning method also provides an adaptive solution to NAND offsets (e.g., material variations or manufacturing line shifts). Furthermore, the adaptive background scanning method allows high-value systems to utilize low-quality NAND devices. Additionally, the adaptive background scanning method improves the overall efficiency of background scanning by focusing on the worst-case segment of the memory device, thereby improving device reliability without sacrificing the performance of additional scans. In this way, the overall rate of background scanning can be reduced while still ensuring the same level of reliability.

[0018] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

[0023] Host system 120 may be coupled to memory subsystem 110 via a host interface. Examples of host interfaces include, but are not limited to, SATA interfaces, PCIe interfaces, USB interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, DIMM interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface). The host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-place write memory, such as three-dimensional (3D) crosspoint memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and 3D NAND.

[0026] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0027] While non-volatile memory components such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point non-volatile memory cell arrays are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0030] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include ROM for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0031] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and ECC, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system 120 into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0032] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130.

[0033] The memory subsystem 110 also includes an Adaptive Background Scan (ABS) component 113 responsible for managing and performing background scans on memory devices 130 and 140. During a background scan, the ABS component 113 reads data from a portion (e.g., a page, block, or portion of a block) of one of the memory devices 130 or 140 to determine metrics (e.g., the amount or type of error correction required, the estimated remaining lifetime, the number of cells operating below a threshold level, and the segment being uncorrectable by the ECC engine), and if the metric is below the threshold, performs a correction action via the memory subsystem controller 115, such as by performing a refresh relocation event on the portion of the memory device from which data is read. To improve the efficiency of the background scan, the ABS component 113 maintains one or more logs of error events occurring at memory devices 130 and 140 and uses one or more logs to identify physical locations within devices 130 and 140 for use in the background scan. As an example, the ABS component 113 may maintain a first log identifying error events via NAND chips and a second log identifying error events via word lines.

[0034] In some embodiments, the memory subsystem controller 115 includes at least a portion of the ABS component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the ABS component 113 is part of the host system 120, an application, or an operating system. In some embodiments, the local media controller 135 includes at least a portion of the ABS component 113.

[0035] Figure 2 This is a data flow diagram illustrating the interactions between components of a memory subsystem during adaptive background scanning, according to some embodiments of the present disclosure. Figure 2 In the example described herein, memory device 130 is a NAND memory device comprising multiple memory blocks.

[0036] As shown, NAND block 200 comprises an array (2D or 3D) of pages (rows) and strings (columns). Each NAND cell contains a transistor, and within each cell, data is stored as the threshold voltage of the transistor. For example, SLC NAND can store one bit per cell. Other types of memory cells, such as MLC, TLC, QLC, and PLC, can store multiple bits per cell. Strings are connected within NAND block 200 to allow data to be stored and retrieved from selected cells. NAND cells in the same column are connected in series to form a bit line (BL). All cells in a bit line are connected to a common ground at one end and to a common sense amplifier at the other end for reading the threshold voltage of one of the cells when decoding data. NAND cells are horizontally connected to word lines (WL) at their control gates to form pages. In MLC, TLC, QLC, and PLC NAND, a page is a collection of connected cells that share the same word line and are the smallest unit of programming.

[0037] The ABS component 113 constructs and maintains an error event log 201 based on error data generated by the memory subsystem controller 115 and the memory device 130. The error event log contains error events detected at the memory device 130. For example, error events may be detected during a background scan. These error events include, for example, read errors, error handling events, and block refresh events described in the error data generated by the memory subsystem controller 115. Each error event contained in the error event log 201 is associated with a physical location (e.g., a page, block, or portion thereof) within the memory device 130. More specifically, each entry in the error event log 201 indicates the type of error event (e.g., read error, error handling event, and block refresh event) and an identifier corresponding to the physical location within the memory device 130 where the event occurred.

[0038] In some embodiments, the error event log 201 is limited to a predetermined number of recent error events. Therefore, once the number of error events in the error event log 201 reaches the predetermined number, the ABS component 113 removes the oldest error event from the log and then adds the newly detected error event. In some embodiments, multiple instances of a single error event may be added to the error event log 201. By adding multiple instances of a single error event, the ABS component 113 can increase the probability of selecting the physical location corresponding to the error event for a background scan.

[0039] At 202, the ABS component 113 continuously monitors and aggregates error data corresponding to the error event log 201, and at a predefined frequency, the ABS component 113 uses the error event log 201 to identify physical locations within the memory device 130 (at 204), and the ABS component 113 performs a background scan on the identified physical locations (at 206). For example, the ABS component 113 may randomly select error events from the error event log 201 and perform a background scan on the corresponding physical locations. The ABS component 113 utilizes a timer (e.g., operated via the memory subsystem controller 115), and when the time reaches a timing threshold, the ABS component 113 identifies the physical locations and performs a background scan on said physical locations. In this way, the ABS component 113 performs background scans at a predefined frequency. The ABS component 113 may adjust the frequency of the background scan based on the rate of error events (e.g., errors per power-on time, errors per written byte, or errors per program-erase cycle). Therefore, the ABS component 113 may include a counter to track the total number of error events added to the error event log 201.

[0040] During a background scan of a physical location, the ABS component 113 analyzes data read from the physical location to determine metrics (e.g., the amount or number of bit errors, the amount or type of error correction required, the estimated remaining lifetime, the number of cells operating below a threshold level, and segments that cannot be corrected by the ECC engine). If the metric is below the threshold, a correction action is performed via the memory subsystem controller 115, for example, by performing a refresh relocation event on the physical location. For example, if a page in memory device 130 is read and determined to have a metric below the threshold, a refresh relocation event can be performed for that page. During the refresh relocation event, data from the scanned page is copied to a new physical location within the memory device (e.g., an open page in open block 200 of memory device 130). If an error event is detected during the background scan (e.g., if the error metric exceeds the threshold), the ABS component 113 can add the newly detected error event to the error event log 201 to support continuous ABS management within the memory subsystem 110.

[0041] Figure 3 and 4 This is a flowchart illustrating an example method 300 for adaptive background scanning in a memory subsystem (e.g., memory subsystem 110) according to some embodiments of the present disclosure. Method 300 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The ABS component 113 is executed. Although the processes are shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0042] At operation 305, the processing device maintains a log (e.g., error event log 201) of error events occurring at one or more memory devices (e.g., memory devices 130 and / or 140). Each error event in the error log is associated with a physical location on the memory device. More specifically, each entry in the error event log contains an indicator of the error event type and an identifier corresponding to the physical location in the memory device where the error event occurred. Multiple examples of a given error event may be included in the log to increase the probability of selecting the location for a background scan.

[0043] To maintain a log of error events, the processing device aggregates error data generated at one or more memory devices and / or memory subsystem controllers coupled to one or more memory devices. The error data aggregated by the processing device describes read errors, error handling events, and block folding events detected at the memory devices. Therefore, the log of error events identifies read errors, error handling events, and block folding events detected at one or more memory devices. Consistent with some embodiments, the processing device may maintain multiple logs of error events. For example, the processing device may maintain a first log identifying error events via a NAND chip or device and a second log identifying error events via word lines.

[0044] In some embodiments, the error event log is limited to a predetermined number of the most recent error events. Therefore, once the error event log reaches the predetermined number, the processing device removes the oldest error event from the log and then adds the newly detected error event.

[0045] At operation 310, the processing unit identifies the physical location within the memory device based on the error event log for background scanning. For example... Figure 4 As shown in the diagram, consistent with some embodiments, operation 310 may include operations 405 and 410. At operation 405, the processing device randomly selects an error event from the error event log, and at operation 410, the processing device identifies the physical location corresponding to the randomly selected error event.

[0046] Return to Figure 3 In some embodiments, the processing device identifies physical locations for background scanning based on the number or frequency of error events occurring at those locations. For example, to identify physical locations, the processing device may determine the number of error events in a log associated with each physical location included in the log. The processing device may then select the physical location with the highest number of error events for background scanning.

[0047] In some embodiments, the processing device identifies physical locations for background scanning based on a predicted probability that a future error event will occur at a physical location. For example, the processing device may analyze a log of error events to predict the probability of a future error event occurring at each physical location included in the log and select the physical location with the highest probability.

[0048] At operation 315, the processing device performs a background scan on the identified physical location. During the background scan, the processing device analyzes data read from the physical location to determine error metrics (e.g., the amount or type of error correction required, estimated remaining lifetime, the number of cells operating below a threshold level, the physical location being uncorrectable by the ECC engine, etc.), and if the error metric is below the threshold, a correction action is performed via the memory subsystem controller 115, for example, by performing a refresh relocation event on the physical location. For example, if a page in memory device 130 is read and determined to have a metric below the threshold, a refresh relocation event can be performed on that page. During the refresh relocation event, data from the scanned page is copied to a new physical location within the memory device (e.g., an open page in open block 200 of memory device 130). If an error event is detected during the background scan (e.g., if the error metric exceeds the threshold), the processing device can add the newly detected error event to a log to support continuous ABS management within the memory subsystem.

[0049] Consistent with some embodiments, operation 305 is performed, and operations 310 and 315 can be repeated at a predetermined frequency. That is, while a new error event is detected and a new physical location is identified and scanned at a predefined frequency, the processing device continues to update the error event log. For example, after scanning a first physical location identified based on the error event log, the processing device waits for a predefined interval (based on the predetermined frequency) before identifying and scanning a second physical location in the memory device based on the log. Consistent with some embodiments, the processing device can vary the frequency at which physical locations are selected (operation 310) and scanned (operation 315). For example, the processing device can vary the frequency based on the rate of error events (e.g., errors per power-on time, errors per byte written, or errors per program-erase cycle).

[0050] Consistent with some embodiments, conventional background scanning of portions of the random scanning memory device may be performed at a predefined frequency and method 300 may be repeated. For example, at each interval, at least operations 310 and 315 may be performed in conjunction with conventional background scanning (e.g., before or after).

[0051] Example

[0052] Example 1 is a memory subsystem comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: maintaining a log of error events associated with the memory device, each error event contained in the log being associated with one of a plurality of physical locations within the memory device; identifying physical locations within the memory device based on the log of error events for background scanning; and performing background scanning on the physical locations identified from the memory device.

[0053] Example 2 includes a memory subsystem according to Example 1, wherein identifying the physical location within the memory device includes: randomly selecting an error event from the log of error events; and determining that the physical location is associated with the error event.

[0054] Example 3 includes a memory subsystem according to any one of Examples 1 and 2, wherein identifying the physical location within the memory device includes: determining the number of error events in the log associated with the physical location; and selecting the physical location based on the number of error events in the log associated with the physical location.

[0055] Example 4 includes a memory subsystem according to any one of Examples 1 to 3, wherein identifying the physical location within the memory device includes: predicting the probability of a future error event occurring at the physical location of the memory device; and selecting the physical location based on the probability of the future error event occurring at the physical location.

[0056] Example 5 includes a memory subsystem according to any of Examples 1 to 4, wherein the log maintaining error events includes aggregated data describing read errors, error handling events, and block folding events detected at the memory device.

[0057] Example 6 includes a memory subsystem according to any one of Examples 1 to 5, wherein the log of error events is limited to a predetermined number of recent error events.

[0058] Example 7 includes a memory subsystem according to any one of Examples 1 to 6, wherein: the physical location is a first physical location; the background scan is a first background scan; and the operation further includes: identifying a second physical location within the memory device for background scanning after a predetermined interval; and performing a background scan on the second physical location.

[0059] Example 8 is a method comprising: maintaining a log of error events associated with a memory device, each error event contained in the log being associated with one of a plurality of physical locations within the memory device; identifying physical locations within the memory device based on the log of error events for background scanning; and performing background scanning on the identified physical locations.

[0060] Example 9 includes the method according to Example 8, wherein identifying the physical location within the memory device includes: randomly selecting an error event from the log of error events; and determining that the physical location is associated with the error event.

[0061] Example 10 includes the method according to any one of Examples 8 and 9, wherein identifying the physical location within the memory device includes: determining the number of error events in the log associated with the physical location; and selecting the physical location based on the number of error events in the log associated with the physical location.

[0062] Example 11 includes the method according to any one of Examples 8 to 10, wherein identifying the physical location within the memory device includes: predicting the probability of a future error event occurring at the physical location of the memory device; and selecting the physical location based on the probability of the future error event occurring at the physical location.

[0063] Example 12 includes the method according to any one of Examples 8 to 11, wherein the log maintaining error events includes aggregated data describing read errors, error handling events, and block folding events detected at the memory device.

[0064] Example 13 includes the method described in any of Examples 8 to 12, wherein the log of error events is limited to a predetermined number of recent error events.

[0065] Example 14 includes the method according to any one of Examples 8 to 13, wherein: the physical location is a first physical location; the background scan is a first background scan; and the method further includes: identifying a second physical location within the memory device for background scanning after a predetermined interval; and performing a background scan on the second physical location.

[0066] Example 15 is a computer-readable storage medium including instructions that, when executed by a processing device, configure the processing device to perform operations including: maintaining a log of error events associated with a memory device, each error event contained in the log being associated with one of a plurality of physical locations within the memory device; identifying physical locations within the memory device based on the log of error events for background scanning; and performing background scanning on the identified physical locations.

[0067] Example 16 includes a computer-readable storage medium according to Example 15, wherein identifying the physical location within the storage device includes: randomly selecting an error event from the log of error events; and determining that the physical location is associated with the error event.

[0068] Example 17 includes a computer-readable storage medium according to any one or more of Examples 15 and 16, wherein identifying the physical location within the storage device includes: determining the number of error events in the log associated with the physical location; and selecting the physical location based on the number of error events in the log associated with the physical location.

[0069] Example 18 includes a computer-readable storage medium according to any one or more of Examples 15 to 17, wherein the log maintaining error events includes aggregated data describing read errors, error handling events, and block folding events detected at the memory device.

[0070] Example 19 includes a computer-readable storage medium according to any one or more of Examples 15 to 18, wherein the log of error events is limited to a predetermined number of recent error events.

[0071] Example 20 includes a computer-readable storage medium according to any one or more of Examples 15 to 19, wherein: the physical location is a first physical location; the background scan is a first background scan; and the operation further includes: identifying a second physical location within the memory device for background scanning after a predetermined interval; and performing a background scan on the second physical location.

[0072] Figure 5 An example machine in the form of a computer system 500 is described, within which a set of instructions for causing the machine to perform any or more of the methods discussed herein can be executed. Figure 5 An example machine is described as representing computer system 500, within which a set of instructions for causing the machine to perform any or more of the methods discussed herein is executable. In some embodiments, computer system 500 may correspond to including, coupled to, or utilizing a memory subsystem (e.g., Figure 1 The host system (e.g., memory subsystem 110) of the memory subsystem 110 Figure 1 The host system 120, or a system that can be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of ABS component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0073] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein.

[0074] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., ROM, flash memory, DRAM such as SDRAM or RDRAM), a static memory 506 (e.g., flash memory, static random access memory (SRAM) such as SRAM), and a data storage system 518, which communicate with each other via a bus 530.

[0075] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as ASICs, FPGAs, digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication on network 520.

[0076] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more instruction sets 526 or software embodying any or more of the methods or functions described herein are stored. The instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, the main memory 504 and processing device 502 also constituting machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0077] In one embodiment, instruction 526 includes instructions for implementing a data destruction component (e.g., Figure 1 The ABS component 113) contains functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0078] Some parts of the previously described in detail have been presented with respect to the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented as a way for those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm here is, and generally is, considered a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0079] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system, or other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0080] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for a particular purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), ROM, RAM, EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0081] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to execute the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0082] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes, for example, ROM, RAM, disk storage media, optical storage media, flash memory components, and other machine-readable (e.g., computer-readable) storage media.

[0083] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: a memory device; and a processing device operatively coupled with the memory device to perform operations comprising: maintaining a log of error events associated with the memory device, each error event included in the log being associated with one of a plurality of physical locations within the memory device; identifying a physical location within the memory device for performing a background scan based on the log of error events, identifying the physical location comprising: randomly selecting an error event from the log of error events; and determining the physical location associated with the error event; and performing a background scan on the physical location identified based on the log of error events.

2. The system of claim 1, wherein: the physical location is a first physical location; the background scan is a first background scan; the operations further comprise: identifying a second physical location within the memory device for performing a background scan based on the log of error events; and performing a second background scan on the second physical location.

3. The system of claim 2, wherein identifying the second physical location within the memory device comprises: determining a number of error events in the log associated with the second physical location; and selecting the second physical location based on the number of error events in the log associated with the second physical location.

4. The system of claim 2, wherein identifying the second physical location within the memory device comprises: predicting a likelihood of a future error event occurring at the second physical location of the memory device; and selecting the second physical location based on the likelihood of the future error event occurring at the second physical location.

5. The system of claim 2, wherein: the identification of the second physical location within the memory device is performed after a predetermined interval.

6. The system of claim 1, wherein maintaining the log of error events comprises aggregating data describing read errors, error handling events, and block folding events detected at the memory device.

7. The system of claim 1, wherein the log of error events is limited to a predetermined number of most recent error events.

8. A method comprising: maintaining a log of error events associated with a memory device, each error event included in the log being associated with one of a plurality of physical locations within the memory device; identifying a physical location within the memory device for performing a background scan based on the log of error events, identifying the physical location comprising: randomly selecting an error event from the log of error events; and determining the physical location associated with the error event; and performing a background scan on the identified physical location.

9. The method of claim 8, wherein: the physical location is a first physical location; the background scan is a first background scan; the method further comprises: ​ ​ identify a second physical location within the memory device for a background scan based on the log of error events; and perform a second background scan on the second physical location.

10. The method of claim 9, wherein identifying the second physical location within the memory device comprises: determining a number of error events in the log associated with the second physical location; and selecting the second physical location based on the number of error events in the log associated with the second physical location.

11. The method of claim 10, wherein: the identifying of the second physical location within the memory device is performed after a predetermined interval.

12. The method of claim 9, wherein identifying the second physical location within the memory device comprises: predicting a likelihood of a future error event occurring at the second physical location of the memory device; and selecting the second physical location based on the likelihood of the future error event occurring at the second physical location.

13. The method of claim 8, wherein maintaining the log of error events comprises aggregating data describing read errors, error handling events, and block folding events detected at the memory device.

14. The method of claim 8, wherein the log of error events is limited to a predetermined number of most recent error events.

15. A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: maintaining a log of error events associated with a memory device, each error event included in the log being associated with one of a plurality of physical locations within the memory device; identifying a physical location within the memory device for a background scan based on the log of error events, identifying the physical location comprising: randomly selecting an error event from the log of error events; and determining the physical location associated with the error event; and performing a background scan on the identified physical location.

16. The computer-readable storage medium of claim 15, wherein: the physical location is a first physical location; the background scan is a first background scan; the operations further comprise: identifying a second physical location within the memory device for a background scan based on the log of error events; and performing a second background scan on the second physical location.

17. The computer-readable storage medium of claim 16, wherein identifying the second physical location within the memory device comprises: determining a number of error events in the log associated with the second physical location; and selecting the second physical location based on the number of error events in the log associated with the second physical location.

18. The computer-readable storage medium of claim 16, wherein: the identifying of the second physical location within the memory device is performed after a predetermined interval.

19. The computer-readable storage medium of claim 15, wherein maintaining the log of error events comprises aggregating data describing read errors, error handling events, and block folding events detected at the memory device.

20. The computer-readable storage medium of claim 15, wherein the log of error events is limited to a predetermined number of most recent error events.

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