High-speed peripheral component interconnect interface device and operation method thereof

Abstract

The present disclosure provides a high-speed peripheral component interconnect (PCIe) interface device and an operation method thereof. The PCIe interface device includes a first buffer, a second buffer and a buffer controller. The first buffer can be configured to store a plurality of first transaction layer packets received from a plurality of functions. The second buffer can be configured to store a plurality of second transaction layer packets received from a plurality of functions. The buffer controller can be configured to rearrange the order of outputting a plurality of second transaction layer packets from the second buffer to the switch based on the IDs of the plurality of second transaction layer packets when the first buffer of the switch is full.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2021-0037512 filed in the Korean Intellectual Property Office on March 23, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a PCIe interface device and a method of operating the PCIe interface device. Background Art

[0004] Peripheral Component Interconnect Express (PCIe) is an interface with a serial structure for data communication. A PCIe-based storage device supports a multi-port structure and a multi-function structure. A PCIe-based storage device may be virtualized or non-virtualized, and may implement quality of service (QoS) of host input / output (I / O) commands through one or more PCIe functions.

[0005] A storage device is a device that stores data under the control of a host device such as a computer or a smartphone. The storage device may include a memory device that stores data and a memory controller that controls the memory device. The memory device is divided into a volatile memory device and a non-volatile memory device.

[0006] A volatile memory device is a memory device that stores data only when power is supplied and loses the stored data when power is interrupted. Examples of volatile memory devices may include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0007] A nonvolatile memory device may be a memory device that retains stored data even when power is interrupted. Examples of nonvolatile memory devices may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory. Summary of the invention

[0008] Various embodiments of the present disclosure relate to a PCIe interface device having improved buffer control performance and a method of operating the PCIe interface device.

[0009] Embodiments of the present disclosure may provide a peripheral component interconnect express (PCIe) interface device. The PCIe interface device may include a first buffer, a second buffer, and a buffer controller.

[0010] The first buffer may be configured to store a plurality of first transaction layer packets received from a plurality of functions.

[0011] The second buffer may be configured to store a plurality of second transaction layer packets received from a plurality of functions. The buffer controller may be configured to rearrange the order in which the plurality of second transaction layer packets are to be output from the second buffer to the switch based on respective IDs of the plurality of second transaction layer packets when the first buffer of the switch is full.

[0012] An embodiment of the present disclosure may provide a method for operating a high-speed peripheral component interconnect (PCIe) interface device, the PCIe interface device including a first buffer configured to store a plurality of first transaction layer packets and a second buffer configured to store a plurality of second transaction layer packets. The method may include receiving a flow control signal from a switch indicating whether the first buffer of the switch is full, and when the first buffer included in the switch is full, rearranging the order in which the plurality of second transaction layer packets are to be output from the second buffer to the switch based on IDs of the plurality of second transaction layer packets. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The communication structure between the host and the PCIe device according to an embodiment of the present disclosure is shown.

[0014] Figure 2 The configuration and operation of a PCIe device according to an embodiment of the present disclosure are shown.

[0015] Figure 3 The configuration and operation of the PCIe interface device according to an embodiment of the present disclosure are shown.

[0016] Figure 4 The present invention describes reordering of transaction layer packets based on their IDs in a PCIe device.

[0017] Figure 5 is a flowchart illustrating the operation of a PCIe interface device according to an embodiment of the present disclosure.

[0018] Figure 6 is a flowchart illustrating the operation of a PCIe interface device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or this application are exemplary to describe the embodiments conceived according to the present disclosure. The embodiments conceived according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or this application.

[0020] Figure 1The communication structure between a host and a plurality of PCIe devices according to an embodiment of the present disclosure is shown.

[0021] Reference Figure 1 , the host 2000 may include a root complex 2100 , a switch 2200 , a central processing unit (CPU) 2300 , and a memory 2400 .

[0022] The root complex 2100 may connect the CPU 2300 and the memory 2400 to an input / output (I / O) hierarchy. The root complex 2100 may include at least one host bridge and at least one root port. The root complex 2100 may support one or more peripheral component interconnect (PCIe) ports.

[0023] Root complex 2100 may support input / output (I / O) requests. Root complex 2100 must support generating configuration requests. Root complex 2100 as a completer must not support lock semantics. Root complex 2100 as a requester may request generating lock requests.

[0024] The switch 2200 may connect at least two ports to each other in order to route transaction layer packets. The switch 2200 may be a set of virtual PCI-to-PCI bridge devices. The switch 2200 may be composed of two or more logical PCI-to-PCI bridges. The switch 2200 may use a PCI bridge mechanism (i.e., an address-based multicast method) to route transactions. The switch 2200 must route all types of transaction layer packets between all ports. The switch 2200 must support lock requests. Each enabled port of the switch 2200 must support flow control. When contention occurs on the same virtual channel, the switch 2200 may arbitrate the contention in a round-robin or weighted round-robin manner.

[0025] Each PCIe device can act as a requester or a completer of a PCIe transaction.

[0026] exist Figure 1 In the embodiment, a plurality of PCIe devices (e.g., first to third PCIe devices 1000_1 to 1000_3) are connected to a host 2000. The first PCIe device 1000_1 may send a transaction layer packet to a root complex 2100 and may receive a transaction layer packet from the root complex 2100. The second PCIe device 1000_2 and the third PCIe device 1000_3 may send a transaction layer packet to a switch 2200 and may receive a transaction layer packet from the switch 2200.

[0027] The switch 2200 may route the transaction layer packet received from the second PCIe device 1000_2 and the third PCIe device 1000_3 to the root complex 2100. The switch 2200 may route the transaction layer packet received from the root complex 2100 to the second PCIe device 1000_2 and the third PCIe device 1000_3.

[0028] Therefore, the root complex 2100 may directly send a transaction layer packet to the first PCIe device 1000_1 and may directly receive a transaction layer packet from the first PCIe device 1000_1. The root complex 2100 may send a transaction layer packet to the second PCIe device 1000_2 and the third PCIe device 1000_3 through the switch 2200 and may receive a transaction layer packet from the second PCIe device 1000_2 and the third PCIe device 1000_3 through the switch 2200. The root complex 2100 may forward the transaction layer packets received from the first PCIe device 1000_1 to the third PCIe device 1000_3 to the CPU 2300 or the memory 2400.

[0029] Figure 2 The configuration and operation of a PCIe device according to an embodiment of the present disclosure are shown.

[0030] Reference Figure 2 , the PCIe device 1000 may include a PCIe interface (I / F) device 100 and at least one direct memory access (DMA) device.

[0031] The PCIe interface device 100 may include a buffer group 110 and a buffer controller 120 .

[0032] The buffer group 110 may store transaction layer packets transmitted and received between the switch 2200 of the host 2000 and the function of the DMA device. The buffer group 110 may store a first transaction layer packet received from the function executed on the DMA device. The buffer group 110 may transmit the first transaction layer packet to the switch 2200. At the same time, the buffer group 110 may store a second transaction layer packet received from the switch 2200. The buffer group 110 may transmit the second transaction layer packet to the function of the DMA device.

[0033] The buffer controller 120 may control the order in which the plurality of transaction layer packets stored in the buffer group 110 are output to the switch 2200. In addition, the buffer controller 120 may rearrange the output order of the plurality of transaction layer packets.

[0034] In an embodiment, the DMA device may include a high-speed non-volatile memory (NVMe) module, an Ethernet card, a sound card, a graphics card, an artificial intelligence central processing unit (AI CPU) module, an artificial intelligence system on a chip (AI SoC) module, etc. The DMA device may further include a data communication device connected to the NVMe module, the Ethernet card, the sound card, the graphics card, the AI ​​CPU module, the AI ​​SoC module, etc.

[0035] exist Figure 2 In the embodiment, the PCIe device 1000 may include a plurality of DMA devices, for example, a first DMA device 200_1 and a second DMA device 200_2. The number of DMA devices included in the PCIe device 1000 is not limited to the present embodiment.

[0036] For each DMA device, at least one function can be performed. Figure 2 , the first function (function 1) and the second function (function 2) can be executed on the first DMA device 200_1, and the third function (function 3) and the fourth function (function 4) can be executed on the second DMA device 200_2. The number of functions executed on each DMA device is not limited to this embodiment.

[0037] For example, the PCIe device 1000 may generate a physical function or a virtual function in response to a virtualization request received from the host 2000. The PCIe device 1000 may allocate one or more functions to each DMA device. The number of functions allocated to each DMA device and executed on each DMA device may be set separately. Therefore, multiple functions may be allocated to one DMA device, and each function may be executed as an independent operation unit.

[0038] Figure 3 The configuration and operation of the PCIe interface device according to an embodiment of the present disclosure are shown.

[0039] Reference Figure 3 , the PCIe device 1000 may include a PCIe interface device 100 and a plurality of DMA devices 200_1 and 200_2 .

[0040] The PCIe interface device 100 may include a buffer group 110 , a buffer controller 120 , and a transaction layer 130 .

[0041] The buffer group 110 may send a transaction layer packet received from the function of each DMA device through the transaction layer 130 to the buffer group 110 as referred to above. Figure 2 The switch 2200 of the host 2000 is described. The buffer group 110 can transmit the transaction layer packet received from the switch 2200 to the function of the corresponding DMA device through the transaction layer 130.

[0042] exist Figure 3 , the buffer group 110 may include a read buffer 111, a write buffer 112, a completion buffer 113, and a playback buffer 114. Each of the read buffer 111, the write buffer 112, and the completion buffer 113 may include a send buffer and a receive buffer, the send buffer sends the stored transaction layer packet to the switch 2200, and the receive buffer stores the transaction layer packet received from the switch 2200. In an embodiment, the buffer group 110 may directly send the transaction layer packet to the root complex 2100 of the host 2000, and may directly receive the transaction layer packet from the root complex 2100 of the host 2000.

[0043] The read buffer 111 may store transaction layer packets related to a read request. The write buffer 112 may store transaction layer packets related to a write request. The completion buffer 113 may store transaction layer packets related to the completion of a read request or a write request. The completion may indicate whether a read request or a write request has been received and whether the processing of the read request or the write request has been completed.

[0044] The transaction layer packets respectively stored in the read buffer 111, the write buffer 112 and the completion buffer 113 may be transmitted to the playback buffer 114. The buffer controller 120 may change the order in which the transaction layer packets are transmitted from the read buffer 111, the write buffer 112 and the completion buffer 113 to the playback buffer 114.

[0045] The playback buffer 114 may output the transaction layer packets to the switch 2200 in the following order: the transaction layer packets are sent from the read buffer 111, the write buffer 112, and the completion buffer 113 to the playback buffer 114. The order in which the transaction layer packets stored in the playback buffer 114 are output to the switch 2200 may be fixed and not changed during operation.

[0046] The buffer controller 120 may rearrange the output order of the transaction layer packets stored in the read buffer 111 and the write buffer 112 based on identifications (IDs) of the transaction layer packets.

[0047] Here, the transaction layer packet may be an information packet that allows ID-based ordering (IDO). In the header of each transaction layer packet that allows IDO, the IDO bit may be set to 1. The transaction layer packet that allows IDO may be independently determined according to transactions between devices, and then the order of the transaction layer packet that allows IDO may be changed in the root complex 2100 or the switch 2200. In another embodiment, the order of the transaction layer packet that allows IDO may be changed by the PCIe device 1000.

[0048] The ID of each transaction layer packet may include an identification number of a bus corresponding to the transaction layer packet, an identification number of a device, and an identification number of a function.

[0049] For example, the PCIe interface device 100 can receive a transaction layer packet from at least one DMA device via at least one bus. The identification number of the bus corresponding to the transaction layer packet can be the one referred to above. Figure 1 The identification number of the device corresponding to the transaction layer packet may be the identification number of the PCIe device 1000. The identification number of the function corresponding to the transaction layer packet may be a unique number for each function implemented in the PCIe device 1000.

[0050] exist Figure 3 , the identification number of the bus may be n (where n is a natural number), and the identification number of the PCIe device 1000 may be 0. The identification numbers of the first to fourth functions are 0 to 3, respectively. Therefore, the ID of the transaction layer packet received from the first function executed on the first DMA device 200_1 may be (n:0:0). The ID of the transaction layer packet received from the second function executed on the first DMA device 200_1 may be (n:0:1). The ID of the transaction layer packet received from the third function executed on the second DMA device 200_2 may be (n:0:2). The ID of the transaction layer packet received from the fourth function executed on the second DMA device 200_2 may be (n:0:3).

[0051] Figure 4 The present invention describes the reordering of transaction layer packets based on their IDs in a PCIe device.

[0052] Reference Figure 4 , the read buffer 2210 and the write buffer 2220 of the switch 2200 can each store four transaction layer packets. However, the number of transaction layer packets that can be stored in each buffer is not limited to this embodiment.

[0053] exist Figure 4 In FIG. 2 , the write buffer 2220 of the switch 2200 stores four first transaction layer packets, so the write buffer 2220 is full of transaction layer packets. The read buffer 2210 of the switch 2200 stores three second transaction layer packets, so the read buffer 2210 can additionally store a new transaction layer packet.

[0054] The PCIe device 1000 may include a first buffer and a second buffer.

[0055] The first buffer may receive a plurality of first transaction layer packets from a plurality of functions (eg, functions 1 to 3) of the DMA device through the transaction layer 130. The second buffer may receive a plurality of second transaction layer packets from a plurality of functions (eg, functions 1 to 3) of the DMA device through the transaction layer 130.

[0056] exist Figure 4 In the example, the first buffer may be the write buffer 112, and the second buffer may be the read buffer 111. The first transaction layer packet may be a transaction layer packet associated with a write request, and the second transaction layer packet may be a transaction layer packet associated with a read request.

[0057] In another embodiment, the first buffer may be the read buffer 111, and the second buffer may be the write buffer 112. The first transaction layer packet may be a transaction layer packet associated with a read request, and the second transaction layer packet may be a transaction layer packet associated with a write request.

[0058] exist Figure 4 In the example, the identification number of the bus may be 2, and the identification number of the PCIe device 1000 may be 0. The identification numbers of the first function to the third function (function 1 to function 3) may be 0 to 2, respectively. Therefore, the ID of the transaction layer packet received from the first function (function 1) may be (2:0:0). The ID of the transaction layer packet received from the second function (function 2) may be (2:0:1). The ID of the transaction layer packet received from the third function (function 3) may be (2:0:2).

[0059] The root complex 2100 and the switch 2200 may exchange flow control signals with each other. The switch 2200 and the PCIe device 1000 may exchange flow control signals with each other.

[0060] The flow control signal may include an Update FC (flow control). When a transaction layer packet is routed from the first side to the third side through the second side, the Update FC may be a PCIe protocol, wherein the second side notifies the first side through the PCIe protocol that the second side is able to re-receive a transaction layer packet (TLP). In other words, when the second side is ready to send a transaction layer packet received from the first side to the third side, the second side may send an Update FC to the first side.

[0061] The PCIe device 1000 can determine whether the switch 2200 is in the following state based on the flow control signal: the first buffer of the switch 2200 is full and thus cannot receive a new transaction layer packet. That is, the first buffer of the switch 2200 is under back pressure. Figure 4In the embodiment, the first buffer of the switch 2200 may be the write buffer 2220, and the second buffer of the switch 2200 may be the read buffer 2210. In another embodiment, the first buffer of the switch 2200 may be the read buffer 2210, and the second buffer of the switch 2200 may be the write buffer 2220.

[0062] The PCIe device 1000 may assign respective priorities to a plurality of second transaction layer packets according to the order in which the second transaction layer packets are input from a plurality of functions (function 1 to function 3) to the read buffer 111 .

[0063] When the write buffer 2220 of the switch 2200 is full, the PCIe device 1000 may rearrange the order in which the plurality of second transaction layer packets are to be output from the read buffer 111 of the PCIe device 1000 to the switch 2200 based on the respective IDs of the second transaction layer packets.

[0064] In the first order rearrangement ( O1 ) process, the PCIe device 1000 may set a priority of a target second transaction layer packet among a plurality of second transaction layer packets stored in the read buffer 111 to be higher than priorities of the remaining second transaction layer packets.

[0065] In an embodiment, the target second transaction layer packet may be a transaction layer packet having an ID different from an ID of a transaction layer packet to be processed in the write buffer 2220 of the switch 2200 .

[0066] For example, the ID of the transaction layer packet to be processed in the write buffer 2220 of the switch 2200 may be (2:0:0). Among the IDs of the second transaction layer packets stored in the read buffer 111, the IDs different from (2:0:0) may be (2:0:1) and (2:0:2).

[0067] Therefore, among the plurality of second transaction layer packets, the second transaction layer packets with IDs (2:0:1) and (2:0:2) may be set as target second transaction layer packets with a higher priority than the second transaction layer packet with ID (2:0:0). The second transaction layer packet with a higher priority may be output to the read buffer 2210, which is a second buffer of the switch 2200, before the second transaction layer packet with a lower priority.

[0068] In another embodiment, the target second transaction layer packet may be a transaction layer packet having an ID different from the IDs of the plurality of first transaction layer packets stored in the write buffer 112 of the PCIe device 1000 .

[0069] For example, the IDs of the plurality of first transaction layer packets stored in the write buffer 112 of the PCIe device 1000 may be (2:0:0) and (2:0:1). Among the IDs of the second transaction layer packets stored in the read buffer 111, an ID different from (2:0:0) and (2:0:1) may be (2:0:2).

[0070] Therefore, among the plurality of second transaction layer packets, the second transaction layer packet with ID (2:0:2) may be set as a target second transaction layer packet having a higher priority than transaction layer packets with IDs (2:0:0) and (2:0:1).

[0071] Therefore, among the multiple second transaction layer packets stored in the read buffer 111 of the PCIe device 1000, the priority of the second transaction layer packet having an ID (2:0:2) different from the ID (2:0:0) and the IDs (2:0:0) and (2:0:1) can be set to be higher than the priority of the remaining second transaction layer packets having IDs (2:0:0) and (2:0:1), where (2:0:0) is the ID of the transaction layer packet to be processed in the write buffer 2220 of the switch 2200, and (2:0:0) and (2:0:1) are the IDs of the multiple first transaction layer packets stored in the write buffer 112 of the PCIe device 1000.

[0072] The priority of a target second transaction layer packet whose ID is different from the ID of the transaction layer packet to be processed in the write buffer 2220 of the switch 2200 can be rearranged so that the target second transaction layer packet is output from the read buffer 111 of the PCIe device 1000 to the read buffer 2210 of the switch 2200 before the remaining second transaction layer packets.

[0073] The reason for this is that the write buffer 2220 of the switch 2200 is under back pressure, but the read buffer 2210 can receive a new transaction layer packet, so the target second transaction layer packet having an ID different from the ID of the transaction layer packet to be processed in the write buffer 2220 is output to the read buffer 2210 of the switch 2200, thereby achieving QoS for each function. In other words, the reason for this is that the transaction layer packet having an ID different from the ID of the transaction layer packet under back pressure is preferentially processed by independently rearranging the output order according to the ID of the transaction layer packet.

[0074] However, even if the output order is rearranged according to the ID of the transaction layer packet, the output order between the first transaction layer packet and the second transaction layer packet having the same ID must be maintained.

[0075] The PCIe device 1000 may rearrange the order in which the plurality of first transaction layer packets are to be output from the write buffer 112 based on the respective IDs of the plurality of first transaction layer packets.

[0076] In the second order rearrangement (O2) process, the PCIe device 1000 may set a priority of a target first transaction layer packet among a plurality of first transaction layer packets stored in a first buffer (eg, write buffer 112) to be higher than priorities of the remaining first transaction layer packets.

[0077] The target first transaction layer packet may be a transaction layer packet having an ID different from an ID of a transaction layer packet to be processed in the write buffer 2220 of the switch 2200 .

[0078] For example, the ID of the transaction layer packet to be processed in the write buffer 2220 of the switch 2200 may be (2:0:0). Among the IDs of the first transaction layer packet stored in the write buffer 112, an ID different from (2:0:0) may be (2:0:1).

[0079] The priority can be rearranged so that a first transaction layer packet having an ID (2:0:1) different from the ID (2:0:0) of the transaction layer packet to be processed in the write buffer 2220 of the switch 2200 is output from the write buffer 112 of the PCIe device 1000 to the write buffer 2220 of the switch 2200 before the remaining first transaction layer packets.

[0080] The reason is that the priority is readjusted so that the first transaction layer packet with an ID different from the ID of the transaction layer packet to be processed in the write buffer 2220 of the switch 2200 is output to the write buffer 2220 first, thereby preventing the transaction layer packet with ID (2:0:0) from being processed continuously.

[0081] That is, a transaction layer packet having an ID different from that of a transaction layer packet under back pressure is processed first, thereby preventing an excessive increase in the occupancy rate of a transaction layer packet having a specific ID and achieving QoS for each function.

[0082] Similar to the first order rearrangement ( O1 ) process, the switch 2200 may rearrange the priorities of the transaction layer packets stored in the read buffer 2210 in the third order rearrangement ( O3 ) process.

[0083] According to an embodiment of the present disclosure, the PCIe device 1000 can independently change the output order of the transaction layer packets according to the ID of the transaction layer packets. That is, not only the root complex 2100 and the switch 2200, but also the PCIe device 1000 can change the output order of the transaction layer packets that allow IDO, thereby more effectively realizing the QoS of each function.

[0084] Figure 5 is a flowchart illustrating the operation of a PCIe interface device according to an embodiment of the present disclosure.

[0085] Reference Figure 5 In S501, the PCIe interface device may store first transaction layer packets received from multiple functions of the DMA device in a first buffer, and may store second transaction layer packets received from multiple functions of the DMA device in a second buffer.

[0086] In an embodiment, the first buffer may be a write buffer, the second buffer may be a read buffer, the first transaction layer packet may be an information packet associated with a write request, and the second transaction layer packet may be an information packet associated with a read request.

[0087] In another embodiment, the first buffer may be a read buffer, the second buffer may be a write buffer, the first transaction layer packet may be an information packet associated with a read request, and the second transaction layer packet may be an information packet associated with a write request.

[0088] At S503, the PCIe interface device may receive a flow control signal from the switch indicating whether the first buffer of the switch is full. The first buffer of the switch may be a write buffer. In an embodiment, the PCIe interface device may receive a flow control signal from the switch indicating whether the first buffer of the switch can receive a new transaction layer packet. The PCIe interface device may determine whether the first buffer of the switch is full or can still receive a new transaction layer packet based on the flow control signal.

[0089] At S505 , when the first buffer of the switch is full, the PCIe interface device may rearrange the order in which the second transaction layer packets stored in the second buffer of the PCIe interface device are to be output to the switch based on the respective IDs of the second transaction layer packets.

[0090] At S507 , when the first buffer of the switch is full, the PCIe interface device may rearrange the order in which the first transaction layer packets stored in the first buffer of the PCIe interface device are to be output to the switch based on the respective IDs of the first transaction layer packets.

[0091] Figure 6 is a flowchart illustrating the operation of a PCIe interface device according to an embodiment of the present disclosure.

[0092] Reference Figure 6 In S601, the PCIe interface device may assign priorities to the second transaction layer packets according to the order in which the second transaction layer packets are input from the plurality of functions to the second buffer of the PCIe interface device.

[0093] In S603, the PCIe interface device may set the priority of the second transaction layer packets stored in the second buffer whose ID is different from the ID of the transaction layer packets to be processed in the first buffer of the switch to be higher than the priority of the remaining second transaction layer packets.

[0094] At S605 , the PCIe interface device may set the priorities of the remaining second transaction layer packets to the same value as their previous priorities.

[0095] According to the present disclosure, a PCIe interface device having improved buffer control performance and a method of operating the PCIe interface device are provided.

[0096] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

Claims

1. A high-speed peripheral component interconnect interface device, i.e., a PCIe interface device, comprising: at least one direct memory access device, i.e., a DMA device, performing at least one function; a first buffer storing a plurality of first transaction layer packets received from the at least one function; a second buffer storing a plurality of second transaction layer packets received from the at least one function; as well as A buffer controller is configured to rearrange an order in which the plurality of second transaction layer packets are to be output from the second buffer to the switch based on the IDs of the plurality of second transaction layer packets when a third buffer of the switch is full.

2. The PCIe interface device according to claim 1, wherein: The first buffer is a write buffer, and The second buffer is a read buffer.

3. The PCIe interface device according to claim 1, wherein: The buffer controller assigns respective priorities of the plurality of second transaction layer packets according to an order in which the plurality of second transaction layer packets are input into the second buffer.

4. The PCIe interface device according to claim 3, wherein: The buffer controller: setting the priority of a target second transaction layer packet among the plurality of second transaction layer packets to be higher than the priorities of the remaining second transaction layer packets except the target second transaction layer packet, The target second transaction layer packet is a second transaction layer packet with an ID different from the ID of the transaction layer packet to be processed in the third buffer of the switch.

5. The PCIe interface device according to claim 4, wherein: The buffer controller maintains the priorities of the remaining second transaction layer packets at the same value as their previous priorities.

6. The PCIe interface device according to claim 4, wherein: The target second transaction layer packet is a second transaction layer packet having an ID different from the IDs of the plurality of first transaction layer packets.

7. The PCIe interface device according to claim 1, wherein: The buffer controller further rearranges the order of outputting the plurality of first transaction layer packets from the first buffer of the PCIe interface device to the switch based on the IDs of the plurality of first transaction layer packets.

8. The PCIe interface device according to claim 7, wherein: The buffer controller: sets the priority of a target first transaction layer packet among the plurality of first transaction layer packets to be higher than the priorities of the remaining first transaction layer packets except the target first transaction layer packet, The target first transaction layer packet is a first transaction layer packet with an ID different from an ID of a transaction layer packet to be processed in the third buffer of the switch.

9. The PCIe interface device according to claim 1, wherein: The first buffer and the second buffer of the PCIe interface device receive the plurality of first transaction layer packets and the plurality of second transaction layer packets from at least one function executed on at least one DMA device through at least one bus.

10. The PCIe interface device according to claim 9, wherein: The ID of each transaction layer packet includes: an identification number of a bus corresponding to the transaction layer packet, an identification number of a PCIe device corresponding to the transaction layer packet, and an identification number of a function corresponding to the transaction layer packet.

11. The PCIe interface device according to claim 9, wherein: The at least one DMA device includes at least one of the following: a high-speed non-volatile memory module, i.e., an NVMe module, an artificial intelligence central processing unit module, i.e., an AI CPU module, an artificial intelligence system-on-chip module, i.e., an AISoC module, an Ethernet card, a sound card, and a graphics card.

12. A method of operating a peripheral component interconnect express (PCIe) interface device, the PCIe interface device comprising a first buffer and a second buffer, the first buffer storing a plurality of first transaction layer packets received from at least one function executed on at least one direct memory access (DMA) device, the second buffer storing a plurality of second transaction layer packets received from the at least one function, the method comprising: receiving a flow control signal from the switch indicating whether a third buffer of the switch is full; and When the third buffer of the switch is full, the order of outputting the plurality of second transaction layer packets from the second buffer to the switch is rearranged based on the IDs of the plurality of second transaction layer packets.

13. The method according to claim 12, wherein: The first buffer is a write buffer, and The second buffer is a read buffer.

14. The method according to claim 12, further comprising: The respective priorities of the plurality of second transaction layer packets are assigned according to an order in which the plurality of second transaction layer packets are input from the at least one function to the second buffer.

15. The method according to claim 14, wherein: Rearranging the order in which the plurality of second transaction layer packets are to be output comprises: setting the priority of a target second transaction layer packet among the plurality of second transaction layer packets to be higher than the priorities of the remaining second transaction layer packets except the target second transaction layer packet, The target second transaction layer packet is a second transaction layer packet with an ID different from the ID of the transaction layer packet to be processed in the third buffer of the switch.

16. The method according to claim 15, wherein: The target second transaction layer packet is a second transaction layer packet having an ID different from the IDs of the plurality of first transaction layer packets.

17. The method according to claim 12, further comprising: Based on the IDs of the plurality of first transaction layer packets, an order in which the plurality of first transaction layer packets are to be output from the first buffer of the PCIe interface device to the switch is rearranged.

18. The method according to claim 17, wherein: Rearranging the order in which the plurality of first transaction layer packets are to be output comprises: setting the priority of a target first transaction layer packet among the plurality of first transaction layer packets to be higher than the priorities of the remaining first transaction layer packets except the target first transaction layer packet, The target first transaction layer packet is a first transaction layer packet with an ID different from an ID of a transaction layer packet to be processed in the third buffer of the switch.

19. The method of claim 14, further comprising: The plurality of first transaction layer packets and the plurality of second transaction layer packets are received from at least one function executing on at least one DMA device over at least one bus.

20. The method according to claim 19, wherein: The ID of each transaction layer packet includes: an identification number of a bus corresponding to the transaction layer packet, an identification number of a PCIe device corresponding to the transaction layer packet, and an identification number of a function corresponding to the transaction layer packet.

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