A method for improving network efficiency of an on-chip network of an FPGA

Abstract

The application provides a method for improving network efficiency of an FPGA on-chip network, and relates to the technical field of FPGA. The method utilizes a logic resource module inside the FPGA to configure a soft core node, and inserts the soft core node between two target network nodes in a raw transmission path of the FPGA on-chip network, wherein the path delay of the raw transmission path exceeds a delay threshold. A data transmission path is formed inside the soft core node, so that the two target network nodes realize data transmission via the soft core node. After the soft core node is inserted, the total path delay of several sub-paths formed between the two target network nodes by the soft core node does not exceed the delay threshold. The path delay between the two target network nodes can be reduced by inserting the soft core node, so that the network efficiency of the on-chip network is improved, and the performance is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of FPGA, and in particular to a method for improving the network efficiency of an FPGA on-chip network. BACKGROUND

[0002] FPGA is widely used in mobile communication, data center, automatic driving, aerospace and other fields. New applications have increasing demands for the bandwidth, storage and data capacity of FPGA. Therefore, in order to optimize the communication performance, more and more FPGAs begin to integrate on-chip networks (NOC) internally.

[0003] When integrating an on-chip network in an FPGA, the output or input of a resource module with large data bandwidth in the FPGA (such as a high-speed serial port, an AI module, etc.) is connected to a NOC node of the on-chip network, and then the data is transmitted to the required NOC node for use via the on-chip network. Generally, these resource modules with large data bandwidth are usually laid out at the edge of the FPGA due to design considerations such as power supply and clock frequency, such as a high-speed transceiver GTH which is usually laid out at the leftmost or rightmost side of the FPGA. This results in the resource modules with large data bandwidth often being far away from the next NOC node connected thereto, which reduces the transmission speed between NOC nodes and affects the network performance. SUMMARY

[0004] The present application relates to the technical field of FPGA, and in particular to a method for improving the network efficiency of an FPGA on-chip network.

[0005] A method for improving the network efficiency of an FPGA on-chip network, the method comprising:

[0006] configuring a soft core node using a logic resource module inside the FPGA and inserting the soft core node between two target network nodes in the on-chip network of the FPGA, the soft core node having a data transmission path formed inside, so that the two target network nodes achieve data transmission via the soft core node;

[0007] The path delay of the original transmission path between the two target network nodes exceeds a delay threshold before the soft core node is inserted; after the soft core node is inserted, the total path delay of the several sub-paths formed between the two target network nodes through the soft core node does not exceed the delay threshold.

[0008] Further, each soft core node comprises an input port and an output port, and each soft core node internally comprises control logic, a buffer and a register, the control logic is connected to the input port of the soft core node through the buffer, the control logic is connected to the output port of the soft core node through the register, and the soft core node forms a data transmission path from the input port to the output port and realizes a unidirectional transmission function.

[0009] Further, the buffer and / or the register in the soft core node are formed by a BRAM module in the FPGA.

[0010] Further, the buffer and / or the register in the soft core node are realized by at least one of a LUT, a REG and a DistRAM in a CLB module in the FPGA.

[0011] Further, each soft core node realizes a unidirectional transmission function, for any first target network node and second target network node, the first target network node sends data to the second target network node via the inserted soft core node, and / or the second target network node sends data to the first target network node via the inserted soft core node, and the inserted soft core nodes on the bidirectional transmission path between the two target network nodes are different.

[0012] Further, the soft core node has a data storage function, when the data sending capability of a first target network node that realizes data transmission via the soft core node is higher than the data receiving capability of a second target network node, the first target network node sends the to-be-sent data to be sent to the second target network node to the soft core node for temporary storage, and the first target network node continues to process data to be sent to other network nodes.

[0013] Further, data transmission between each two target network nodes is realized via one or more soft core nodes, and data transmission between a group or multiple groups of target network nodes in the network-on-chip is realized via the soft core nodes.

[0014] Further, the FPGA is a multi-die FPGA, the FPGA comprises a substrate, a silicon connection layer stacked on the substrate, and a plurality of dies stacked on the silicon connection layer, and two target network nodes that realize data transmission via the soft core nodes are located in different dies, respectively.

[0015] Further, the soft core nodes inserted between the two target network nodes in different dies are located on one of the dies, and / or on the other die, and / or in the silicon connection layer.

[0016] Further technical solutions are as follows: The method for inserting a soft core node between two target network nodes in an on-chip network of an FPGA includes:

[0017] An original input netlist is obtained, a soft core node is inserted in a connection relationship between two target network nodes, an original input netlist is updated to obtain an updated global netlist, and the FPGA is laid out and routed according to the updated global netlist and the design is completed.

[0018] The present application has the following beneficial technical effects:

[0019] The present application provides a method for improving the network efficiency of an on-chip network of an FPGA, which inserts a soft core node between network nodes in the on-chip network by configuring a logic resource module inside the FPGA, so that data transmission between two target network nodes is realized via the soft core node, thereby reducing the path delay between the two target network nodes and improving the network efficiency and optimizing the performance of the on-chip network.

[0020] The soft core node is configured by a logic resource module, has a simple structure and is easy to implement, and by using the data storage function inside the soft core node, the data transmission capacity between the two target network nodes can be balanced by temporarily storing data in the soft core node, thereby avoiding the problem of congestion caused by different data transmission capacities of the two target network nodes and further improving the network efficiency of the on-chip network. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 Fig. 1 is a structural schematic diagram of an on-chip network before and after a soft core node is inserted in an example.

[0022] Figure 2 Fig. 1 is a structural schematic diagram of an on-chip network before and after a soft core node is inserted in an example. DETAILED DESCRIPTION

[0023] The specific embodiments of the present application will be further described below with reference to the accompanying drawings.

[0024] The present application provides a method for improving the network efficiency of an on-chip network of an FPGA, which inserts a soft core node between network nodes in the on-chip network by configuring a logic resource module inside the FPGA, so that data transmission between two target network nodes is realized via the soft core node, thereby reducing the path delay between the two target network nodes and improving the network efficiency and optimizing the performance of the on-chip network. Figure 1In the example shown, the on-chip network designed on the FPGA includes network nodes R1-R9, and the path delay of the original transmission path from the target network node R3 to the target network node R2 exceeds the delay threshold. Figure 1 Only the schematic diagram of the connection between the network nodes is shown, and the path routing is not specifically shown.

[0025] In this scenario, the method of the present application is to configure a soft core node using the logic resource modules inside the FPGA, and insert it between two target network nodes in the on-chip network of the FPGA. The soft core node has a data transmission path formed inside it, so that the two target network nodes can achieve data transmission via the soft core node. After inserting the soft core node, the total path delay of the several sub-paths formed between the two target network nodes through the soft core node does not exceed the delay threshold. For example Figure 1 In the example shown, a soft core node r is inserted between the target network node R3 and the target network node R2, and two sub-paths including the sub-path R3→r and the sub-path r→R2 are formed through the soft core node r. The target network node R3 transmits data to the soft core node r, and then to the target network node R2, and the total path delay of the two sub-paths does not exceed the delay threshold.

[0026] In practice, the original input netlist is obtained, which records the connection relationship between the logic resource modules, and there are logic resource modules as network nodes to form the structure of the on-chip network using the connection relationship. If the layout and routing are directly performed on the FPGA according to the original input netlist, the traditional design result is obtained, that is, the path delay of the original transmission path of at least two target network nodes exceeds the delay threshold. The method of the present application does not directly perform layout and routing according to the original input netlist. Instead, the two network nodes whose original transmission path delay exceeds the delay threshold are first determined by timing analysis of the original input netlist, and then a soft core node is inserted in the connection relationship between the two target network nodes, thereby updating the original input netlist to obtain an updated global netlist. Then, the FPGA is laid out and routed according to the updated global netlist and the design is completed, so that the soft core node can be laid out at a suitable position and the wiring between the target network nodes and the soft core node can be completed, that is, the two target network nodes can achieve data transmission via the soft core node, and the total path delay does not exceed the delay threshold.

[0027] When the two target network nodes are far apart, resulting in a large path delay of the original transmission path, if only one soft core node is inserted, the target network node and the soft core node can still be far apart, resulting in a large path delay. In this case, multiple soft core nodes can be inserted between the two target network nodes, that is, data transmission is achieved between every two target network nodes via one or more soft core nodes. Two target network nodes can form p+1 sub-paths through p soft core nodes. The number of inserted soft core nodes needs to be ensured to meet the delay requirement.

[0028] In addition, when the path delay of the original transmission path between multiple groups of target network nodes in the original on-chip network recorded in the original input netlist exceeds the delay threshold, soft core nodes can be inserted between different target network nodes according to the method of the present application, that is, data transmission is achieved between one or more groups of target network nodes in the on-chip network via soft core nodes.

[0029] Any two network nodes in the on-chip network can generally achieve bidirectional transmission, such as Figure 1 As shown, network node R3 can send data to network node R2, and network node R2 can also send data to network node R3. When layout and routing are performed, the routing paths of the original transmission paths for bidirectional transmission between the two network nodes are often different, and thus the path delays of the original transmission paths for bidirectional transmission can also be different. Therefore, the path delay of the original transmission path for R3 to send data to R2 can exceed the delay threshold, but the path delay of the original transmission path for R2 to send data to R3 can not exceed the delay threshold. In addition, the path delays of the original transmission paths for bidirectional transmission can both exceed or not exceed the delay threshold. That is, soft core nodes can need to be inserted in the bidirectional transmission paths of the two target network nodes, or soft core nodes can need to be inserted in the unidirectional transmission paths of the two target network nodes. In order to adapt to different situations, the soft core node in the present application is internally formed with a unidirectional data transmission path to achieve unidirectional transmission function. For the scenario where soft core nodes need to be inserted in bidirectional transmission, the soft core node can of course be configured to have two data transmission paths to meet the use requirement. However, designing soft core nodes for unidirectional insertion and bidirectional insertion scenarios increases the design difficulty. In addition, the soft core node has the function of data relay, and the function and purpose are relatively clear. Therefore, the structure of the soft core node should be as simple as possible. Configuring the soft core node to have two data transmission paths does not have additional benefits. Therefore, based on the use requirement and the consideration of reducing design difficulty, each soft core node in the present application achieves unidirectional transmission function.

[0030] Figure 2The internal structure of the soft core node in one embodiment is shown, each soft core node includes an input port and an output port, and each soft core node internally includes control logic, a buffer and a register, the control logic is connected to the input port of the soft core node through the buffer, the control logic is connected to the output port of the soft core node through the register, and the soft core node forms a data transmission path from the input port to the output port, and realizes a unidirectional transmission function.

[0031] In one embodiment, the buffer and / or register inside the soft core node is formed by BRAM module configuration inside the FPGA.

[0032] In another embodiment, the buffer and / or register inside the soft core node is realized by at least one of LUT, REG, DistRAM in the CLB module inside the FPGA. Compared with the method of being formed by BRAM configuration, this method can further maintain the layout flexibility of the soft core node.

[0033] Since each soft core node realizes a unidirectional transmission function, for any first target network node and second target network node, the first target network node transmits data to the second target network node via the inserted soft core node, and / or the second target network node transmits data to the first target network node via the inserted soft core node, and the inserted soft core nodes on the bidirectional transmission path between the two target network nodes are different, including the number, layout position and wiring between the target network nodes of the inserted soft core nodes.

[0034] In addition to optimizing the path delay between the two target network nodes, the inserted soft core node can also balance the data transmission capacity between the two target network nodes by using the built-in data storage function, so that Figure 2 For example, the structure of the soft core node built-in buffer and / or register can provide data storage function. For a network-on-chip, each network node will have data transmission with other multiple network nodes, such as Figure 1 In the above, in addition to the need to transmit data to network node R2, network node R3 also needs to transmit data to network node R6, and the data transmission and reception capabilities between different network nodes may be different, including data transmission and reception frequency, transmission bandwidth, etc. When the data transmission capability of network node R3 is higher than the data reception capability of network node R2, network node R3 needs to wait for network node R2 to be idle before transmitting data to network node R2, and after transmitting data to network node R2, it can receive new data packets, which can easily cause network node R3 to be blocked.

[0035] When the data sending capability of the first target network node is higher than the data receiving capability of the second target network node via the soft-core node for data transmission, the soft-core node inserted in the application temporarily stores the to-be-sent data to be sent to the second target network node by the first target network node, and the first target network node can continue to process data to be sent to other network nodes. That is, in the above example, network node R3 can first send data to be sent to network node R2 to soft-core node r for temporary storage, and wait for network node R2 to be idle before sending the data to network node R2 by soft-core node r. Network node R3 can empty the data packets to be sent to network node R2 and receive new data packets. If the received new data packets need to be sent to network node R6, network node R3 can successfully send the new data packets to network node R6 without waiting for network node R2, and is not affected by the blocking of network node R3 by network node R2, so that the network efficiency is improved.

[0036] The FPGA to which the application is directed can be a conventional single-die FPGA or a multi-die FPGA. The multi-die FPGA includes a substrate, a silicon connection layer stacked on the substrate, and a plurality of dies stacked on the silicon connection layer. The network nodes in the network-on-chip formed inside the multi-die FPGA can all be located in the same die, which is similar to the case of a single-die FPGA. Alternatively, the network nodes in the network-on-chip formed inside the multi-die FPGA can be located in multiple dies. In this case, the two target network nodes for data transmission via the soft-core node can be located in the same die, which is also similar to the case of a single-die FPGA. Alternatively, the two target network nodes for data transmission via the soft-core node are located in different dies. In this case, the soft-core node inserted between the two target network nodes in different dies is located on one of the dies, and / or on the other die, and / or in the silicon connection layer. In theory, the soft-core node can be located in any of the above three positions, but in actual design, if the silicon connection layer is a passive silicon connection layer, the soft-core node cannot be located in the silicon connection layer, but only on one of the dies. In addition, when data transmission via the soft-core node is required between multiple groups of target network nodes across dies, the soft-core node can be uniformly located in the die where the target network node for sending data is located, or uniformly located in the die where the target network node for receiving data is located. Maintaining a fixed strategy is conducive to implementation and simplifies the design workload.

Claims

1. A method for improving network efficiency of a network-on-chip of an FPGA, the method comprising: The method comprises: A soft core node is configured by using a logic resource module inside the FPGA and is inserted between two target network nodes in the network-on-chip of the FPGA, a data transmission path is formed inside the soft core node, so that the two target network nodes realize data transmission via the soft core node; Before the soft core node is inserted, the path delay of an original transmission path between the two target network nodes exceeds a delay threshold, the original transmission path is a transmission path between the two network nodes when layout and routing are directly performed based on the structure of the network-on-chip; after the soft core node is inserted, the total path delay of a plurality of sub-paths formed between the two target network nodes via the soft core node does not exceed the delay threshold; The soft core node has a data storage function, when the data sending capability of a first target network node that realizes data transmission via the soft core node is higher than the data receiving capability of a second target network node, the first target network node sends to-be-sent data to be sent to the second target network node to the soft core node for temporary storage, and the first target network node continues to process data to be sent to other network nodes.

2. The method of claim 1, wherein, Each soft core node comprises an input port and an output port, and each soft core node comprises control logic, a buffer and a register inside, the control logic is connected to the input port of the soft core node through the buffer, the control logic is connected to the output port of the soft core node through the register, and the soft core node forms a data transmission path from the input port to the output port to realize a one-way transmission function.

3. The method of claim 2, wherein, The buffer and / or the register inside the soft core node are formed by a BRAM module inside the FPGA.

4. The method of claim 2, wherein, The buffer and / or the register inside the soft core node are realized by at least one of a LUT, a REG and a DistRAM in a CLB module inside the FPGA.

5. The method of claim 1, wherein, Each soft core node realizes a one-way transmission function, for any first target network node and second target network node, the first target network node sends data to the second target network node via the inserted soft core node, and / or the second target network node sends data to the first target network node via the inserted soft core node, and the inserted soft core nodes are different on a bidirectional transmission path between the two target network nodes.

6. The method of claim 1, wherein, Data transmission between every two target network nodes is realized via one or more soft core nodes, data transmission between a group or a plurality of groups of target network nodes in the network-on-chip is realized via the soft core nodes.

7. The method of claim 1, wherein, The FPGA is a multi-die FPGA, the FPGA comprises a substrate, a silicon connection layer stacked on the substrate and a plurality of dies stacked on the silicon connection layer, and the two target network nodes that realize data transmission via the soft core nodes are respectively located in different dies.

8. The method of claim 7, wherein, The inserted soft core node between the two target network nodes in different dies is located on one of the dies, and / or on the other die, and / or in the silicon connection layer.

9. The method of claim 1, wherein, The method for inserting a soft core node between two target network nodes in the network-on-chip of the FPGA comprises: The original input netlist is acquired, a soft core node is inserted in the connection relationship of two target network nodes, the original input netlist is updated to obtain an updated global netlist, and the FPGA is laid out and routed according to the updated global netlist and design is completed.

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