A display panel

Abstract

The present application discloses a display panel, which includes a display GOA unit and a virtual GOA unit connected to the display GOA unit, the pull-down module of the display GOA unit is connected to a frame start signal, and the pull-down module of the virtual GOA unit is connected to a control signal; wherein, within a frame duration, the frame start signal includes a frame start pulse, and the control signal includes a first pulse and a second pulse generated at intervals; the first pulse of the previous frame is generated between the last clock pulse of the previous frame connected to the display GOA unit and the frame start pulse of the next frame; the second pulse of the previous frame is generated between the last clock pulse of the previous frame connected to the display GOA unit and the frame start pulse of the next frame or is generated synchronously with the frame start pulse of the next frame, so that the potential of the virtual GOA unit can be pulled down in advance, reducing the time that the virtual GOA unit is at a high potential, and thus extending the life of the virtual GOA unit.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] Display devices, as the display components of electronic devices, are widely used in various electronic products. Gate drive circuits are a key component of these devices. Gate drive circuits, also known as GOA (Gate Driver on Array) circuits, utilize the array manufacturing process of thin-film transistor displays to fabricate gate row scan drive signal circuits on the array substrate, achieving progressive gate scanning.

[0003] In this case, some GOA circuits include multi-stage cascaded effective GOA units (also referred to as effective gate drive circuits) and virtual GOA units (i.e., Dummy GOA units, also referred to as virtual gate drive circuits); wherein the effective GOA units are connected to the gate lines located in the display area, while the dummy GOA units are not connected to the gate lines, so that the loads of the effective GOA units and the dummy GOA units are different.

[0004] Typically, a GOA circuit using a staged pull-down circuit includes a dummy GOA unit. The pull-down module of the dummy GOA unit is activated by the STV (Start Voltage) signal of the next frame. However, there is no staged STV signal for the next frame. Therefore, in actual products, this design causes the Q point of the dummy GOA unit to be at a high potential for a long period of time, causing the TFT (Thin Film Transistor) connected to the Q point to be stressed for a longer period of time, resulting in a shorter lifespan of the dummy GOA unit than the effective GOA unit. Summary of the Invention

[0005] The present application provides a display panel to solve the technical problem of a short lifespan of a virtual GOA unit.

[0006] The present application provides a display panel, comprising:

[0007] It includes a display GOA unit and a virtual GOA unit connected to the display GOA unit, the pull-down module of the display GOA unit is connected to the frame start signal, and the pull-down module of the virtual GOA unit is connected to the control signal; wherein, within a frame duration, the frame start signal includes a frame start pulse, and the control signal includes a first pulse and a second pulse generated at intervals; the first pulse of the previous frame is generated between the last clock pulse of the previous frame connected to the display GOA unit and the frame start pulse of the next frame; the second pulse of the previous frame is generated between the last clock pulse of the previous frame connected to the display GOA unit and the frame start pulse of the next frame or is generated synchronously with the frame start pulse of the next frame.

[0008] Optionally, in some embodiments of the present application, the virtual GOA unit includes:

[0009] A pull-up control module, the pull-up control module being electrically connected to the first terminal and the second terminal of the display GOA unit and electrically connected to a first node, the pull-up control module being configured to pull up the potential of the first node under the control of the first terminal and the second terminal of the display GOA unit;

[0010] a pull-up module, the pull-up module receiving a clock signal and electrically connected to the first node and the first output end, the pull-up module being configured to output the clock signal to the first output end under the control of the first node;

[0011] The pull-down module of the virtual GOA unit receives the control signal and the low-level signal and is electrically connected to the first node and the first output end. The pull-down module of the virtual GOA unit is used to pull down the potential of the first node and the first output end to the potential of the low-level signal under the control of the control signal;

[0012] A pull-down maintaining module is electrically connected to the first node and the first output end, and is used to maintain the potential of the first node and the first output end at the potential of the low-level signal.

[0013] Optionally, in some embodiments of the present application, the pull-down module of the virtual GOA unit pulls down the potential of the first node and the first output end to the potential of the low-level signal under the control of the first pulse.

[0014] Optionally, in some embodiments of the present application, the second pulse is located between the first pulse of the previous frame and the frame start signal of the next frame, and the pull-down module of the virtual GOA unit resets the potential of the first node and the first output end to the potential of the low-level signal under the control of the second pulse.

[0015] Optionally, in some embodiments of the present application, the second pulse of the previous frame is generated between the first pulse of the previous frame and the frame start pulse of the frame start signal of the next frame.

[0016] Optionally, in some embodiments of the present application, the virtual GOA unit further includes:

[0017] A pre-charge module is connected to the control signal and the low-level signal and is electrically connected to the first node. The pre-charge module is used to pull down the potential of the first node to the potential of the low-level signal under the control of the control signal.

[0018] Optionally, in some embodiments of the present application, between the second pulse of the previous frame and the second pulse of the next frame, the driving timing of the display panel includes:

[0019] a reset phase, during which the pull-down module of the virtual GOA unit resets the potentials of the first node and the first output end to the potential of the low-level signal under the control of the second pulse;

[0020] a pull-up output stage, during which the pull-up control module is configured to pull up the potential of the first node under the control of the first terminal and the second terminal of the display GOA unit, and the pull-up module outputs the clock signal to the first output end under the control of the first node;

[0021] a pull-down phase, during which the pull-down module of the virtual GOA unit pulls down the potentials of the first node and the first output end to the potential of the low-level signal under the control of the first pulse;

[0022] A pull-down maintaining phase, during which the pull-down maintaining module maintains the potentials of the first node and the first output end at the potential of the low-level signal under the control of the converted low-frequency control signal.

[0023] Optionally, in some embodiments of the present application, the driving timing of the display panel further includes:

[0024] A gap stage is located between the output stage and the pull-down stage.

[0025] Optionally, in some embodiments of the present application, within the same frame, the time interval between the first pulse and the last clock pulse connected to the display GOA unit is greater than 0 seconds and less than or equal to 2 / (P×N) microseconds, where P is the refresh frequency of the display panel, N is the number of levels of the display GOA unit, and N is a positive integer.

[0026] Optionally, in some embodiments of the present application, the time interval between the second pulse of the previous frame and the frame start signal of the next frame is greater than or equal to 1 / (P×N) microseconds and less than or equal to 2 / (P×N) microseconds, where P is the refresh frequency of the display panel, N is the number of levels of the display GOA unit, and N is a positive integer.

[0027] The present application provides a display panel, which includes a display GOA unit and a virtual GOA unit connected to the display GOA unit, wherein the pull-down module of the display GOA unit accesses a frame start signal, characterized in that the pull-down module of the virtual GOA unit accesses a control signal; wherein, within a frame duration, the frame start signal includes a frame start pulse, and the control signal includes a first pulse and a second pulse generated at intervals; the first pulse of the previous frame is generated between the last clock pulse of the display GOA unit accessed in the previous frame and the frame start pulse of the next frame; the second pulse of the previous frame is generated between the last clock pulse of the display GOA unit accessed in the previous frame and the frame start pulse of the next frame or is generated synchronously with the frame start pulse of the next frame. The pull-down module of the present application uses a control signal to pull down the virtual GOA unit, and the pulse signal of the control signal is generated between the last clock pulse of the display GOA unit accessed in the previous frame and the frame start signal of the next frame, so that the potential of the virtual GOA unit can be pulled down in advance, reducing the time when the virtual GOA unit is at a high potential, thereby extending the life of the virtual GOA unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A first structural diagram of a display panel provided in this application;

[0030] Figure 2 This is a schematic diagram of the first structure of the virtual GOA unit of the display panel provided by this application;

[0031] Figure 3 Schematic diagram of a first embodiment of a signal timing sequence of a virtual GOA unit of a display panel of the present application;

[0032] Figure 4 Schematic diagram of a second embodiment of the signal timing sequence of a virtual GOA unit of a display panel of the present application;

[0033] Figure 5 This is a second structural diagram of the virtual GOA unit of the display panel provided by this application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative work shall fall within the scope of protection of this application.

[0035] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0036] The transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other pole is called the drain. According to the form in the accompanying drawings, the middle end of the pull-down module is specified as the gate, the signal input end is the source, and the output end is the drain. In addition, the transistors used in the embodiments of the present application can include P-type transistors and / or N-type transistors, wherein the P-type transistor is turned on when the gate is low and cut off when the gate is high, and the N-type transistor is turned on when the gate is high and cut off when the gate is low.

[0037] The present application provides a display panel, which is described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.

[0038] See also Figures 1 to 3 , Figure 1 This is a first structural diagram of the display panel 100 provided in this application. Figure 2 This is a first structural diagram of the virtual GOA unit 20 of the display panel 100 provided in this application. Figure 3 Schematic diagram of a first embodiment of a signal timing sequence of a virtual GOA unit of a display panel of the present application. The present application provides a display panel 100 , which includes a display GOA unit 10 and a virtual GOA unit 20 connected to the display GOA unit 10 .

[0039] Among them, the pull-down module of the display GOA unit 10 is connected to the frame start signal, and the pull-down module 23 of the virtual GOA unit 20 is connected to the control signal; wherein, within a frame duration, the frame start signal STV includes a frame start pulse, and the control signal RESET includes a first pulse RE1 and a second pulse RE2 generated at intervals; the first pulse RE1 of the previous frame is generated between the last clock pulse of the previous frame connected to the display GOA unit 10 and the frame start pulse of the next frame; the second pulse RE2 of the previous frame is generated between the last clock pulse LP of the previous frame connected to the display GOA unit 10 and the frame start pulse of the next frame or is generated synchronously with the frame start pulse of the next frame.

[0040] The virtual GOA unit 20 includes a pull-up module 22 , a pull-up control module 21 , a pull-down module 23 and a pull-down maintaining module.

[0041] The pull-up control module 21 is electrically connected to the first terminal and the second terminal of the display GOA unit 10, and is electrically connected to the first node Q. The pull-up control module 21 is used to pull up the potential of the first node Q under the control of the electrical connection between the first terminal and the second terminal of the display GOA unit 10. Wherein, the number of stages of the display GOA unit 10 is N, N is a positive integer, and now an N-stage cascaded display GOA unit 10 is used as an example. At this time, the pull-up control module 21 is electrically connected to the first terminal and the second terminal of the display GOA unit 10 of the Nth stage, and the first terminal of the display GOA unit 10 of the Nth stage outputs the stage transmission signal ST(N) of the display GOA unit 10, and the second terminal of the display GOA unit 10 of the Nth stage outputs the scan signal G(N) of the display GOA unit 10.

[0042] The pull-up module 22 receives the clock signal CK and is electrically connected to the first node Q and the first output terminal G. The pull-up module 22 is configured to output the clock signal CK to the first output terminal G under the control of the first node Q.

[0043] The pull-down module 23 of the virtual GOA unit 20 is connected to the control signal RESET and the low-level signal VSS, and is electrically connected to the first node Q and the first output end G. The pull-down module 23 of the virtual GOA unit 20 is used to pull down the potential of the first node Q and the first output end G to the low-level signal VSS under the control of the control signal RESET.

[0044] The pull-down maintaining module is electrically connected to the first node Q and the first output terminal G, and is configured to maintain the potentials of the first node Q and the first output terminal G at the potential of the low-level signal VSS. Specifically, the pull-down maintaining module receives the converted low-frequency control signal and the low-level signal VSS and is electrically connected to the first node Q and the first output terminal G. After the pull-down module 23 of the virtual GOA unit 20 pulls down the potentials of the first node Q and the first output terminal G, the pull-down maintaining module is configured to maintain the potentials of the first node Q and the first output terminal G at the potential of the low-level signal VSS under the control of the converted low-frequency control signal.

[0045] In some embodiments, the pull-up control module 21 includes:

[0046] A first transistor T1, wherein the gate of the first transistor T1 is electrically connected to the first terminal of the display GOA unit 10, the source of the first transistor T1 is electrically connected to the second terminal of the display GOA unit 10, and the drain of the first transistor T1 is electrically connected to the first node Q.

[0047] In some embodiments, the pull-up module 22 includes:

[0048] The second transistor T2 has a gate electrically connected to the first node Q, a source connected to the clock signal CK, and a drain electrically connected to the first output terminal G.

[0049] Furthermore, in some embodiments, the pull-up module 22 further includes:

[0050] A bootstrap capacitor C, wherein a first electrode of the bootstrap capacitor C is electrically connected to the first node Q, and a second electrode of the bootstrap capacitor C is electrically connected to the first output terminal G.

[0051] In some embodiments, the pull-down module 23 of the virtual GOA unit 20 includes:

[0052] a third transistor T31, wherein a gate of the third transistor T31 is connected to the control signal RESET, a source of the third transistor T31 is electrically connected to the first node Q, and a drain of the third transistor T31 is connected to the low-level signal VSS;

[0053] The fourth transistor T32 has a gate connected to the control signal RESET, a drain connected to the low-level signal VSS, and a source electrically connected to the first output terminal G.

[0054] The virtual GOA unit 20 further includes:

[0055] The pre-charge module 27 is connected to the control signal RESET and the low-level signal VSS and is electrically connected to the first node Q. The pre-charge module 27 is used to pull down the potential of the first node Q to the potential of the low-level signal VSS under the control of the control signal RESET.

[0056] Furthermore, in some embodiments, the pre-charging module 27 includes:

[0057] A fifth transistor T71 , wherein a gate of the fifth transistor T71 is connected to a control signal RESET, a drain of the fifth transistor T71 is connected to a low-level signal VSS, and a source of the fifth transistor T71 is electrically connected to the first node Q.

[0058] The prior art uses a frame start signal STV as a control signal to pull down the flat scanning signal line in the virtual GOA unit 20. Since the frame start signal STV is in the initial stage of a frame, after the frame start signal STV pulls down the flat scanning signal line in the virtual GOA unit 20, the flat scanning signal line in the virtual GOA unit 20 will actually become a pull-up signal only when the scanning signal G(N) of the display GOA unit 10 and the level transfer signal ST(N) of the display GOA unit 10 begin. If the frame start signal STV is used as a control signal to pull down the flat scanning signal line in the virtual GOA unit 20, the flat scanning signal line in the virtual GOA unit 20 will be pulled down in the next frame, thereby causing the flat scanning signal line in the virtual GOA unit 20 to be at a high potential for a longer time, which also causes the life of the virtual GOA unit 20 to be shorter.

[0059] The pull-down module 23 of the present application pulls down the level of the first output terminal G to the low-level signal VSS under the control of the control signal RESET. Since the first pulse RE1 of the control signal RESET is generated between the last clock pulse LP connected to the display GOA unit 10 in the previous frame and the frame start signal STV of the next frame, the level of the first output terminal G can be pulled down to the low-level signal VSS in advance, thereby reducing the time that the first output terminal G in the virtual GOA unit 20 is in a high-level state and extending the life of the virtual GOA unit 20. In addition, since the second pulse RE2 of the control signal RESET is generated between the last clock pulse LP connected to the display GOA unit 10 in the previous frame and the frame start signal STV of the next frame, before the start of the next frame, the level of the first output terminal G is pulled down to the low-level signal VSS under the control of the control signal RESET, resetting the first output terminal G of the entire display panel 100, clearing the residual potential of the first output terminal G, and extending the accuracy of the output of the first output terminal G of the virtual GOA unit 20.

[0060] In some embodiments, the virtual GOA unit 20 further includes:

[0061] The downlink module 24 receives the clock signal CK and is electrically connected to the first node Q and the second output terminal ST. The pull-up module 22 is used to output the clock signal CK to the second output terminal ST under the control of the first node Q.

[0062] Furthermore, the download module 24 includes:

[0063] A sixth transistor T4 , wherein a gate of the sixth transistor T4 is electrically connected to the first node Q, a source of the sixth transistor T4 is connected to the clock signal CK, and a drain of the sixth transistor T4 is electrically connected to the second output terminal ST.

[0064] In some embodiments, the pull-down maintaining module includes:

[0065] The first pull-down maintaining module 25 is connected to the first conversion low-frequency control signal LC1 and the low-level signal VSS, and is electrically connected to the first node Q and the first output terminal G. After the pull-down module 23 of the virtual GOA unit 20 pulls down the potential of the first node Q and the first output terminal G, the first pull-down maintaining module 25 is used to maintain the potential of the first node Q and the first output terminal G at the potential of the low-level signal VSS under the control of the first conversion low-frequency control signal LC1.

[0066] Furthermore, the first pull-down maintaining module 25 includes: a seventh transistor T51 , an eighth transistor T52 , a ninth transistor T53 , a tenth transistor T54 , an eleventh transistor T55 and a twelfth transistor T56 .

[0067] The gate and source of the seventh transistor T51 are both connected to the first low-frequency clock signal LC1, and the drain of the seventh transistor T51 is electrically connected to the drain of the eighth transistor T52. The gate of the eighth transistor T52 is electrically connected to the first node Q, and the source of the eighth transistor T52 is connected to the low-level signal VSS. The gate of the ninth transistor T53 is electrically connected to the drain of the eighth transistor T52, the source of the ninth transistor T53 is connected to the first low-frequency clock signal LC1, and the drain of the ninth transistor T53 is electrically connected to the second node P. The gate of the tenth transistor T54 is electrically connected to the first node Q, the source of the tenth transistor T54 is connected to the low-level signal VSS, and the drain of the tenth transistor T54 is electrically connected to the second node P.

[0068] The gate of the eleventh transistor T55 is electrically connected to the second node P, the source of the eleventh transistor T55 is electrically connected to the first node Q, and the drain of the eleventh transistor T55 is connected to the low level signal VSS;

[0069] A gate of the twelfth transistor T56 is electrically connected to the second node P, a source of the twelfth transistor T56 is electrically connected to the first output terminal G, and a drain of the twelfth transistor T56 is connected to the low-level signal VSS.

[0070] Please refer to Figure 3 , Figure 3 Schematic diagram of the first embodiment of the signal timing of the virtual GOA unit of the display panel of the present application. The control signal RESET includes a first pulse RE1 and a second pulse RE2, and the first pulse RE1 and the second pulse RE2 are generated between the last clock pulse LP of the display GOA unit 10 connected to the previous frame and the frame start pulse of the frame start signal STV of the next frame, and the previous frame is adjacent to the next frame. Specifically, the first pulse RE1 and the second pulse RE2 are generated between the clock pulse of the last clock pulse LP of the display GOA unit 10 connected to the previous frame and the frame start pulse of the frame start signal STV of the next frame. The clock signal CK is a high-frequency clock signal.

[0071] The prior art uses a frame start signal STV as a control signal to pull down the first node Q in the virtual GOA unit 20. Since the frame start signal STV is in the initial stage of a frame, after the frame start signal STV pulls down the first node Q in the virtual GOA unit 20, from the scan signal G(N) of the display GOA unit 10 at the Nth level and the level transfer signal ST(N) of the display GOA unit 10 at the Nth level to the frame start signal STV of the next frame, the first node Q in the virtual GOA unit 20 is at a high potential. As a result, the first node Q is at a high potential for a longer time, and the life of the virtual GOA unit 20 is shorter.

[0072] The pull-down module 23 of the present application uses the control signal RESET as the control signal to pull down the first node Q in the virtual GOA unit 20, and the control signal RESET is generated between the last clock pulse LP connected to the display GOA unit 10 in the previous frame and the frame start signal STV of the next frame, so that the potential of the first node Q can be pulled down in advance, reducing the time that the first node Q is at a high potential, and thus extending the life of the virtual GOA unit 20.

[0073] It should also be noted that the scanning signal G(N) of the display GOA unit 10 of the Nth level is output to the gate of the pixel TFT of the display panel 100, while the first output end G of the virtual GOA unit 20 does not need to be connected to the gate of the pixel TFT of the display panel 100.

[0074] In some embodiments, the pull-down module 23 of the virtual GOA unit 20 pulls down the potentials of the first node Q and the first output terminal G to the potential of the low-level signal VSS under the control of the first pulse RE1 .

[0075] In some embodiments, the pull-down module 23 of the virtual GOA unit 20 resets the potentials of the first node Q and the first output terminal G to the potential of the low-level signal VSS under the control of the second pulse RE2. Moreover, the second pulse RE2 of the previous frame is generated between the first pulse RE1 of the previous frame and the frame start pulse of the frame start signal STV of the next frame.

[0076] Specifically, between the second pulse RE2 of the previous frame and the second pulse RE2 of the next frame, the driving timing of the display panel 100 includes:

[0077] A reset phase t1, during which the pull-down module 23 of the virtual GOA unit 20 resets the potentials of the first node Q and the first output terminal G to the potential of the low-level signal VSS under the control of the second pulse RE2;

[0078] A pull-up output stage t2, during which the pull-up control module 21 is configured to pull up the potential of the first node Q under the control of the first terminal and the second terminal of the display GOA unit 10, and the pull-up module 22 outputs the clock signal to the first output terminal G under the control of the first node Q;

[0079] During the pull-down phase t3, the pull-down module 23 of the virtual GOA unit 20 pulls down the potentials of the first node Q and the first output terminal G to the potential of the low-level signal VSS under the control of the first pulse RE1;

[0080] During the pull-down maintaining phase t4, the pull-down maintaining module maintains the potentials of the first node Q and the first output terminal G at the potential of the low-level signal VSS under the control of the converted low-frequency control signal.

[0081] As can be seen from the above, since the second pulse RE2 of the previous frame is generated between the first pulse RE1 of the previous frame and the frame start signal STV of the next frame, compared to the prior art, the present application can reset the potential of the first node Q and the first output terminal G to the potential of the low-level signal VSS in advance, thereby stabilizing the voltage of the first node Q and the first output terminal G during the blanking time and reducing voltage coupling fluctuations. In addition, the reset signal adopts a dual-pulse configuration, which can reduce signal introduction and facilitate simplified wiring configuration.

[0082] Please refer to Figure 4 , Figure 4 Schematic diagram of a second embodiment of the signal timing of the virtual GOA unit of the display panel of the present application. In this embodiment, between the second pulse RE2 of the previous frame and the second pulse RE2 of the next frame, the driving timing of the display panel includes:

[0083] A reset phase t1, during which the pull-down module 23 of the virtual GOA unit 20 resets the potentials of the first node Q and the first output terminal G to the potential of the low-level signal VSS under the control of the second pulse RE2;

[0084] A pull-up output stage t2, during which the pull-up control module 21 is configured to pull up the potential of the first node Q under the control of the first terminal and the second terminal of the display GOA unit 10, and the pull-up module 22 outputs the clock signal to the first output terminal G under the control of the first node Q;

[0085] A pull-down phase t3, during which the pull-down module 23 of the virtual GOA unit 20 pulls down the potentials of the first node Q and the first output terminal G to the potential of the low-level signal VSS under the control of the first pulse RE1;

[0086] a pull-down maintaining phase t4, during which the pull-down maintaining module maintains the potentials of the first node Q and the first output terminal G at the potential of the low-level signal VSS under the control of the converted low-frequency control signal;

[0087] The gap stage t5 is located between the pull-up output stage t2 and the pull-down stage t3.

[0088] In some embodiments, within the same frame, the time interval H1 between the first pulse RE1 and the last clock pulse LP connected to the display GOA unit 10 in the previous frame is greater than 0 seconds and less than or equal to 2 / (P×N) microseconds, where P is the refresh rate of the display panel 100, N is the number of display GOA units 10, and N is a positive integer. That is, the gap phase t5 includes the time interval H1 between the first pulse RE1 and the last clock pulse LP connected to the display GOA unit 10 in the previous frame. After the output phase is completed, the pull-down phase is entered after the gap phase, thereby stabilizing the signal output of the output phase.

[0089] That is, the display panel 100 includes N-level display GOA units 10, where N is a positive integer. In the same frame, the time interval H1 between the first pulse RE1 and the last clock pulse LP of the N-level display GOA unit 10 is greater than 0 seconds and less than or equal to 2 / (P×N) microseconds. Therefore, after the pull-up control module 21 pulls up the potential of the first node Q under the control of the scan signal G(N) of the N-level display GOA unit 10 and the stage transmission signal ST(N) of the N-level display GOA unit 10, within a range greater than 0 seconds and less than or equal to 2 / (P×N) microseconds, the control signal RESET provides the first pulse RE1 to the pull-down module 23 of the virtual GOA unit 20. The pull-down module 23 of the virtual GOA unit 20 pulls down the potential of the first node Q of the virtual GOA unit 20 to the low-level signal VSS, thereby further reducing the time that the first node Q is at a high potential, thereby extending the life of the virtual GOA unit 20. Specifically, in the embodiment, the time interval between the first pulse RE1 and the last clock pulse LP of the Nth stage display GOA unit 10 is 1 / (P×N) microseconds.

[0090] In some embodiments, the duration of the first pulse RE1 is 9 / (P×N) microseconds. For example, 1 / (P×N)=2.51 microseconds, then 9 / (P×N)=22.59 microseconds. The duration of the first pulse RE1 is 22.59 microseconds. Within the same frame, the time interval between the first pulse RE1 and the last clock pulse LP of the Nth-level display GOA unit 10 ranges from 0 seconds to 5.02 microseconds.

[0091] In some embodiments, a time interval H2 between the second pulse RE2 of the previous frame and the frame start signal STV of the next frame is greater than or equal to 1 / (P×N) microseconds and less than or equal to 2 / (P×N) microseconds. A gap is provided between the second pulse RE2 of the previous frame and the frame start signal STV of the next frame to avoid interference between the second pulse RE2 of the previous frame and the frame start signal STV of the next frame. The time interval between the second pulse RE2 of the previous frame and the frame start signal STV of the next frame is 1 / (P×N) microseconds.

[0092] The frame start signal STV of each frame is the dividing point between adjacent frames. Therefore, before the start of the next frame, the present application controls the signal RESET to output the second pulse RE2, and the pull-down module 23 of the virtual GOA unit 20 pulls down the potential of the first node Q of the virtual GOA unit 20 to the low-level signal VSS again. That is, relative to the frame start signal STV, the present application pulls down the potential of the first node Q of the virtual GOA unit 20 to the low-level signal VSS again before the start of the next frame, which is conducive to clearing the accumulated charge of the first node Q and preventing excessive current caused by variable refresh rate frequency conversion.

[0093] In some embodiments, the duration of the second pulse RE2 is 9 / (P×N) microseconds. For example, if 1 / (P×N)=2.51 microseconds, then 9 / (P×N)=22.59 microseconds. The duration of the second pulse RE2 is 22.59 microseconds, and the time interval between the second pulse RE2 of the previous frame and the frame start signal STV of the next frame ranges from 2.51 microseconds to 5.02 microseconds.

[0094] Please refer to Figure 5 , Figure 5 This is a second structural diagram of the virtual GOA unit 20 of the display panel 100 provided in this application. In this embodiment, the pull-down maintenance module further includes:

[0095] The second pull-down maintaining module 26, the second pull-down maintaining module 26 is connected to the second conversion low-frequency control signal LC2 and the low-level signal VSS, and is electrically connected to the first node Q and the first output terminal G. After the pull-down module 23 of the virtual GOA unit 20 pulls down the potential of the first node Q and the first output terminal G, the second pull-down maintaining module 26 is used to maintain the potential of the first node Q and the first output terminal G at the potential of the low-level signal VSS under the control of the second conversion low-frequency control signal LC2.

[0096] Furthermore, the second pull-down maintaining module 26 includes: a thirteenth transistor T61, a fourteenth transistor T62, a fifteenth transistor T63, a sixteenth transistor T64, a seventeenth transistor T65 and an eighteenth transistor T66;

[0097] The gate and source of the thirteenth transistor T61 are both connected to the second low-frequency clock signal LC2, and the drain of the thirteenth transistor T61 is electrically connected to the drain of the fourteenth transistor T62. The gate of the fourteenth transistor T62 is electrically connected to the first node Q, and the source of the fourteenth transistor T62 is connected to the low-level signal VSS. The gate of the fifteenth transistor T63 is electrically connected to the drain of the fourteenth transistor T62, the source of the fifteenth transistor T63 is connected to the second low-frequency clock signal LC2, and the drain of the fifteenth transistor T63 is electrically connected to the third node O. The gate of the sixteenth transistor T64 is electrically connected to the first node Q, the source of the sixteenth transistor T64 is connected to the low-level signal VSS, and the drain of the sixteenth transistor T64 is electrically connected to the third node O.

[0098] The gate of the seventeenth transistor T65 is electrically connected to the third node O, the source of the seventeenth transistor T65 is electrically connected to the first node Q, and the drain of the seventeenth transistor T65 is connected to the low-level signal VSS;

[0099] A gate of the eighteenth transistor T66 is electrically connected to the third node O, a source of the eighteenth transistor T66 is electrically connected to the first output terminal G, and a drain of the eighteenth transistor T66 is connected to the low-level signal VSS.

[0100] Please refer to Figure 3 and Figure 4 , wherein the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 have opposite phases, that is, the first pull-down maintaining module 25 and the second pull-down maintaining module 26 work alternately, which can avoid the thin film transistor from failing due to voltage stress.

[0101] The above is a detailed introduction to a display panel and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel comprising a display GOA unit and a virtual GOA unit connected to the display GOA unit, wherein a pull-down module of the display GOA unit is connected to a frame start signal, wherein: The virtual GOA unit includes a first node and a first output end, and the pull-down module of the virtual GOA unit is connected to the control signal and is electrically connected to the first node and the first output end; wherein, within a frame duration, the frame start signal includes a frame start pulse, and the control signal includes a first pulse and a second pulse generated at intervals; the first pulse of the previous frame is generated between the last clock pulse of the previous frame connected to the display GOA unit and the frame start pulse of the next frame; the second pulse of the previous frame is generated between the last clock pulse of the previous frame connected to the display GOA unit and the frame start pulse of the next frame or is generated synchronously with the frame start pulse of the next frame; The first pulse is used to pull down the potential of the first node and the first output end after the display GOA unit scan is completed; The second pulse is used to reset the potentials of the first node and the first output terminal before frame switching, so as to reduce the time that the virtual GOA unit is in a high potential state.

2. The display panel according to claim 1, wherein: The virtual GOA unit includes: A pull-up control module, the pull-up control module being electrically connected to the first terminal and the second terminal of the display GOA unit and electrically connected to the first node, the pull-up control module being configured to pull up the potential of the first node under the control of the first terminal and the second terminal of the display GOA unit; a pull-up module, the pull-up module receiving a clock signal and electrically connected to the first node and the first output end, the pull-up module being configured to output the clock signal to the first output end under the control of the first node; The pull-down module of the virtual GOA unit receives the control signal and the low-level signal and is electrically connected to the first node and the first output end. The pull-down module of the virtual GOA unit is used to pull down the potential of the first node and the first output end to the potential of the low-level signal under the control of the control signal; A pull-down maintaining module is electrically connected to the first node and the first output end, and is used to maintain the potential of the first node and the first output end at the potential of the low-level signal.

3. The display panel according to claim 2, wherein: The pull-down module of the virtual GOA unit pulls down the potentials of the first node and the first output end to the potential of the low-level signal under the control of the first pulse.

4. The display panel according to claim 2, wherein: The pull-down module of the virtual GOA unit resets the potentials of the first node and the first output end to the potentials of the low-level signal under the control of the second pulse.

5. The display panel according to claim 1, wherein: The second pulse of the previous frame is generated between the first pulse of the previous frame and the frame start pulse of the frame start signal of the next frame.

6. The display panel according to claim 2, wherein: The virtual GOA unit further includes: A pre-charge module is connected to the control signal and the low-level signal and is electrically connected to the first node. The pre-charge module is used to pull down the potential of the first node to the potential of the low-level signal under the control of the control signal.

7. The display panel according to claim 2, wherein: Between the second pulse of the previous frame and the second pulse of the next frame, the driving timing of the display panel includes: a reset phase, during which the pull-down module of the virtual GOA unit resets the potentials of the first node and the first output end to the potential of the low-level signal under the control of the second pulse; a pull-up output stage, during which the pull-up control module pulls up the potential of the first node under the control of the first terminal and the second terminal of the display GOA unit, and the pull-up module outputs the clock signal to the first output end under the control of the first node; a pull-down phase, during which the pull-down module of the virtual GOA unit pulls down the potentials of the first node and the first output end to the potential of the low-level signal under the control of the first pulse; A pull-down maintenance phase, during which the pull-down maintenance module maintains the potentials of the first node and the first output end at the potential of the low-level signal under the control of the converted low-frequency control signal.

8. The display panel according to claim 7, wherein: The driving timing sequence of the display panel further includes: a gap phase, and the gap phase is located between the pull-up output phase and the pull-down phase.

9. The display panel according to claim 5, wherein: In the same frame, the time interval between the first pulse and the last clock pulse connected to the display GOA unit is greater than 0 seconds and less than or equal to 2 / (P×N) microseconds, where P is the refresh frequency of the display panel, N is the number of levels of the display GOA unit, and N is a positive integer.

10. The display panel according to claim 5, wherein: Within the same frame, the time interval between the second pulse of the control signal and the frame start signal is greater than or equal to 1 / (P×N) microseconds and less than or equal to 2 / (P×N) microseconds, where P is the refresh frequency of the display panel, N is the number of levels of the display GOA unit, and N is a positive integer.

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