Display panel, manufacturing method thereof and display device

Abstract

Embodiments of the present application provide a display panel, a manufacturing method thereof and a display device. In the display panel provided by the embodiments of the present application, a recess is arranged in a first electrode of a capacitor structure, a first source / drain electrode of a first thin film transistor is located at the recess, and a second source / drain electrode is located at a side of the first electrode away from the recess. Thus, the interference of the first electrode with the first source / drain electrode and the second source / drain electrode can be reduced, the distance between the first source / drain electrode and the second source / drain electrode can be reduced, the resistance between the first source / drain electrode and the second source / drain electrode in the first thin film transistor can be reduced, and the performance of the first thin film transistor can be ensured.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] In display panels, the pixel circuits used to control pixel units often include thin-film transistors and capacitor structures. Currently, thin-film transistors and capacitor structures are often integrated into display panels.

[0003] To ensure that the capacitance value of the capacitor structure meets the requirements, the capacitor structure often occupies a certain amount of space. Due to the limitations of the capacitor structure, especially the limitations of the electrodes in the capacitor structure, the source and drain of the thin-film transistor that are electrically connected to the capacitor structure are located on opposite sides of the electrodes, resulting in a large distance between the source and drain, which in turn leads to a large resistance between the source and drain, affecting the performance of the thin-film transistor. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a display panel, its manufacturing method, and a display device to solve the technical problem of a large distance between the source and drain of thin-film transistors in the display panel in the prior art.

[0005] In a first aspect, embodiments of this application provide a display panel, including: a first thin-film transistor and a capacitor structure;

[0006] The first thin-film transistor includes:

[0007] An active structure is disposed on one side of the substrate;

[0008] An interlayer dielectric layer is disposed on the side of the active structure away from the substrate; a first via and a second via are formed in the interlayer dielectric layer;

[0009] The first source / drain electrode and the second source / drain electrode are disposed on the side of the interlayer dielectric layer away from the substrate; the first source / drain electrode is connected to the active structure through a first via, and the second source / drain electrode is connected to the active structure through a second via.

[0010] The capacitor structure includes a first electrode, which is disposed in the same layer as and separate from a first source / drain electrode and a second source / drain electrode; the first electrode includes a recess, which is configured to surround a portion of the first source / drain electrode, and the first source / drain electrode is located on the side of the first electrode away from the recess.

[0011] Secondly, embodiments of this application provide a display device, including: a display panel as provided in the first aspect.

[0012] Thirdly, embodiments of this application provide a method for manufacturing a display panel, comprising:

[0013] An active structure and an interlayer dielectric layer are sequentially formed on one side of the substrate;

[0014] The first and second vias are formed in the interlayer dielectric layer based on a patterning process;

[0015] A first source / drain electrode, a second source / drain electrode, and a first electrode are formed in the same layer, such that the first source / drain electrode is connected to the active structure through a first via and is surrounded by the recessed portion of the first electrode, and the second source / drain electrode is located on the side of the first electrode away from the recess and is connected to the active structure through a second via.

[0016] The beneficial technical effects of the technical solutions provided in this application include:

[0017] In the display panel provided in this application embodiment, by providing a recess in the first electrode of the capacitor structure, the first source / drain electrode of the first thin film transistor is located in the recess, and the second source / drain electrode is located on the side of the first electrode away from the recess, thereby reducing the interference of the first electrode on the first source / drain electrode and the second source / drain electrode, reducing the distance between the first source / drain electrode and the second source / drain electrode, thereby reducing the resistance between the first source / drain electrode and the second source / drain electrode in the first thin film transistor, and ensuring the performance of the first thin film transistor.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0021] Figure 2 Provided for the embodiments of this application Figure 1 A schematic diagram of the AA' cross-sectional structure of the display panel shown;

[0022] Figure 3 A schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of the structure after the light-shielding layer is formed in a method for manufacturing a display panel according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the structure after the active structure is formed in a method for manufacturing a display panel according to an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure after the gate metal layer is formed in a method for manufacturing a display panel according to an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the structure after forming contact holes in the interlayer dielectric layer in a method for manufacturing a display panel according to an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the structure after forming vias in the interlayer dielectric layer in a method for manufacturing a display panel according to an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures:

[0029] 100-substrate;

[0030] 101-Light-shielding layer; 102-Buffer layer; 103-Passivation layer; 104-Pixel unit layer; 105-Semiconductor layer; 106-Gate metal layer; 107-Contact hole; 108-Via hole; 109-Source / drain layer;

[0031] 10 - First thin-film transistor;

[0032] 11-Active structure of the first thin-film transistor 10; 12-Interlayer dielectric layer; 131-First source / drain electrode; 132-Second source / drain electrode; 14-Gate insulating layer; 15-Gate;

[0033] 20 - Capacitor structure; 21 - First electrode; 211 - Recess;

[0034] 30 - Second thin-film transistor; 31 - Active structure of second thin-film transistor 30;

[0035] 40 - Third thin-film transistor. Detailed Implementation

[0036] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0037] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the word “comprising” as used in this application's specification means the presence of the stated features, integers, steps, and / or operations, but does not exclude implementation as supported by this art, other features, information, data, steps, operations, and / or combinations thereof. The term “and / or” as used herein refers to at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0039] First, the relevant technologies involved in this application will be explained:

[0040] Currently, pixel circuits often include capacitor structures and multiple thin-film transistors. For example, the pixel circuit of an AMOLED (Active-Matrix Organic Light-Emitting Diode) display panel typically includes three thin-film transistors (T) and one capacitor structure (C), forming a 3T1C pixel circuit.

[0041] In display panels, pixel circuits are often located below the pixel layer, meaning that thin-film transistors and capacitor structures often need to be integrated together.

[0042] Since most capacitor structures are planar capacitors, the planar electrodes of the capacitor structure need to occupy a certain area in order to ensure that the capacitance value of the capacitor structure meets the usage requirements. For thin film transistors with the source and drain located on opposite sides of the electrode, the distance between the source and drain is limited by the size of the planar electrode due to the limitation of the planar electrode. This results in a large distance between the source and drain, which in turn leads to a large resistance between the source and drain, affecting the performance of the thin film transistor.

[0043] The display panel, its manufacturing method, and display device provided in this application are intended to address the aforementioned technical problems of the prior art.

[0044] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0045] This application provides a display panel, the structural schematic diagram of which is shown below. Figure 1 As shown, Figure 1 The schematic diagram of the AA' cross-sectional structure of the display panel shown is as follows: Figure 2 As shown, the display panel includes: a first thin-film transistor 10 and a capacitor structure 20.

[0046] The first thin-film transistor 10 includes: an active structure 11 disposed on one side of a substrate 100; an interlayer dielectric layer 12 disposed on the side of the active structure 11 away from the substrate 100; a first via and a second via formed in the interlayer dielectric layer 12; a first source / drain electrode 131 and a second source / drain electrode 132 disposed on the side of the interlayer dielectric layer 12 away from the substrate 100; the first source / drain electrode 131 is connected to the active structure 11 through the first via, and the second source / drain electrode 132 is connected to the active structure 11 through the second via.

[0047] The capacitor structure 20 includes a first electrode 21, which is disposed in the same layer as the first source / drain electrode 131 and the second source / drain electrode 132 but separated from each other; the first electrode 21 includes a recess 211, which is configured to surround part of the first source / drain electrode 131, and the second source / drain electrode 132 is located on the side of the first electrode 21 away from the recess 211.

[0048] In the display panel provided in this application embodiment, by providing a recess 211 in the first electrode 21 of the capacitor structure 20, the first source / drain electrode 131 of the first thin film transistor 10 is located in the recess 211, and the second source / drain electrode 132 is located on the side of the first electrode 21 away from the recess 211, thereby reducing the interference of the first electrode 21 on the first source / drain electrode 131 and the second source / drain electrode 132, reducing the distance between the first source / drain electrode 131 and the second source / drain electrode 132, thereby reducing the resistance between the first source / drain electrode 131 and the second source / drain electrode 132 in the first thin film transistor 10, and ensuring the performance of the first thin film transistor 10.

[0049] In the embodiments of this application, such as Figure 2 As shown, the active structure 11 and the interlayer dielectric layer 12 of the first thin film transistor 10 are stacked sequentially on one side of the substrate 100. The interlayer dielectric layer 12 has a first via and a second via. Part of the first source / drain electrode 131 is filled in the first via to connect with the active structure 11, and part of the second source / drain electrode 132 is filled in the second via to connect with the active structure 11.

[0050] It should be noted that, since the interlayer dielectric layer 12 is an inorganic transparent film layer, therefore, Figure 1 Interlayer medium 12 is not marked. Although Figure 1 and Figure 2 The first and second vias are not directly labeled, but combined with... Figure 2It can be seen that the first source / drain electrode 131 is filled with the first via, and the second source / drain electrode 132 is filled with the second via.

[0051] In the embodiments of this application, such as Figure 1 and Figure 2 As shown, the first electrode 21 of the capacitor structure 20 is disposed in the same layer as the first source / drain electrode 131 and the second source / drain electrode 132 of the first thin film transistor 10 and is separated from it, which can improve the integration of the first thin film transistor 10 and the capacitor structure 20 and is beneficial to the thinning of the display panel.

[0052] In this embodiment, the first electrode 21 includes a recess 211, which is configured to partially surround the first source / drain electrode 131. Specifically, the first source / drain electrode 131 is located on the side closest to the recess 211, and the second source / drain electrode 132 is located on the side of the first electrode 21 away from the recess 211. Figure 1 and Figure 2 It can be seen that the outer contour of the recess 211 surrounds the orthogonal projection of the first source / drain electrode 131 on the substrate 100, and the orthogonal projection of the second source / drain electrode 132 on the substrate 100 is located on the side of the first electrode 21 on the substrate 100 away from the recess 211.

[0053] By providing a recess 211 in the first electrode 21, the restriction on the placement of the first source / drain electrode 131 and the second source / drain electrode 132 by the first electrode 21 can be reduced, and the interference of the first electrode 21 on the first source / drain electrode 131 and the second source / drain electrode 132 can be reduced. This allows the distance d between the first source / drain electrode 131 and the second source / drain electrode 132 to be smaller than the dimension of the first electrode 21 along the direction from the first source / drain electrode 131 to the second source / drain electrode 132. Compared with the existing solution, the distance d between the first source / drain electrode 131 and the second source / drain electrode 132 can be reduced, thereby reducing the resistance between the first source / drain electrode 131 and the second source / drain electrode 132 in the first thin film transistor 10 and ensuring the performance of the first thin film transistor 10.

[0054] In this embodiment, by providing a recess 211 in the first electrode 21, the positional restrictions of the capacitor structure 20, particularly the first electrode 21 of the capacitor structure 20, on the first and second vias opened in the interlayer dielectric layer 12 can be reduced during the design and process of the display panel. Compared with the prior art, by changing the layout of the first and second vias, the straight-line distance between the first and second vias can be shortened, thereby shortening the distance between the first source / drain electrode 131 partially filled in the first via and the second source / drain electrode 132 partially filled in the second via.

[0055] Optionally, in this embodiment, the first thin-film transistor 10 is a driving thin-film transistor. The first thin-film transistor 10 is also electrically connected to the light-emitting unit. By reducing the distance d between the first source-drain electrode 131 and the second source-drain electrode 132, the resistance between the first source-drain electrode 131 and the second source-drain electrode 132 can be reduced, thereby increasing the on-state current of the first thin-film transistor 10 and thus increasing the luminous brightness of the light-emitting unit.

[0056] In this embodiment, one of the first source / drain electrode 131 and the second source / drain electrode 132 can be the source and the other can be the drain. Those skilled in the art can specifically set the source and drain of the first transistor 10 according to actual needs.

[0057] In one embodiment of this application, the first thin-film transistor 10 further includes: a gate insulating layer 14 disposed on the side of the interlayer dielectric layer 12 away from the substrate 100; a gate 15 disposed on the side of the gate insulating layer 14 away from the substrate 100; the interlayer dielectric layer 12 covers the gate 15, and the gate 15 is located between the first source / drain electrode 131 and the second source / drain electrode 132; a portion of the gate 15 is projected onto the substrate 100, which overlaps with a portion of the first electrode 21 is projected onto the substrate 100.

[0058] In the embodiments of this application, such as Figure 2 As shown, the gate insulating layer 14 and the gate 15 are stacked sequentially on one side of the substrate 100, meaning that the first thin-film transistor 10 is a top-gate thin-film transistor. The interlayer dielectric layer 12 covers the gate 15 to prevent the gate 15 from contacting the first electrode 21, the first source / drain electrode 131, and the second source / drain electrode 132.

[0059] like Figure 1 and Figure 2 As shown, the gate 15 is located between the first source / drain electrode 131 and the second source / drain electrode 132, and the first electrode 21 covers part of the gate 15.

[0060] Optionally, the gate insulating layer 14 is a GI (Gate Insulation) layer, and the interlayer dielectric layer 12 is an ILD (Inter-Layer Dielectric).

[0061] In one embodiment of this application, the orthographic projection of the first electrode 21 onto the substrate 100 is U-shaped, and the orthographic projection of the first electrode 21 onto the substrate 100 surrounds a portion of the orthographic projection of the first source / drain electrode 131 onto the substrate 100.

[0062] In the embodiments of this application, such as Figure 1As shown, the orthographic projection shape of the first electrode 21 is U-shaped, and the first source / drain electrode 131 is located at the opening of the U-shape of the first electrode 21. By designing the first electrode 21 as U-shaped, the distance d between the first source / drain electrode 131 and the second source / drain electrode 132 can be reduced while ensuring the area of ​​the first electrode 21, thereby ensuring the capacitance value of the capacitor structure 10.

[0063] Those skilled in the art will understand that, in combination Figure 1 and Figure 2 It can be seen that by reducing the size of the bottom of the U-shaped first electrode 21, the distance d between the first source / drain electrode 131 and the second source / drain electrode 132 can be further shortened, thereby further reducing the resistance between the first source / drain electrode 131 and the second source / drain electrode 132. The bottom of the U-shaped first electrode 21 is the part of the first electrode 21 located between the first source / drain electrode 131 and the second source / drain electrode 132.

[0064] It should be noted that the embodiments of this application only provide a specific shape of the first electrode 21. Those skilled in the art can choose to set different shapes of the first electrode 21 according to actual needs, as long as the area of ​​the first electrode 21 meets the requirements and the first electrode 21 has a recess 211 for accommodating the first source / drain electrode 131.

[0065] In one embodiment of this application, the display panel further includes: a light-shielding layer 101 disposed on one side of the substrate 100, and a first thin-film transistor 10 disposed on the side of the light-shielding layer 101 away from the substrate 100; a portion of the light-shielding layer 101 is the second electrode of the capacitor structure 20, and the orthographic projection of the portion of the light-shielding layer 101 on the substrate 100 overlaps with the orthographic projection of the first electrode 21 on the substrate 100.

[0066] In the embodiments of this application, such as Figure 1 and Figure 2 As shown, a light-shielding layer 101 is provided on one side of the substrate 100. Optionally, the light-shielding layer 101 is a shield layer. The light-shielding layer 101 is made of a metal material with high reflectivity. Therefore, the light-shielding layer 101 has good conductivity.

[0067] like Figure 1 and Figure 2 As shown, the orthographic projection of part of the light-shielding layer 101 onto the substrate 100 overlaps with the orthographic projection of the first electrode 21 onto the substrate 100. That is, the portion of the light-shielding layer 101 that is completely opposite to the first electrode 21 is constructed as the second electrode of the capacitor structure 20, and the film layer sandwiched between the light-shielding layer 101 and the first electrode 21 is constructed as the dielectric layer of the capacitor structure 20.

[0068] In this embodiment, by constructing a portion of the light-shielding layer 101 as the second electrode of the capacitor structure 20, the integration level of the capacitor structure 20 can be improved. Meanwhile, the main body of the capacitor structure 20 is located between the first source / drain electrode 131 and the second source / drain electrode 132 of the first thin-film transistor 10, thereby further improving the integration level of the pixel circuit and the integration level of the display panel.

[0069] In one embodiment of this application, a first via penetrates the active structure 11, and the first source / drain electrode 131 is connected to the light-shielding layer 101 through the first via.

[0070] In the embodiments of this application, such as Figure 2 As shown, the first via penetrates the active structure 11, so that the first source / drain electrode 131 filled in the first via can be connected to both the active structure 11 and the light-shielding layer 101 at the same time, thereby realizing the electrical connection between the first thin film transistor 10 and the capacitor structure 20. This avoids the need for separate traces and reduces the manufacturing cost of the display panel.

[0071] In one embodiment of this application, the display panel further includes: a second thin-film transistor 30 disposed on the side of the light-shielding layer 101 away from the substrate 100; one of the source or drain of the second thin-film transistor 30 is shared with the first source or drain electrode 131 of the first thin-film transistor 10.

[0072] In this embodiment of the application, combined with Figure 1 and Figure 2 It is known that a second thin-film transistor 30 is also provided on the side of the light-shielding layer 101 away from the substrate 100. Optionally, the second thin-film transistor 30 can be one of a switching transistor and a compensation transistor.

[0073] like Figure 2 As shown, the first source / drain electrode 131 is connected to the active structure 31 of the second thin-film transistor 30, so that the first source / drain electrode 131 can serve as the source or drain of the second thin-film transistor 30, realizing that the two transistors share a first source / drain electrode 131, which can further improve the integration level of the display panel.

[0074] In one embodiment of this application, the orthographic projection of the first source / drain electrode 131 onto the substrate 100 covers the orthographic projection of a portion of the active structure 11 of the first thin-film transistor 10 and a portion of the active structure 31 of the second thin-film transistor 30 onto the substrate 100.

[0075] In the embodiments of this application, such as Figure 1 and Figure 2As shown, the active structure 11 of the first thin-film transistor 10 and the active structure 31 of the second thin-film transistor 30 are configured as the peripheral wall of a portion of the first via, such that the first source / drain electrode 131 can cover a portion of the active structure 11 of the first thin-film transistor 10 and a portion of the active structure 31 of the second thin-film transistor 30, so as to ensure the connection area between the first source / drain electrode 131 and the active structures 11 and 31, and to ensure that the two transistors share a single first source / drain electrode 131.

[0076] In one embodiment of this application, the display panel further includes: a buffer layer 102 disposed on the side of the light-shielding layer 101 away from the substrate 100; a first sub-hole is formed in the buffer layer 102, and the first source / drain electrode 131 is connected to the light-shielding layer 101 through the first sub-hole; the center of the first sub-hole coincides with the center of the first via.

[0077] In the embodiments of this application, such as Figure 2 As shown, a buffer layer 102 is disposed on the side of the light-shielding layer 101 away from the substrate 100. Optionally, the buffer layer 102 is a buffer layer. The buffer layer 102 is made of an inorganic insulating material.

[0078] It should be noted that, Figure 1 Buffer layer 102 is not marked in the text. Although Figure 1 and Figure 2 The first sub-hole is not directly marked, but combined with Figure 2 It can be seen that the first source / drain electrode 131 is filled with the first sub-via. The first sub-via is connected to the first via, and the center of the first sub-via coincides with the center of the first via, so that the first source / drain electrode 131 can be connected to the light-shielding layer 101.

[0079] In one embodiment of this application, the display panel further includes a third thin-film transistor 40, wherein a portion of the first electrode 21 serves as the source or drain of the third thin-film transistor 40.

[0080] In the embodiments of this application, such as Figure 1 As shown, the display panel also includes a third thin-film transistor 40. Optionally, the third thin-film transistor 40 can be another of the switching transistor and the compensation transistor, i.e. Figure 1 The display panel shown illustrates a complete 3T1C pixel circuit structure.

[0081] like Figure 1 As shown, part of the first electrode 21 of the capacitor structure 20 can be constructed as the source or drain of the third thin-film transistor 40, which can further improve the integration level of the display panel and reduce the manufacturing cost of the display panel.

[0082] Optionally, such as Figure 2As shown, the display panel further includes a passivation layer 103 and a pixel unit layer 104. The passivation layer 103 is disposed on the side of the first electrode 21, the first source / drain electrode 131, and the second source / drain electrode 132 away from the substrate 100, and the pixel unit layer 104 is disposed on the side of the passivation layer 103 away from the substrate 100. Optionally, the pixel unit layer 104 includes a light-emitting layer and a color filter layer.

[0083] Based on the same inventive concept, this application provides a display device, including: a display panel provided in any of the above embodiments.

[0084] In this embodiment, the display device uses any of the display panels provided in the foregoing embodiments. The principle and technical effects are described in the foregoing embodiments and will not be repeated here.

[0085] Optionally, in this embodiment, the display device is a mobile phone, tablet computer, laptop computer, or smart TV, etc.

[0086] Based on the same inventive concept, this application provides a method for manufacturing a display panel, the flowchart of which is shown below. Figure 3 As shown, the steps S301-S303 are as follows:

[0087] S301, an active structure and an interlayer dielectric layer are sequentially formed on one side of the substrate.

[0088] S302, a first via and a second via are formed in the interlayer dielectric layer based on a patterning process.

[0089] S303, forming a first source / drain electrode, a second source / drain electrode, and a first electrode arranged in the same layer, such that the first source / drain electrode is connected to the active structure through a first via and is surrounded by the recessed portion of the first electrode, and the second source / drain electrode is located on the side of the first electrode away from the recess and is connected to the active structure through a second via.

[0090] In the display panel manufacturing method provided in this application embodiment, by forming a first via and a second via at a preset position in the interlayer dielectric layer, during the process of forming the first source / drain electrode, the second source / drain electrode, and the first electrode disposed in the same layer, the first source / drain electrode 131 of the first thin film transistor 10 is located at the recess 211, and the second source / drain electrode 132 is located on the side of the first electrode 21 away from the recess 211. This reduces the interference of the first electrode 21 on the first source / drain electrode 131 and the second source / drain electrode 132, reduces the distance between the first source / drain electrode 131 and the second source / drain electrode 132, and further reduces the resistance between the first source / drain electrode 131 and the second source / drain electrode 132 in the first thin film transistor 10, thus ensuring the performance of the first thin film transistor 10.

[0091] To facilitate readers' intuitive understanding of the manufacturing method of the display panel provided in the embodiments of this application and the advantages of the display panel prepared by this method, the following will be combined with... Figures 4-8 Please provide a detailed explanation.

[0092] It should be noted that, Figure 1 and Figures 4-8 In this context, structures located within the same film layer but in different positions or with different functions are distinguished using letter suffixes such as a, b, c, d, etc. For example, the light-shielding layer 101 is formed as a single layer across the entire display panel, but its position and size need to be specifically set according to the placement and size of different thin-film transistors or other devices. Figure 4 As shown, a light-shielding layer 101a, a light-shielding layer 101b, and a light-shielding layer 101c are provided.

[0093] In one embodiment of this application, the above step S301, in which an active structure 11 and an interlayer dielectric layer 12 are sequentially formed on one side of the substrate 100, further includes: forming a light-shielding layer 101 on one side of the substrate 100.

[0094] Optionally, a metal layer, such as aluminum, is formed by depositing a highly reflective metal material on one side of the substrate 100, and then patterning the metal layer to obtain a light-shielding layer 101, such as... Figure 4 As shown, it includes a light-shielding layer 101a, a light-shielding layer 101b, and a light-shielding layer 101c.

[0095] In one embodiment of this application, step S301, which sequentially forms an active structure 11 and an interlayer dielectric layer 12 on one side of the substrate 100, specifically includes the following steps:

[0096] First, semiconductor material is deposited on the side of the light-shielding layer 101 away from the substrate 100 and in the area of ​​the substrate 100 not covered by the light-shielding layer 101, and then patterned to obtain the semiconductor layer 105, such as... Figure 5 As shown, it includes semiconductor layer 105a, semiconductor layer 105b and semiconductor layer 105c, with a portion of semiconductor layer 105 serving as the active structure 11 of a transistor.

[0097] Optionally, the semiconductor layer 105 may be made of IGZO (Indium Gallium Zinc Oxide).

[0098] Then, a gate insulating layer 14 is formed on the side of the semiconductor layer 105 away from the substrate 100. Figure 6 (Not shown in the image).

[0099] Next, using deposition and patterning processes, a gate metal layer 106 is formed on the side of the gate insulating layer 14 away from the substrate 100, such as... Figure 6As shown, it includes gate metal layer 106a, gate metal layer 106b and gate metal layer 106c. A portion of the gate metal layer 106 serves as the gate 15 of the transistor. Specifically, the portion of the gate metal layer 106 that overlaps with the semiconductor layer 105 is configured as the gate 15 of the transistor.

[0100] Then, an inorganic insulating material, such as silicon oxide, is deposited on one side of the gate metal layer 106 to form an interlayer dielectric layer 12.

[0101] In one embodiment of this application, step S302, which involves forming a first via and a second via in the interlayer dielectric layer based on a patterning process, specifically includes the following steps:

[0102] First, the interlayer dielectric layer 12 is patterned, and a contact hole (CNT) 107 is formed at a set position in the interlayer dielectric layer. Optionally, the contact hole 107 is a blind hole, that is, the contact hole 107 does not penetrate the interlayer dielectric layer.

[0103] like Figure 7 As shown, it includes contact holes 107a, 107b, 107c, and 107d. Contact hole 107 is where the source and drain electrodes of the subsequently formed transistor are located.

[0104] Optionally, such as Figure 7 As shown, two adjacent contact holes 107b and 107c are the first sub-hole and the second sub-hole, respectively. The first sub-hole and the second sub-hole are blind holes, both of which penetrate part of the interlayer dielectric layer 12.

[0105] Then, the patterned interlayer dielectric layer 12 is processed using a patterning process to form a via 108. Optionally, the via 108 is a through hole, that is, the via 108 at least penetrates the interlayer dielectric layer 12.

[0106] like Figure 8 As shown, this includes vias 108a, 108b, and 108c. Via 108 is where the source and drain electrodes of the subsequently formed transistor are located.

[0107] Optionally, such as Figure 8 As shown, the second via is formed based on the first sub-via and the second sub-via, so that the light-shielding layer 101 is exposed.

[0108] In this embodiment, the interlayer dielectric layer 12 is patterned twice to form contact holes 107 and vias 108 respectively. Compared with the process of forming vias 108 by patterning once, the risk of over-etching can be reduced, thereby ensuring the yield of the display panel.

[0109] In one embodiment of this application, step S303, which forms a first source / drain electrode, a second source / drain electrode, and a first electrode disposed on the same layer, specifically includes the following steps:

[0110] A metal material is deposited on the side of the interlayer dielectric layer 12 away from the substrate 100, and a source / drain layer 109 is patterned to form it, such as... Figure 1 As shown, the source-drain layer 109 includes source-drain electrodes 109a and 109b, as well as the source and drain of each transistor. Source-drain electrodes 109a and 109b can be used as signal traces.

[0111] Optionally, a subsequent passivation layer 103, pixel unit layer 104, and pixel electrode are formed through a deposition process to obtain a display panel.

[0112] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0113] In the display panel provided in this application embodiment, by providing a recess in the first electrode 21 of the capacitor structure 20, the first source / drain electrode 131 of the first thin film transistor 10 is located in the recess 211, and the second source / drain electrode 132 is located on the side of the first electrode 21 away from the recess 211. This reduces the interference of the first electrode 21 on the first source / drain electrode 131 and the second source / drain electrode 132, reduces the distance between the first source / drain electrode 131 and the second source / drain electrode 132, and further reduces the resistance between the first source / drain electrode 131 and the second source / drain electrode 132 in the first thin film transistor 10, thus ensuring the performance of the first thin film transistor 10.

[0114] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0115] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0116] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0117] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0118] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0119] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application, the steps in each process can be executed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages may be executed at the same time or at different times. In scenarios where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application does not limit this.

[0120] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: First thin-film transistor and capacitor structure; The first thin-film transistor includes: An active structure is disposed on one side of the substrate; An interlayer dielectric layer is disposed on the side of the active structure away from the substrate; a first via and a second via are formed in the interlayer dielectric layer; A first source / drain electrode and a second source / drain electrode are disposed on the side of the interlayer dielectric layer away from the substrate; the first source / drain electrode is connected to the active structure through the first via, and the second source / drain electrode is connected to the active structure through the second via; The capacitor structure includes a first electrode, which is disposed in the same layer as the first source / drain electrode and the second source / drain electrode but is separated from them; the first electrode includes a recess, which is configured to surround a portion of the first source / drain electrode, and the second source / drain electrode is located on the side of the first electrode away from the recess. The orthographic projection of the first electrode onto the substrate is U-shaped, and the orthographic projection of the first electrode onto the substrate surrounds a portion of the orthographic projection of the first source / drain electrode onto the substrate; the first source / drain electrode is located at the U-shaped opening of the first electrode; A light-shielding layer is disposed on one side of the substrate, and the first thin-film transistor is disposed on the side of the light-shielding layer away from the substrate; Part of the light-shielding layer is the second electrode of the capacitor structure, and the orthographic projection of this part of the light-shielding layer on the substrate overlaps with the orthographic projection of the first electrode on the substrate; The first via penetrates the active structure, and the first source / drain electrode is connected to the light-shielding layer through the first via, so that the first source / drain electrode filled in the first via is simultaneously connected to the active structure and the light-shielding layer, thereby realizing the electrical connection between the first thin-film transistor and the capacitor structure.

2. The display panel according to claim 1, characterized in that, The first thin-film transistor further includes: A gate insulating layer is disposed on the side of the interlayer dielectric layer near the substrate; A gate is disposed on the side of the gate insulating layer away from the substrate; the interlayer dielectric layer covers the gate, and the gate is located between the first source / drain electrode and the second source / drain electrode; a portion of the gate's orthogonal projection onto the substrate overlaps with a portion of the first electrode's orthogonal projection onto the substrate.

3. The display panel according to claim 1, characterized in that, Also includes: A second thin-film transistor is disposed on the side of the light-shielding layer away from the substrate; One of the source or drain electrodes of the second thin-film transistor is shared with the first source or drain electrode of the first thin-film transistor.

4. The display panel according to claim 3, characterized in that, The orthographic projection of the first source / drain electrode onto the substrate covers the orthographic projections of a portion of the active structure of the first thin-film transistor and a portion of the active structure of the second thin-film transistor onto the substrate.

5. The display panel according to claim 4, characterized in that, Also includes: A buffer layer is disposed on the side of the light-shielding layer away from the substrate; The buffer layer has a first sub-hole, through which the first source / drain electrode is connected to the light-shielding layer; the center of the first sub-hole coincides with the center of the first via.

6. The display panel according to claim 1, characterized in that, Also includes: In a third thin-film transistor, a portion of the first electrode serves as the source or drain of the third thin-film transistor.

7. A display device, characterized in that, include: The display panel as described in any one of claims 1-6.

8. A method for manufacturing a display panel, characterized in that, include: An active structure and an interlayer dielectric layer are sequentially formed on one side of the substrate; The first and second vias are formed in the interlayer dielectric layer using a patterning process; A first source / drain electrode, a second source / drain electrode, and a first electrode are formed in the same layer, such that the first source / drain electrode is connected to the active structure through the first via and is surrounded by the recessed portion of the first electrode; the second source / drain electrode is located on the side of the first electrode away from the recess and is connected to the active structure through the second via; the orthographic projection of the first electrode on the substrate is U-shaped, and the orthographic projection of the first electrode on the substrate surrounds a portion of the orthographic projection of the first source / drain electrode on the substrate. The first source / drain electrode is located at the U-shaped opening of the first electrode; The process of sequentially forming an active structure and an interlayer dielectric layer on one side of the substrate, prior to which includes: A light-shielding layer is formed on one side of the substrate; And, the formation of the first via and the second via in the interlayer dielectric layer based on the patterning process includes: The interlayer dielectric layer is patterned, and two adjacent first sub-holes and second sub-holes are formed at a predetermined position on the interlayer dielectric layer, such that the orthographic projection of a portion of the active structure and a portion of the light-shielding layer on the interlayer dielectric layer is located within the first sub-hole; the first sub-hole and the second sub-hole extend into a portion of the interlayer dielectric layer; The patterned interlayer dielectric layer is patterned to form the first via and the second via, wherein the second via is formed based on the first sub-via and the second sub-via.

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