Semiconductor device and method of manufacturing

Abstract

Embodiments of the invention provide a semiconductor device and a method of manufacturing the same, the method comprising: depositing a dielectric layer over a substrate; forming carbon nanotubes on the dielectric layer; forming a dummy gate stack on the carbon nanotubes; forming gate spacers on opposite sides of the dummy gate stack; and removing the dummy gate stack to form trenches between the gate spacers. The carbon nanotubes are exposed to the trenches. The method further comprises: etching a portion of the dielectric layer underlying the carbon nanotubes, wherein the carbon nanotubes are suspended; forming a replacement gate dielectric surrounding the carbon nanotubes; and forming a gate electrode surrounding the replacement gate dielectric.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] The semiconductor industry has consistently followed Moore's Law, doubling the number of transistors per unit area every two years. This has resulted in higher computing performance with lower power and lower cost in each generation of new technologies. However, as transistor size shrinks, unwanted short-channel effects (SCEs), such as drain-induced barrier reduction (DIBL) and the large subthreshold swing (SS) required to turn off transistors, become increasingly severe. This significantly limits the scaling of transistors. New innovations are needed to extend Moore's Law.

[0003] Although SCE can be mitigated by correspondingly reducing the channel thickness, transistors using 3D bulk crystalline channel materials (e.g., silicon, germanium, and III-V compound semiconductors) suffer performance degradation due to significant carrier scattering near the channel surface. Furthermore, as the bulk thickness decreases, the threshold voltage variation increases rapidly due to increased sensitivity to changes in bulk thickness. Summary of the Invention

[0004] According to one aspect of the present invention, a method of manufacturing a semiconductor device is provided, comprising: depositing a dielectric layer over a substrate; forming carbon nanotubes on the dielectric layer; forming a dummy gate stack on the carbon nanotubes; forming gate spacers on opposite sides of the dummy gate stack; removing the dummy gate stack to form trenches between the gate spacers, wherein the carbon nanotubes are exposed in the trenches; etching a portion of the dielectric layer located beneath the carbon nanotubes, wherein the carbon nanotubes are suspended; forming an alternative gate dielectric surrounding the carbon nanotubes; and forming a gate electrode surrounding the alternative gate dielectric.

[0005] According to another aspect of the present invention, a semiconductor device is provided, comprising: a dielectric layer located above a substrate; a plurality of carbon nanotubes located above and in contact with a first portion and a second portion of the dielectric layer; and a gate stack extending between the first and second portions of the dielectric layer. The gate stack includes: a gate dielectric surrounding a portion of the plurality of carbon nanotubes, wherein a portion of the plurality of carbon nanotubes is located between the first and second portions of the dielectric layer; and a gate electrode surrounding a combined region of the plurality of carbon nanotubes and the gate dielectric, wherein the gate electrode includes an upper portion overlapping the combined region and a lower portion overlapping the combined region.

[0006] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate having a top surface; a plurality of carbon nanotubes substantially parallel and spaced apart from each other, wherein the plurality of carbon nanotubes are substantially aligned with a common plane located above and parallel to the top surface of the substrate; a gate stack; and a gate spacer located on a sidewall of the gate stack, wherein a first portion of a gate dielectric and a third portion of a gate electrode extend above a bottom surface of the gate spacer, and a second portion of the gate dielectric and a fourth portion of the gate electrode extend below a bottom surface of the gate spacer. The gate stack includes: a gate dielectric including a first portion directly above the plurality of carbon nanotubes and a second portion directly below the plurality of carbon nanotubes; and a gate electrode including a third portion above the first portion of the gate dielectric and a fourth portion below the second portion of the gate dielectric. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0008] Figures 1-6 , Figure 7A , Figure 8A , Figures 9-11 and Figure 12A A perspective view showing an intermediate stage in the formation of a dual-gate carbon nanotube transistor according to some embodiments.

[0009] Figures 7B-7F The outline of a trench formed by removing dummy gate stacks according to some embodiments is shown.

[0010] Figure 8B and Figure 8C A cross-sectional view of a carbon nanotube and a gate dielectric surrounding the carbon nanotube is shown according to some embodiments.

[0011] Figure 12B A cross-sectional view of the gates of two dual-gate carbon nanotube transistors according to some embodiments is shown.

[0012] Figure 13 A perspective view of a dual-gate carbon nanotube transistor according to some embodiments is shown.

[0013] Figure 14 A perspective view of a cross section of a carbon nanotube and a corresponding gate stack according to some embodiments is shown.

[0014] Figure 15 The subthreshold swing (SS) of various types of transistors as a function of gate length is shown according to some embodiments.

[0015] Figure 16 The effective drive current of various types of transistors as a function of gate length is shown according to some embodiments.

[0016] Figure 17 The process flow for forming a dual-gate carbon nanotube transistor is shown according to some embodiments. Detailed Implementation

[0017] The following disclosure provides various embodiments or examples to achieve different features of the invention. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0019] A dual-gate carbon nanotube (CNT) transistor and a method for forming the same are provided. According to some embodiments of this disclosure, carbon nanotubes are formed over a dielectric layer. A dummy gate is formed on the carbon nanotube. The dummy gate is subsequently removed, followed by the removal of a portion of the dielectric layer beneath the carbon nanotube transistor. The carbon nanotube is thus suspended. A gate dielectric is formed to surround (in a cross-sectional view) the carbon nanotube. The gate dielectric comprises multiple portions located on different carbon nanotubes, and the multiple portions are bonded together. A gate electrode is formed to surround the gate dielectric. The use of a dual-gate transistor reduces short-channel effects. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made will be readily understood by those skilled in the art while remaining within the contemplated scope of the different embodiments. Throughout the various views and exemplary embodiments, the same reference numerals are used to designate the same elements. While method embodiments may be discussed as being implemented in a particular order, other method embodiments may also be implemented in any reasonable order.

[0020] Figures 1-6 , Figure 7A , Figure 8A , Figures 9-11 and Figure 12A A cross-sectional view is shown illustrating an intermediate stage in the formation of a dual-gate carbon nanotube transistor according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in... Figure 17 The process flow shown is as follows.

[0021] refer to Figure 1 A wafer 10 including a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc. The substrate 20 may be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor substrate 20 may be part of the wafer 10 (such as a silicon wafer). Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include: silicon; germanium; compound semiconductors including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, SiC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The substrate 20 can also be formed of other materials, such as sapphire, indium tin oxide (ITO), etc.

[0022] An isolation layer 22 is deposited over the substrate 20. The corresponding process is shown as follows. Figure 17 Process 202 is shown in the process flow 200. According to some embodiments, the isolation layer 22 is in physical contact with the substrate 20. According to alternative embodiments, other layers and devices, including but not limited to dielectric layers, metal components, etc., may be present between the isolation layer 22 and the substrate 20. For example, interlayer dielectrics, intermetallic dielectrics (which may include low-k dielectric layers), etc., may be present. Integrated circuit devices, such as passive devices (capacitors, resistors, inductors, etc.) and / or active devices (transistors, diodes, etc.), may or may not be present between the isolation layer 22 and the substrate 20.

[0023] According to some embodiments of this disclosure, the isolation layer 22 is formed of or includes a high-k dielectric material such as an oxide of silicon oxide, a nitride of silicon nitride, or an alumina, hafnium oxide, zirconium oxide, or lanthanum oxide. The thickness of the isolation layer 22 can be in the range of about 30 nm to about 50 nm. The isolation layer 22 can be formed by a deposition process, which can be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0024] An etch stop layer 24 is deposited over an isolation layer 22. The corresponding process is shown as follows. Figure 17 Process 204 in process flow 200 is shown in the diagram. The material of the etch stop layer 24 is a dielectric material different from that of the isolation layer 22. According to some embodiments, the etch stop layer 24 is formed or includes alumina (Al2O3), oxygen-doped silicon carbide (SiOC), silicon nitride, or combinations thereof, or multiples thereof. The thickness of the etch stop layer 24 can be in the range of about 5 nm to about 10 nm. The etch stop layer 24 can be formed by deposition processes such as CVD, ALD, PECVD, LPCVD, etc.

[0025] Then, dielectric layer 26 is deposited over etch stop layer 24. The corresponding process is shown as follows. Figure 17 Process 206 in process flow 200 is shown in the diagram. According to some embodiments, dielectric layer 26 is formed of a dielectric material different from that of etch stop layer 24, and may be the same as or different from the material of isolation layer 22. According to some embodiments of this disclosure, dielectric layer 26 is formed of or includes materials such as oxides of silicon oxide, nitrides such as silicon nitride, silicon oxynitride, etc. Dielectric layer 26 can also be formed by deposition processes such as CVD, ALD, PECVD, LPCVD, etc.

[0026] Then, nanostructure 30 is formed over dielectric layer 26. The corresponding process is shown as follows. Figure 17Process 208 is shown in process flow 200. According to some embodiments, the nanostructure 30 is carbon nanotubes 30, but they can also be formed from other semiconductor materials. Throughout the description, the nanostructure 30 is referred to as carbon nanotubes 30. The carbon nanotubes 30 are grown on dielectric layer 26, or grown on another wafer and then transferred to dielectric layer 26. According to some embodiments, parallel catalyst strips (not shown) can be formed to form the carbon nanotubes 30. The catalyst strips can be formed from metals such as iron, nickel, copper, molybdenum, and tungsten, and can be formed from pure or substantially pure metals as described above, for example, with a metal atomic percentage greater than about 95%. The formation of the catalyst strips can include a stripping process, or a deposition process followed by a patterning process. The deposition process can include physical vapor deposition (PVD), chemical vapor deposition (CVD), etc.

[0027] Carbon nanotubes 30 can be grown using carbon-containing precursors (such as CH4, C2H6O, C3H8O, or combinations thereof) and can be formed, for example, by CVD. The temperature of wafer 10 can be in the range of about 600°C to about 1000°C, causing the precursor to decompose and carbon to grow from the catalyst band to form carbon nanotubes 30. Carbon nanotubes 30 grow from the catalyst band and toward adjacent catalyst bands. The growth direction of carbon nanotubes 30 is generally perpendicular to the sidewalls of the catalyst bands and parallel to the top surface of dielectric layer 26. According to some embodiments of this disclosure, the diameter of carbon nanotubes 30 can be in the range of about 0.5 nm to about 2 nm.

[0028] According to some embodiments, the catalyst strip is formed directly on the dielectric layer 26, thereby the carbon nanotubes 30 are grown directly on the dielectric layer 26. According to an alternative embodiment, the catalyst strip is formed on another wafer, and the resulting carbon nanotubes 30 are grown on another wafer. After growth, the carbon nanotubes 30 are transferred onto the dielectric layer 26. The carbon nanotubes can also be grown using a solution-based method and then deposited on the wafer surface.

[0029] According to some embodiments, the spacing between adjacent carbon nanotubes 30 is controlled within the range of approximately 2 nm to approximately 20 nm. It should be understood that, although... Figure 2 The carbon nanotubes 30 are shown to be parallel to each other and have a uniform spacing. However, due to variations in the manufacturing process, the carbon nanotubes 30 may have non-parallel portions, and the spacing between adjacent carbon nanotubes 30 may vary, although the general trend of the carbon nanotubes 30 is parallelism. Furthermore, although a monolayer of carbon nanotubes 30 is shown, where each of the carbon nanotubes 30 is above and in contact with the dielectric layer 26, some portions of some carbon nanotubes 30 may be slightly suspended.

[0030] Figure 2The formation and patterning of the etching mask 32 are also illustrated. According to some embodiments, the etching mask 32 comprises photoresist that, after patterning, covers portions of a plurality of carbon nanotubes 30. The edges of the etching mask 32 are oriented parallel to (or perpendicular to) the length direction of the carbon nanotubes 30. Next, the carbon nanotubes 30 are etched using the etching mask 32, thereby removing exposed portions of the carbon nanotubes 30 while retaining portions of the carbon nanotubes 30 directly beneath the etching mask 32. The corresponding process is shown as follows: Figure 17 Process 210 in process flow 200 is shown in the diagram. Then the etch mask 32 is removed, resulting in the structure shown in the diagram. Figure 3 As shown, carbon nanotubes 30 collectively occupy a region. According to some embodiments, this region has a width W1, which can range from about 15 nm to about 35 nm. Therefore, in an exemplary embodiment, about 5 to 15 carbon nanotubes remain. It should be understood that the desired width W1 and desired number of carbon nanotubes are determined by the desired current of the resulting transistor and can differ from those discussed above.

[0031] refer to Figure 4 A dummy gate stack 40 is formed over the dielectric layer 26 and the carbon nanotubes 30. The corresponding process is shown as follows. Figure 17 Process 212 in process flow 200 shown in the diagram. The process for forming the dummy gate stack 40 may include depositing a dummy gate dielectric layer (if formed), depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing a hard mask layer over the dummy gate electrode layer, and etching the deposited layers to form the dummy gate stack 40. The dummy gate stack 40 may include a dummy gate dielectric 34 and a dummy gate electrode 36 located over the respective dummy gate dielectric 34. The dummy gate dielectric 34 may include silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, etc., covering and contacting the carbon nanotube 30. According to an alternative embodiment, the formation of the gate dielectric is skipped, and the subsequently formed dummy gate electrode 36 is formed directly on the carbon nanotube 30. According to some embodiments, the gate dielectric 34 may be formed of a material different from the material of the dielectric layer 26 so that in a subsequent etching process, the etching of the gate dielectric stops on the dielectric layer 26. According to an alternative embodiment, the gate dielectric layer 34 may be formed of the same material as the dielectric layer 26 so that both the gate dielectric layer 34 and the dielectric layer 26 are etched in the same etching process in a subsequent etching process. For example, polysilicon may be used to form the dummy gate electrode 36, and other materials such as amorphous carbon may also be used. The dummy gate stack 40 may also include one or more hard mask layers 38 located above the dummy gate electrode 36. The hard mask layer 38 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or multiple layers thereof.

[0032] The dummy gate stack 40 spans over the plurality of carbon nanotubes 30 and has a length direction perpendicular to the length direction of the carbon nanotubes 30. It should be understood that although one dummy gate stack 40 is shown, multiple parallel dummy gate stacks may be formed, which are parallel to each other and span over the same set of carbon nanotubes 30.

[0033] Next, gate spacers 42 are formed on the sidewalls of the dummy gate stack 40. The corresponding process is shown as follows. Figure 17 Process 214 in process flow 200 is shown in the diagram. According to some embodiments of this disclosure, the gate spacer 42 is formed of a dielectric material, such as silicon nitride (e.g., Si3N4), silicon oxynitride, silicon carbonitride, silicon carbonitride, etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers. Forming the gate spacer 42 may include depositing one or more spacer layers and performing an anisotropic etching process on the spacer layers to remove the horizontal portions of the spacer layers, while leaving the vertical portions of the spacer layers as the gate spacer 42.

[0034] Figure 4 The formation of the contact etch stop layer (CESL) 44 and the interlayer dielectric (ILD) 46 is also shown. The corresponding process is illustrated as follows. Figure 17 Process 216 in process flow 200 shown in the diagram. CESL44 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 46 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition processes. ILD 46 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based dielectric material such as silicon oxide (e.g., formed using tetraethyl orthosilicate (TEOS) as a process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process such as chemical mechanical polishing (CMP) or mechanical polishing can be performed to make the top surfaces of ILD 46, dummy gate stack 40, and gate spacer 42 flush with each other.

[0035] Figure 5 , Figure 6 , Figure 7A , Figure 8A and Figures 9-10 This illustrates the removal of the dummy gate stack 40 and the formation of the replacement gate stack 62. Figure 10 ). Figure 5 Showing with Figure 4 Same structure, but Figure 5 Showing from and Figure 4 Views taken from different angles. Furthermore, the ends of the dummy gate stack 40 and corresponding portions of the gate spacer 42 are shown.

[0036] Then the dummy gate stack 40, including the hard mask layer 38, the dummy gate electrode 36, and the dummy gate dielectric 34, is removed. Figure 6 The obtained structure is shown in the figure. The corresponding process is shown as follows. Figure 17 Process 218 in process flow 200 is shown in the diagram. This forms trench 50. Depending on the materials of mask layer 38, dummy gate electrode 36, and dummy gate dielectric 34, the removal process can be performed by one or more etching processes. Etching can include wet and / or dry etching processes. As a result of removing the dummy gate stack 40, carbon nanotubes 30 are exposed. According to some embodiments, etching stops at the top surface of dielectric layer 26. It should be understood that carbon nanotubes 30 may include portions exposed in trench 50 and other portions located below gate spacers 42, CESL 44, and ILD 46. The ends of carbon nanotubes 30 are... Figure 6 As shown in the image.

[0037] Next, refer to Figure 7A An etching process is performed to etch the dielectric layer 26. The corresponding process is shown as follows. Figure 17 Process 220 is shown in the process flow 200. Etching passes through dielectric layer 26, and the etching process stops at etch stop layer 24. Etching can be performed using an isotropic etching process, which can be a wet etching process or a dry etching process. By employing an isotropic etching process, the portion of dielectric layer 26 directly below carbon nanotubes 30 is also etched. Etching can also be anisotropic etching with a slight isotropic etching effect. As a result of etching dielectric layer 26, carbon nanotubes 30 are suspended, with the portion of carbon nanotubes located below gate spacers 42 and CESL 44 serving as support for the suspended portion. The suspended portions of carbon nanotubes 30 are separated from each other by air gaps. According to some embodiments in which dielectric layer 26 is formed of or includes silicon oxide, when dry etching is performed, the etching gas can include CF4, SF6, etc. When wet etching is used, the etching chemicals can include HF, NH4F, etc.

[0038] Figures 7B to 7F Illustrations based on some embodiments Figure 7A Reference sections 7B-7B are shown in these figures. The dashed lines in these figures extend downwards from the inner edge of the gate spacer 42. Figure 7B The outline of trench 50 according to some embodiments of the present disclosure is shown. This outline is the result of an anisotropic etching process for etching dielectric layer 26. Due to shading and pattern loading effects, when plasma is generated in the anisotropic etching process, the middle portion of dielectric layer 26 near the opposing gate dielectric 34 is etched faster than the portion near gate spacer 42, thus forming curved sidewalls. According to some embodiments, trench 50 does not extend directly below gate spacer 42. Due to Figure 7BThe outline shown is used to form the subsequent replacement gate stack 62. Figure 10 The alternative gate stack 62 has a bottom portion extending below the bottom surface of the gate spacer 42 and is confined in the region between the opposing gate spacers 42. Figure 10 The bottom surface will also have a planar portion that connects to the curved (rounded) sidewalls.

[0039] Figure 7C The outline of trench 50 according to an alternative embodiment of the present disclosure is shown. This outline can be the result of an isotropic etching process according to some embodiments, wherein the dielectric layer 26 is etched vertically and horizontally. The outline can also be formed by an anisotropic etching process followed by an extended over-etching process, wherein the bottom portion of trench 50 is laterally extended due to the over-etching process. The bottom portion of trench 50 in dielectric layer 26 extends directly below gate spacer 42, and the edge of the bottom portion of trench 50 can be aligned with the outer edge of gate spacer 42. Since... Figure 7C The outline shown is used to form the subsequent replacement gate stack 62. Figure 10 The trench 50 has a bottom portion extending below the bottom surface of the gate spacer 42, and this bottom portion includes a portion located directly below the gate spacer 42. The outer edge of the trench 50 may also be vertically aligned with the outer edge of the gate spacer 42. The resulting alternative gate stack 62 ( Figure 10 The bottom surface will also have a planar portion that connects to the curved (rounded) sidewalls.

[0040] Figure 7D The outline of trench 50 according to an alternative embodiment of the present disclosure is shown. This outline is the result of an anisotropic etching process. As a result of the anisotropic etching process, the edge of the dielectric layer 26 facing the bottom portion of trench 50 is straight and vertical, and aligned with the inner edge of the gate spacer 42. Due to Figure 7D The outline shown is used for the subsequent formation of the alternative gate stack 62. Figure 10 The bottom portion of the gate stack 62 has a vertical edge in the dielectric layer 26. The bottom portion of the alternative gate stack 62 is also confined in the region between the gate spacers 42 and does not extend directly below the gate spacers 42.

[0041] Figure 7EThe outline of trench 50 according to an alternative embodiment of the present disclosure is shown. This outline can be the result of an isotropic etching process according to some embodiments, wherein the dielectric layer 26 is etched vertically and horizontally. The outline can also be formed by an anisotropic etching process followed by an extended over-etching process, wherein the bottom portion of trench 50 is laterally extended due to the over-etching process. The bottom portion of trench 50 in dielectric layer 26 extends directly below gate spacer 42, and the edge of the bottom portion of trench 50 may fall between the inner and outer edges of gate spacer 42. Since... Figure 7E The outline shown is used to form the subsequent replacement gate stack 62. Figure 10 The alternative gate stack 62 has a bottom portion extending below the bottom surface of the gate spacer 42, and this bottom portion includes a portion located directly below the gate spacer 42. The bottom surface of the alternative gate stack 62 will also have a planar portion connected to the curved (rounded) sidewalls.

[0042] Figure 7F The outline of trench 50 according to an alternative embodiment of this disclosure is shown. This outline may be the result of an isotropic etching process according to some embodiments, wherein dielectric layer 26 is etched vertically and horizontally. The bottom portion of trench 50 in dielectric layer 26 extends laterally beyond the outer edge of gate spacer 42 and is vertically aligned with CESL 44 or even ILD 46. Because... Figure 7F The outline shown is used to form the subsequent replacement gate stack 62. Figure 10 The alternative gate stack 62 has a bottom portion extending below the bottom surface of the gate spacer 42, and this bottom portion includes a portion located directly below the gate spacer 42. Figure 10 It can extend beyond the outer edge of the gate spacer 42 and can extend directly below CESL44 and ILD 46. The bottom surface of the alternative gate stack 62 will also have a planar portion connected to the curved (rounded) sidewalls.

[0043] Figure 8A A perspective view is shown of the formation of the gate dielectric 58, which includes the interface layer 54. The corresponding process is shown as follows. Figure 17 Process 222 is shown in process flow 200. According to some embodiments, the interface layer 54 is formed of or includes the aforementioned materials such as silicon oxide and aluminum oxide. The interface layer 54 may have a thickness in the range of about 0.5 nm to about 1.5 nm. The deposition process may include ALD, CVD, nano-atomization, etc., such that the interface layer 54 is conformal and may extend on exposed surfaces, including the top surface, sidewalls, and exposed bottom surface of the carbon nanotubes 30 and gate spacers 42. The interface layer 54 also extends on the top surfaces of CESL 44 and ILD 46.

[0044] According to some embodiments, the gate dielectric 58 further includes a high-k dielectric layer 56 on the interface layer 54. According to some embodiments, the high-k dielectric layer 56 is formed of or includes aluminum oxide (Al₂O₃), hafnium oxide, zirconium oxide, lanthanum oxide, silicon nitride, or composite layers thereof. Some dielectric materials can induce electrons or holes in the carbon nanotubes 30 and can further improve n-type or p-type conductivity. For example, carbon nanotubes are often p-type when formed without doping, while a hafnium-containing film can provide electrons to the carbon nanotubes, which is beneficial for n-type conductivity. Therefore, a hafnium film can be used to form the interface layer of an n-type transistor, while aluminum oxide can be used to form the interface layer of a p-type transistor. The high-k dielectric layer 56 can have a thickness in the range of about 1 nm to about 5 nm. The deposition process can include ALD, CVD, etc., so that the high-k dielectric layer 56 is conformal.

[0045] Figure 8B and Figure 8C Show Figure 8A Reference section 8B-8B. Figure 8B Each carbon nanotube 30 is surrounded by an interface layer 54, and the interface layers 54 on different carbon nanotubes 30 are separated by high-k dielectric layers 56. The high-k dielectric layers 56 surround each of the carbon nanotubes 30 and the corresponding portion of the discrete interface layers 54.

[0046] exist Figure 8C In this configuration, each carbon nanotube 30 is surrounded by an interface layer 54, and the interface layers 54 on different carbon nanotubes 30 are bonded together to form a continuous interface layer. A high-k dielectric layer 56 surrounds the combined region comprising the carbon nanotubes 30 and the interface layer 54. The high-k dielectric layer 56 does not separate the interface layers 54 on different carbon nanotubes 30 from each other.

[0047] refer to Figure 9 Multiple stacked conductive layers 60A are formed to extend into the trench 50. Figure 8A The corresponding process is shown in the diagram. Figure 17Process 224 in process flow 200 is shown in the diagram. According to some embodiments, the layers in the stacked conductive layer 60A are not shown individually, but the stacked conductive layers can be distinguished from each other. The deposition of the stacked conductive layer 60A can be performed using conformal deposition methods such as ALD or CVD. The stacked conductive layer 60A may include a diffusion barrier layer (sometimes also called a binder layer) and one (or more) work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work function layers determine the work function of the gate and include at least one layer or multiple layers formed of different materials. The material of the work function layer is selected depending on whether the corresponding transistor is an n-type transistor or a p-type transistor. For example, when the transistor is an n-type transistor, the work function layer may include a low work function metal, which may have a work function in the range of about 3 eV to about 4 eV. The low work function metal may include Sc, Y, Er, La, Hf, Al, Ti, etc., or alloys thereof. When the transistor is a p-type transistor, the work function layer may include a high work function metal, which may have a work function in the range of about 5 eV to about 6 eV. The high work function metal may include Pt, Pd, Ni, Au, or alloys thereof. After depositing the work function layer, a capping layer, which may be another TiN layer, may be formed. The capping layer may or may not completely fill the trench 50.

[0048] The deposited conductive layer 60A is formed as a conformal layer extending into the trench and includes a portion above ILD46. Next, if the deposited conductive layer 60A does not completely fill the trench 50, a filler metal material 60B is deposited to fill the remaining trench. The corresponding process is shown as follows. Figure 17 Process 226 in process flow 200 shown in the diagram. The metallic material 60B can be formed from, for example, tungsten or cobalt.

[0049] refer to Figure 10 This involves performing planarization processes such as CMP or mechanical polishing. The corresponding processes are shown as follows: Figure 17 Process 228 in process flow 200 is shown in the diagram. A portion of the gate dielectric layer, the stacked conductive layer, and the metal material above ILD 46 is removed. As a result, gate electrode 60 and gate dielectric 58 are formed. Gate electrode 60 and gate dielectric 58 are collectively referred to as alternative gate stack 62. At this point, the top surfaces of alternative gate stack 62, gate spacer 42, CESL 44, and ILD 46 can be substantially coplanar. (See reference...) Figures 7B to 7F The bottom portion of the alternative gate stack 62 within the dielectric layer 26, as discussed, can have different profiles and different widths (relative to the distance between the gate spacers 42), as determined by... Figures 7B to 7F The outline of the opening 50 shown is defined.

[0050] refer to Figure 11 An etching process is performed to etch CESL 44 and ILD 46, thereby forming the source / drain contact opening 64. The corresponding process is shown as follows. Figure 17 Process 230 in process flow 200 is shown in the diagram. This exposes the carbon nanotubes 30. Etching stops at the top surface of the dielectric layer 26. According to some embodiments, such as... Figure 11 As shown, the sidewalls of the gate spacer 42 are exposed. According to an alternative embodiment, the source / drain contact opening 64 is spaced apart from the nearest gate spacer 42 by some unetched portions of CESL 44 and ILD 46.

[0051] Next, refer to Figure 12A A source / drain contact plug 66 is formed in the source / drain contact opening 64. The corresponding process is shown as follows. Figure 17 Process 232 in process flow 200 is shown in the diagram. According to some embodiments, the source / drain contact plug 66 is formed of or includes a conductive material selected from tungsten, cobalt, palladium (Pd), silver (Ag), nickel (Ni), gold (Au), titanium (Ti), gadolinium (Gd), or alloys thereof. The formation process may include filling the source / drain contact opening 64 with conductive material, followed by a planarization process (such as CMP or mechanical polishing) to remove excess conductive material above the ILD 46. The source / drain contact plug 66 may or may not include a barrier layer, which, if formed, may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Thus, a dual-gate carbon nanotube transistor 68 is formed.

[0052] In the processes discussed above, the source / drain contact plug 66 is formed after the alternative gate stack 62 is formed. According to an alternative embodiment, the source / drain contact plug 66 is formed before the alternative gate stack 62 is formed, and Figure 11 and Figure 12A The process shown is in Figure 6 , Figure 7A , Figure 8A and Figures 9-10 The process shown is performed beforehand.

[0053] Figure 12A A cross-section cut through one of the carbon nanotubes 30 is also shown. (See figure) Figure 12A As shown, the gate electrode 60 includes an upper portion overlapping the carbon nanotube 30 and a lower portion overlapping the carbon nanotube 30. In addition to the portion surrounding the carbon nanotube 30, the gate dielectric 58 also has a first portion deposited on the sidewalls of the dielectric layer 26 and the gate spacer 42, and a second portion deposited on the top surface of the etch stop layer 24. Figure 12B Show Figure 12A Reference section 12B-12B.

[0054] Figure 13 A perspective view of a nanotube transistor 68 sharing a common gate stack 62 is shown. The internal structure of one of the gate stacks 62 is also shown. Figure 13 As shown, the gate electrode 60 surrounds the combined region comprising the carbon nanotubes 30 and the gate dielectric 58. Because the gate dielectric 58 is farther from most of the carbon nanotubes 30, the portions of the gate electrode 60 on the left and right sides of the combined region provide less channel control over the carbon nanotubes 30. The portions of the gate electrode on the top and bottom sides of the combined region provide effective channel control over the carbon nanotubes 30. Therefore, the transistor 68 is referred to as a dual-gate nanotube transistor, the term "dual-gate" referring to a top gate and a bottom gate. Figure 14 Showing with Figure 13 A similar structure, but with both the gate length and gate width sections exposed, allowing a clear view of the shapes of the components in the gate stack in both cross-sectional views.

[0055] Figure 15 The gate length L is shown. G Simulated subthreshold swing (SS) of various types of transistors as a function of the given information is presented. Lines 80A, 80B, 80C, and 80D show simulation results obtained from a gate-all-around (GAA) nanotube transistor, a dual-gate nanotube transistor, a top-gate nanotube transistor, and a bottom-gate nanotube transistor, respectively. The dual-gate nanotube transistor (line 80B) is a simulation based on embodiments of this disclosure. The results show that the dual-gate nanotube transistor has a desired low subthreshold swing, which is significantly better than that of the top-gate and bottom-gate nanotube transistors and approaches the subthreshold swing of the GAA nanotube transistor. For example, the subthreshold swing of the dual-gate nanotube transistor can be as small as 61 mV / dec, while that of the top-gate nanotube transistor is approximately 70 mV / dec. Moreover, with the gate length L... G The decrease in voltage level results in a very small increase in the subthreshold swing of the dual-gate nanotube transistor, indicating that the dual-gate nanotube transistor has good scaling capability and low short-channel effect. Besides... Figure 15 The results show that the drain-induced barrier reduction (DIBL) of the dual-gate nanotube transistor can be as low as 17 mV / V, while the DIBL of the top-gate nanotube transistor is about 51 mV / V, which also indicates that the short-channel effect of the dual-gate nanotube transistor is much lower than that of the top-gate nanotube transistor.

[0056] Figure 16 This shows the effective drive current I of various types of transistors as a function of the supply voltage VDD. effLines 82A, 82B, and 82C show simulation results obtained from GAA nanotube transistors, dual-gate nanotube transistors, and top-gate nanotube transistors, respectively. The results show that the effective drive current of the dual-gate nanotube transistor is significantly better than that of the top-gate nanotube transistor (especially at low V). DD (at voltage) (approximately 1.8 to 2.5 times), close to the effective drive current of a GAA transistor.

[0057] The embodiments of the present invention have several advantageous features. The dual-gate nanotube transistor exhibits less short-channel effect than top-gate and bottom-gate nanotube transistors, with the short-channel effect approaching that of GAA nanotube transistors. Furthermore, compared to GAA nanotube transistors, the carbon nanotubes in the dual-gate nanotube transistor can be located closer to each other because the dual-gate nanotube transistor does not require space for the gate to separate the carbon nanotubes. Therefore, compared to GAA transistors, the number of carbon nanotubes per unit chip area increases, thus increasing the drive current.

[0058] According to some embodiments of this disclosure, a method includes: depositing a dielectric layer over a substrate; forming carbon nanotubes on the dielectric layer; forming a dummy gate stack on the carbon nanotubes; forming gate spacers on the opposite side of the dummy gate stack; removing the dummy gate stack to form a trench between the gate spacers, wherein the carbon nanotubes are exposed in the trench; etching a portion of the dielectric layer beneath the carbon nanotubes, wherein the carbon nanotubes are suspended; forming an alternative gate dielectric surrounding the carbon nanotubes; and forming a gate electrode surrounding the alternative gate dielectric. In embodiments, forming the alternative gate dielectric includes: depositing an interface layer surrounding the carbon nanotubes, wherein portions of the interface layers surrounding different carbon nanotubes are bonded to form a continuous interface layer; and depositing a high-k dielectric layer surrounding the interface layer. In embodiments, forming the alternative gate dielectric includes: depositing an interface layer surrounding the carbon nanotubes; and depositing a high-k dielectric layer surrounding the interface layer, wherein portions of the interface layers surrounding different carbon nanotubes are physically separated from each other by the high-k dielectric layer. In embodiments, forming the carbon nanotubes includes transferring the carbon nanotubes onto the dielectric layer. In an embodiment, the method further includes: depositing an isolation layer over a substrate; and depositing an etch stop layer over the isolation layer, wherein a dielectric layer is deposited over and contacts the etch stop layer, and wherein etching of a portion of the dielectric layer stops on the etch stop layer. In an embodiment, the method further includes: forming a contact etch stop layer extending on the sidewall of a gate spacer, wherein the contact etch stop layer is also located over and contacts the carbon nanotube; and forming an interlayer dielectric over the contact etch stop layer. In an embodiment, the method further includes: etching through the interlayer dielectric and the contact etch stop layer to form a contact opening, wherein a portion of the carbon nanotube is exposed in the contact opening; and forming a source / drain contact plug in the contact opening. In an embodiment, removing the dummy gate stack to form a trench includes an isotropic etching process. In an embodiment, etching a portion of the dielectric layer beneath the carbon nanotube includes an isotropic etching process.

[0059] According to some embodiments of this disclosure, a semiconductor device includes: a dielectric layer located above a substrate; a plurality of carbon nanotubes located above and in contact with a first and second portion of the dielectric layer; and a gate stack extending between the first and second portions of the dielectric layer, wherein the gate stack includes: a gate dielectric surrounding a portion of the plurality of carbon nanotubes, wherein a portion of the plurality of carbon nanotubes is located between the first and second portions of the dielectric layer; and a gate electrode surrounding a combined region of the plurality of carbon nanotubes and the gate dielectric, wherein the gate electrode includes an upper portion overlapping the combined region and a lower portion overlapping the combined region. In embodiments, the semiconductor device further includes an etch stop layer including a portion located above and in contact with the gate stack, wherein the etch stop layer also extends directly below the first and second portions of the dielectric layer. In embodiments, the substrate is a semiconductor substrate, and the semiconductor device further includes: an isolation layer located below the etch stop layer, wherein the isolation layer also is located above and in contact with the semiconductor substrate. In embodiments, the gate dielectric includes an interface layer surrounding the plurality of carbon nanotubes and a high-k dielectric layer surrounding the interface layer, wherein portions of the interface layer surrounding different carbon nanotubes are physically bonded. In one embodiment, the gate dielectric includes an interface layer surrounding a plurality of carbon nanotubes and a high-k dielectric layer surrounding the interface layer, wherein portions of the interface layer surrounding different carbon nanotubes are physically separated from each other by the high-k dielectric layer. In another embodiment, the semiconductor device further includes a gate spacer located on the opposite side of the top portion of the gate stack, wherein the gate stack also includes a bottom portion extending below the bottom surface of the gate spacer. In another embodiment, the gate stack includes: a flat bottom surface; and curved sidewalls connected to the opposite end of the flat bottom surface.

[0060] According to some embodiments of this disclosure, a semiconductor device includes: a substrate having a top surface; a plurality of carbon nanotubes, substantially parallel and spaced apart from each other, wherein the plurality of carbon nanotubes are substantially aligned with a plane located above and parallel to the top surface of the substrate; a gate stack including a gate dielectric including a first portion directly above the plurality of carbon nanotubes and a second portion directly below the plurality of carbon nanotubes; and a gate electrode including a third portion above the first portion of the gate dielectric and a fourth portion below the second portion of the gate dielectric; and a gate spacer located on a sidewall of the gate stack, wherein the first portion of the gate dielectric and the third portion of the gate electrode extend above the bottom surface of the gate spacer, and the second portion of the gate dielectric and the fourth portion of the gate electrode extend below the bottom surface of the gate spacer. In embodiments, the gate electrode completely surrounds the gate dielectric. In embodiments, the semiconductor device further includes a dielectric layer located below and in contact with the gate spacer, wherein the plurality of carbon nanotubes also extend between the gate spacer and the dielectric layer. In embodiments, the bottom portion of the gate stack extends directly below the gate spacer.

[0061] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: An isolation layer is deposited above the substrate; An etch stop layer is deposited over the isolation layer; A dielectric layer is deposited above the etch stop layer; Carbon nanotubes are formed on the dielectric layer; A pseudo-gate stack is formed on the carbon nanotubes; A gate spacer is formed on the opposite side of the dummy gate stack; The dummy gate stack is removed to form a trench between the gate spacers, wherein the carbon nanotubes are exposed in the trench; Etching a portion of the dielectric layer located beneath the carbon nanotubes, wherein the etching of the portion of the dielectric layer stops at the etch stop layer, wherein the carbon nanotubes are suspended; Forming an alternative gate dielectric surrounding the carbon nanotubes; and A gate electrode is formed around the alternative gate dielectric.

2. The method according to claim 1, wherein, The alternative gate dielectric comprises: An interface layer is deposited surrounding the carbon nanotubes, wherein portions of the interface layer surrounding different carbon nanotubes are bonded to form a continuous interface layer; and A high-k dielectric layer is deposited around the interface layer.

3. The method according to claim 1, wherein, The alternative gate dielectric comprises: An interfacial layer is deposited surrounding the carbon nanotubes; and A high-k dielectric layer is deposited around the interface layer, wherein portions of the interface layer surrounding different carbon nanotubes are physically separated from each other by the high-k dielectric layer.

4. The method according to claim 1, wherein, Forming the carbon nanotubes includes transferring the carbon nanotubes onto the dielectric layer.

5. The method according to claim 1, characterized in that, The thickness of the etch stop layer is in the range of 5 nm to 10 nm.

6. The method according to claim 1, further comprising: A contact etch stop layer is formed extending on the sidewall of the gate spacer, wherein the contact etch stop layer is also located above and in contact with the carbon nanotube; and An interlayer dielectric is formed above the contact etch stop layer.

7. The method according to claim 6, further comprising: Etching is performed through the interlayer dielectric and the contact etch stop layer to form a contact opening, wherein a portion of the carbon nanotube is exposed through the contact opening; and A source / drain contact plug is formed in the contact opening.

8. The method according to claim 1, wherein, Removing the dummy gate stack to form the trench includes an isotropic etching process.

9. The method according to claim 1, wherein, Etching a portion of the dielectric layer beneath the carbon nanotubes involves an isotropic etching process.

10. A semiconductor device, comprising: The dielectric layer is located above the substrate; Multiple carbon nanotubes are located above and in contact with the first and second portions of the dielectric layer; A gate stack extending between a first portion and a second portion of the dielectric layer, wherein the gate stack comprises: A gate dielectric surrounding a portion of the plurality of carbon nanotubes, wherein a portion of the plurality of carbon nanotubes is located between a first portion and a second portion of the dielectric layer; and A gate electrode surrounds a combined region of the plurality of carbon nanotubes and the gate dielectric, wherein the gate electrode includes an upper portion overlapping the combined region and a lower portion overlapping the combined region; An etch stop layer, the etch stop layer including a portion located below and in contact with the gate stack, wherein the etch stop layer also extends directly below the first and second portions of the dielectric layer.

11. The semiconductor device according to claim 10, characterized in that, The diameter of the carbon nanotubes is in the range of 0.5 nm to 2 nm.

12. The semiconductor device according to claim 10, wherein, The substrate is a semiconductor substrate, and the device further includes: An isolation layer is located below the etch stop layer, wherein the isolation layer is also located above the semiconductor substrate and in contact with the semiconductor substrate.

13. The semiconductor device according to claim 10, wherein, The gate dielectric includes an interface layer surrounding the plurality of carbon nanotubes and a high-k dielectric layer surrounding the interface layer, wherein the portion of the interface layer surrounding the different carbon nanotubes is physically bonded.

14. The semiconductor device according to claim 10, wherein, The gate dielectric includes an interface layer surrounding the plurality of carbon nanotubes and a high-k dielectric layer surrounding the interface layer, wherein portions of the interface layer surrounding different carbon nanotubes are physically separated from each other by the high-k dielectric layer.

15. The semiconductor device of claim 10, further comprising: A gate spacer located on the opposite side of the top portion of the gate stack, wherein the gate stack further includes a bottom portion extending below the bottom surface of the gate spacer.

16. The semiconductor device according to claim 10, wherein, The gate stack includes: A flat bottom surface; and The curved sidewalls connect to the opposite end of the flat bottom surface.

17. A semiconductor device, comprising: Substrate, having a top surface; Multiple carbon nanotubes are substantially parallel to each other and spaced apart, wherein the multiple carbon nanotubes are substantially aligned with the same plane, which is located above and parallel to the top surface of the substrate. Gate stack, including: The gate dielectric includes a first portion located directly above the plurality of carbon nanotubes and a second portion located directly below the plurality of carbon nanotubes; and The gate electrode includes a third portion located above a first portion of the gate dielectric and a fourth portion located below a second portion of the gate dielectric; and A gate spacer is located on the sidewall of the gate stack, wherein a first portion of the gate dielectric and a third portion of the gate electrode extend above the bottom surface of the gate spacer, and a second portion of the gate dielectric and a fourth portion of the gate electrode extend below the bottom surface of the gate spacer. A dielectric layer is located below and in contact with the gate spacer, and the gate stack extends between a first portion and a second portion of the dielectric layer. An etch stop layer, the etch stop layer including a portion located below and in contact with the gate stack, wherein the etch stop layer also extends directly below the first portion and the second portion.

18. The semiconductor device according to claim 17, wherein, The gate electrode completely surrounds the gate dielectric.

19. The semiconductor device of claim 17, further comprising the plurality of carbon nanotubes extending between the gate spacer and the dielectric layer.

20. The semiconductor device according to claim 17, wherein, The bottom portion of the gate stack extends directly beneath the gate spacer.

Images