Photonic integrated circuit and optoelectronic system including the same

Abstract

The present disclosure relates to a photonic integrated circuit (1), comprising an InP-based substrate (2) and a dielectric planarization layer (5), wherein the InP-based substrate (2) is provided with a first InP-based optical waveguide (3) and an adjacent second InP-based optical waveguide (4), and the dielectric planarization layer (5) is arranged at least between the first optical waveguide and the second optical waveguide. At least between the first optical waveguide and the adjacent second optical waveguide, the dielectric planarization layer is provided with a groove (6), which is arranged to reduce or prevent optical interaction between the first optical waveguide and the second optical waveguide via the dielectric planarization layer. At the location of the groove, the dielectric planarization layer has a first sidewall (7) arranged obliquely toward the first optical waveguide and a second sidewall (8) arranged obliquely toward the second optical waveguide. The present disclosure also relates to an optoelectronic system (20) comprising the PIC.

Description

Technical Field

[0001] The present disclosure relates to an Indium Phosphide (InP) based Photonic Integrated Circuit (PIC), which may be used, for example but not exclusively, in telecommunication applications or sensor applications. The present disclosure also relates to an optoelectronic system, which may be used, for example but not exclusively, in telecommunication applications or sensor applications, wherein the optoelectronic system comprises the InP based PIC. Background Art

[0002] PICs, for example but not exclusively used in the field of optical telecommunication applications, are becoming increasingly complex as more and more optical and electrical functions are integrated on a single die, which preferably has as small a footprint as possible. The most common PIC technology platform, especially for optical telecommunication applications, uses wafers containing InP-based semiconductor materials. InP-based technology enables monolithic integration of both active components (e.g. light generating optics and / or light absorbing optics) and passive components (e.g. light guiding optics and / or light switching optics) in a single die on one PIC.

[0003] A common problem associated with PICs having a high component density is optical crosstalk or inter-waveguide interference between adjacent optical waveguides. Solutions known in the art for reducing optical crosstalk or inter-waveguide interference result in disadvantages such as those related to intra-waveguide interference caused by optical radiation reflected back to the originating waveguide. Known solutions for eliminating the latter disadvantage introduce other disadvantages, such as those related to environmental protection of the PIC, especially when hermetic packaging of complex PICs is cumbersome and therefore costly.

[0004] Based on the above, there is a need to provide a PIC that is less susceptible to inter-waveguide interference and intra-waveguide interference and allows for an improved performance-to-cost ratio. Summary of the invention

[0005] It is an object of the present disclosure to provide an InP-based PIC, which may be used, for example but not exclusively, in telecommunication applications or sensor applications, preventing or at least reducing the above-mentioned disadvantages and / or other disadvantages associated with complex InP-based PICs known in the art.

[0006] Another object of the present disclosure is to provide an optoelectronic system which may be used, for example but not exclusively, in telecommunication applications or sensor applications comprising a PIC according to the present disclosure.

[0007] Various aspects of the present disclosure are set out in the attached independent claims and dependent claims. The features of the dependent claims can be appropriately combined with the features of the independent claims, not just those explicitly set out in the claims. In addition, all features can be replaced by other technically equivalent features.

[0008] At least one of the above objects is achieved by a photonic integrated circuit PIC, the PIC comprising:

[0009] An indium phosphide (InP) based substrate having a first InP based optical waveguide and an adjacent second InP based optical waveguide;

[0010] A dielectric planarization layer, which is arranged at least between the first optical waveguide and the second optical waveguide, wherein, at least between the first optical waveguide and the second optical waveguide, the dielectric planarization layer is provided with:

[0011] a groove arranged to reduce or prevent optical interaction between the first optical waveguide and the second optical waveguide via the dielectric planarization layer;

[0012] Wherein, at the groove position, the dielectric planarization layer has:

[0013] A first side wall arranged obliquely toward the first optical waveguide; and

[0014] The second side wall is arranged obliquely toward the second optical waveguide.

[0015] By increasing the refractive index difference of the InP-based layers constituting the InP-based optical waveguide of an InP-based PIC, the size of the InP-based optical waveguide can be reduced. This allows to reduce the die area of ​​the PIC, thereby reducing the overall cost of the PIC. In order to exploit the active optical properties of the InP-based optical waveguides, it is necessary to provide them with electrical contacts. In order to be able to accurately and reliably manufacture electrical contacts on top of optical waveguides with small dimensions, a dielectric planarization layer is usually applied. In addition, the dielectric planarization layer can be configured to provide passivation and protection of the optical waveguide, thereby improving the environmental protection of the PIC according to the present disclosure.

[0016] Note that the dielectric planarization layer can capture and propagate optical radiation originating from the optical waveguide. In order to at least reduce and ultimately prevent optical interactions, such as inter-waveguide interference or optical crosstalk, between a first optical waveguide of the PIC and an adjacent second optical waveguide via the dielectric planarization layer, the dielectric planarization layer is provided with grooves at least between the first optical waveguide and the second optical waveguide.

[0017] By providing a slope to the first sidewall and the second sidewall of the dielectric planarization layer, the phase front of the optical radiation captured by the dielectric planarization layer can be tilted, thereby at least reducing and ultimately preventing the optical radiation incident on the first sidewall and the second sidewall from being reflected back to the originating light waveguide, i.e., the first optical waveguide and / or the second optical waveguide, respectively. Therefore, intra-waveguide interference in the first optical waveguide and / or the second optical waveguide can be at least reduced and ultimately prevented, respectively. Therefore, the PIC according to the present disclosure is not susceptible to inter-waveguide interference and intra-waveguide interference.

[0018] Furthermore, providing the dielectric planarization layer with a recess defined by a first sidewall and a second sidewall inclined towards the first optical waveguide and the second optical waveguide, respectively, provides additional advantages, in particular related to the metallization process, mechanical stress reduction and / or mechanical stress redistribution in additional dielectric layers that may be arranged above the dielectric planarization layer, and trapping of residues in corners between, for example, the inclined sidewalls of the dielectric planarization layer and an InP-based substrate.

[0019] With regard to the metallization process, it should be noted that the first and second sidewalls of the dielectric planarization layer being inclined in the above-mentioned direction enable good step coverage of a metal layer arranged to coincide with these inclined sidewalls of the dielectric planarization layer and / or of an additional metal layer arranged to coincide with the sidewalls of an additional dielectric layer, the sidewalls of which are inclined due to the inclined sidewalls of the dielectric planarization layer, which additional dielectric layer is deposited on top of the dielectric planarization layer. The good step coverage provided by the inclined sidewalls of the dielectric planarization layer enables the use of anisotropic metal deposition and metal etching techniques.

[0020] With regard to the additional dielectric layer deposited on top of the dielectric planarization layer, the dielectric planarization layer being provided with a recess defined by the inclined first and second sidewalls of the dielectric planarization layer, it should be noted that by allowing the additional dielectric layer to contact the region of the layer arranged below the dielectric planarization layer at the location of the recess, mechanical stress generation can be reduced and / or mechanical stress can be redistributed in the additional dielectric layer arranged to at least cover the recess. The layer arranged below the dielectric planarization layer can be any suitable dielectric layer or InP-based layer.

[0021] Regarding the capture of residues in, for example, a corner between an inclined sidewall of a dielectric planarization layer and an InP-based substrate, it is noteworthy that the first inclined sidewall and the second inclined sidewall of the dielectric planarization layer result in less residue capture compared to sidewalls arranged at a 90 degree angle relative to the InP-based substrate.

[0022] In summary, the skilled person will appreciate that the dielectric planarization layer of the PIC according to the present disclosure can be understood as a multifunctional layer. The skilled person will appreciate that prevention of inter-waveguide interference and intra-waveguide interference can be achieved by completely removing the dielectric planarization layer after the electrical contacts have been provided for the InP-based optical waveguide. However, in that case, the above-mentioned additional advantages provided by the multifunctional dielectric planarization layer of the PIC according to the present disclosure will not be available.

[0023] Those skilled in the art will appreciate that an InP-based substrate may be provided with any suitable number of InP-based optical waveguides. By providing at least one groove in the dielectric planarization layer between adjacent optical waveguides in the manner described above, inter-waveguide interference and / or intra-waveguide interference between any number of adjacent optical waveguides may be at least reduced and ultimately prevented. Thus, more than one groove may be provided between some or all adjacent optical waveguides, depending on the specific requirements of the PIC.

[0024] In summary, those skilled in the art will appreciate that the InP-based PIC according to the present disclosure avoids or at least reduces at least one of the above-mentioned disadvantages and / or other disadvantages associated with inter-waveguide interference and intra-waveguide interference. In addition, the multifunctional dielectric planarization layer of the PIC according to the present disclosure provides additional technical advantages, such as advantages with respect to environmental protection, metallization process, mechanical stress reduction and / or mechanical stress redistribution in the additional dielectric layer, and capture of residues. Therefore, those skilled in the art will appreciate that the PIC according to the present disclosure provides improved overall performance and improved performance-to-cost ratio.

[0025] In an embodiment of the photonic integrated circuit according to the present disclosure, at the recess position, the first sidewall and the second sidewall of the dielectric planarization layer have an inclination angle with the InP-based substrate of less than 85 degrees.

[0026] In this way, it is possible to reduce and eventually prevent the optical radiation incident on the first inclined sidewall and the second inclined sidewall of the dielectric planarization layer from being reflected back to the originating light emitting waveguide, i.e., the first optical waveguide and / or the second optical waveguide, respectively. Therefore, it is possible to at least reduce and eventually prevent the intra-waveguide interference in the first optical waveguide and / or the second optical waveguide, respectively.

[0027] It should be noted that the reduction in the above-mentioned mechanical stress generation and / or the redistribution of mechanical stress in the additional dielectric layer arranged to at least cover the grooves provided in the dielectric planarization layer can be optimized by tailoring the tilt angle within the above-mentioned range, for example by selecting a tilt angle in the range between 30 degrees and 70 degrees.

[0028] In an embodiment of a photonic integrated circuit according to the present disclosure, the recess is arranged to provide access to an InP-based substrate.

[0029] According to this embodiment of the PIC, the groove is a through hole providing access to a region of the InP-based substrate which, except for this region, is at least partially in contact with the dielectric planarization layer. A person skilled in the art will appreciate that in this case, inter-waveguide interference between a first optical waveguide of the PIC and an adjacent second optical waveguide via the dielectric planarization layer is completely prevented. The inclined first and second sidewalls of the dielectric planarization layer allow reducing and ultimately preventing the above-mentioned intra-waveguide interference.

[0030] With regard to the above-mentioned additional dielectric layer deposited on the dielectric planarization layer, it should be noted that the first additional dielectric layer of the additional dielectric layer is allowed to contact the area of ​​the InP-based substrate at the location of the groove. Therefore, it is possible to reduce the mechanical stress generation and / or redistribute the mechanical stress in the additional dielectric layer arranged to at least cover the groove.

[0031] In an embodiment of the photonic integrated circuit according to the present disclosure, the groove has an elongated shape and is arranged to extend longitudinally between the first InP-based optical waveguide and the second InP-based optical waveguide.

[0032] Those skilled in the art will appreciate that the groove may have any suitable shape as long as it allows at least reduction and ultimately prevention of inter-waveguide interference and intra-waveguide interference associated with a first InP-based optical waveguide and an adjacent second InP-based optical waveguide. The groove may have an elongated shape, such as a trench.

[0033] In an embodiment of the photonic integrated circuit according to the present disclosure, a first sidewall of the dielectric planarization layer is at least partially provided with a first pattern, according to which the first sidewall is at least partially arranged at a first angle relative to the first InP-based optical waveguide, and / or a second sidewall of the dielectric planarization layer is at least partially provided with a second pattern, according to which the second sidewall is at least partially arranged at a second angle relative to the second InP-based optical waveguide, the first angle and the second angle being between 10 degrees and 170 degrees.

[0034] In this way, any intra-waveguide interference occurring in the first InP-based optical waveguide due to optical radiation originating from the first InP-based optical waveguide being reflected back to the first InP-based optical waveguide upon incident on the first sidewall of the dielectric planarization layer can be even further reduced. Similar reasoning holds true for further reducing any intra-waveguide interference occurring in the second InP-based optical waveguide of the PIC according to the present disclosure.

[0035] It should be noted that, according to specific requirements of the PIC, the first angle and the second angle may be the same or different. The same is true for the first pattern and the second pattern, which may be the same or different.

[0036] In an embodiment of the photonic integrated circuit according to the present disclosure, the first pattern and / or the second pattern includes at least one of a sawtooth pattern, a wavy pattern, and a dither pattern.

[0037] Note that the first pattern and the second pattern may both be regular or irregular. It is also possible that the first pattern is regular and the second pattern is irregular, or vice versa. In addition to the aforementioned regular or irregular, when the first pattern and / or the second pattern includes, for example, a sawtooth pattern, the sawtooth pattern may be symmetrical, asymmetrical, or partially symmetrical and partially asymmetrical. The same remarks apply to wavy patterns and flutter patterns.

[0038] In an embodiment of the photonic integrated circuit according to the present disclosure, the photonic integrated circuit further comprises a first dielectric protection layer arranged to cover at least the first sidewall and the second sidewall of the dielectric planarization layer.

[0039] The first dielectric protection layer can provide environmental protection for the PIC from environmental pollutants such as dust particles and moisture. The thickness of the first dielectric protection layer can be between 0.5 μm and 100 μm, preferably between 0.5 μm and 10 μm. Thus, the thickness of the first dielectric protection layer should be sufficient to limit the diffusion of environmental pollutants, thereby achieving environmental protection of the PIC.

[0040] In an exemplary embodiment of a PIC according to the present disclosure, according to the embodiment, a region of an InP-based substrate is accessible via a recess provided in a dielectric planarization layer, and a first dielectric protection layer may be arranged to cover the dielectric planarization layer, a first inclined sidewall and an adjacent second inclined sidewall of the dielectric planarization layer, and the region of the InP-based substrate accessible via the recess. As described above, in this manner, a reduction in mechanical stress generation and / or a redistribution of mechanical stress in the first dielectric protection layer and any possible other dielectric layers deposited on the first dielectric protection layer may be achieved.

[0041] In an embodiment of the photonic integrated circuit according to the present disclosure, the photonic integrated circuit further comprises a metal layer, which is arranged to be in conductive contact with the first InP-based optical waveguide and / or the second InP-based optical waveguide, and / or covers at least a portion of the dielectric planarization layer and / or a portion of the first dielectric protection layer.

[0042] By providing at least one of the first optical waveguide and the second optical waveguide with a metal layer, at least one electrical contact may be provided for at least one of them. In this way, the active optical properties of the optical waveguide may be fully exploited. A person skilled in the art will appreciate that the metal layer in contact with either of the first optical waveguide and the second optical waveguide may be applied before or after providing the dielectric planarization layer with a groove.

[0043] By arranging the metal layer to cover at least a portion of the dielectric planarization layer and / or a portion of the first dielectric protection layer, a metal track with reduced parasitic capacitance can be provided. Those skilled in the art will appreciate that by increasing the thickness of the dielectric planarization layer and / or the thickness of the first dielectric protection layer, the parasitic capacitance associated with the metal track can be further reduced.

[0044] The inclined first sidewall and the inclined second sidewall of the first dielectric protection layer that appear when the first dielectric protection layer is arranged to cover the groove provided in the underlying dielectric planarization layer provide good edge coverage for the metal track. Since the edge coverage of the metal track is improved, the PIC according to the present disclosure is less prone to failure due to interruption of the metal track when the horizontal level changes. Therefore, the reliability of the metal track can be improved, and thus the overall performance of the PIC can be improved.

[0045] In an embodiment of the photonic integrated circuit according to the present disclosure, the first dielectric protection layer includes one of the following: silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and tantalum oxide, or a polymer-based material including one of the following: polyacrylate, polycarbonate, polyimide, polyurethane, polyxylylene, benzocyclobutene and polysiloxane.

[0046] It is worth noting that any of the above-mentioned types of polymer-based materials can be applied to a whole wafer including a plurality of PICs by one of spin coating, dip coating, screen printing, and vapor deposition. Alternatively, the polymer-based material can be applied to a single PIC obtained by dicing the whole wafer by one of dip coating, screen printing, dispense, and vapor deposition. It will be appreciated by those skilled in the art that in the case where the polymer-based material is applied as a liquid phase, after its application, the polymer-based material is cured or cross-linked by heat treatment and / or ultraviolet (UV) treatment in a vacuum or a specific atmosphere containing oxygen (O 2 ), argon (Ar) and nitrogen (N 2 As a result of curing, a toughened or hardened polymer-based material is obtained, which is suitable for providing protection to the PIC from environmental contaminants such as dust particles and moisture.

[0047] Those skilled in the art will appreciate that halogenation of polymer-based materials may be used to adjust the transparency window of the polymer-based material such that the transmission of optical radiation having a wavelength in the range of, for example, 1300 nm to 1600 nm is reduced.

[0048] In addition, those skilled in the art will appreciate that a primer may be required to activate, for example, the surface of the dielectric planarization layer or the surface of the InP-based substrate accessible via the recesses in the dielectric planarization layer, and to improve the adhesion between the first dielectric protection layer and the activated surface of the above-mentioned layer. Obviously, a suitable primer may be selected taking into account the composition of the first dielectric protection layer, the composition of the InP-based substrate, and / or the composition of the dielectric planarization layer.

[0049] In an exemplary embodiment of a PIC according to the present disclosure, the first dielectric protection layer may be a conformal coating or a planarization coating. In this way, sufficient sealing of the PIC may be achieved by the first dielectric protection layer. Furthermore, the first dielectric protection layer may provide improved environmental protection for the PIC according to the present disclosure. Thus, non-hermetic packaging may be relied upon instead of hermetic packaging.

[0050] In an embodiment of the photonic integrated circuit according to the present disclosure, the photonic integrated circuit further comprises a second dielectric protection layer, which is arranged to cover at least a portion of the metal layer and / or a portion of the first dielectric protection layer.

[0051] By applying a second dielectric protection layer, the environmental protection of the PIC can be further improved from environmental contaminants such as dust particles and / or moisture. Thus, non-hermetic packaging can be increasingly relied upon instead of hermetic packaging.

[0052] In an embodiment of the photonic integrated circuit according to the present disclosure, the second dielectric protection layer includes one of the following: silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and tantalum oxide, or a polymer-based material including one of the following: polyacrylate, polycarbonate, polyimide, polyurethane, polydimethylenebenzene, benzocyclobutene and polysiloxane.

[0053] Those skilled in the art will appreciate that the above remarks regarding materials that may be used for the first dielectric cap layer apply mutatis mutandis to materials that may be used for the second dielectric cap layer.

[0054] In an embodiment of the photonic integrated circuit according to the present disclosure, the dielectric planarization layer comprises one of the following: silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and tantalum oxide, or a polymer-based material comprising one of the following: polyacrylate, polycarbonate, polyimide, polyurethane, polydimethylenebenzene, benzocyclobutene and polysiloxane.

[0055] Those skilled in the art will appreciate that the above remarks regarding materials that may be used for the first dielectric cap layer apply mutatis mutandis to materials that may be used for the dielectric planarization layer.

[0056] Note that in the case where the dielectric planarization layer comprises a standard polymer-based material, it will be appreciated by those skilled in the art that the standard polymer-based material can be provided with a groove defined by a sidewall having a positive slope, i.e., the sidewall is tilted in the direction of the nearest optical waveguide by applying a combination of photolithography and etching. First, the sidewalls of the photoresist used to define the groove can have a circular profile. It will be appreciated by those skilled in the art that such a circular profile can be obtained by applying an appropriate combination of exposure conditions and thermal treatment to the photoresist. Another method of providing a photoresist with a sidewall having a circular profile involves the use of a greyscale mask. After the sidewalls of the photoresist have been provided with a suitable circular profile, the photoresist can be dry etched using, for example, reactive ion etching (RIE) or inductively coupled plasma etching (ICP). By carefully selecting and adjusting the process conditions and etching rate, the circular profile of the sidewalls of the photoresist can be converted into a straight inclined profile of the sidewalls of the standard polymer layer.

[0057] Those skilled in the art will appreciate that similar methods may be used to provide a dielectric planarization layer comprising one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and tantalum oxide, and having a sidewall with a straight slope profile.

[0058] However, in the case where the dielectric planarization layer comprises a polymer-based material, it is noted that photodefinable polymer materials that are directly patterned by photolithography and wet development steps may also be used. Those skilled in the art will appreciate that by applying a combination of exposure conditions and thermal treatment to the photodefinable polymer material, sloped sidewalls may again be obtained.

[0059] In an embodiment of the photonic integrated circuit according to the present disclosure, the polymer-based material contains at least one of an organic additive and an inorganic additive.

[0060] By including at least one of said additives, which may be, for example, a filler, a getter or a stabilizer, at least one of the environmental protection, mechanical stability and chemical stability of the polymer-based material, which may be used for at least one of the dielectric planarization layer, the first dielectric protection layer and the second dielectric protection layer, may be enhanced. In particular, the environmental protection provided may be further improved by enhancing its ability to inhibit chemical reactions or by enhancing its hydrophobicity to moisture. The latter may be achieved by applying a thin layer of a halogenated polymer or poly(p-xylylenes) by atomic layer deposition or molecular vapour deposition. Thus, the environmental protection of the PIC against environmental pollutants, such as dust particles and / or moisture, may be improved to a level where a non-hermetic package may be used instead of a hermetic package. This is advantageous for the overall cost of the PIC according to the present disclosure.

[0061] In an embodiment of the photonic integrated circuit according to the present disclosure, the photonic integrated circuit is provided with one of a non-hermetic package and a hermetic package.

[0062] By containing the PIC in a non-hermetic package, the environmental protection of the PIC and thus the service life of the PIC can be improved. Those skilled in the art will appreciate that by containing the PIC in a hermetic package, the environmental protection of the PIC and thus the service life of the PIC can be further improved.

[0063] In an exemplary embodiment of an InP-based PIC according to the present disclosure, the PIC is a monolithic photonic integrated circuit.

[0064] According to another aspect of the present disclosure, there is provided an optoelectronic system comprising a photonic integrated circuit according to the present disclosure. The optoelectronic system may be used, for example but not exclusively, for telecommunication applications. In this case, the optoelectronic system may be one of a transmitter, a receiver, a transceiver, a coherent transmitter, a coherent receiver, and a coherent transceiver. In summary, it is apparent that the cost of the optoelectronic system according to the present disclosure may be reduced because the performance-cost ratio of the PIC according to the present disclosure is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Other features and advantages of the present disclosure will become apparent from the description of exemplary and non-limiting embodiments of InP-based PICs and optoelectronic systems including such PICs according to the present disclosure.

[0066] Those skilled in the art will appreciate that the described embodiments of the PIC and optoelectronic system are merely exemplary in nature and should not be construed as limiting the scope of protection in any way. Those skilled in the art will appreciate that alternative and equivalent embodiments of the PIC and optoelectronic system may be conceived and simplified for practice without departing from the scope of protection of the present disclosure.

[0067] Reference will be made to the figures in the accompanying drawings. These figures are schematic in nature and are not necessarily drawn to scale. Additionally, like reference numerals designate like or similar parts. In the accompanying drawings:

[0068] Figure 1A shows a schematic cross-section of a portion of a first exemplary, non-limiting embodiment of an InP-based PIC according to the present disclosure, wherein a dielectric planarization layer is provided with a recess defined by sloped sidewalls, the recess providing access to a region of an InP-based substrate;

[0069] Figure 1B Shown according to Figure 1A A schematic top view of a portion of a first exemplary, non-limiting embodiment of an InP-based PIC is shown;

[0070] Figure 2 shows a schematic cross-section of a portion of a second exemplary, non-limiting embodiment of an InP-based PIC according to the present disclosure, the InP-based PIC comprising a first dielectric capping layer in contact with an InP-based substrate at a recessed location disposed in a dielectric planarization layer;

[0071] Figure 3A shows a schematic cross-section of a portion of a third exemplary, non-limiting embodiment of an InP-based PIC according to the present disclosure, the InP-based PIC comprising a metal track arranged to contact an electrical contact provided to an optical waveguide and arranged to conform to an inclined sidewall of a first dielectric protection layer deposited over a dielectric planarization layer;

[0072] Figure 3B shows a schematic cross-section of a portion of a fourth exemplary, non-limiting embodiment of an InP-based PIC according to the present disclosure, the InP-based PIC comprising a metal track arranged to contact an electrical contact provided to an optical waveguide and arranged to conform to an inclined sidewall of a first dielectric protection layer deposited over a dielectric planarization layer;

[0073] Figure 3C shows a schematic cross-section of a portion of a fifth exemplary, non-limiting embodiment of an InP-based PIC according to the present disclosure, the InP-based PIC comprising a second dielectric capping layer deposited over a metal track arranged to contact an electrical contact provided to an optical waveguide and arranged to conform to an inclined sidewall of a first dielectric capping layer deposited over a dielectric planarization;

[0074] Figure 4A shows a schematic cross-section of a portion of a sixth exemplary, non-limiting embodiment of an InP-based PIC according to the present disclosure, wherein a dielectric planarization layer is provided with a recess defined by an inclined sidewall provided with a sawtooth pattern, the recess providing access to a region of an InP-based substrate;

[0075] Figure 4B Shown according to Figure 4A A schematic top view of a portion of a sixth exemplary, non-limiting embodiment of an InP-based PIC is shown;

[0076] Figure 4C shows a schematic top view of a portion of a seventh exemplary, non-limiting embodiment of an InP-based PIC according to the present disclosure, wherein a dielectric planarization layer is provided with a recess defined by a sloped sidewall provided with a wavy pattern, the recess providing access to a region of an InP-based substrate;

[0077] Figure 5 shows a schematic cross-section of an eighth exemplary, non-limiting embodiment of an InP-based PIC according to the present disclosure, wherein the PIC is provided with a hermetic package; and

[0078] Figure 6 A schematic diagram of a first exemplary, non-limiting embodiment of an optoelectronic system according to the present disclosure is shown, which may be used, for example but not exclusively, in telecommunication applications or sensor applications, the optoelectronic system comprising an InP-based PIC according to the present disclosure.

[0079] Description of Reference Numerals

[0080] 1 Photonic Integrated Circuit (PIC)

[0081] 2 InP-based substrates

[0082] 3 The first InP-based optical waveguide

[0083] 4 The second InP-based optical waveguide

[0084] 5 Dielectric planarization layer

[0085] 6. Recesses in the dielectric planarization layer

[0086] 7. First sidewall of dielectric planarization layer

[0087] 8 Second sidewall of dielectric planarization layer

[0088] 9. A first pattern provided to a first sidewall of the dielectric planarization layer

[0089] 10 A second pattern is provided to the second sidewall of the dielectric planarization layer

[0090] 11. First dielectric protection layer

[0091] 12 Metal Layer

[0092] 13. Second dielectric protection layer

[0093] 14 Hermetic packaging

[0094] 20 Photoelectric system

[0095] α is the tilt angle of the first sidewall and the second sidewall relative to the InP-based substrate

[0096] β first angle of the first sidewall relative to the first InP-based optical waveguide

[0097] γ The second angle of the second sidewall relative to the second InP-based optical waveguide DETAILED DESCRIPTION

[0098] Note that while the exemplary, non-limiting embodiments of the environmentally protected PIC 1 according to the present disclosure are presented involving a dielectric planarization layer 5, a first dielectric protection layer 11, a metal layer 12, and a second dielectric protection layer 13, a person skilled in the art will be able to envision, without undue burden, embodiments of the PIC 1 falling within the scope of the present disclosure, the embodiments involving more than one of the above layers, the layers comprising one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and tantalum oxide, or a polymer-based material comprising one of polyacrylate, polycarbonate, polyimide, polyurethane, polydimethylenebenzene, benzocyclobutene, and polysiloxane.

[0099] Figure 1A A schematic cross section of a portion of a first exemplary, non-limiting embodiment of an InP-based PIC 1 according to the present disclosure is shown. The PIC 1 comprises an InP-based substrate 2 provided with a first InP-based optical waveguide 3 and an adjacent second InP-based optical waveguide 4. A dielectric planarization layer 5 is provided, which is arranged between the first optical waveguide 3 and the second optical waveguide 4. The dielectric planarization layer 5 is applied to enable accurate and reliable fabrication of a metal layer 12 above each of the first optical waveguide 3 and the second optical waveguide 4. The electrical contacts allow full exploitation of the active optical properties of the first optical waveguide 3 and the second optical waveguide 4. The dielectric planarization layer 5 may also be configured to provide passivation and protection of the optical waveguides 3, 4, thereby improving environmental protection of the PIC 1 according to the present disclosure.

[0100] The dielectric planarization layer 5 can capture and propagate optical radiation originating from any one of the optical waveguides 3, 4. In order to at least reduce and eventually prevent inter-waveguide interference or optical crosstalk between the first optical waveguide 3 and the adjacent second optical waveguide 4 via the dielectric planarization layer 5, the dielectric planarization layer 5 is provided with a groove 6 between the first optical waveguide 3 and the second optical waveguide 4.

[0101] At the location of the groove 6, the dielectric planarization layer 5 has a first sidewall 7 arranged obliquely toward the first optical waveguide 3 and a second sidewall 8 arranged obliquely toward the second optical waveguide 4. The groove 6 provides access to the region of the InP-based substrate 2 defined by the first and second sidewalls.

[0102] By providing a slope to the first sidewall 7 and the second sidewall 8 of the dielectric planarization layer 5, the phase front of the optical radiation captured by the dielectric planarization layer 5 can be tilted, thereby at least reducing and eventually preventing the optical radiation incident on the first sidewall 7 and the second sidewall 8 from being reflected back to the originating light emitting waveguide, i.e., the first optical waveguide 3 and / or the second optical waveguide 4, respectively. Therefore, it is possible to at least reduce and eventually prevent intra-waveguide interference in the first optical waveguide 3 and / or the second optical waveguide 4. Therefore, the PIC 1 according to the present disclosure is not susceptible to inter-waveguide interference and intra-waveguide interference.

[0103] Furthermore, providing the dielectric planarization layer 5 with a recess 6 defined by a first side wall 7 and a second side wall 8 having a positive slope, i.e. inclined towards the first optical waveguide 3 and the second optical waveguide 4, respectively, provides the additional advantages mentioned above, in particular with regard to metallization processes, mechanical stress reduction and / or mechanical stress redistribution in additional dielectric layers that may be arranged above the dielectric planarization layer 5, and residue capture, e.g. in the corners between the inclined side walls 7, 8 of the dielectric planarization layer 5 and the InP-based substrate 2. Therefore, a person skilled in the art will appreciate that the dielectric planarization layer 5 of the PIC 1 according to the present disclosure may be understood as a multifunctional layer.

[0104] In summary, those skilled in the art will understand that Figure 1A The exemplary embodiment of the InP-based PIC 1 shown in FIG. 1 avoids or at least reduces at least one of the above-mentioned disadvantages and / or other disadvantages associated with inter-waveguide interference and intra-waveguide interference. In addition, the multifunctional dielectric planarization layer 5 of the PIC 1 according to the present disclosure provides the above-mentioned additional technical advantages. Therefore, those skilled in the art will appreciate that Figure 1A The exemplary embodiment of the PIC 1 shown in provides improved overall performance and improved performance to cost ratio.

[0105] At the location of the groove 6, the inclination angle α of the first side wall 7 and the second side wall 8 of the dielectric planarization layer 5 relative to the InP-based substrate 2 is less than 85 degrees. In this way, it is possible to reduce and eventually prevent the optical radiation incident on the first inclined side wall 7 and the second inclined side wall 8 of the dielectric planarization layer 5 from being reflected back to the originating light emitting waveguide, i.e., the first optical waveguide 3 and / or the second optical waveguide 4, respectively. Therefore, it is possible to at least reduce and eventually prevent the intra-waveguide interference in the first optical waveguide 3 and / or the second optical waveguide 4, respectively.

[0106] exist Figure 1A In the exemplary embodiment of the PIC 1 shown, the groove 6 is a through hole, thus providing access to the InP-based substrate 2, which is in contact with the dielectric planarization layer 5, between the optical waveguides 3, 4. A person skilled in the art will appreciate that in this case, inter-waveguide interference between the first optical waveguide 3 and the adjacent second optical waveguide 4 of the PIC 1 via the dielectric planarization layer 5 is completely prevented. The inclined first sidewall 7 and second sidewall 8 of the dielectric planarization layer 5 allow the above-mentioned intra-waveguide interference to be reduced and eventually prevented.

[0107] Figure 1B Shows Figure 1A A schematic top view of a portion of a first exemplary, non-limiting embodiment of an InP-based PIC 1 is shown. Figure 1A and Figure 1BIn the exemplary embodiment of the PIC shown, the groove 6 has an elongated shape and is arranged to extend longitudinally between the first InP-based optical waveguide 3 and the second InP-based optical waveguide 4. Those skilled in the art will understand that the groove 6 can have any suitable shape as long as it allows at least reducing and ultimately preventing inter-waveguide interference and intra-waveguide interference associated with the first InP-based optical waveguide 3 and the adjacent second InP-based optical waveguide 4. Figure 1B The recesses 6 shown in FIG. 5 are grooves.

[0108] Figure 2 A schematic cross-section of a portion of a second exemplary, non-limiting embodiment of an InP-based PIC 1 according to the present disclosure is shown, the InP-based PIC 1 comprising a first dielectric protection layer 11 arranged to cover a dielectric planarization layer 5, a first inclined sidewall 7 and an adjacent second inclined sidewall 8 of the dielectric planarization layer 5, and a region of an InP-based substrate 2 accessible via a recess 6.

[0109] The first dielectric protection layer 11 can provide environmental protection for the PIC 1 from environmental pollutants such as dust particles and moisture. The thickness of the first dielectric protection layer 11 can be between 0.5 μm and 100 μm, preferably between 0.5 μm and 10 μm. Thus, the thickness of the first dielectric protection layer 11 should be sufficient to limit the diffusion of environmental pollutants, thereby achieving environmental protection of the PIC 1.

[0110] Figure 3A A schematic cross-section of a portion of a third exemplary, non-limiting embodiment of an InP-based PIC 1 according to the present disclosure is shown, the InP-based PIC 1 comprising a metal track 12 arranged to contact an electrical contact provided to a second optical waveguide 4 and arranged to conform to the inclined sidewalls of a first dielectric protection layer 11 deposited on top of a dielectric planarization layer 5.

[0111] exist Figure 3A In the exemplary embodiment of the PIC 1 shown, the metal layer 12 covers a portion of the first dielectric protection layer 11. In this way, a metal track 12 with reduced parasitic capacitance can be provided. Those skilled in the art will appreciate that by increasing the thickness of the dielectric planarization layer 5 and / or the thickness of the first dielectric protection layer 11, the parasitic capacitance associated with the metal track 12 can be further reduced.

[0112] Figure 3BA schematic cross-section of a portion of a fourth exemplary, non-limiting embodiment of an InP-based PIC 1 according to the present disclosure is shown, the InP-based PIC 1 comprising a metal track 12 arranged to contact the electrical contacts provided to the optical waveguides 3, 4 and arranged to conform to the inclined sidewalls of a first dielectric protection layer 11 deposited on top of the dielectric planarization layer 5.

[0113] The inclined first sidewall and the inclined second sidewall of the first dielectric protection layer 11, which appear due to the first dielectric protection layer 11 covering the groove 6 disposed in the dielectric planarization layer 5 below, provide good edge coverage for the metal track 12. Due to the improved edge coverage of the metal track 12, the PIC 1 according to the present disclosure is less prone to failure due to the interruption of the metal track 12 when the level of the underlying layer (in this case, the dielectric planarization layer 5 and the first dielectric protection layer 11) changes. Therefore, the reliability of the metal track 12 can be improved, and thus the overall performance of the PIC 1 can be improved.

[0114] Figure 3C A schematic cross-section of a portion of a fifth exemplary, non-limiting embodiment of an InP-based PIC 1 according to the present disclosure is shown, the InP-based PIC 1 comprising a second dielectric protection layer 13 deposited over metal tracks 12 arranged to be in contact with electrical contacts provided to the optical waveguides 3, 4 and arranged to conform to the inclined side walls of a first dielectric protection layer 11 deposited over a dielectric planarization layer 5 provided with grooves 6.

[0115] The environmental protection of the PIC 1 from environmental contaminants, such as dust particles and / or moisture, may be further improved by applying a second dielectric protection layer 13. Thus, non-hermetic packaging may be increasingly relied upon instead of hermetic packaging.

[0116] Figure 4A A schematic cross section of a portion of a sixth exemplary, non-limiting embodiment of an InP-based PIC 1 according to the present disclosure is shown, wherein a dielectric planarization layer 5 is provided with a recess 6 defined by inclined side walls 7, 8 provided with a sawtooth pattern 9, 10. The recess 6 provides access to a region of an InP-based substrate 2.

[0117] Figure 4B Shows Figure 4AA schematic top view of a portion of a sixth exemplary, non-limiting embodiment of an InP-based PIC 1 is shown. The first sidewall 7 of the dielectric planarization layer 5 is provided with a regular sawtooth pattern 9, according to which the first sidewall 7 is at least partially arranged at a first angle β relative to the first InP-based optical waveguide 3. The second sidewall 8 of the dielectric planarization layer 5 is also provided with a regular sawtooth pattern 10, according to which the second sidewall 8 is at least partially arranged at a second angle γ relative to the second InP-based optical waveguide 4. The first angle β and the second angle γ may be between 10 degrees and 170 degrees. It should be noted that, depending on the specific requirements of the PIC 1, the first angle β and the second angle γ may be the same or different. In Figure 4B In the exemplary embodiment of the PIC 1 shown, the first angle β and the second angle γ are the same. Similar remarks apply to the first pattern 9 and the second pattern 10, which may be the same or different. Figure 4B In the exemplary embodiment of the PIC 1 shown, the first pattern 9 and the second pattern 10 are identical.

[0118] As described above, the first pattern 9 and the second pattern 10 allow for further reduction of any intra-waveguide interference occurring in the first InP-based optical waveguide 3 due to optical radiation originating from the first InP-based optical waveguide 3 being reflected back to the first InP-based optical waveguide 3 when incident on the first sidewall 7 of the dielectric planarization layer 5. Similar reasoning holds true for further reduction of any intra-waveguide interference occurring in the second InP-based optical waveguide 4 of the PIC 1 according to the present disclosure.

[0119] Figure 4C A schematic top view of a portion of a seventh exemplary, non-limiting embodiment of an InP-based PIC 1 according to the present disclosure is shown, wherein a dielectric planarization layer 5 is provided with a recess 6, which is bounded by inclined sidewalls 7, 8 provided with a wavy pattern 9, 10. The recess 6 provides access to a region of an InP-based substrate 2. Figure 4B Similar remarks as described for the exemplary embodiment of PIC 1 shown are for Figure 4C The same holds true for the exemplary embodiment of PIC 1 shown.

[0120] Figure 5 A schematic cross-section of an eighth exemplary, non-limiting embodiment of an InP-based PIC 1 according to the present disclosure is shown, wherein the PIC 1 is provided with a hermetic package 14. As described above, the hermetic package 14 may improve environmental protection and thereby improve the service life of the PIC 1. Those skilled in the art will appreciate that the PIC 1 may also be provided with a non-hermetic package (not shown). In the latter case, environmental protection and therefore the service life of the PIC 1 may also be improved, but to a lesser extent.

[0121] Figure 6 A schematic diagram of a first exemplary, non-limiting embodiment of an optoelectronic system 20 is shown, which may be used, for example but not exclusively, in telecommunication applications or sensor applications, the optoelectronic system 20 including a PIC 1 according to the present disclosure. The optoelectronic system 20 may be, for example, one of a transmitter, a receiver, a transceiver, a coherent transmitter, a coherent receiver, and a coherent transceiver.

[0122] The present disclosure can be summarized as being related to a photonic integrated circuit 1, which comprises an InP-based substrate 2 provided with a first InP-based optical waveguide 3 and an adjacent second InP-based optical waveguide 4; a dielectric planarization layer 5, which is arranged at least between the first optical waveguide 3 and the second optical waveguide 4. At least between the first optical waveguide 3 and the adjacent second optical waveguide 4, the dielectric planarization layer 5 is provided with a groove 6, which is arranged to reduce or prevent optical interaction between the first optical waveguide 3 and the second optical waveguide 4 via the dielectric planarization layer 5. At the location of the groove 6, the dielectric planarization layer 5 has a first sidewall 7 arranged obliquely towards the first optical waveguide 3 and a second sidewall 8 arranged obliquely towards the second optical waveguide 4. The present disclosure also relates to an optoelectronic system 20 comprising the PIC 1.

[0123] It will be clear to those skilled in the art that the scope of the present disclosure is not limited to the examples discussed above, but that several modifications and variations may be made thereto without departing from the scope of the present disclosure as defined by the following claims. In particular, the specific features of various aspects of the present disclosure may be combined. An aspect of the present disclosure may be further advantageously enhanced by adding features described with respect to another aspect of the present disclosure. Although the present disclosure has been described and described in detail in the drawings and the specification, such description and illustration are considered to be illustrative or exemplary only, and not restrictive.

[0124] The present disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments may be understood and implemented by those skilled in the art in practicing the claimed disclosure by studying the drawings, the description and the appended claims. In the claims, the word "comprising" does not exclude other steps or elements, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope of the present disclosure.

Claims

1. A photonic integrated circuit (1), comprising: An indium phosphide (InP)-based substrate (2), the InP-based substrate (2) being provided with a first InP-based optical waveguide (3) and an adjacent second InP-based optical waveguide (4); A dielectric planarization layer (5), the dielectric planarization layer (5) being arranged at least between the first InP-based optical waveguide (3) and the second InP-based optical waveguide (4), wherein at least between the first InP-based optical waveguide (3) and the second InP-based optical waveguide (4), the dielectric planarization layer (5) is provided with: a groove (6) arranged to reduce or prevent optical interaction between the first InP-based optical waveguide (3) and the second InP-based optical waveguide (4) via the dielectric planarization layer (5), wherein the groove (6) is arranged to provide access to the InP-based substrate (2); Wherein, at the location of the groove (6), the dielectric planarization layer (5) has: a first side wall (7) arranged obliquely toward the first InP-based optical waveguide (3); and A second side wall (8) arranged obliquely toward the second InP-based optical waveguide (4); The photonic integrated circuit (1) further comprises a first dielectric protection layer (11), which is arranged to cover the dielectric planarization layer (5), the first side wall (7) and the second side wall (8) of the dielectric planarization layer (5), and a region of the InP-based substrate (2) accessible via the groove (6).

2. The photonic integrated circuit (1) according to claim 1, wherein: At the location of the groove (6), the inclination angle α between the first side wall (7) and the second side wall (8) of the dielectric planarization layer (5) and the InP-based substrate (2) is less than 85 degrees.

3. The photonic integrated circuit (1) according to claim 1, wherein: The groove (6) has an elongated shape and is arranged to extend longitudinally between the first InP-based optical waveguide (3) and the second InP-based optical waveguide (4).

4. The photonic integrated circuit (1) according to claim 1, wherein: The first side wall (7) of the dielectric planarization layer (5) is at least partially provided with a first pattern (9), according to which the first side wall (7) is at least partially arranged at a first angle β relative to the first InP-based optical waveguide (3); and / or The second side wall (8) of the dielectric planarization layer (5) is at least partially provided with a second pattern (10), according to which the second side wall (8) is at least partially arranged at a second angle γ relative to the second InP-based optical waveguide (4); The first angle and the second angle are between 10 degrees and 170 degrees.

5. The photonic integrated circuit (1) according to claim 4, wherein: The first pattern (9) and / or the second pattern (10) comprises at least one of a sawtooth pattern, a wavy pattern and a dithering pattern.

6. The photonic integrated circuit (1) according to claim 1, further comprising a metal layer (12), the metal layer (12) being arranged as follows: In electrical contact with the first InP-based optical waveguide (3) and / or the second InP-based optical waveguide (4); and / or At least a portion of the dielectric planarization layer and / or a portion of the first dielectric protection layer (11) is covered.

7. The photonic integrated circuit (1) according to claim 1, wherein: The first dielectric protection layer (11) comprises: One of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and tantalum oxide; or A polymer-based material, the polymer-based material comprising one of the following: polyacrylate, polycarbonate, polyimide, polyurethane, polydimethylenebenzene, benzocyclobutene and polysiloxane.

8. The photonic integrated circuit (1) according to claim 6, wherein: The first dielectric protection layer (11) comprises: One of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and tantalum oxide; or The polymer-based material comprises one of the following: polyacrylate, polycarbonate, polyimide, polyurethane, polydimethylenebenzene, benzocyclobutene and polysiloxane.

9. The photonic integrated circuit (1) according to claim 6, further comprising a second dielectric protection layer (13), the second dielectric protection layer (13) being arranged to cover at least a portion of the metal layer (12) and / or a portion of the first dielectric protection layer (11).

10. The photonic integrated circuit (1) according to claim 8, further comprising a second dielectric protection layer (13), the second dielectric protection layer (13) being arranged to cover at least a portion of the metal layer (12) and / or a portion of the first dielectric protection layer (11).

11. The photonic integrated circuit (1) according to claim 9, wherein: The second dielectric protection layer (13) comprises: One of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and tantalum oxide; or A polymer-based material, the polymer-based material comprising one of the following: polyacrylate, polycarbonate, polyimide, polyurethane, polydimethylenebenzene, benzocyclobutene and polysiloxane.

12. The photonic integrated circuit (1) according to claim 1, wherein: The dielectric planarization layer (5) comprises: One of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and tantalum oxide; or A polymer-based material, the polymer-based material comprising one of the following: polyacrylate, polycarbonate, polyimide, polyurethane, polydimethylenebenzene, benzocyclobutene and polysiloxane.

13. The photonic integrated circuit (1) according to claim 7, wherein: The polymer-based material includes at least one of an organic additive and an inorganic additive.

14. The photonic integrated circuit (1) according to claim 10, wherein: The polymer-based material includes at least one of an organic additive and an inorganic additive.

15. The photonic integrated circuit (1) according to claim 12, wherein: The polymer-based material includes at least one of an organic additive and an inorganic additive.

16. The photonic integrated circuit (1) according to claim 1, wherein: The photonic integrated circuit (1) is provided in one of a non-hermetic package and a hermetic package (14).

17. An optoelectronic system (20) comprising a photonic integrated circuit (1) according to claim 1, wherein: The optoelectronic system (20) is one of a transmitter, a receiver, a transceiver, a coherent transmitter, a coherent receiver and a coherent transceiver.

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