Memory devices in memory subsystems and related methods

Abstract

The present disclosure relates to dynamic start voltage programming of all levels of memory devices in a memory sub-system. Control logic in a memory device identifies a set of multiple memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and, as part of the program operation, causes one or more program pulses to be applied to the set of multiple memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to respective program levels in a plurality of program levels. In response to the one or more program pulses being applied, the control logic further performs a program verify operation to verify whether the memory cells in the set of memory cells configured as MLC memory are programmed to the respective program levels in the plurality of program levels.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to dynamic start voltage programming of all levels of memory devices in a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] In one aspect, the present disclosure is directed to a memory device comprising: a memory array comprising a plurality of memory cells configured as multi-level cell (MLC) memory; and control logic operably coupled with the memory array to perform operations comprising: identifying a set of the plurality of memory cells configured as MLC memory to be programmed during a program operation; causing, as part of the program operation, one or more program pulses to be applied to the set of the plurality of memory cells configured as MLC memory to program a memory cell in the set of the memory cells configured as MLC memory to a respective program level of a plurality of program levels, wherein respective magnitudes of the one or more program pulses are based at least in part on a previous program operation; and performing, in response to the one or more program pulses being applied, a program verify operation to verify whether the memory cell in the set of the memory cells configured as MLC memory is programmed to the respective program level of the plurality of program levels.

[0004] In another aspect, the present disclosure is directed to a method comprising: identifying a set of a plurality of memory cells in a memory device configured as multi-level cell (MLC) memory to be programmed during a program operation; causing, as part of the program operation, one or more program pulses to be applied to the set of the plurality of memory cells configured as MLC memory to program a memory cell in the set of the memory cells configured as MLC memory to a respective program level of a plurality of program levels, wherein respective magnitudes of the one or more program pulses are based at least in part on a previous program operation; and performing, in response to the one or more program pulses being applied, a program verify operation to verify whether the memory cell in the set of the memory cells configured as MLC memory is programmed to the respective program level of the plurality of program levels.

[0005] In yet another aspect, the disclosure relates to a method comprising: identifying a word line of a memory array of a memory device to be programmed, the word line comprising a plurality of memory cells; causing one or more programming pulses to be applied to the word line to program a first memory cell of the plurality of memory cells to a first program level and, without performing an intermediate program verify operation, program a second memory cell of the plurality of memory cells to a second program level, wherein respective magnitudes of the one or more programming pulses are based at least in part on a previous program operation; and after programming the first memory cell to the first program level and the second memory cell to the second program level, performing a program verify operation on the first memory cell and the second memory cell. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which:

[0007] Figure 1 An example computing system including a memory sub-system according to some embodiments of the disclosure is described.

[0008] Figure 2 is a block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system according to embodiments.

[0009] Figure 3 is a flowchart of an example method of dynamic start voltage (DSV) programming of all levels of a memory device in a memory sub-system according to some embodiments of the disclosure.

[0010] Figures 4A-4C is a chart illustrating different programming pulse options that can be used for dynamic start voltage (DSV) programming of all levels of a memory device in a memory sub-system according to some embodiments of the disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0012] Aspects of the disclosure are directed to dynamic start voltage (DSV) programming of all levels of a memory device in a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. In conjunction with Figure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system including one or more components, such as a memory device that stores data. The host system can provide data to store at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0013] Memory sub-systems can include high-density non-volatile memory devices in which the retention of data is required when no power is supplied to the memory devices. One example of a non-volatile memory device is a NAND memory device. Other examples of non-volatile memory devices are described below in connection with Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary bits of information and have various logical states related to the number of bits stored. The logical states can be represented by binary values (e.g., “0” and “1” or combinations of such values).

[0014] A memory device can be composed of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. Hereinafter, a block refers to a unit of a memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks can be grouped together to form a plane of a memory device in order to allow concurrent operations on each plane. A memory device can include circuitry to perform concurrent memory page accesses of two or more memory planes. For example, a memory device can include multiple access line driver circuits and power circuits that can be shared by the planes of the memory device to facilitate concurrent accesses of pages including different page types of two or more memory planes. For ease of description, these circuits can be generally referred to as independent plane driver circuits. Depending on the storage architecture employed, data can be stored across memory planes (i.e., in stripes). Thus, one request to read a segment of data (e.g., corresponding to one or more data addresses) can result in read operations performed on two or more of the memory planes of the memory device.

[0015] Some memory devices use certain types of memory cells (e.g., quad-level cell (QLC) memory cells) that store four data bits in each memory cell, which enables more applications to move from traditional hard disk drives to newer memory subsystems (e.g., NAND solid state drives (SSDs)). QLC memory is particularly well-suited for read-intensive workloads, which are common in data center applications where data is typically generated once and then read periodically to perform computations and analytics. As a result, QLC memory is typically viewed as fragile and only used for very light write workloads because endurance and quality of service (QoS) can limit availability in data center applications.

[0016] Certain memory subsystems that implement QLC memory use a standard 16-16 coarse-fine two-pass programming algorithm. Since QLC memory cells store four data bits, there are 16 possible program levels (i.e., 2 4 ) representing the possible values for those four data bits. Programming a word line begins with a coarse programming of all 16 levels in a first pass. The goal of this “coarse” first pass is to program all cells to slightly below their final target program level. During a slower “fine” second pass, the memory cells are programmed to the slightly higher final target program voltage. This two-pass programming minimizes cell-to-cell (C2C) disturbance because when the fine programming pass is performed, each cell and its neighboring cells are at their final target program voltage and only need “minor modifications.” In this standard 16-16 coarse-fine programming, a first pulse corresponding to a first program level is applied to all cells being programmed (e.g., all cells of a word line). Then, a program verify operation is performed to verify that memory cells intended to be programmed to the first program level reach the corresponding target voltage level. Those cells that pass the program verify operation are inhibited, and a second pulse corresponding to a second program level is applied to the remaining cells. Another program verify operation is performed, and this sequence continues with additional pulses and program verify operations until programming is complete. By having each program pulse be accompanied by a program verify operation, accurate programming results can be achieved, but each transition between a program phase and a program verify phase adds latency to the programming process as different voltage pumps are turned on / off, reference voltages are prepared, etc. As a result, the overall programming time associated with performing a program operation on a memory device is relatively long, which adversely impacts performance in a memory subsystem.

[0017] Aspects of the disclosure address the above and other deficiencies by implementing dynamic start voltage (DSV) programming of all levels of memory devices in a memory sub-system. In one embodiment, rather than performing an intermediate program verify operation after each program level is reached, the memory cells of a memory device can be programmed to a plurality of different program levels before a program verify operation is performed. In one embodiment, all program levels (e.g., 16 program levels for QLC memory) are applied before a program verify operation is finally performed. For example, upon identifying a set of memory cells to be programmed (e.g., memory cells associated with one or more word lines of a memory array), the control logic of a memory device can cause a number of program pulses to be applied to the identified set of memory cells to program those memory cells to a plurality of respective program levels (i.e., LI, L2,..., L15). Once all program pulses have been applied, the control logic can perform a program verify operation to verify that the memory cells in the set are programmed to the respective program levels.

[0018] Advantages of this approach include, but are not limited to, performance improvements in a memory sub-system. The total program time is reduced due to fewer transitions between the program phase and the program verify phase being performed. Fewer program verify operations are performed, thus the latency associated with program verify start and resume times is minimized, and the total program time is reduced. Accordingly, the overall quality of service level provided by the memory sub-system is improved.

[0019] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the disclosure is illustrated. The memory sub-system 110 can include media such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such.

[0020] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked consumer device), or the like computing device that includes a memory and a processing device.

[0022] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 One example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0023] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, e.g., to write data to and read data from the memory sub-system 110.

[0024] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access memory components (e.g., memory devices 130). The physical host interface can provide an interface for communicating control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1The memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory device 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0026] Some examples of non-volatile memory devices (e.g., the memory device 130) include “not- and” (NAND) type flash memory and in-place write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can incorporate a stackable cross-grided data access array to store bits based on changes in bulk resistance. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), and five-to-level cells (PLCs), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination of such arrays of memory cells. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to a logical unit of the memory device for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks. In one embodiment, the term “MLC memory” can be used to refer to any type of memory cell that stores more than one bit per cell (e.g., 2 bits, 3 bits, 4 bits, or 5 bits per cell).

[0028] While non-volatile memory components are described, such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memory (e.g., 2D NAND, 3D NAND), the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non- (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0029] The memory sub-system controller 115 (controller 115 for simplicity) can communicate with the memory devices 130 to perform operations, such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0030] The memory sub-system controller 115 can be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0031] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 in Figure 1 While the example memory sub-system 110 in Figure 1 has been illustrated as including the memory sub-system controller 115, in another embodiment of the present disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but instead can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0032] Generally, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to effectuate desired accesses to memory devices 130. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) associated with memory devices 130. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from a host system into command instructions to access memory devices 130, as well as convert responses associated with memory devices 130 into information for host system 120.

[0033] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0034] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory units of memory devices 130. An external controller (e.g., memory system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory sub-system 110 is a managed memory device that includes raw memory devices 130 with control logic on-die (e.g., local media controller 135) and a controller (e.g., memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0035] In one embodiment, the memory sub-system 110 includes a memory interface component 113. The memory interface component 113 is responsible for handling the interaction of the memory sub-system controller 115 with the memory devices (e.g., memory device 130) of the memory sub-system 110. For example, the memory interface component 113 can send memory access commands, such as program commands, read commands, or other commands, to the memory device 130 corresponding to requests received from the host system 120. Additionally, the memory interface component 113 can receive data from the memory device 130, such as data retrieved in response to a read command or an acknowledgement of a successfully executed program command. For example, the memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0036] In one embodiment, the memory device 130 includes a program manager 134 configured to perform corresponding memory access operations in response to receiving memory access commands from the memory interface 113. In some embodiments, the local media controller 135 includes at least a portion of the program manager 134 and is configured to perform the functionality described herein. In some embodiments, the program manager 134 is implemented on the memory device 130 using firmware, hardware components, or a combination of the above. In one embodiment, the program manager 134 receives a request from a requester, such as the memory interface 113, to program data to a memory array of the memory device 130. The memory array can include an array of memory cells formed at intersections of word lines and bit lines. In one embodiment, the memory cells are grouped into blocks, which can be further divided into sub-blocks, with a given word line shared across a number of sub-blocks. In one embodiment, each sub-block corresponds to a separate plane in the memory array. A group of memory cells associated with a word line within a sub-block is referred to as a physical page. In one embodiment, there can be multiple portions of the memory array, such as a first portion in which sub-blocks are configured as SLC memory and a second portion in which sub-blocks are configured as multi-level cell (MLC) memory (i.e., memory cells that can store two or more bits of information per cell). For example, the second portion of the memory array can be configured as QLC memory. Voltage levels of memory cells in QLC memory form a set of 16 program distributions that represent 16 different combinations of four bits stored in each memory cell. Depending on how it is configured, each physical page in a sub-block can include multiple page types. For example, a physical page formed of single-level cells (SLC) has a single page type referred to as a lower logical page (LP). Multi-level cell (MLC) physical page types can include LP and upper logical page (UP), TLC physical page types are LP, UP, and extra logical page (XP), and QLC physical page types are LP, UP, XP, and top logical page (TP). For example, a physical page formed of memory cells of a QLC memory type can have a total of four logical pages, with each logical page can store data different from the data stored in the other logical pages associated with the physical page.

[0037] Depending on the programming scheme used, each logical page of a memory cell can be programmed in a separate programming pass, or multiple logical pages can be programmed together. For example, in a QLC physical page, LP and UP can be programmed in one pass, and XP and TP can be programmed in a second pass. Other programming schemes are possible. In one embodiment, the programming manager 134 may receive, for example, four host data pages to be programmed into the QLC memory. Therefore, in order to program each memory cell with one bit from each of the four pages, the programming manager 134 may program each memory cell to one of 16 possible programming levels (i.e., voltages representing 16 different values ​​for those four bits). Thus, the four host data pages will be represented by 16 different programming distributions. In one embodiment, the programming manager 134 may program memory cells in the QLC portion of the memory array to multiple corresponding programming levels (e.g., 16 programming levels) before performing subsequent programming verification operations. For example, after identifying the set of memory cells to be programmed (e.g., memory cells associated with one or more word lines of a memory array), the programming manager 134 can immediately cause several programming pulses to be applied to the identified set of memory cells to program those memory cells to multiple corresponding programming levels (i.e., L1, L2, ..., L15). Once all programming pulses have been applied, the programming manager 134 can perform a programming verification operation to verify whether the memory cells in the set have been programmed to the corresponding programming level. Further details regarding the operation of the programming manager 134 are described below.

[0038] Figure 2 The first device, in the form of a memory device 130, and the memory subsystem controller 115, in the form of a memory subsystem, are, according to the embodiment, (e.g., Figure 1 A simplified block diagram of communication between a second device and a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular phones, and so on. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0039] Memory device 130 includes an array 250 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., a word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 250 ( Figure 2 (Not shown in the image) can be programmed to one of at least two target data states.

[0040] Row decode circuitry 208 and column decode circuitry 210 are provided to decode address signals. Address signals are received and decoded to access the memory cell array 250. The memory device 130 also includes input / output (I / O) control circuitry 212 to manage the input of commands, addresses and data to the memory device 130 and the output of data and status information from the memory device 130. Address registers 214 are in communication with the I / O control circuitry 212 and the row and column decode circuitry 208, 210 to latch the address signals prior to decoding. Command registers 224 are in communication with the I / O control circuitry 212 and the local media controller 135 to latch incoming commands.

[0041] The controller (e.g., the local media controller 135 internal to the memory device 130) controls access to the memory cell array 250 in response to commands and generates status information for the external memory sub-system controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 250. The local media controller 135 is in communication with the row and column decode circuitry 208, 210 to control the row and column decode circuitry 208, 210 in response to addresses. In one embodiment, the local media controller 134 includes a program manager 134 that can implement dynamic start voltage (DSV) programming at all levels of the memory device 130, as described herein.

[0042] The local media controller 135 is also in communication with a cache register 218. The cache register 218 latches incoming or outgoing data as directed by the local media controller 135 to temporarily store data while the memory cell array 250 is busy writing or reading other data, respectively. During a program operation (e.g., a write operation), data can be transferred from the cache register 218 to a data register 220 for transfer to the memory cell array 250; new data can then be latched from the I / O control circuit 212 in the cache register 218. During a read operation, data can be transferred from the cache register 218 to the I / O control circuit 212 for output to the memory sub-system controller 115; new data can then be transferred from the data register 220 to the cache register 218. The cache register 218 and / or the data register 220 can form a page buffer of the memory device 130 (e.g., can form part thereof). The page buffer can additionally include sensing circuitry Figure 2State register 222 (not shown in FIG. 2B) is used to sense a data state of a memory cell, for example, by sensing a state of a data line connected to the memory cell of memory cell array 250. State register 222 can communicate with I / O control circuitry 212 and local memory controller 135 to latch state information for output to memory sub-system controller 115.

[0043] Memory device 130 receives control signals at the memory sub-system controller 115 from local media controller 135 via control link 232. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can be received via control link 232 depending on the nature of memory device 130. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from memory sub-system controller 115 via a multiplexed input / output (I / O) bus 234 and outputs data to memory sub-system controller 115 via I / O bus 234.

[0044] For example, a command can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then can be written into command register 224. An address can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] of I / O bus 234 and then can be written into address register 214. Data can be received at I / O control circuitry 212 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices of I / O bus 234 and then can be written into cache register 218. Data can then be written into data register 220 for programming memory cell array 250.

[0045] In an embodiment, cache register 218 can be omitted and data can be written directly into data register 220. Data can also be outputted by input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While reference can be made to I / O pins, they can include any electrically conductive node that enables electrical connection to memory device 130 by an external device (e.g., memory sub-system controller 115), such as commonly used electrically conductive pads or electrically conductive bumps.

[0046] Those of skill in the art will appreciate that additional circuitry and signals can be provided and that the circuitry and signals have been simplifiedFigure 2 of memory device 130. It is recognized that the functionality of the various block components described with reference to Figure 2 may not necessarily be separate from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device can be adapted to perform the functionality of more than one block component of Figure 2 . Alternatively, one or more components or component portions of the integrated circuit device can be combined to perform the functionality of a single block component of Figure 2 . Further, although specific I / O pins are described in terms of popular convention for receipt and output of various signals, it is noted that other combinations of I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) can be used in various embodiments.

[0047] Figure 3 is an example method of dynamic start voltage (DSV) programming for all levels of memory devices in a memory sub-system in accordance with some embodiments of the present disclosure. The method 300 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by the program manager 134 of the memory device 130 and the memory sub-system controller 115. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, understanding that the illustrated embodiments are Figure 1 and Figure 2 performed by the program manager 134. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, understanding that the illustrated embodiments are examples, it is to be appreciated that the illustrated process can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

[0048] At operation 305, a set of memory cells is identified. For example, processing logic (e.g., the program manager 134) can receive a request from a requester (e.g., the memory interface 113 of the memory sub-system controller 115) to perform a memory access operation on a memory array (e.g., the memory array 250) of a memory device (e.g., the memory device 130). In one embodiment, the memory access operation comprises a program operation directed to a particular address. In one embodiment, the processing logic can identify a set of memory cells (e.g., a subset of memory cells of the memory array 250, such as those associated with a particular word line or multiple word lines of the memory array 250) based on the address specified in the received request. In one embodiment, the set of memory cells is configured as MLC memory (e.g., any type of memory cell that stores more than one bit per cell, including 2 bits, 3 bits, 4 bits, or more bits per cell).

[0049] At operation 310, programming pulse magnitudes are determined. For example, the processing logic can determine respective magnitudes of one or more programming pulses to be applied to the memory array 250 to program the identified set of memory cells. In one embodiment, the respective magnitudes can correspond to respective program levels (e.g., 16 program levels for QLC memory). In one embodiment, indications of the respective magnitudes are stored in a data structure managed by the control logic. For example, the program manager 134 can maintain a table or other data structure having a plurality of entries, each entry corresponding to a respective program level. Each entry can include an indication of a respective voltage magnitude (Vg) of a programming pulse determined from a previous program operation, the programming pulse to be applied to a gate terminal of a memory cell (e.g., via an associated word line) in order to program that memory cell to a threshold voltage (Vt) level representing the corresponding program level. Thus, the respective voltage magnitudes (Vg) are dynamically determined from the data structure. For example, if a first threshold voltage (Vt_1) represents a first program level (i.e., associated with a particular four-bit value), then an associated entry in the table can include an indication of a first voltage magnitude (Vpgm_1) to be applied. In one embodiment, the program manager 134 performs a calibration routine, which can double as a first program operation. During the calibration routine, the program manager 134 causes programming pulses having respective default voltage magnitudes corresponding to each program level to be applied to the memory cells. During a subsequent program verify operation, the program manager 134 can determine a number of data bytes that pass the program verify operation and compute a corresponding respective threshold voltage associated with the respective default voltage magnitude. If this calibration routine is performed two or more times, then sufficient data (i.e., Vg Vt slope) is obtained to predict threshold voltages for the entire range of voltage magnitudes. Thus, the respective voltage magnitudes (Vpgm) needed to achieve the desired threshold voltages for each program level can be determined and stored in a data structure managed by the control logic.

[0050] At operation 315, programming pulses are applied. For example, as part of a program operation, the processing logic can cause one or more programming pulses to be applied to a set of memory cells configured as MLC memory to program the memory cells in the set to respective program levels. In one embodiment, the program manager 134 can send control signals to one or more drive circuits that drive respective programming pulses on word lines associated with the set of memory cells being programmed. As described above, the respective magnitudes of the one or more programming pulses can correspond to a plurality of respective program levels and can be determined from a data structure managed by the control logic. Depending on the embodiment, the one or more programming pulses applied can include a plurality of programming pulses or a single programming pulse.

[0051] For example, as Figure 4AAs described, the applied programming pulses may comprise multiple programming pulses corresponding to respective programming levels. After a block erase operation, a memory cell may be in an unprogrammed level (L0) and may be programmed from that level to several other programming levels, each representing a different value of the stored data. Thus, there may be a first pulse 402 with a first voltage value corresponding to a first programming level (L1), a second programming pulse 404 with a second voltage value corresponding to a second programming level (L2), and so on, up to a fifteenth programming pulse 406 corresponding to a fifteenth programming level (L15). As described, the applied voltage signal ramps up to a lower voltage (e.g., ground voltage) between each pulse; however, no intermediate programming verification operation is performed between each pulse. In one embodiment, the first pulse 402 is applied to all memory cells in the set of memory cells being programmed (i.e., including those intended to be programmed to L1 and those intended to be programmed to higher programming levels). After the first pulse 402 is applied, those cells intended to be programmed to L1 are suppressed, and the second pulse 404 is applied to the remaining memory cells. This sequence may continue until all memory cells except those intended to be programmed into L15 have been suppressed, and the fifteenth pulse 406 has been applied.

[0052] In another instance, such as Figure 4B As illustrated, the applied programming pulses may comprise a single programming pulse 408 having a value that decreases over time to cover each of the corresponding programming levels. As illustrated, the applied voltage signal begins with a voltage value corresponding to the fifteenth programming level (L15) and, after a certain time period, slopes down to a lower value corresponding to the fourteenth programming level (L14). This sequence may continue until a voltage value corresponding to the first programming level (L1) is reached. The applied voltage signal does not slope down to a lower voltage (e.g., ground voltage) before rising back to a value corresponding to the next programming level. In one embodiment, during a first time period, all memory cells except those intended to be programmed to L15 are suppressed, such that the voltage value corresponding to L15 is applied only to those cells intended to be programmed to L15. During a second time period, all memory cells except those intended to be programmed to L15 and L14 are suppressed, such that the voltage value corresponding to L14 is applied only to those cells intended to be programmed to L15 and L14. However, since the voltage value corresponding to L14 is lower than the voltage value corresponding to L15, only those memory cells intended to be programmed to L14 are programmed (while memory cells intended to be programmed to L15 remain programmed according to the higher voltage value corresponding to L15). This sequence may continue until the voltage value corresponding to the first programming level (L1) is applied to all memory cells.

[0053] In yet another example, as explained in Figure 4C As explained in there can be a first pulse 410 that starts at a voltage magnitude corresponding to the fifteenth program level (L15) and after a certain time period, ramps down to a lower magnitude corresponding to the fourteenth program level (L14). This sequence can continue until a voltage magnitude corresponding to the eleventh program level (Ll l) is reached. At that time, the applied voltage signal ramps down to a lower voltage (e.g., a ground voltage), however, no intermediate program verify operation is performed. Subsequently, there can be a second pulse 412 that starts at a voltage magnitude corresponding to the tenth program level (L10) and after a certain time period, ramps down to a lower magnitude corresponding to the ninth program level (L9). This sequence can continue until a voltage magnitude corresponding to the sixth program level (L6) is reached. At that time, the applied voltage signal ramps down to a lower voltage (e.g., a ground voltage), however, no intermediate program verify operation is performed. Subsequently, there can be a third pulse 414 that starts at a voltage magnitude corresponding to the fifth program level (L5) and after a certain time period, ramps down to a lower magnitude corresponding to the fourth program level (L4). This sequence can continue until a voltage magnitude corresponding to the first program level (LI) is reached. Thus, as explained, each of the plurality of pulses covers a respective subset of the respective program levels (e.g., 5 program levels). In other embodiments, there can be some other number of pulses and / or each pulse can cover some other number of program levels.

[0054] Referring again to Figure 3 At operation 320, a program verify operation is performed. For example, in response to the one or more program pulses being applied, the processing logic can perform a program verify operation to verify whether the memory cells in the set are programmed to the respective program levels. During the program verify phase, the program manager 134 causes a read voltage to be applied to the programmed memory cells (e.g., the corresponding word line) to read the charge level stored at the programmed memory cells to confirm that the desired value is properly programmed (i.e., reaches the target threshold voltage). In one embodiment, the program verify operation is performed only after the respective memory cells have been programmed to two or more different program levels (e.g., a first memory cell is programmed to a first program level and a second memory cell is programmed to a second program level). In another embodiment, the program verify operation is performed only after the respective memory cells have been programmed to all of the different program levels (e.g., 16 program levels for QLC memory).

[0055] At operation 325, the memory cells are classified. For example, processing logic can associate the memory cells in the set with respective classes based on the application of the first one or more program pulses and the subsequently performed program verify operations. In one embodiment, this includes the application of the program pulses at operation 315 and the application of the program verify operations at operation 320 can be part of a first pass or a second pass of a multi-pass program operation. Due to physical inconsistencies between individual memory cells, each memory cell can react differently to the application of the program pulses. For example, in response to the application of the same magnitude of program pulse, certain cells can store more charge (i.e., closer to the respective target threshold voltage) while other cells store less charge (i.e., further from the respective target threshold voltage). This difference between the actual voltage level and the target threshold voltage level can be determined during the program verify operations, and the program manager 134 can classify the memory cells based on the difference. In one embodiment, the program manager 134 can associate each memory cell with a first class (e.g., indicating that the memory cell was programmed to a lower voltage relative to the respective target voltage) or a second class (e.g., indicating that the memory cell was programmed to a higher voltage relative to the respective target voltage). In other embodiments, there can be any other number of three or more classes that can be associated with the memory cells.

[0056] At operation 330, additional program pulses are applied. For example, processing logic can cause one or more second program pulses to be applied to the memory cells in the set. In one embodiment, the one or more second program pulses can be part of the same pass (i.e., first pass or second pass) as the one or more first program pulses applied at operation 315, can have respective magnitudes based on the respective class determined at operation 325. For example, if the program manager 134 determines that a given memory cell is associated with a first class (e.g., indicating that the memory cell was programmed to a lower voltage relative to the respective target voltage), the program manager 134 can cause a program pulse having a higher magnitude to be applied during the second pass of the multi-pass program operation. Similarly, if the program manager 134 determines that a given memory cell is associated with a second class (e.g., indicating that the memory cell was programmed to a higher voltage relative to the respective target voltage), the program manager 134 can cause a program pulse having a lower magnitude to be applied during the second pass of the multi-pass program operation. In one embodiment, the magnitude of the second program pulse applied to a given cell is proportional to the difference between the voltage to which the cell is programmed and the respective target voltage of the cell. In other embodiments, the magnitude of the second program pulse applied to a given cell can have some other relationship to the difference between the voltage to which the cell is programmed and the respective target voltage of the cell.

[0057] Figure 5An example machine of computer system 500 is illustrated and described with reference to FIG. 5. Computer system 500 can be a special purpose or general purpose machine that has the capacity to execute a set of instructions that are used to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, computer system 500 corresponds to a host system (e.g., host system 120) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110) or can be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to programming manager 134 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment. Figure 1 Figure 1 The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein. Figure 1

[0058] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0059] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0060] ​​Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 to perform the operations and steps discussed herein. Computer system 500 may additionally include a network interface device 508 for communication on network 520.

[0061] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) storing one or more instruction sets 526 or software embodying any or more of the methods or functions described herein. Instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0062] In one embodiment, instruction 526 includes instructions for implementing the corresponding Figure 1 The programming manager 114 provides functional instructions. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods disclosed herein. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0063] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In this context, and for purposes of

[0064] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0065] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0066] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0067] The disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0068] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A memory device comprising: a memory array comprising a plurality of memory cells configured as multi-level cell (MLC) memory; and control logic operably coupled with the memory array to perform operations comprising: identifying a set of the plurality of memory cells configured as MLC memory to be programmed during a program operation; determining respective magnitudes of a plurality of program pulses corresponding to respective program levels of a plurality of program levels, wherein an indication of the respective magnitudes is stored in a data structure managed by the control logic, and wherein the respective magnitudes of the plurality of program pulses are based at least in part on a previous program operation; causing, as part of the program operation and without performing an intermediate program verify operation, the plurality of program pulses to be applied to at least a portion of the set of the plurality of memory cells configured as MLC memory to program memory cells in the set of the plurality of memory cells configured as MLC memory to the respective program levels of the plurality of program levels, wherein the plurality of program pulses each have a respective magnitude that decreases over time to cover a respective subset of the respective program levels of the plurality of program levels, and wherein each successive program pulse has an initial magnitude that is lower than a final magnitude of a previous program pulse; and in response to the plurality of program pulses being applied, performing a program verify operation to verify whether the memory cells in the set of the plurality of memory cells configured as MLC memory are programmed to the respective program levels of the plurality of program levels.

2. The memory device of claim 1, wherein the plurality of program pulses are applied to program a first memory cell of the set of the plurality of memory cells configured as MLC memory to a first program level of the plurality of program levels and to program a second memory cell of the set of the plurality of memory cells configured as MLC memory to a second program level of the plurality of program levels.

3. The memory device of claim 1, wherein the program verify operation is not performed until all of the plurality of program pulses have been applied to program the memory cells in the set of the plurality of memory cells configured as MLC memory to the respective program levels of the plurality of program levels.

4. The memory device of claim 1, wherein the plurality of program pulses correspond to the respective program levels of the plurality of program levels.

5. The memory device of claim 1, wherein the control logic further performs operations comprising: associating the memory cells in the set of the plurality of memory cells configured as MLC memory with a respective plurality of categories based on the plurality of program pulses and the application of the program verify operation; and causing one or more second program pulses to be applied to the memory cells in the set of the plurality of memory cells configured as MLC memory, the one or more second program pulses having respective magnitudes based on the respective plurality of categories.

6. A method for a memory device, the method comprising: identifying a set of multiple memory cells in a memory device configured as multi-level cell (MLC) memory that are to be programmed during a programming operation; determining respective magnitudes of a plurality of program pulses corresponding to respective program levels of a plurality of program levels, wherein an indication of the respective magnitudes is stored in a data structure managed by control logic, and wherein the respective magnitudes of the plurality of program pulses are based at least in part on a previous programming operation; causing, as part of the programming operation and without performing an intermediate program verify operation, the plurality of program pulses to be applied to at least a portion of the set of multiple memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to the respective program levels of the plurality of program levels, wherein the plurality of program pulses each have respective magnitudes that decrease over time to cover respective subsets of the respective program levels of the plurality of program levels, and wherein each successive program pulse has an initial magnitude that is lower than a final magnitude of a previous program pulse; and in response to the plurality of program pulses being applied, performing a program verify operation to verify whether the memory cells in the set of memory cells configured as MLC memory are programmed to the respective program levels of the plurality of program levels.

7. The method of claim 6, wherein the plurality of program pulses are applied to program a first memory cell of the set of multiple memory cells configured as MLC memory to a first program level of the plurality of program levels and to program a second memory cell of the set of multiple memory cells configured as MLC memory to a second program level of the plurality of program levels.

8. The method of claim 6, wherein the program verify operation is not performed until after all of the plurality of program pulses have been applied to program the memory cells in the set of memory cells configured as MLC memory to the respective program levels of the plurality of program levels.

9. The method of claim 6, wherein the plurality of program pulses correspond to the respective program levels of the plurality of program levels.

10. The method of claim 6, further comprising: based on the plurality of program pulses and the application of the program verify operation, associating the memory cells in the set of memory cells configured as MLC memory with a respective plurality of categories; and causing one or more second program pulses to be applied to the memory cells in the set of memory cells configured as MLC memory, the one or more second program pulses having respective magnitudes based on the respective plurality of categories.

11. A method for a memory device, the method comprising: identifying a word line of a memory array of the memory device that is to be programmed, the word line comprising multiple memory cells; determining respective magnitudes of a plurality of program pulses corresponding to a first program level and a second program level, wherein an indication of the respective magnitudes is stored in a data structure associated with the memory device, and wherein the respective magnitudes of the plurality of program pulses are based at least in part on a previous program operation; causing the plurality of program pulses to be applied to the word line to program a first memory cell of the plurality of memory cells to the first program level and, without performing an intermediate program verify operation, to program a second memory cell of the plurality of memory cells to the second program level, wherein the plurality of program pulses each have a respective magnitude that decreases over time to cover a respective subset of the respective program levels of the plurality of program levels, and wherein each successive program pulse has an initial magnitude that is lower than a final magnitude of a previous program pulse; and after programming the first memory cell to the first program level and the second memory cell to the second program level, performing a program verify operation on the first memory cell and the second memory cell.

12. The method of claim 11, wherein the plurality of program pulses includes a first program pulse corresponding to the first program level and a second program pulse corresponding to the second program level.

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