Active component substrate and manufacturing method thereof

Abstract

The present invention discloses an active component substrate and a manufacturing method thereof, wherein the active component substrate comprises a substrate, a first semiconductor component and a second semiconductor component. The first semiconductor component and the second semiconductor component are arranged on the substrate. The first semiconductor component comprises a first gate, a first semiconductor layer, a first source and a first drain. A gate dielectric structure is sandwiched between the first gate and the first semiconductor layer. The gate dielectric structure comprises a stack of a portion of the gate dielectric layer and a portion of a ferroelectric material layer. The second semiconductor component is electrically connected to the first semiconductor component and comprises a second gate, a second semiconductor layer, a second source and a second drain. Another portion of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer.

Description

Technical Field

[0001] The invention relates to an active component substrate and a manufacturing method thereof. Background Art

[0002] Since thin-film transistors containing metal oxide semiconductors are easily affected by oxygen, hydrogen and water in the environment, they are prone to performance degradation after long-term use, affecting the electrical properties of the thin-film transistors. For example, in a display device including a thin-film transistor array, if the metal oxide semiconductors of some thin-film transistors experience performance degradation, it is easy to cause the picture displayed by the display device to have an uneven (Mura) problem. Generally speaking, in order to reduce this uneven problem, the pixel circuit is connected to an external chip, and a large amount of current information is stored in an external compensation memory. The above-mentioned current information is calculated by an algorithm to obtain a compensation current or voltage, and then the compensation current or voltage is fed back to the pixel circuit. However, the circuit design of the external chip is complex and the cost is high. Summary of the invention

[0003] The invention provides an active component substrate, which can save the production cost of an external memory.

[0004] The invention provides a method for manufacturing an active component substrate, which can save the production cost of an external memory.

[0005] At least one embodiment of the present invention provides an active component substrate. The active component substrate includes a substrate, a first semiconductor component and a second semiconductor component. The first semiconductor component and the second semiconductor component are arranged on the substrate. The first semiconductor component includes a first gate, a first semiconductor layer, a first source and a first drain. A gate dielectric structure is sandwiched between the first gate and the first semiconductor layer. The gate dielectric structure includes a stack of a portion of the gate dielectric layer and a portion of a ferroelectric material layer. The first source and the first drain are electrically connected to the first semiconductor layer. The second semiconductor component is electrically connected to the first semiconductor component and includes a second gate, a second semiconductor layer, a second source and a second drain. Another portion of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer. The second source and the second drain are electrically connected to the second semiconductor layer.

[0006] At least one embodiment of the present invention provides a method for manufacturing an active component substrate, comprising: forming a first semiconductor layer and a second semiconductor layer on the substrate; forming a gate dielectric layer on the first semiconductor layer; forming a ferroelectric material layer on the gate dielectric layer and the second semiconductor layer; forming a first gate and a second gate on the ferroelectric material layer, wherein the gate dielectric layer is located between the first gate and the first semiconductor layer, and the ferroelectric material layer is located between the first gate and the first semiconductor layer and between the second gate and the second semiconductor layer; forming a first source and a first drain electrically connected to the first semiconductor layer; forming a second source and a second drain electrically connected to the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention;

[0008] FIG. 2A to FIG. 2F yes Figure 1 A cross-sectional schematic diagram of a method for manufacturing an active component substrate;

[0009] Figure 3 is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention;

[0010] FIG. 4A to FIG. 4D yes Figure 3 A cross-sectional schematic diagram of a method for manufacturing an active component substrate;

[0011] Figure 5 is a schematic diagram of an equivalent circuit of a pixel circuit according to an embodiment of the present invention;

[0012] Figure 6 A display device according to an embodiment of the present invention is Figure 5 Pixel compensation operation flow chart under the pixel circuit setting.

[0013] Explanation of symbols

[0014] 10,20: Active component substrate

[0015] 100:Substrate

[0016] 102: Buffer layer

[0017] 112, 112': first semiconductor layer

[0018] 112a: first source region

[0019] 112b: first channel region

[0020] 112c: first drain region

[0021] 114, 114': second semiconductor layer

[0022] 114a: second source region

[0023] 114b: second channel region

[0024] 114c: second drain region

[0025] 116, 116': third semiconductor layer

[0026] 116a: third source region

[0027] 116b: third channel region

[0028] 116c: third drain region

[0029] 120: gate dielectric layer

[0030] 122: first gate dielectric pattern

[0031] 124: second gate dielectric pattern

[0032] 140: Ferroelectric material layer

[0033] 142: first ferroelectric material pattern

[0034] 144: Second ferroelectric material pattern

[0035] 150: interlayer dielectric layer

[0036] a: first node

[0037] b: Second node

[0038] c: The third node

[0039] Cst: Storage capacitor

[0040] D1: First drain

[0041] D2: Second drain

[0042] D3: The third drain

[0043] EL: Light Emitting Element

[0044] G1: First gate

[0045] G2: Second gate

[0046] G3: The third gate

[0047] GI: Gate dielectric structure

[0048] ND: Normal direction

[0049] O1, O2, O3, O4, O5, O6, OP: Open

[0050] PX: Pixel circuit

[0051] S1: First source

[0052] S2: Second source

[0053] S3: The third source

[0054] T1: The first semiconductor element

[0055] T2: Second semiconductor element

[0056] T3: The third semiconductor element

[0057] V S1 ,V data ,V DD ,V S2 ,V sus ,V SS :Voltage DETAILED DESCRIPTION

[0058] Figure 1 It is a cross-sectional schematic diagram of an active component substrate according to an embodiment of the present invention.

[0059] Please refer to Figure 1 , the active device substrate 10 includes a substrate 100, a first semiconductor device T1, and a second semiconductor device T2. In this embodiment, the active device substrate 10 further includes a third semiconductor device T3 and a buffer layer 102. In some embodiments, the second semiconductor device T2 is electrically connected to the first semiconductor device T1 through a conductive member not shown in the drawings. In some embodiments, the second semiconductor device T2 is electrically connected to the third semiconductor device T3 through a conductive member not shown in the drawings. In some embodiments, the third semiconductor device T3 is electrically connected to the first semiconductor device T1 through a conductive member not shown in the drawings.

[0060] The material of the substrate 100 may be glass, quartz, organic polymer, or opaque / reflective material (e.g., conductive material, metal, chip, ceramic or other applicable material) or other applicable material. If a conductive material or metal is used, an insulating layer (not shown) is covered on the first substrate 100 to avoid short circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyimide (PI) or metal foil or other flexible materials. The buffer layer 102 is located on the substrate 100, and the material of the buffer layer 102 may include silicon nitride, silicon oxide, silicon oxynitride or other suitable materials or stacked layers of the above materials, but the present invention is not limited thereto.

[0061] The first semiconductor element T1, the second semiconductor element T2 and the third semiconductor element T3 are disposed on the substrate 100 and the buffer layer 102. The first semiconductor element T1 includes a first gate G1, a first semiconductor layer 112, a first source S1 and a first drain D1. The second semiconductor element T2 includes a second gate G2, a second semiconductor layer 114, a second source S2 and a second drain D2. The third semiconductor element T3 includes a third gate G3, a third semiconductor layer 116, a third source S3 and a third drain D3.

[0062] The first semiconductor layer 112, the second semiconductor layer 114 and the third semiconductor layer 116 are disposed on the substrate 100 and the buffer layer 102. The first semiconductor layer 112 includes a first source region 112a, a first drain region 112c and a first channel region 112b located between the first source region 112a and the first drain region 112c. The second semiconductor layer 114 includes a second source region 114a, a second drain region 114c and a second channel region 114b located between the second source region 114a and the second drain region 114c. The third semiconductor layer 116 includes a third source region 116a, a third drain region 116c and a third channel region 116b located between the third source region 116a and the third drain region 116c.

[0063] The first gate G1 overlaps the first channel region 112b of the first semiconductor layer 112 in the normal direction ND of the top surface of the substrate 100, and a gate dielectric structure GI is sandwiched between the first gate G1 and the first semiconductor layer 112. The gate dielectric structure includes a stack of a portion of the gate dielectric layer 120 and a portion of the ferroelectric material layer 140. The gate dielectric layer 120 covers the upper surface and sidewalls of the first semiconductor layer 112, and the ferroelectric material layer 140 is located on the upper surface of the gate dielectric layer 120.

[0064] The second gate G2 overlaps the second channel region 114b of the second semiconductor layer 114 in the normal direction ND of the top surface of the substrate 100, and another portion of the ferroelectric material layer 140 is sandwiched between the second gate G2 and the second semiconductor layer 114. The gate dielectric layer 120 covers the sidewalls of the second semiconductor layer 114, and the ferroelectric material layer 140 contacts the upper surface of the second semiconductor layer 114. In some embodiments, the ferroelectric material layer 140 extends continuously from between the first gate G1 and the gate dielectric layer 120 to between the second gate G2 and the second semiconductor layer 114.

[0065] The third gate G3 overlaps the third channel region 116b of the third semiconductor layer 116 in the normal direction ND of the top surface of the substrate 100, and another portion of the gate dielectric layer 120 is sandwiched between the third gate G3 and the third semiconductor layer 116. The gate dielectric layer 120 covers the upper surface and sidewalls of the third semiconductor layer 116.

[0066] In some embodiments, a distance between the first gate G1 and the first semiconductor layer 112 is greater than a distance between the second gate G2 and the second semiconductor layer 114 and a distance between the third gate G3 and the third semiconductor layer 116 .

[0067] In one embodiment, the materials of the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 include single crystal silicon, polycrystalline silicon, microcrystalline silicon, organic semiconductor materials, metal oxide semiconductor materials (for example, quaternary metal compounds such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), or oxides composed of ternary metals including any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W)) or other suitable materials. In some embodiments, the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 include materials with the same or different compositions. In some embodiments, the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 include the same or different thicknesses.

[0068] In one embodiment, the material of the first gate G1, the second gate G2 and the third gate G3 may include metal, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn) or alloys of any combination of the above metals or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The first gate G1, the second gate G2 and the third gate G3 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties. In some embodiments, the first gate G1, the second gate G2 and the third gate G3 include materials of the same or different compositions. In some embodiments, the first gate G1, the second gate G2 and the third gate G3 include the same or different thicknesses.

[0069] In some embodiments, the gate dielectric layer 120 is made of, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials. In some embodiments, the gate dielectric layer 120 has a thickness of 50 nanometers to 100 nanometers.

[0070] In some embodiments, the material of the ferroelectric material layer 140 includes Ni x Mg y Zn 0.98-y O or Hf z Zr 1-z O 2 , wherein x is 0.01 to 0.05, y is 0.05 to 0.15, and z is 0.4 to 0.6. In some embodiments, the thickness of the ferroelectric material layer 140 is 5 nanometers to 50 nanometers.

[0071] The interlayer dielectric layer 150 is disposed on the first gate G1, the second gate G2, the third gate G3, the ferroelectric material layer 140 and the gate dielectric layer 120, and covers the first gate G1, the second gate G2, the third gate G3, the ferroelectric material layer 140 and the gate dielectric layer 120. The material of the interlayer dielectric layer 150 is, for example, silicon oxide, silicon nitride, silicon oxynitride or other suitable materials.

[0072] The openings O1 and O2 in the interlayer dielectric layer 150, the ferroelectric material layer 140 and the gate dielectric layer 120 overlap the first source region 112a and the first drain region 112c, respectively. The first source S1 and the first drain D1 are located on the interlayer dielectric layer 150 and are filled in the openings O1 and O2, respectively, to be electrically connected to the first source region 112a and the first drain region 112c of the first semiconductor layer 112.

[0073] The openings O3 and O4 in the interlayer dielectric layer 150, the ferroelectric material layer 140 and the gate dielectric layer 120 overlap the second source region 114a and the second drain region 114c, respectively. The second source S2 and the second drain D2 are located on the interlayer dielectric layer 150 and are filled in the openings O3 and O4, respectively, to be electrically connected to the second source region 114a and the second drain region 114c of the second semiconductor layer 114.

[0074] It should be noted that although Figure 1 In the embodiment, the ferroelectric material layer 140 is divided into a plurality of blocks by the first source S1, the first drain D1, the second source S2 and the second drain D2, but the ferroelectric material layer 140 is actually a continuous structure. In other words, the ferroelectric material layer 140 surrounds the first source S1, the first drain D1, the second source S2 and the second drain D2, and the first source S1, the first drain D1, the second source S2 and the second drain D2 pass through the ferroelectric material layer 140.

[0075] The openings O5 and O6 in the interlayer dielectric layer 150 and the gate dielectric layer 120 overlap the third source region 116a and the third drain region 116c, respectively. The third source S3 and the third drain D3 are located on the interlayer dielectric layer 150 and are filled in the openings O5 and O6, respectively, to be electrically connected to the third source region 116a and the third drain region 116c of the third semiconductor layer 116.

[0076] In one embodiment, the materials of the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 may include metals, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc or alloys of any combination of the above metals or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties. In some embodiments, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 include materials with the same or different compositions. In some embodiments, the first source S1 , the first drain D1 , the second source S2 , the second drain D2 , the third source S3 , and the third drain D3 have the same or different thicknesses.

[0077] Based on the above, the gate dielectric structure GI between the first gate G1 of the first semiconductor element T1 and the first semiconductor layer 112 includes a gate dielectric layer 120 and a ferroelectric material layer 140. Therefore, the sub-threshold swing of the first semiconductor element T1 can be made less than 60mV / dec through the negative capacitor effect, and the hysteresis effect of the ferroelectric material layer 140 between the first gate G1 and the first semiconductor layer 112 is reduced. In addition, since the ferroelectric material layer 140 is sandwiched between the second gate G2 of the second semiconductor element T2 and the second semiconductor layer 114, the second semiconductor element T2 can be used as a driving element and also has the function of storing current information or voltage information. Finally, the gate dielectric layer 120 is sandwiched between the first gate G1 of the third semiconductor element T3 and the first semiconductor layer 112, which can provide a stable forward or reverse current.

[0078] FIG. 2A to FIG. 2F yes Figure 1 A cross-sectional schematic diagram of a method for manufacturing an active device substrate 10 is shown.

[0079] Please refer to Figure 2A , forming a first semiconductor layer 112', a second semiconductor layer 114' and a third semiconductor layer 116' on the substrate 100. In the present embodiment, the first semiconductor layer 112', the second semiconductor layer 114' and the third semiconductor layer 116' are formed on the buffer layer 102. In some embodiments, the method of forming the first semiconductor layer 112', the second semiconductor layer 114' and the third semiconductor layer 116' comprises the following steps: first, forming a blanket semiconductor material layer (not shown) on the substrate 110 and the buffer layer 102; then, forming a patterned photoresist (not shown) on the semiconductor material layer by using a photolithography process; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the semiconductor material layer to form the first semiconductor layer 112', the second semiconductor layer 114' and the third semiconductor layer 116'; thereafter, removing the patterned photoresist. In other words, the first semiconductor layer 112 ′, the second semiconductor layer 114 ′ and the third semiconductor layer 116 ′ are, for example, formed simultaneously.

[0080] Please refer to Figure 2B, forming a gate dielectric layer 120 on the first semiconductor layer 112' and the third semiconductor layer 116'. In some embodiments, the method for forming the gate dielectric layer 120 includes the following steps: first, forming a blanket dielectric material layer (not shown) on the first semiconductor layer 112', the second semiconductor layer 114', the third semiconductor layer 116' and the buffer layer 102; then, using a photolithography process, forming a patterned photoresist (not shown) on the dielectric material layer; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the dielectric material layer to form a gate dielectric layer 120 including an opening OP, wherein the opening OP exposes the second semiconductor layer 114'; then, removing the patterned photoresist. In some embodiments, the length of the opening OP is less than the length of the second semiconductor layer 114', and the gate dielectric layer 120 covers the sidewalls and a portion of the surface of the second semiconductor layer 114'. In some embodiments, the length of the opening OP is greater than the length of the second semiconductor layer 114', and the gate dielectric layer 120 does not contact the second semiconductor layer 114'. In some embodiments, the material of the gate dielectric layer 120 may be an oxide that does not contain hydrogen, thereby preventing hydrogen atoms in the gate dielectric layer 120 from diffusing into the first semiconductor layer 112', the second semiconductor layer 114', and the third semiconductor layer 116' during the manufacturing process.

[0081] Please refer to Figure 2C , forming a ferroelectric material layer 140 on the gate dielectric layer 120 and the second semiconductor layer 114'. The ferroelectric material layer 140 is filled into the opening OP of the gate dielectric layer 120 to contact the second semiconductor layer 114'. In some embodiments, the method of forming the ferroelectric material layer 140 includes the following steps: first, forming a blanket ferroelectric material layer (not shown) on the gate dielectric layer 120 and the second semiconductor layer 114'; then, using a photolithography process, forming a patterned photoresist (not shown) on the ferroelectric material layer; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the ferroelectric material layer to form a ferroelectric material layer 140 that does not overlap the third semiconductor layer 116'; thereafter, removing the patterned photoresist.

[0082] Please refer to Figure 2D, forming a first gate G1 and a second gate G2 on the ferroelectric material layer 140, and forming a third gate G3 on the gate dielectric layer 120. The gate dielectric layer 120 is located between the first gate G1 and the first semiconductor layer 112 and between the third gate G3 and the third semiconductor layer 116, and the ferroelectric material layer 140 is located between the first gate G1 and the first semiconductor layer 112 and between the second gate G2 and the second semiconductor layer 114. In some embodiments, the method of forming the first gate G1, the second gate G2, and the third gate G3 includes the following steps: first, forming a blanket conductive material layer (not shown) on the gate dielectric layer 120 and the ferroelectric material layer 140; then, forming a patterned photoresist (not shown) on the conductive material layer by using a photolithography process; then, using the patterned photoresist as a mask to perform a wet or dry etching process on the conductive material layer to form the first gate G1, the second gate G2, and the third gate G3; and then, removing the patterned photoresist. In other words, the first gate G1 , the second gate G2 , and the third gate G3 are, for example, formed at the same time.

[0083] Next, the first gate G1, the second gate G2, and the third gate G3 are used as masks to perform a doping process P on the first semiconductor layer 112', the second semiconductor layer 114', and the third semiconductor layer 116' to form a first semiconductor layer 112 including a first source region 112a, a first channel region 112b, and a first drain region 112c, a second semiconductor layer 114' including a second source region 114a, a second channel region 114b, and a second drain region 114c, and a third semiconductor layer 116 including a third source region 116a, a third channel region 116b, and a third drain region 116c. In some embodiments, the doping process P includes a hydrogen plasma process or an ion implantation process.

[0084] Please refer to Figure 2E , an interlayer dielectric layer 150 is formed on the gate dielectric layer 120 and the ferroelectric material layer 140. In some embodiments, the interlayer dielectric layer 150 is an insulating layer that does not contain hydrogen, thereby preventing hydrogen atoms in the interlayer dielectric layer 150 from diffusing into the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116, but the present invention is not limited thereto. In some embodiments, the interlayer dielectric layer 150 contains hydrogen atoms, and therefore, the hydrogen atoms can be diffused into the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 by heat treatment to adjust the resistivity of the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116. In some embodiments, when the hydrogen atoms in the interlayer dielectric layer 150 are used to dope the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116, the step of doping the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 can be omitted. Figure 2D Doping process P.

[0085] Please refer to Figure 2F , forming openings O1, O2, O3, O4, O5, and O6, the method includes the following steps: first, using a photolithography process to form a patterned photoresist (not shown) on the interlayer dielectric layer 150; then, using the patterned photoresist as a mask to perform a wet or dry etching process to form openings O1, O2, O3, O4, O5, and O6 in the interlayer dielectric layer 150, the ferroelectric material layer 140, and the gate dielectric layer 120; thereafter, removing the patterned photoresist.

[0086] The openings O1 and O2 penetrate the interlayer dielectric layer 150, the ferroelectric material layer 140, and the gate dielectric layer 120 to respectively expose the first source region 112a and the first drain region 112c of the first semiconductor layer 112. The openings O3 and O4 penetrate the interlayer dielectric layer 150, the ferroelectric material layer 140, and the gate dielectric layer 120 to respectively expose the second source region 114a and the second drain region 114c of the second semiconductor layer 114. The openings O5 and O6 penetrate the interlayer dielectric layer 150 and the gate dielectric layer 120 to respectively expose the third source region 116a and the third drain region 116c of the third semiconductor layer 116.

[0087] Finally, please return Figure 1 , forming a first source S1, a first drain D1, a second source S2, a second drain D2, a third source S3 and a third drain D3 on the interlayer dielectric layer 150. The first source S1 and the first drain D1 are filled into the openings O1 and O2 respectively. The second source S2 and the second drain D2 are filled into the openings O3 and O4 respectively. The third source S3 and the third drain D3 are filled into the openings O5 and O6 respectively. In some embodiments, the method of forming the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 includes the following steps: first, a blanket conductive material layer (not shown) is formed on the interlayer dielectric layer 150; then, a patterned photoresist (not shown) is formed on the conductive material layer using a photolithography process; then, the conductive material layer is wet or dry etched using the patterned photoresist as a mask to form the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3; then, the patterned photoresist is removed. In other words, the first source S1, the first drain D1, the second source S2, the second drain D2, the third source S3 and the third drain D3 are, for example, formed simultaneously.

[0088] After the above manufacturing processes, the manufacturing of the active device substrate 10 can be substantially completed.

[0089] Figure 3FIG. 2 is a cross-sectional view of an active device substrate 20 according to an embodiment of the present invention. It must be noted that: Figure 3 The implementation examples are used Figure 1 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0090] Figure 3 The active component substrate 20 and Figure 1 The main difference between the active device substrate 10 and the active device substrate 20 is that the gate dielectric layer 120 of the active device substrate 20 is aligned with the first channel region 112b and the third channel region 116b, and the ferroelectric material layer 140 is aligned with the first channel region 112b and the second channel region 114b.

[0091] Please refer to Figure 3 The gate dielectric layer 120 includes a first gate dielectric pattern 122 and a second gate dielectric pattern 124, wherein the first gate dielectric pattern 122 and the second gate dielectric pattern 124 are separated from each other. The ferroelectric material layer 140 includes a first ferroelectric material pattern 142 and a second ferroelectric material pattern 144, wherein the first ferroelectric material pattern 142 and the second ferroelectric material pattern 144 are separated from each other.

[0092] The first gate dielectric pattern 122 and the first ferroelectric material pattern 142 overlap the first gate G1 and the first channel region 112b in the normal direction ND of the top surface of the substrate 100, and the first gate dielectric pattern 122 and the first ferroelectric material pattern 142 are located between the first gate G1 and the first channel region 112b, and form a gate dielectric structure GI. The sidewalls of the first gate dielectric pattern 122 and the sidewalls of the first ferroelectric material pattern 142 are aligned with the sidewalls of the first gate G1.

[0093] The second ferroelectric material pattern 144 overlaps the second gate G2 and the second channel region 114b in the normal direction ND of the top surface of the substrate 100 and is located between the second gate G2 and the second channel region 114b. The sidewalls of the second ferroelectric material pattern 144 are aligned with the sidewalls of the second gate G2.

[0094] The second gate dielectric pattern 124 overlaps the third gate G3 and the third channel region 116b in the normal direction ND of the top surface of the substrate 100 and is located between the third gate G3 and the third channel region 116b. The sidewalls of the second gate dielectric pattern 124 are aligned with the sidewalls of the third gate G3.

[0095] In the present embodiment, the gate dielectric layer 120 and the ferroelectric material layer 140 do not overlap with the first source region 112a, the first drain region 112c, the second source region 114a, the second drain region 114c, the third source region 116a and the third drain region 116c. Therefore, the gate dielectric layer 120 and the ferroelectric material layer 140 can be prevented from affecting the doping concentrations of the first source region 112a, the first drain region 112c, the second source region 114a, the second drain region 114c, the third source region 116a and the third drain region 116c, and the negative impact of the doping manufacturing process on the gate dielectric layer 120 and the ferroelectric material layer 140 can also be avoided.

[0096] FIG. 4A to FIG. 4D yes Figure 3 A cross-sectional schematic diagram of a method for manufacturing an active component substrate.

[0097] Please refer to Figure 4A , continued Figure 2C The first gate G1 and the second gate G2 are formed on the ferroelectric material layer 140, and the third gate G3 is formed on the gate dielectric layer 120. Then, the gate dielectric layer 120 and the ferroelectric material layer 140 are patterned using the first gate G1, the second gate G2 and the third gate G3 as masks to form a first gate dielectric pattern 122, a second gate dielectric pattern 124, a first ferroelectric material pattern 142 and a second ferroelectric material pattern 144.

[0098] Please refer to Figure 4B , using the first gate G1, the second gate G2 and the third gate G3 as masks, the first semiconductor layer 112', the second semiconductor layer 114' and the third semiconductor layer 116' are subjected to a doping process P to form a first semiconductor layer 112 including a first source region 112a, a first channel region 112b and a first drain region 112c, a second semiconductor layer 114' including a second source region 114a, a second channel region 114b and a second drain region 114c, and a third semiconductor layer 116 including a third source region 116a, a third channel region 116b and a third drain region 116c. In some embodiments, the doping process P includes a hydrogen plasma process or an ion implantation process.

[0099] Please refer to Figure 4C, an interlayer dielectric layer 150 is formed on the gate dielectric layer 120 and the ferroelectric material layer 140. The interlayer dielectric layer 150 contacts the first source region 112a, the first drain region 112c, the second source region 114a, the second drain region 114c, the third source region 116a, and the third drain region 116c. In some embodiments, the interlayer dielectric layer 150 contains hydrogen atoms, so the hydrogen atoms can be diffused into the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116 by heat treatment to adjust the resistivity of the first semiconductor layer 112, the second semiconductor layer 114, and the third semiconductor layer 116. In some embodiments, the doping process is performed by hydrogen atoms in the interlayer dielectric layer 150, so the doping process can be omitted. Figure 4B Doping process P.

[0100] Please refer to Figure 4D , openings O1 , O2 , O3 , O4 , O5 , and O6 are formed in the interlayer dielectric layer 150 .

[0101] Finally, please return Figure 3 , a first source S1, a first drain D1, a second source S2, a second drain D2, a third source S3 and a third drain D3 are formed on the interlayer dielectric layer 150. The first source S1 and the first drain D1 are respectively filled into the openings O1 and O2 to be electrically connected to the first source region 112a and the first drain region 112c of the first semiconductor layer 112. The second source S2 and the second drain D2 are respectively filled into the openings O3 and O4 to be electrically connected to the second source region 114a and the second drain region 114c of the second semiconductor layer 114. The third source S3 and the third drain D3 are respectively filled into the openings O5 and O6 to be electrically connected to the third source region 116a and the third drain region 116c of the third semiconductor layer 116.

[0102] After the above manufacturing process, the manufacturing of the active device substrate 20 can be substantially completed.

[0103] Figure 5 is a schematic diagram of an equivalent circuit of a pixel circuit PX according to an embodiment of the present invention. Figure 5 The pixel circuit PX is, for example, the pixel circuit PX on the active device substrate in any of the aforementioned embodiments.

[0104] Please refer to Figure 5 The pixel circuit PX includes a first semiconductor element T1, a second semiconductor element T2, a third semiconductor element T3, a storage capacitor Cst and a light emitting element EL.

[0105] The first semiconductor element T1 can be used as a switch transistor. The first gate of the first semiconductor element T1 is electrically connected to a voltage V S1(for example, a scan line voltage), the first drain (or first source) of the first semiconductor element T1 is electrically connected to the voltage V data (eg, a data line voltage), the first source (or the first drain) of the first semiconductor element T1 is electrically connected to the first node a.

[0106] The second semiconductor element T2 has the functions of a driving transistor and a memory. The second gate of the second semiconductor element T2 is electrically connected to the first node a. The second drain of the second semiconductor element T2 is electrically connected to the voltage V DD , the second source of the second semiconductor element T2 is electrically connected to the second node b.

[0107] The third semiconductor element T3 can be used as a sensing transistor, for example. The third gate of the third semiconductor element T3 is electrically connected to the voltage V S2 The third drain of the third semiconductor element T3 is electrically connected to the third node c, and the third source of the third semiconductor element T3 is electrically connected to the voltage V sus Voltage V S2 It is used to control the switch of the third semiconductor element T3 so as to transmit the information of the driving current to the external chip through the third semiconductor element T3.

[0108] One end of the storage capacitor Cst is electrically connected to the first node a, and the other end of the storage capacitor Cst is electrically connected to the third node c. The second node b is electrically connected to the third node c. Since the second gate of the second semiconductor element T2 is electrically connected to the storage capacitor Cst, even if the first semiconductor element T1 is turned off, the second semiconductor element T2 can still be turned on for a short period of time.

[0109] One end of the light emitting element EL is electrically connected to the second node b, and the other end of the light emitting element EL is electrically connected to the voltage V SS The brightness of the light emitting element EL will change due to the different magnitudes of the driving current passing through the second semiconductor element T2. The light emitting element EL is, for example, a micro light emitting diode, an organic light emitting diode or other light emitting elements.

[0110] In the present embodiment, at the first node a, the first source (or first drain) of the first semiconductor element T1, the second gate of the second semiconductor element T2, and one end of the storage capacitor Cst are electrically connected to each other. At the second node b, the second source of the second semiconductor element T2 and one end of the light emitting element EL are electrically connected to each other. At the third node c, the third drain of the third semiconductor element T3 and the other end of the storage capacitor Cst are electrically connected to each other. The third drain of the third semiconductor element T3 is electrically connected to the second source of the second semiconductor element T2 through the third node c and the second node b.

[0111] Figure 6A display device according to an embodiment of the present invention is Figure 5 Pixel compensation operation flow chart under the pixel circuit setting.

[0112] The following briefly describes the operation of pixel compensation in the display device under the setting of the pixel circuit PX. Please also refer to Figure 5 and Figure 6 First, the display device is in a closed state, so that the pixel circuit PX performs gray level sensing in the background. The gray level sensing method is, for example, to turn on the first semiconductor element T1, the second semiconductor element T2 and the third semiconductor element T3, so that the driving voltage through the first semiconductor element T1 and the driving current of the second semiconductor element T2 can be transmitted to the external chip through the third semiconductor element T3.

[0113] Next, the external chip establishes a corresponding model through signal processing and calculation, and then calculates the corresponding compensation information. After that, the compensation information is written into the pixel circuit PX. For example, the first semiconductor element T1, the second semiconductor element T2, and the third semiconductor element T3 are turned on to write the compensation information calculated by the external chip into the ferroelectric material layer in the second semiconductor element T2. Specifically, by polarizing the ferroelectric material layer in the second semiconductor element T2, the information is recorded in the second semiconductor element T2. In some embodiments, the third semiconductor element T3 is turned on to reduce the voltage difference between the source and the drain of the second semiconductor element T2, or further to eliminate the voltage difference between the source and the drain of the second semiconductor element T2.

[0114] Next, the display device is turned on. Since the compensation information has been written into the second semiconductor element T2, the magnitude of the driving current passing through the second semiconductor element T2 can be adjusted, thereby achieving the function of pixel compensation. In some embodiments, when the display device is turned on, the third semiconductor element T3 is in an off state.

[0115] In summary, the second semiconductor element T2 of the present invention has the function of a memory, so there is no need to set up a compensation memory in an external chip, which simplifies the overall system and reduces the cost.

Claims

1. An active component substrate, comprising: substrate; A first semiconductor element is disposed on the substrate, wherein the first semiconductor element comprises: A first gate and a first semiconductor layer, wherein the first semiconductor layer includes a first source region, a first channel region and a first drain region, wherein a gate dielectric structure is sandwiched between the first gate and the first semiconductor layer, wherein the gate dielectric structure includes a stack of a portion of a gate dielectric layer and a portion of a ferroelectric material layer, the gate dielectric layer covers the upper surface and sidewalls of the first semiconductor layer, and the ferroelectric material layer is located on the upper surface of the gate dielectric layer and contacts the lower surface of the first gate, and the subthreshold swing of the first semiconductor element is less than 60mV / dec; A first source electrode and a first drain electrode, electrically connected to the first semiconductor layer; A second semiconductor element is disposed on the substrate and electrically connected to the first semiconductor element, wherein the second semiconductor element comprises: A second gate and a second semiconductor layer, wherein the second semiconductor layer includes a second source region, a second channel region and a second drain region, wherein another portion of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer, the gate dielectric layer covers the sidewall of the second semiconductor layer, and the ferroelectric material layer contacts the upper surface of the second semiconductor layer and the lower surface of the second gate, the ferroelectric material layer extends continuously from between the first gate and the gate dielectric layer to between the second gate and the second semiconductor layer, the second semiconductor element has the function of driving a transistor and a memory, wherein the material of the ferroelectric material layer includes Ni x Mg y Zn 0.98-y O or Hf z Zr 1-z O2, wherein x is 0.01 to 0.05, y is 0.05 to 0.15, and z is 0.4 to 0.6, wherein the thickness of the ferroelectric material layer is 5 nanometers to 50 nanometers, and the thickness of the gate dielectric layer is 50 nanometers to 100 nanometers; A second source and a second drain are electrically connected to the second semiconductor layer, wherein the ferroelectric material layer does not overlap the first source region, the first drain region, the second source region, and the second drain region; and A third semiconductor element is disposed on the substrate and electrically connected to the second semiconductor element, wherein the third semiconductor element comprises: A third gate and a third semiconductor layer, wherein another portion of the gate dielectric layer is sandwiched between the third gate and the third semiconductor layer; The third source and the third drain are electrically connected to the third semiconductor layer, wherein the ferroelectric material layer does not overlap the third semiconductor layer, and the third semiconductor element is used as a sensing transistor. 2 . The active device substrate as claimed in claim 1 , wherein a distance between the first gate and the first semiconductor layer is greater than a distance between the second gate and the second semiconductor layer. 3 . The active device substrate as claimed in claim 1 , wherein the ferroelectric material layer extends from between the first gate and the gate dielectric layer to between the second gate and the second semiconductor layer. 4 . The active device substrate as claimed in claim 1 , wherein the ferroelectric material layer surrounds the first source, the first drain, the second source and the second drain. 5 . The active device substrate as claimed in claim 1 , wherein the first source, the first drain, the second source and the second drain pass through the ferroelectric material layer.

6. The active device substrate as claimed in claim 1, wherein the ferroelectric material layer comprises: A first ferroelectric material pattern overlapping the first gate; as well as The second ferroelectric material pattern overlaps the second gate, wherein the first ferroelectric material pattern is separated from the second ferroelectric material pattern. 7 . The active device substrate as claimed in claim 6 , wherein a sidewall of the first ferroelectric material pattern is aligned with a sidewall of the first gate, and a sidewall of the second ferroelectric material pattern is aligned with a sidewall of the second gate.

8. The active device substrate according to claim 1, further comprising: A third semiconductor element is disposed on the substrate and electrically connected to the second semiconductor element, wherein the third semiconductor element comprises: A third gate and a third semiconductor layer, wherein another portion of the gate dielectric layer is sandwiched between the third gate and the third semiconductor layer; The third source and the third drain are electrically connected to the third semiconductor layer. 9 . The active device substrate as claimed in claim 8 , wherein the first drain is electrically connected to the second gate, and the third drain is electrically connected to the second source.

10. A method for manufacturing an active component substrate, comprising: Forming a first semiconductor layer of a first semiconductor element, a second semiconductor layer of a second semiconductor element, and a third semiconductor layer of a third semiconductor element on a substrate, wherein the first semiconductor layer includes a first source region, a first channel region, and a first drain region, wherein the second semiconductor layer includes a second source region, a second channel region, and a second drain region; Forming a gate dielectric layer on the first semiconductor layer and the third semiconductor layer, wherein the gate dielectric layer covers the upper surface and sidewalls of the first semiconductor layer and the sidewalls of the second semiconductor layer; A ferroelectric material layer is formed on the gate dielectric layer and the second semiconductor layer, wherein the material of the ferroelectric material layer includes Ni x Mg y Zn 0.98-y O or Hf z Zr 1-z O2, wherein x is 0.01 to 0.05, y is 0.05 to 0.15, and z is 0.4 to 0.6, wherein the thickness of the ferroelectric material layer is 5 nanometers to 50 nanometers, and the thickness of the gate dielectric layer is 50 nanometers to 100 nanometers, and the ferroelectric material layer does not overlap the first source region, the first drain region, the second source region, the second drain region, and the third semiconductor layer; Forming a first gate of the first semiconductor element, a second gate of the second semiconductor element, and a third gate of the third semiconductor element on the ferroelectric material layer, wherein the gate dielectric layer is located between the first gate and the first semiconductor layer, and the ferroelectric material layer is located between the first gate and the first semiconductor layer and between the second gate and the second semiconductor layer, wherein the ferroelectric material layer is located on the upper surface of the gate dielectric layer and contacts the lower surface of the first gate, and the ferroelectric material layer contacts the upper surface of the second semiconductor layer and the lower surface of the second gate, and the ferroelectric material layer continuously extends from between the first gate and the gate dielectric layer to between the second gate and the second semiconductor layer; Forming a first source and a first drain of the first semiconductor element electrically connected to the first semiconductor layer; forming a second source and a second drain of the second semiconductor element electrically connected to the second semiconductor layer; as well as forming a third source and a third drain of the third semiconductor element electrically connected to the third semiconductor layer, The subthreshold swing of the first semiconductor element is less than 60mV / dec, the second semiconductor element has the functions of a driving transistor and a memory, the third semiconductor element is electrically connected to the second semiconductor element, and the third semiconductor element is used as a sensing transistor.

11. The method for manufacturing an active device substrate according to claim 10, further comprising: Using the first gate and the second gate as masks, a doping process is performed on the first semiconductor layer and the second semiconductor layer.

12. The method for manufacturing an active device substrate according to claim 10, further comprising: The gate dielectric layer and the ferroelectric material layer are patterned using the first gate and the second gate as masks. 13 . The method for manufacturing an active device substrate as claimed in claim 10 , wherein the gate dielectric layer comprises an opening exposing the second semiconductor layer, and the ferroelectric material layer is filled in the opening to contact the second semiconductor layer.

14. The method for manufacturing an active device substrate according to claim 10, The first semiconductor layer, the second semiconductor layer and the third semiconductor layer are formed simultaneously; the first gate, the second gate and the third gate are formed simultaneously; the first source, the first drain, the second source, the second drain, the third source and the third drain are formed simultaneously.

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