Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. It relates to the technical field of display technology, and aims to solve the technical problem of display uniformity deviation of the display panel. The display panel comprises: an opening area, a display area surrounding at least part of the opening area, the display area comprising: a first sub-display area located on at least one side of the opening area in a first direction, and a second sub-display area other than the first sub-display area; wherein the first sub-display area and the second sub-display area both have semiconductor segments, and the second sub-display area has a plurality of semiconductor segments arranged along the first direction, and the orthographic projection of two semiconductor segments adjacent along the first direction in the second sub-display area in the stacking direction of the display panel does not contact.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) display panel is a display device that utilizes the self-luminous principle of organic electroluminescent materials to realize display. Compared with liquid crystal display devices, the organic light emitting diode display panel has many advantages such as self-luminous, fast response speed, low-voltage driving, high brightness, thinness, etc., and thus gradually becomes the mainstream in the display field.

[0003] In order to improve the screen ratio of the display panel, an opening area is usually arranged on the display panel for mounting functional elements such as a camera module or a light sensor. At present, the opening area is formed by removing the pixel driving circuit and the semiconductor layer and other layer structures at a specific position in the display panel. Therefore, the semiconductor in the same row as the opening area is different from the semiconductor in the different row from the opening area, resulting in different display effects of the two regions, and thus affecting the display uniformity of the display panel. SUMMARY

[0004] In view of the above problems, the embodiments of the present application provide a display panel and a display device, which can reduce the possibility of characteristic non-uniformity of the semiconductor layers in different regions and improve the display uniformity of the display panel.

[0005] In order to achieve the above-mentioned purpose, the embodiments of the present application provide the following technical solutions:

[0006] The first aspect of the embodiments of the present application provides a display panel, which comprises:

[0007] an opening area, and a display area surrounding at least part of the opening area, the display area comprising: a first sub-display area located on at least one side of the opening area in a first direction, and a second sub-display area other than the first sub-display area;

[0008] wherein the first sub-display area and the second sub-display area both have semiconductor segments, and the second sub-display area has a plurality of semiconductor segments arranged along the first direction, and the orthographic projection of any two semiconductor segments adjacent in the first direction in the second sub-display area in the stacking direction of the display panel does not contact.

[0009] In a possible implementation manner, the first sub-display area has a plurality of semiconductor segments arranged along the first direction, and the orthographic projection of any two semiconductor segments adjacent in the first direction in the first sub-display area in the stacking direction of the display panel does not contact.

[0010] In a possible implementation, a length difference between the semiconductor segment of the first sub-display region and the semiconductor segment of the second sub-display region is less than or equal to a preset value, and the preset value is a product of a length of the semiconductor segment of the first sub-display region or the second sub-display region and a number less than 1.

[0011] Optionally, the semiconductor segment of the first sub-display region and the semiconductor segment of the second sub-display region have the same length.

[0012] In a possible implementation, the display panel further includes a pixel driving circuit, and the first sub-display region and the second sub-display region both have the pixel driving circuit.

[0013] For the semiconductor segment in any one of the first sub-display region and the second sub-display region, the semiconductor segment includes a semiconductor pattern of at least one pixel driving circuit and / or a partial semiconductor pattern of one pixel driving circuit.

[0014] In a possible implementation, the pixel driving circuit includes an initialization module, a light-emitting control module, and a light-emitting unit, the initialization module includes a first switch transistor for initializing the light-emitting unit, the light-emitting control module includes a second switch transistor for controlling the light-emitting unit to emit light in a light-emitting stage, and the second switch transistor is electrically connected to the light-emitting unit.

[0015] The semiconductor segment includes a first semiconductor part of the first switch transistor, and a first disconnected end of the semiconductor segment is located at the first semiconductor part.

[0016] The semiconductor segment includes a second semiconductor part of the second switch transistor, and a second disconnected end of the semiconductor segment is located at the second semiconductor part.

[0017] In a possible implementation, a first pole of the first switch transistor is electrically connected to a first reference voltage signal line, and a second pole of the first switch transistor and a first pole of the second switch transistor are both electrically connected to the light-emitting unit.

[0018] The second pole of the first switch transistor serves as the first disconnected end of the semiconductor segment, and the first pole of the second switch transistor serves as the second disconnected end of the semiconductor segment.

[0019] In a possible implementation, one semiconductor segment of the first sub-display region and the second sub-display region both includes M semiconductor patterns of the pixel driving circuit, and M is an integer greater than or equal to 1.

[0020] In a possible implementation, the display panel further includes a conversion trace, the conversion trace being configured to electrically connect two adjacent semiconductor segments that are not contacted by the orthographic projection in the stacking direction of the display panel, the conversion trace and the semiconductor segments being disposed in different layers.

[0021] In a possible implementation, the conversion trace is disposed on a third metal layer, the third metal layer being a metal layer on which at least one of a functional signal line, a source electrode, and a drain electrode is disposed.

[0022] A second aspect of the embodiments of the present application provides a display device including the display panel as described above.

[0023] In the display panel and the display device provided by the embodiments of the present application, the first sub-display area and the second sub-display area of the display area are both provided with semiconductor segments. The semiconductor segments in the first sub-display area are relatively short due to the opening area, and the second sub-display area has a plurality of semiconductor segments arranged along the first direction, and the orthographic projection of any two adjacent semiconductor segments in the second sub-display area in the stacking direction of the display panel does not contact, that is, the longer semiconductor segment in the second sub-display area is broken to form a plurality of shorter semiconductor segments. In this way, the length difference between the semiconductor segments in the first sub-display area and the semiconductor segments in the second sub-display area is shortened, thereby reducing the characteristic difference between the semiconductor segments in the first sub-display area and the semiconductor segments in the second sub-display area, which is beneficial to improving the display uniformity of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0025] Figure 1 A structural schematic diagram of the display panel provided by an embodiment of the present application;

[0026] Figure 2 A structural schematic diagram of the display panel provided by an embodiment of the present application; Figure 1 An enlarged schematic diagram of R in the middle;

[0027] Figure 3 A structural schematic diagram of the display panel provided by an embodiment of the present application;

[0028] Figure 4 A structural schematic diagram of the display panel provided by another embodiment of the present application;

[0029] Figure 5 A structural schematic diagram of a local area in the display panel provided by an embodiment of the present application;

[0030] Figure 6 An equivalent circuit schematic diagram of a pixel driving circuit provided for an embodiment of the present application;

[0031] Figure 7 A partial structure schematic diagram of a display panel provided for another embodiment of the present application;

[0032] Figure 8 A structure schematic diagram of a partial area in a display panel provided for an embodiment of the present application;

[0033] Figure 9 A structure schematic diagram of a display panel provided for another embodiment of the present application; Figure 7 A cross-sectional structure schematic diagram along the direction of W-W;

[0034] Figure 10 A partial structure schematic diagram of a display panel provided for another embodiment of the present application.

[0035] Explanation of reference signs:

[0036] 10, display panel;

[0037] 20, pixel driving circuit;

[0038] 30, semiconductor segment; 30a, first disconnection end; 30b, second disconnection end;

[0039] 301, first semiconductor part;

[0040] 302, second semiconductor part;

[0041] 303, third semiconductor part;

[0042] 40, conversion wire;

[0043] 50, connection wire;

[0044] AA, display area; AA1, first sub-display area; AA2, second sub-display area;

[0045] K, opening area;

[0046] P, light emitting unit;

[0047] X, first direction;

[0048] Y, second direction. DETAILED DESCRIPTION

[0049] In a display panel, in order to improve the screen ratio of the display panel, an opening area is usually arranged on the display panel. The opening area can be used to mount functional elements such as a camera module or a light sensor. The position of the opening area can be located at the middle position of the top of the display panel, or can be located at the position close to the edge of the top of the display panel, which is not limited in the present application. Since the area of the display panel where the opening area is arranged cannot be arranged with a pixel driving circuit and a semiconductor layer, part of the number of semiconductor layers on the display panel is discontinuous at the opening area, while other semiconductor layers are continuous. The length of the discontinuous semiconductor layer is less than that of the continuous semiconductor layer, thereby causing the problem of characteristic non-uniformity of semiconductor layers with different lengths, which affects the display uniformity of the display panel.

[0050] In view of the above technical problems, the present application provides an improved technical solution, in which the display panel includes an opening area, a display area and a semiconductor segment. The display area is provided with a semiconductor segment. Among all the semiconductor segments arranged at different positions on the display panel, the length difference of any two semiconductor segments is small, thereby facilitating to reduce the possibility of characteristic non-uniformity of the semiconductor segment, and facilitating to improve the display uniformity of the display panel. It should be noted that one semiconductor segment refers to a continuous semiconductor pattern of the semiconductor.

[0051] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme of the embodiments of the present application will be further described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0052] Figure 1 The structure of the display panel 10 of an embodiment of the present application is schematically shown. Figure 2 For Figure 1 The enlarged view at R in the middle. Referring to Figure 1 and Figure 2As shown, the display panel 10 has a backlight surface and a light emitting surface. The light emitting surface of the display panel 10 is used to emit light rays to display image information. The display panel 10 includes a display area AA and an aperture area K. The display panel 10 can form image information by light rays emitted by light emitting units P arranged in the display area AA. The light emitting units P can be self-luminous devices, for example, can be organic light emitting diodes. The aperture area K can be a region without display function. The aperture area K can be provided with a light sensing element (not shown in the figure), for example, but not limited to, a camera module or a light sensor. Exemplarily, the aperture area K can have a circular structure or a rectangular structure, which is not limited in the present application. In some possible implementation manners, the display area AA can be arranged around at least part of the aperture area K. In some examples, the display area AA can completely surround the aperture area K, so that the area of the display panel 10 around the aperture area K can be used to display image information. In other examples, the display area AA can also not completely surround the aperture area K, which is not limited herein.

[0053] Referring to Figure 2 As shown, the display area AA includes a first sub-display area AA1 located on at least one side of the aperture area K in the first direction X, and a second sub-display area AA2 other than the first sub-display area AA1. Figure 2 It is shown that the number of the first sub-display area AA1 is two, and located on both sides (left and right) of the aperture area K. Of course, the number of the first sub-display area AA1 can also be one, for example, the aperture area K is located on the left side of the display panel, and the first sub-display area AA1 is located on the right side of the aperture area K. The number and position of the first sub-display area AA1 are not limited herein. Figure 3 The partial structure of the display panel 10 of the present application is schematically shown. Referring to Figure 3 As shown, the first sub-display area AA1 and the second sub-display area AA2 of the display area AA are both provided with a pixel driving circuit 20. The display area AA is provided with multiple rows of pixel driving circuits 20. Each row of pixel driving circuits 20 includes multiple pixel driving circuits 20. The number of the pixel driving circuits 20 can be arranged one-to-one with the number of the light emitting units P. Each pixel driving circuit 20 can be used to provide a voltage required for light emission for the corresponding light emitting unit P to drive the corresponding light emitting unit P to emit light. In some possible implementation manners, the multiple pixel driving circuits 20 arranged in the display area AA are arranged in an array, that is, the multiple pixel driving circuits 20 are arranged in multiple rows and multiple columns.

[0054] It should be noted that the first direction X intersects the second direction Y. In order to facilitate the description of the scheme, the first direction X can refer to the row direction as shown in Figure 3 , and the second direction Y can refer to the column direction as shown in Figure 3The first direction can be the column direction and the second direction can be the row direction. The first direction and the second direction are not limited herein.

[0055] Since the aperture region K is not provided with the pixel driving circuit 20, the number of the pixel driving circuit 20 in each row of the pixel driving circuit 20 in the first sub-display region AA1 is less than the number of the pixel driving circuit 20 in each row of the pixel driving circuit 20 in the second sub-display region AA2.

[0056] Figure 4 The partial structure of the display panel 10 is schematically shown. Referring to FIG. 1, the display panel 10 includes a display region AA. The display region AA includes a first sub-display region AA1 and a second sub-display region AA2. Figure 4 As shown in FIG. 1, the display panel 10 further includes a semiconductor segment 30. The first sub-display region AA1 and the second sub-display region AA2 of the display region AA are both provided with the semiconductor segment. The second sub-display region AA2 has a plurality of semiconductor segments 30 arranged along the first direction X. The orthographic projection of two semiconductor segments 30 adjacent along the first direction X in the second sub-display region AA2 in the stacking direction of the display panel 10 does not contact.

[0057] Further, the semiconductor segment 30 of the second sub-display region AA2 includes a first disconnecting end and a second disconnecting end. For two semiconductor segments 30 adjacent along the first direction X in the second sub-display region AA2, the first disconnecting end of one semiconductor segment 30 and the second disconnecting end of the other semiconductor segment 30 are adjacent, so that the first disconnecting end of one semiconductor segment 30 and the second disconnecting end of the other semiconductor segment 30 are electrically connected. The orthographic projection of two semiconductor segments 30 adjacent along the first direction X in the second sub-display region AA2 in the stacking direction of the display panel 10 does not contact means that there is a gap between the first disconnecting end of one semiconductor segment 30 and the second disconnecting end of the other semiconductor segment 30 of the two semiconductor segments 30.

[0058] The first direction X and the second direction Y are both perpendicular to the stacking direction of the display panel 10. It should be noted that the semiconductor segment 30 of the embodiment of the present application can be one of poly silicon (PSI) and metal oxide semiconductor. The semiconductor segment 30 can include a semiconductor pattern of the pixel driving circuit 20. In the embodiment in which the semiconductor segment 30 adopts poly silicon, the pixel driving circuit 20 has a faster response speed. In the embodiment in which the semiconductor segment 30 adopts metal oxide semiconductor, the pixel driving circuit 20 can generate a stable light-emitting current. Therefore, when the semiconductor segment 30 in the display panel 10 is one of poly silicon and metal oxide semiconductor, the display panel 10 can have good light-emitting performance.

[0059] The display panel 10 provided by the embodiments of the present application has the first sub-display area AA1 and the second sub-display area AA2 of the display area AA both provided with the semiconductor segments 30. The semiconductor segments of the first sub-display area AA1 are relatively short due to the opening area K, and the second sub-display area AA2 has a plurality of semiconductor segments arranged along the first direction X, and the orthographic projection of the adjacent two semiconductor segments in the stacking direction of the display panel does not contact, that is, the longer semiconductor in the second sub-display area AA2 is disconnected to form a plurality of shorter semiconductor segments. Compared with the scheme in the related art that the semiconductor pattern of the second sub-display area AA2 is continuous along the first direction X, the semiconductor pattern of the second sub-display area AA2 is disconnected along the first direction X in the present application, thereby forming a plurality of semiconductor segments arranged along the first direction X, and the length of the semiconductor segments of the first sub-display area AA1 is shortened. In this way, the length difference between the semiconductor segments of the first sub-display area AA1 and the semiconductor segments of the second sub-display area AA2 is shortened, thereby reducing the characteristic difference between the semiconductor segments of the first sub-display area AA1 and the semiconductor segments of the second sub-display area AA2 in the process, and the display uniformity of the display panel is improved.

[0060] In addition, the semiconductor segments 30 are easy to collect charges, and the longer the length of the continuous extension of the semiconductor segments 30, the more charges are collected. If the semiconductor segments 30 are connected with the gate of the transistor, the higher potential is easy to break the thin gate insulating layer of the transistor, causing the transistor to fail. The semiconductor of the second sub-display area AA2 is disconnected along the first direction X in the present application, thereby shortening the length difference between the semiconductor segments of the first sub-display area AA1 and the semiconductor segments of the second sub-display area AA2. In this way, the adjacent two semiconductor segments along the first direction in the second sub-display area AA2 are disconnected before being electrically connected, thereby reducing the difference in the ability to collect charges between the semiconductor segments of the first sub-display area AA1 and the semiconductor segments of the second sub-display area AA2 in the process, and the display uniformity of the display panel is improved.

[0061] In some implementable manners, the first sub-display area AA1 has a plurality of semiconductor segments 30 arranged along the first direction X. The orthographic projection of the adjacent two semiconductor segments 30 along the first direction X in the first sub-display area AA1 in the stacking direction of the display panel does not contact.

[0062] Further, the semiconductor segments 30 in the first sub-display area AA1 include first disconnection ends and second disconnection ends, for two semiconductor segments 30 adjacent in the first direction X in the first sub-display area AA1, a first disconnection end of one semiconductor segment 30 and a second disconnection end of another semiconductor segment 30 are adjacent, so that the first disconnection end of the one semiconductor segment 30 and the second disconnection end of the another semiconductor segment 30 are electrically connected. The orthographic projection of the two semiconductor segments 30 adjacent in the first direction X in the first sub-display area AA1 in the stacking direction of the display panel 10 does not contact, which means that there is a gap between the first disconnection end of the one semiconductor segment 30 and the second disconnection end of the another semiconductor segment 30.

[0063] In the embodiments of the present application, for any one of the first sub-display area AA1 and the second sub-display area AA2, the two semiconductor segments 30 adjacent in the first direction in the sub-display area do not contact, so as to disconnect the semiconductors of the first sub-display area AA1 and the second sub-display area AA2, which is conducive to further reducing the length difference of the semiconductor segments 30 of the first sub-display area AA1 and the semiconductor segments 30 of the second sub-display area AA2.

[0064] In the display panel 10 provided by the embodiments of the present application, the first sub-display area AA1 and the second sub-display area AA2 each have a plurality of semiconductor segments 30 arranged in the first direction X, so that the semiconductor segments 30 are no longer a whole transverse trace continuously extending in the first direction X, effectively reducing the ability of the semiconductor segments 30 to collect charges, thereby reducing the possibility that a higher potential caused by the semiconductor segments 30 collecting more charges will further break down the thin gate insulating layer of the transistor. Before electrically connecting two semiconductor segments 30 adjacent in the first direction X, the two semiconductor segments 30 are in a disconnected state, thereby narrowing the gap in the ability to collect charges between the semiconductor segments of the first sub-display area AA1 and the semiconductor segments of the second sub-display area AA2 during the process, and improving the display effect and display life of the display panel 10.

[0065] In some implementable manners, the length difference between the semiconductor segments of the first sub-display area AA1 and the semiconductor segments of the second sub-display area AA2 is less than or equal to a preset value, and the preset value is a product of the length of the semiconductor segments of the first sub-display area AA1 or the second sub-display area AA2 and a number less than 1. In this way, the length difference of the semiconductor segments 30 of the first sub-display area AA1 and the semiconductor segments 30 of the second sub-display area AA2 is small.

[0066] Further, the semiconductor segments 30 of the first sub-display area AA1 and the semiconductor segments 30 of the second sub-display area AA2 have the same length, specifically, the length of the single semiconductor segment 30 of the first sub-display area AA1 and the length of the single semiconductor segment 30 of the second sub-display area AA2 are the same, so that the length difference of the semiconductor segments 30 of the first sub-display area AA1 and the semiconductor segments 30 of the second sub-display area AA2 is zero or substantially zero, further improving the uniformity of the characteristics of the semiconductor segments 30 of the first sub-display area AA1 and the semiconductor segments 30 of the second sub-display area AA2.

[0067] In some implementable manners, for the semiconductor segments 30 in any one of the first sub-display area AA1 and the second sub-display area AA2, the semiconductor segment 30 includes the semiconductor pattern of at least one pixel driving circuit 20 and / or the partial semiconductor pattern of one pixel driving circuit 20. For example, one semiconductor segment 30 includes the semiconductor pattern of one pixel driving circuit 20 or the semiconductor pattern of two pixel driving circuits 20. For another example, the semiconductor patterns of three pixel driving circuits 20 are divided into two semiconductor segments, one semiconductor segment includes the semiconductor pattern of one pixel driving circuit 20 and the partial semiconductor pattern of another pixel driving circuit 20.

[0068] In some examples, one semiconductor segment 30 of the first sub-display area AA1 and the second sub-display area AA2 each includes the semiconductor pattern of M pixel driving circuits 20, where M is an integer greater than or equal to 1. Exemplarily, one semiconductor segment 30 of the first sub-display area AA1 and the second sub-display area AA2 each includes the semiconductor pattern of two pixel driving circuits 20.

[0069] One semiconductor segment 30 of the first sub-display area AA1 and the second sub-display area AA2 each includes the same number of semiconductor patterns of pixel driving circuits 20, so that the length of one semiconductor segment 30 of the first sub-display area AA1 and the second sub-display area AA2 is the same or substantially the same.

[0070] In some implementable manners, Figure 5 The local structure of two adjacent semiconductor segments 30 of the present application is schematically shown. Referring to FIG. 2, the local structure of two adjacent semiconductor segments 30 of the present application is schematically shown. Figure 5 As shown, the semiconductor segment 30 includes a first disconnected end 30a and a second disconnected end 30b. In the two adjacent semiconductor segments 30, the first disconnected end 30a of one semiconductor segment 30 is arranged close to the second disconnected end 30b of the other semiconductor segment 30. There is a spacing between the first disconnected end 30a of one semiconductor segment 30 and the second disconnected end 30b of the other semiconductor segment 30 to ensure that the first disconnected end 30a and the second disconnected end 30b close to each other meet the insulation requirements.

[0071] In some examples, along the first direction X, the first disconnected end 30a of one semiconductor segment 30 is located at one side of the second disconnected end 30b of another semiconductor segment 30 (for example, at the left side as shown in FIG. 1). Figure 5

[0072] In some implementable manners, Figure 6 An equivalent circuit of a pixel driving circuit 20 of the present application is schematically shown. Referring to FIG. 2, Figure 6 As shown in FIG. 2, each pixel driving circuit 20 can include a plurality of transistors. For example, each pixel driving circuit 20 can include seven transistors and one storage capacitor, i.e., the pixel driving circuit 20 can be a 7T1C circuit.

[0073] It should be noted that the types of the transistors in the pixel driving circuit 20 can all be P-type transistors or N-type transistors. Alternatively, among the transistors in the pixel driving circuit 20, a part of the transistors can be P-type transistors, and the rest of the transistors can be N-type transistors. Different enable levels are provided according to different transistor types. The enable level refers to a level at which the transistor is turned on. For example, when the transistor is a P-type transistor, the enable level is a low level. When the transistor is an N-type transistor, the enable level is a high level.

[0074] The pixel driving circuit 20 includes an initialization module, a light-emitting control module, and a light-emitting unit P. The initialization module includes a first switch transistor T1 for initializing the light-emitting unit P. The semiconductor segment 30 includes a first semiconductor part 301 of the first switch transistor T1. The first disconnected end 30a is located at the first semiconductor part 301.

[0075] In some implementable manners, Figure 7 A partial structure of the display panel 10 of the present application is schematically shown. Referring to FIG. 3, Figure 5 to Figure 7 As shown in FIG. 3, the display panel 10 further includes a first reference voltage signal line Vref1. The first reference voltage signal line Vref1 can provide an initialization voltage. The first switch transistor T1 includes a first pole T11 and a second pole T12. The first pole T11 of the first switch transistor T1 is electrically connected to the first reference voltage signal line Vref1. The second pole T12 of the first switch transistor T1 is electrically connected to the light-emitting unit P. When the first switch transistor T1 is turned on, the initialization voltage of the first reference voltage signal line Vref1 can be transmitted to the light-emitting unit P, so that the voltage of the light-emitting unit P is the initialization voltage, thereby the potential of the light-emitting unit P can be initialized to reset the light-emitting unit P.

[0076] In some examples, the second pole T12 of the first switch transistor T1 serves as the first disconnected end 30a of the semiconductor segment 30.

[0077] ​In some examples, the first pole T11 can be a drain, and the second pole T12 can be a source.

[0078] In some examples, the first reference voltage signal line Vref1 is electrically connected with the first pole T11 of the first switch transistor T1 through a via of the insulating layer.

[0079] The light emitting control module includes a second switch transistor T2 for controlling the light emitting unit P to emit light in a light emitting stage, and the second switch transistor T2 is electrically connected with the light emitting unit P. The semiconductor segment 30 includes a second semiconductor part 302 of the second switch transistor T2. The second disconnecting end 30b is located at the second semiconductor part 302.

[0080] In some examples, the second switch transistor T2 includes a first pole T21 and a second pole T22. The first pole T21 of the second switch transistor T2 is electrically connected with the light emitting unit P.

[0081] In some examples, the first pole T21 of the second switch transistor T2 is the second disconnecting end 30b of the semiconductor segment 30. In some examples, the first pole T21 can be a drain, and the second pole T22 can be a source.

[0082] In some examples, one semiconductor segment includes the first switch transistor T1 and the second switch transistor T2, and the two disconnecting ends of the semiconductor segment are respectively located at the second pole of the first switch transistor and the first pole of the second switch transistor, so that the two adjacent semiconductor segments extending in the first direction are disconnected between the second pole of the first switch transistor and the first pole of the second switch transistor.

[0083] In some realizable manners, the pixel driving circuit 20 further includes a driving transistor T3. The driving transistor T3 includes a third semiconductor part 303 located at the semiconductor segment 30, and the third semiconductor part 303 includes a first pole T31 and a second pole T32 of the driving transistor T3. The second pole T32 of the driving transistor T3 can be electrically connected with the power voltage line VDD. The second pole T22 of the second switch transistor T2 is electrically connected with the first pole T31 of the driving transistor T3. The driving transistor T3 is used for outputting a driving current. When the second switch transistor T2 is turned on, the light emitting unit P can receive the driving current of the driving transistor T3 to realize light emitting display.

[0084] In some examples, the display panel 10 further comprises a second reference voltage signal line Vref2. The second reference voltage signal line Vref2 can provide an initialization voltage. When a switch transistor T5 located between the second reference voltage signal line Vref2 and the gate of the driving transistor T3 is turned on, the initialization voltage of the second reference voltage signal line Vref2 can be transmitted to the gate of the driving transistor T3, so that the gate voltage of the driving transistor T3 is the initialization voltage, thereby the potential of the gate of the driving transistor T3 can be initialized to reset the gate of the driving transistor T3.

[0085] In some implementable manners, Figure 8 The structure of the semiconductor segment 30 in a local area of the display panel 10 of the present application is schematically shown. Referring to FIG. 1, the display panel 10 comprises a plurality of semiconductor segments 30. The semiconductor segment 30 is a semiconductor pattern of the pixel driving circuit 20. Figure 8 As shown, the display panel 10 further comprises a conversion trace 40. The conversion trace 40 is used to electrically connect two adjacent semiconductor segments 30 which are not in contact in the orthographic projection in the stacking direction of the display panel 10, so that the two adjacent semiconductor segments 30 can be turned on with each other. The conversion trace 40 is disposed in a different layer from the semiconductor segment 30.

[0086] It should be noted that, in order to facilitate the description of the present application, Figure 8 In FIG. 1, only four semiconductor segments 30 are schematically shown. The four semiconductor segments 30 are distributed in two rows and two columns. One semiconductor segment 30 comprises two semiconductor patterns of the pixel driving circuit 20. Figure 8 Only one shape of the semiconductor segment 30 is shown. It can be understood that the semiconductor segment 30 can also be other shapes, which are not specifically limited in the present application.

[0087] In some examples, the two ends of the conversion trace 40 are electrically connected to the first disconnected end 30a of one semiconductor segment 30 and the second disconnected end 30b of another semiconductor segment 30, respectively.

[0088] In some examples, the display panel 10 comprises a third metal layer M3. The conversion trace 40 can be disposed in the third metal layer M3. The third metal layer M3 is a metal layer in which at least one of a functional signal line, a source electrode or a drain electrode is disposed. The functional signal line can be but is not limited to a data signal line Data. The functional signal line, the source electrode or the drain electrode needs to be electrically connected to devices in other layers through a via of an insulating layer. By disposing the conversion trace 40 in the third metal layer M3 and electrically connecting the conversion trace 40 to the semiconductor segment 30 through the via of the insulating layer, the preparation process of separately preparing the conversion trace 40 can be reduced, and the processing difficulty of the display panel 10 can be reduced.

[0089] In some possible implementation manners, the conversion wire 40 is arranged on the third metal layer M3. The orthographic projection of the functional signal line or the first reference voltage signal line Vref1 on the stacking direction of the display panel does not overlap the first semiconductor part 301 of one semiconductor segment 30 and the second semiconductor part 302 of the other semiconductor segment 30. Therefore, the first disconnecting end 30a of one semiconductor segment 30 and the second disconnecting end 30b of the other semiconductor segment 30 are disconnected, so that a larger space can be provided at the position for arranging the conversion wire 40, thereby on the one hand, ensuring that the distance between the conversion wire 40 and the functional signal line or the distance between the conversion wire 40 and the first reference voltage signal line Vref1 meets the requirement, and reducing the possibility that interference exists between the conversion wire 40 and the functional signal line or the first reference voltage signal line Vref1 due to the small distance therebetween; on the other hand, ensuring that the area of the conversion wire 40 itself meets the requirement, so as to ensure that the conduction effect of the adjacent two semiconductor segments 30 after being electrically connected through the conversion wire 40 meets the requirement.

[0090] In some possible implementation manners, the display panel 10 includes a plurality of first reference voltage signal lines Vref1 extending along the first direction X and a plurality of first reference voltage signal lines Vref1 extending along the second direction Y. The first reference voltage signal lines Vref1 extending along the first direction X and the first reference voltage signal lines Vref1 extending along the second direction Y intersect each other. The first reference voltage signal lines Vref1 extending along the first direction X are electrically connected to the first reference voltage signal lines Vref1 extending along the second direction Y. The first electrode T11 is electrically connected to the first reference voltage signal lines Vref1 extending along the first direction X. When the first switch transistor T1 is turned on, the initialization voltage of the first reference voltage signal lines Vref1 extending along the first direction X and the first reference voltage signal lines Vref1 extending along the second direction Y can be transmitted to the corresponding light emitting unit P, so that the corresponding light emitting unit P can be reset.

[0091] In some examples, the first reference voltage signal lines Vref1 extending along the first direction X and the first reference voltage signal lines Vref1 extending along the second direction Y are located on different metal layers, thereby reducing the possibility that the first reference voltage signal lines Vref1 extending in different directions are difficult to arrange due to the large space occupied by the first reference voltage signal lines Vref1 extending in different directions arranged on the same layer, and also reducing the possibility that the first reference voltage signal lines Vref1 extending in different directions interfere with each other.

[0092] For example, the first reference voltage signal lines Vref1 extending along the first direction X are located on the second metal layer M2, and the first reference voltage signal lines Vref1 extending along the second direction Y are located on the third metal layer M3.

[0093] Exemplarily, Figure 9 For Figure 7 The cross-sectional structure along the direction W-W. Referring to Figure 7 and Figure 9 As shown in FIG. 4, the conversion trace 40 and the first reference voltage signal line Vref1 extending along the second direction Y can be arranged in the same layer. The conversion trace 40 and the first reference voltage signal line Vref1 extending along the second direction Y can be both located in the third metal layer M3.

[0094] In some possible implementation manners, the display panel 10 includes a plurality of second reference voltage signal lines Vref2 extending along the first direction X and a plurality of second reference voltage signal lines Vref2 extending along the second direction Y. The second reference voltage signal lines Vref2 extending along the first direction X and the second reference voltage signal lines Vref2 extending along the second direction Y intersect with each other. The second reference voltage signal lines Vref2 extending along the first direction X are electrically connected with the second reference voltage signal lines Vref2 extending along the second direction Y.

[0095] In some examples, along the second direction Y, the first reference voltage signal lines Vref1 and the second reference voltage signal lines Vref2 are arranged alternately. Along the first direction X, the first reference voltage signal lines Vref1 and the second reference voltage signal lines Vref2 are arranged alternately. The first reference voltage signal lines Vref1 and the second reference voltage signal lines Vref2 form a mesh structure.

[0096] In some examples, the second reference voltage signal lines Vref2 extending along the first direction X and the second reference voltage signal lines Vref2 extending along the second direction Y are located in different metal layers, which can reduce the possibility that the second reference voltage signal lines Vref2 extending in different directions are difficult to arrange due to the large space occupied by the second reference voltage signal lines Vref2 extending in different directions, and can also reduce the possibility that the second reference voltage signal lines Vref2 extending in different directions interfere with each other.

[0097] Exemplarily, the second reference voltage signal lines Vref2 extending along the first direction X are located in the second metal layer M2, and the second reference voltage signal lines Vref2 extending along the second direction Y are located in the third metal layer M3.

[0098] Exemplarily, referring to Figure 7 and Figure 9As shown, the conversion trace 40, the first reference voltage signal line Vref1 extending along the second direction Y and the second reference voltage signal line Vref2 extending along the second direction Y can be arranged in the same layer. The conversion trace 40, the first reference voltage signal line Vref1 extending along the second direction Y and the second reference voltage signal line Vref2 extending along the second direction Y can all be located in the third metal layer M3.

[0099] In some examples, along the first direction X, the first disconnected end 30a of one semiconductor segment 30, the second disconnected end 30b of another semiconductor segment 30 and the conversion trace 40 are located in the space between the adjacent first reference voltage signal line Vref1 and the second reference voltage signal line Vref2. The space between the adjacent first reference voltage signal line Vref1 and the second reference voltage signal line Vref2 is large, which is conducive to reducing the difficulty of arranging the conversion trace 40, and can also make the area of the conversion trace 40 larger.

[0100] In some implementable manners, along the second direction Y, the orthographic projection of the adjacent two semiconductor segments 30 in the stacking direction of the display panel 10 does not contact, that is, along the second direction Y, the adjacent two semiconductor segments 30 are independent of each other and do not have an electrical connection relationship with each other.

[0101] In some implementable manners, Figure 10 The partial structure of the display panel 10 of the present application is schematically shown. Referring to Figure 10 As shown, the display area AA includes a first sub-display area AA1 located on both sides of the aperture area K. The display panel 10 further includes a connection trace 50. The connection trace 50 can be arranged around the aperture area K. Along the first direction X, the semiconductor segments 30 located on both sides of the aperture area K can be electrically connected through the connection trace 50.

[0102] In some examples, the connection trace 50 and the semiconductor segment 30 can be arranged in different layers. For example, the connection trace 50 can be located in the third metal layer M3. The conversion trace 40 and the connection trace 50 can be arranged in the same layer, which is conducive to reducing the preparation process of the conversion trace 40 and the connection trace 50 and reducing the processing difficulty.

[0103] The embodiment of the present application also provides a display device including the display panel 10 of the above-mentioned embodiment. The display device further includes a photosensitive element. The photosensitive element can be arranged in the aperture area K. The display device of the present application can be a mobile phone, a tablet, a notebook, a television and the like.

[0104] In some implementable manners, the photosensitive element can be a camera module, an infrared sensor, a proximity sensor, a fingerprint recognition sensor, an ambient light sensor and the like.

[0105] The embodiments or examples in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be mutually referred to.

[0106] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0107] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: an aperture region, a display region surrounding at least part of the aperture region, the display region comprising: a first sub-display region located on at least one side of the aperture region in a first direction, and a second sub-display region other than the first sub-display region; wherein the first sub-display region and the second sub-display region each have a semiconductor segment, and the second sub-display region has a plurality of semiconductor segments arranged in the first direction, and the normal projection of two semiconductor segments adjacent in the first direction in the second sub-display region in the stacking direction of the display panel does not contact; the display panel further comprises a pixel driving circuit, and the first sub-display region and the second sub-display region each have the pixel driving circuit; the pixel driving circuit comprises an initialization module, a light-emitting control module, and a light-emitting unit, the initialization module comprises a first switch transistor for initializing the light-emitting unit, the light-emitting control module comprises a second switch transistor for controlling the light-emitting unit to emit light in a light-emitting stage, and the second switch transistor is electrically connected with the light-emitting unit; the semiconductor segment comprises a first semiconductor part of the first switch transistor, and a first disconnected end of the semiconductor segment is located at the first semiconductor part; the semiconductor segment further comprises a second semiconductor part of the second switch transistor, and a second disconnected end of the semiconductor segment is located at the second semiconductor part; the display panel further comprises a conversion wire, the conversion wire is used to electrically connect two adjacent semiconductor segments whose normal projection in the stacking direction of the display panel does not contact, and two ends of the conversion wire are respectively electrically connected with the first disconnected end of one semiconductor segment and the second disconnected end of another semiconductor segment.

2. The display panel of claim 1, wherein, The first sub-display region has a plurality of semiconductor segments arranged in the first direction, and the normal projection of two semiconductor segments adjacent in the first direction in the first sub-display region in the stacking direction of the display panel does not contact.

3. The display panel of claim 1, wherein, The length difference between the semiconductor segment of the first sub-display region and the semiconductor segment of the second sub-display region is less than or equal to a preset value, and the preset value is the product of the length of the semiconductor segment of the first sub-display region or the semiconductor segment of the second sub-display region and a number less than 1.

4. The display panel of claim 3, wherein, The length of the semiconductor segment of the first sub-display region is the same as the length of the semiconductor segment of the second sub-display region.

5. The display panel of claim 1, wherein for the semiconductor segment in any one of the first sub-display region and the second sub-display region, the semiconductor segment comprises at least one semiconductor pattern of the pixel driving circuit and / or a partial semiconductor pattern of the pixel driving circuit.

6. The display panel of claim 1, wherein the first pole of the first switch transistor is electrically connected to a first reference voltage signal line, and the second pole of the first switch transistor and the first pole of the second switch transistor are both electrically connected to the light-emitting unit. The second electrode of the first switch transistor is the first disconnecting end of the semiconductor segment, and the first electrode of the second switch transistor is the second disconnecting end of the semiconductor segment.

7. The display panel of claim 5, wherein, Each of the semiconductor segments of one of the first sub-display area and the second sub-display area includes a semiconductor pattern of M pixel driving circuits, M being an integer greater than or equal to 1.

8. The display panel of any one of claims 1 to 7, wherein, The conversion trace and the semiconductor segments are disposed in different layers.

9. The display panel of claim 8, wherein, The conversion trace is disposed on a third metal layer, and the third metal layer is a metal layer on which at least one of a functional signal line, a source electrode, and a drain electrode is disposed.

10. A display device, characterized by comprising: A display panel comprising any one of claims 1 to 9.

Images