Method and apparatus for wireless charging of electric vehicles

Abstract

The application provides a method for a wireless charging system, the wireless charging system comprising a primary side subsystem and a secondary side subsystem, the secondary side subsystem comprising a secondary side inductor coil, an impedance matching circuit and a rectifier, the rectifier comprising first, second, third and fourth power switch tubes, the method comprising: obtaining a resonant current from the impedance matching circuit; detecting a zero-crossing point of the resonant current; generating a zero-crossing square wave signal based on the detected zero-crossing point, wherein the zero-crossing square wave signal jumps in response to the zero-crossing point of the resonant current; obtaining a period of the resonant current based on the zero-crossing square wave signal; generating an enable instruction in response to the obtaining of the period of the resonant current, to generate drive signals of the first, second, third and fourth power switch tubes according to the zero-crossing square wave signal.

Description

Technical Field

[0001] The present disclosure relates to the field of vehicles, and in particular to a method and apparatus for wireless charging of electric vehicles. Background Art

[0002] With the development of electric vehicles, wireless charging has also become widely used. Wireless charging for electric vehicles uses magnetic coupling to transfer energy between the vehicle and the ground. In an electric vehicle's wireless charging system, the primary and secondary inductors are coupled via a high-frequency magnetic field to achieve wireless power transmission. The AC power from the secondary inductor is rectified at high frequency to output a DC voltage, which charges the electric vehicle's battery.

[0003] To achieve precise control of the secondary side of an electric vehicle's wireless charging system, the secondary rectifier's drive signal must be synchronized with the AC current flowing through the secondary inductor. A solution is needed to stably and accurately synchronize the drive signal and the AC current flowing through the secondary inductor. Summary of the Invention

[0004] To address the above technical issues in the prior art, the present application provides a method for wireless charging of electric vehicles. This method uses digital circuits to synchronize the drive signal of a power switch tube with the resonant current, making the synchronization more stable and accurate. This method also significantly reduces the number of analog components and simplifies the hardware circuit. Furthermore, the present application generates an enable instruction for the drive signal when obtaining the period of the resonant current. This allows the drive signal for the power switch tube to be generated only after the period of the resonant current has stabilized, further saving circuit power.

[0005] In one aspect, the present application provides a method for a wireless charging system, the wireless charging system including a primary subsystem and a secondary subsystem, the secondary subsystem including a secondary inductor, an impedance matching circuit with parallel resonance characteristics, and a rectifier, the rectifier including a first power switch tube, a second power switch tube, a third power switch tube, and a fourth power switch tube, the first power switch tube and the second power switch tube forming a left bridge arm of a phase-shifted full-bridge circuit, and the third power switch tube and the fourth power switch tube forming a right bridge arm of the phase-shifted full-bridge circuit, the method comprising:

[0006] Obtaining a resonant current from the impedance matching circuit;

[0007] detecting a zero-crossing point of the resonant current;

[0008] generating a zero-crossing square wave signal based on the detected zero-crossing point, wherein the zero-crossing square wave signal transitions in response to the zero-crossing point of the resonant current;

[0009] acquiring a period of the resonant current based on the zero-crossing square wave signal;

[0010] An enable instruction is generated in response to obtaining the period of the resonant current to generate drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube according to the zero-crossing square wave signal.

[0011] Optionally, acquiring the period of the resonant current based on the zero-crossing square wave signal includes:

[0012] Capturing a rising edge of a square wave in the zero-crossing square wave signal;

[0013] Determine the time length L(i) between the rising edges of two adjacent square waves;

[0014] L(i) is determined as the period of the resonant current when L(i) satisfies the following formula:

[0015] L(i)=αL(i)+(1-α)L(i-1),

[0016] Where 0<α<1.

[0017] Optionally, the method further comprises:

[0018] counting the square wave of the zero-crossing square wave signal using a synchronous counter, wherein the synchronous signal of the synchronous counter is cleared in response to counting to its maximum count value and detecting a square wave rising edge of the zero-crossing square wave signal; and

[0019] The driving signals of the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube are generated according to the synchronization signal of the synchronization counter.

[0020] Optionally, the driving signal of the first power switch tube and the driving signal of the second power switch tube are complementary, and the driving signal of the third power switch tube and the driving signal of the fourth power switch tube are complementary.

[0021] Optionally, the method further includes determining a phase difference between the driving signal of the first power switch tube and the driving signal of the third power switch tube according to a duty cycle of the output voltage.

[0022] Another aspect of the present application provides a wireless charging device, comprising a secondary subsystem, the secondary subsystem comprising a secondary inductor, an impedance matching circuit, a rectifier, a zero-crossing detector, and a processor; the rectifier comprising a first power switch tube, a second power switch tube, a third power switch tube, and a fourth power switch tube; the first power switch tube and the second power switch tube constitute a left arm of a phase-shifted full-bridge circuit, and the third power switch tube and the fourth power switch tube constitute a right arm of the phase-shifted full-bridge circuit;

[0023] wherein the zero crossing detector is configured to:

[0024] Obtaining a resonant current from the impedance matching circuit;

[0025] detecting a zero-crossing point of the resonant current;

[0026] wherein the processor is configured to:

[0027] generating a zero-crossing square wave signal based on the detected zero-crossing point, wherein the zero-crossing square wave signal transitions in response to the zero-crossing point of the resonant current;

[0028] acquiring a period of the resonant current based on the zero-crossing square wave signal;

[0029] An enable instruction is generated in response to obtaining the period of the resonant current to generate drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube according to the zero-crossing square wave signal.

[0030] Optionally, acquiring the period of the resonant current based on the zero-crossing square wave signal includes:

[0031] Capturing a rising edge of a square wave in the zero-crossing square wave signal;

[0032] Determine the time length L(i) between the rising edges of two adjacent square waves;

[0033] L(i) is determined as the period of the resonant current when L(i) satisfies the following formula:

[0034] L(i)=αL(i)+(1-α)L(i-1),

[0035] Where 0<α<1.

[0036] Optionally, the processor is further configured to:

[0037] counting the square wave of the zero-crossing square wave signal using a synchronous counter, wherein the synchronous signal of the synchronous counter is cleared in response to counting to its maximum count value and detecting a square wave rising edge of the zero-crossing square wave signal; and

[0038] The driving signals of the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube are generated according to the synchronization signal of the synchronization counter.

[0039] Optionally, the driving signal of the first power switch tube and the driving signal of the second power switch tube are complementary, and the driving signal of the third power switch tube and the driving signal of the fourth power switch tube are complementary.

[0040] Optionally, the processor is further configured to determine a phase difference between the driving signal of the first power switch tube Q1 and the driving signal of the third power switch tube Q3 according to a duty cycle of the output voltage.

[0041] Yet another aspect of the present application provides a motor vehicle comprising the wireless charging device described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a diagram of a wireless charging system according to aspects of the present disclosure.

[0043] Figure 2 is a timing diagram of a wireless charging system according to aspects of the present disclosure.

[0044] Figure 3 is a timing diagram of a wireless charging system according to aspects of the present disclosure.

[0045] Figure 4 is a timing diagram of a wireless charging system according to aspects of the present disclosure.

[0046] Figure 5 is a flow chart of a method for wireless charging according to aspects of the present disclosure.

[0047] Figure 6 is a diagram of a wireless charging system according to aspects of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned objectives, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0049] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0050] Figure 1 is a diagram of a wireless charging system according to the present disclosure.

[0051] like Figure 1 As shown, the wireless charging system may include a primary subsystem and a secondary subsystem.

[0052] The primary subsystem can obtain electrical energy from the grid, convert the industrial frequency AC power into high frequency AC power through a conversion circuit (not shown), and convert the electrical energy into magnetic field energy through the primary inductor Lp for transmission to the secondary subsystem.

[0053] The secondary subsystem may include a secondary inductor, an impedance matching circuit, and a rectifier.

[0054] The secondary inductor Ls converts the magnetic field energy induced by the primary coil Lp into high-frequency electric field energy through electromagnetic induction.

[0055] The impedance matching circuit may include a capacitor Cs, an inductor Lf, and a capacitor Cf, wherein the capacitor Cs is a compensation capacitor for the secondary inductor Ls, and the capacitor Cf and the inductor Lf are a parallel resonant inductor and capacitor, and the following relationship is satisfied between them:

[0056]

[0057] Where ω = 2πf, f is the frequency of the AC current of the impedance matching circuit.

[0058] Please note that Figure 1 The impedance matching circuit is shown to include a pair of parallel resonant inductors and capacitors, but other numbers of resonant inductor and capacitor pairs are also contemplated by the present application.

[0059] The rectifier may include a phase-shifted full-bridge circuit, comprising a first power switch Q1, a second power switch Q2, a third power switch Q3, and a fourth power switch Q4. The first and second power switches Q1 and Q2 form the left arm of the phase-shifted full-bridge circuit, while the third and fourth power switches Q3 and Q4 form the right arm of the phase-shifted full-bridge circuit. The power switches Q1-Q4 may be MOS (field-effect transistors) or insulated gate bipolar transistors (IGBTs).

[0060] The resonant current output by the impedance matching circuit is input to the midpoint of the bridge arm of the phase-shifted full-bridge circuit, that is, connected to the source (S) of Q1 and Q3 and the drain (D) of Q2 and Q4.

[0061] The rectifier receives the resonant current ILf output from the impedance matching circuit and the drive signals for the power switches Q1-Q4 from the processor. The rectifier converts the resonant current ILf (AC current) into DC current to charge the vehicle's battery UBat.

[0062] During operation, the driving signals for the power switches Q1 - Q4 need to be synchronized with the resonant current ILf, thereby controlling the on and off times of the power switches Q1 - Q4 .

[0063] In the prior art, the synchronization of the resonant current ILf and the drive signals for the power switches Q1-Q4 uses multiple analog circuits (e.g., phase-locked loops). However, the analog circuit approach has significant limitations, and when the parameters change, the corresponding analog circuit parameters need to be modified.

[0064] The present application uses a digital logic circuit to synchronize the drive signal of the resonant circuit and the power switch tube, simplifies the circuit, and achieves more accurate drive signal generation, which is described in detail below.

[0065] like Figure 1 As shown, the zero-crossing detector is used to detect the output resonant current I1 ( Figure 1 ILf) performs zero-crossing detection to generate a zero-crossing square wave signal S (also referred to as a synchronization signal in this article).

[0066] The zero-crossing detector responds to the zero-crossing of the AC current I1 and causes the zero-crossing square wave signal S to jump, as shown in FIG. Figure 2 shown.

[0067] The zero-crossing detector inputs the generated square wave signal S to the processor, and the processor processes the zero-crossing square wave signal S to generate driving signals for Q1 , Q2 , Q3 and Q4 , as described below.

[0068] The processor can be a CPLD (Complex Programmable Logic Device) or an FPGA (Field Programmable Gate Array).

[0069] When the circuit is initially started, the period of the resonant current I1 fluctuates, so the synchronization signal (ie, the zero-crossing square wave signal S) obtained based on the resonant current I1 is not accurate. Therefore, the synchronization signal needs to be obtained after the period of the resonant current I1 stabilizes.

[0070] According to aspects of the present disclosure, each rising edge of the zero-crossing square wave signal S may be detected, and the time length L(i) between adjacent rising edges may be determined.

[0071] The two adjacent time lengths L(i-1) and L(i) can then be substituted into the following equation to determine whether the equation holds:

[0072] L(i)=αL(i)+(1-α)L(i-1) (1)

[0073] Where 0<α<1.

[0074] If equation (1) holds true, it means that the time length between adjacent rising edges of the square wave signal S has stabilized, and thus the period of the corresponding resonant current I1 has stabilized. Therefore, L(i) can be determined as the period of the resonant current for subsequent synchronization operations of the drive signal.

[0075] The synchronous counter CNTS can then be driven using the square wave signal S to generate a count signal. Specifically, the count signal of the synchronous counter CNTS can count the square wave signal S and be cleared in response to counting to its maximum count value and detecting a rising edge of the square wave signal S.

[0076] exist Figure 2 In the example, the maximum count value of the synchronous counter CNTS is 1, so the period of the counting signal of the synchronous counter CNTS is the same as the period of the square wave signal S, for example, the period is L(i) satisfying formula (1).

[0077] If the maximum count value is N, the period of the count signal of the synchronous counter CNTS is N times the period of the square wave signal S, for example, the period is N*L(i).

[0078] Furthermore, since the synchronous counter CNTS has the function of a hysteresis comparator, it is possible to avoid the disturbance of the counting caused by the burr signal in the square wave signal S.

[0079] In the solution of the present disclosure, an enable instruction EN (e.g., Figure 3 EN in the ). Figure 3 As shown, at time t EN Generate enable instruction, at t EN After that, the enable signal is at a high level.

[0080] In response to the enable instruction EN, the processor starts to generate driving signals for the power switches Q1 - Q4 according to the counting signal of the synchronous counter CNTS.

[0081] The driving signal of the first power switch tube Q1 is complementary to the driving signal of the second power switch tube Q2 (that is, there is a pair of driving signals of Q1 and Q2 within one cycle of the resonant current), and the driving signal of the third power switch tube Q3 is complementary to the driving signal of the fourth power switch tube Q4.

[0082] In one aspect of the present disclosure, a counter CNTA can be used to generate a drive signal for the first power switch tube Q1 and a drive signal for the second power switch tube Q2, and another counter CNTB can be used to generate a drive signal for the third power switch tube Q3 and a drive signal for the fourth power switch tube Q4.

[0083] In tEN Afterwards (ie, after the enable instruction EN is generated), in response to the clearing of the synchronization counter CNTS, at time t A , starts the counter CNTA. In other words, in response to the EN enable signal being high and CNTS being cleared, the counter CNTA is started to generate counting signals for the first power switch tube Q1 and the second power switch tube Q2. The period of the counter CNTA is the same as the period of CNTS, as shown in FIG. Figure 3 shown.

[0084] The counter CNTB is activated after the counter CNTA is started for a time period of Δt=t B -t A Then, the counter CNTB is started to generate a counting signal for generating a driving signal for the third power switch Q3 and the fourth power switch Q4. That is, the phase difference between the counter CNTB and the counter CNTA (and the counter CNTS) is Δt. The period of the counter CNTB is the same as that of the CNTS.

[0085] The difference (phase difference) Δt between the start-up times of counters CNTA and CNTB is determined by the effective duty cycle of the output voltage. By adjusting Δt, the output power of the rectifier can be adjusted.

[0086] The count signals of counters CNTA and CNTB can be used as references to generate drive signals for power switches Q1-Q4. Specifically, the count signal of counter CNTA can be used as a reference to generate drive signals for Q1 and Q2, and the count signal of counter CNTB can be used as a reference to generate drive signals for Q3 and Q4.

[0087] Figure 4 FIG shows a timing diagram of generating the driving signals of Q1 and Q2 using the counting signal of the counter CNTA as a reference. Figure 4 As shown, the driving signals of Q1 and Q2 are complementary, that is, one driving signal of Q1 and Q2 is included in one cycle of CNTA. In other words, a pair of driving signals of Q1 and Q2 is included in one cycle of CNTA.

[0088] Furthermore, the periods of the driving signals of Q1 and Q2 are the same as that of the counter CNTA.

[0089] There can be an interval between the drive signals for Q1 and Q2, i.e., t2-t1. This interval is the dead time between the drive signals for Q1 and Q2, preventing Q1 and Q2 from being turned on at the same time, causing a short circuit and damaging the system.

[0090] The driving signals of Q3 and Q4 can be generated in the same manner using the counting signal of the counter CNTB as a reference, which will not be described in detail here.

[0091] Figure 5 is a flow chart of a method for wireless charging according to aspects of the present disclosure.

[0092] The method is applied to a wireless charging system, which includes a primary subsystem and a secondary subsystem. The secondary subsystem includes a secondary inductor, an impedance matching circuit, and a rectifier. The rectifier includes a first power switch tube, a second power switch tube, a third power switch tube, and a fourth power switch tube. The first power switch tube and the second power switch tube form the left bridge arm of a phase-shifted full-bridge circuit, and the third power switch tube and the fourth power switch tube form the right bridge arm of the phase-shifted full-bridge circuit. Figure 1 As shown in .

[0093] In step 502, a resonant current may be obtained from an impedance matching circuit.

[0094] At step 504 , a zero crossing of the resonant current may be detected.

[0095] At step 506 , a zero-crossing square wave signal may be generated based on the detected zero-crossing point, wherein the zero-crossing square wave signal transitions in response to the zero-crossing point of the resonant current.

[0096] In step 508 , the period of the resonant current may be acquired based on the zero-crossing square wave signal.

[0097] Specifically, the rising edge of the square wave in the zero-crossing square wave signal can be captured; the time length L(i) between the rising edges of two adjacent square waves can be determined; and L(i) can be determined as the period of the resonant current when L(i) satisfies the following formula:

[0098] L(i)=αL(i)+(1-α)L(i-1),

[0099] Where 0<α<1.

[0100] In step 510 , an enable instruction may be generated in response to obtaining the period of the resonant current to generate drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube according to the zero-crossing square wave signal.

[0101] In one aspect, the driving signal of the first power switch tube is complementary to the driving signal of the second power switch tube, and the driving signal of the third power switch tube is complementary to the driving signal of the fourth power switch tube.

[0102] In one aspect, the phase difference between the driving signal of the first power switch tube and the driving signal of the third power switch tube may be determined according to the duty cycle of the output voltage.

[0103] In one aspect, a synchronous counter may be used to count the square waves of the zero-crossing square wave signal, wherein a synchronization signal of the synchronous counter is cleared in response to the count reaching its maximum count value and detecting a rising edge of the square wave of the zero-crossing square wave signal. Furthermore, drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube may be generated based on the synchronization signal of the synchronous counter.

[0104] Figure 6 is a diagram of a wireless charging system according to aspects of the present disclosure.

[0105] The wireless charging system includes a primary side subsystem and a secondary side subsystem.

[0106] The primary subsystem can obtain electrical energy from the grid and convert the electrical energy into magnetic field energy through the primary inductor Lp, so as to be transmitted to the secondary inductor Ls of the secondary subsystem.

[0107] The secondary subsystem may include a secondary inductor 602 , an impedance matching circuit 604 , a rectifier 606 , a zero-crossing detector 608 , and a processor 610 .

[0108] The impedance matching circuit 604 may include a compensation capacitor Cs of the secondary inductor Ls, a parallel resonant inductor Lf and a capacitor Cf, such as Figure 1 As shown in .

[0109] The rectifier 606 may include a first power switch tube Q1, a second power switch tube Q2, a third power switch tube Q3, and a fourth power switch tube Q4, wherein the first power switch tube and the second power switch tube constitute the left bridge arm of the phase-shifted full-bridge circuit, and the third power switch tube and the fourth power switch tube constitute the right bridge arm of the phase-shifted full-bridge circuit.

[0110] The zero-crossing detector 608 may be configured to obtain the resonant current from the impedance matching circuit and detect a zero-crossing point of the resonant current.

[0111] The processor 610 may be configured to receive the detected zero-crossing point from the zero-crossing detector 608 , and generate a zero-crossing square wave signal based on the detected zero-crossing point, wherein the zero-crossing square wave signal transitions in response to the zero-crossing point of the resonant current.

[0112] The processor 610 may be further configured to obtain a period of the resonant current based on the zero-crossing square wave signal.

[0113] Specifically, the processor 610 may be configured to capture a rising edge of a square wave in a zero-crossing square wave signal; determine a time length L(i) between rising edges of two adjacent square waves; and determine L(i) as the period of the resonant current when L(i) satisfies the following equation:

[0114] L(i)=αL(i)+(1-α)L(i-1),

[0115] Where 0<α<1.

[0116] The processor 610 may be further configured to generate an enable instruction in response to obtaining the period of the resonant current to generate drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube according to the zero-crossing square wave signal.

[0117] The processor 610 can be further configured to: use a synchronous counter to count the square wave of the zero-crossing square wave signal, wherein the synchronization signal of the synchronous counter is cleared in response to counting to its maximum count value and detecting the rising edge of the square wave of the zero-crossing square wave signal; and generate drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube according to the synchronization signal of the synchronous counter.

[0118] The driving signal of the first power switch tube is complementary to the driving signal of the second power switch tube, and the driving signal of the third power switch tube is complementary to the driving signal of the fourth power switch tube.

[0119] The processor 610 may be further configured to determine a phase difference between a driving signal of the first power switch Q1 and a driving signal of the third power switch Q3 according to a duty cycle of the output voltage.

[0120] The processor 610 may send the generated driving signal to the rectifier 606 .

[0121] The rectifier 606 can drive the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 according to the driving signal from the processor 610 to generate a DC voltage according to the resonant current from the impedance matching circuit 604 for charging the battery.

[0122] Compared with the prior art method of using analog circuits (e.g., phase-locked loops) to synchronize the drive signal of the power switch tube with the period of the resonant current, the present application uses digital circuits (e.g., using formula (1)) to obtain the period of the resonant current, which greatly reduces the number of analog hardware devices and simplifies the circuit structure. Furthermore, the present application generates an enable instruction for the drive signal when obtaining the period of the resonant current, thereby enabling the drive signal for the power switch tube to be generated only after the period of the resonant current is stabilized, further saving the power of the circuit. The present application utilizes the function of the hysteresis comparator in the counter to reduce the probability of false triggering.

[0123] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that can be implemented or fall within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and does not mean "better than" or "better than other examples." This detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0124] In the accompanying drawings, similar components or features may have the same reference number. In addition, components of the same type may be distinguished by following the reference number with a dash and a second reference number that distinguishes between the similar components. If only the first reference number is used in the specification, the description applies to any of the similar components having the same first reference number, regardless of the second reference number.

[0125] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or executed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0126] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, each function may be stored on or transmitted by a computer-readable medium as one or more instructions or code. Other examples and implementations fall within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features that implement the functions may also be physically located in various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0127] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the universal principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for a wireless charging system, the wireless charging system comprising a primary subsystem and a secondary subsystem, the secondary subsystem comprising a secondary inductor, an impedance matching circuit, and a rectifier, the rectifier comprising a first power switch tube, a second power switch tube, a third power switch tube, and a fourth power switch tube, the first power switch tube and the second power switch tube forming a left arm of a phase-shifted full-bridge circuit, and the third power switch tube and the fourth power switch tube forming a right arm of the phase-shifted full-bridge circuit, the method comprising: Obtaining a resonant current from the impedance matching circuit; detecting a zero-crossing point of the resonant current; generating a zero-crossing square wave signal based on the detected zero-crossing point, wherein the zero-crossing square wave signal transitions in response to the zero-crossing point of the resonant current; acquiring a period of the resonant current based on the zero-crossing square wave signal; Generating an enable instruction in response to obtaining the period of the resonant current to generate drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube according to the zero-crossing square wave signal, including: counting the square wave of the zero-crossing square wave signal using a synchronous counter, wherein the synchronous signal of the synchronous counter is cleared in response to counting to its maximum count value and detecting a square wave rising edge of the zero-crossing square wave signal; and In response to the generation of the enable instruction, generating drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube according to the synchronization signal of the synchronization counter; Wherein obtaining the period of the resonant current based on the zero-crossing square wave signal includes: Capturing a rising edge of a square wave in the zero-crossing square wave signal; Determine the time length L(i) between the rising edges of two adjacent square waves; When L(i) satisfies the following formula, it is determined that the period of the resonant current has stabilized and L(i) is determined as the period of the resonant current: ， in .

2. The method according to claim 1, wherein the driving signal of the first power switch tube and the driving signal of the second power switch tube are complementary, and the driving signal of the third power switch tube and the driving signal of the fourth power switch tube are complementary. 3 . The method according to claim 1 , further comprising determining a phase difference between the driving signal of the first power switch tube and the driving signal of the third power switch tube according to a duty cycle of the output voltage.

4. A wireless charging device, comprising a secondary subsystem comprising a secondary inductor, an impedance matching circuit, a rectifier, a zero-crossing detector, and a processor; the rectifier comprising a first power switch tube, a second power switch tube, a third power switch tube, and a fourth power switch tube; the first power switch tube and the second power switch tube forming a left arm of a phase-shifted full-bridge circuit, and the third power switch tube and the fourth power switch tube forming a right arm of the phase-shifted full-bridge circuit; wherein the zero crossing detector is configured to: Obtaining a resonant current from the impedance matching circuit; detecting a zero-crossing point of the resonant current; wherein the processor is configured to: generating a zero-crossing square wave signal based on the detected zero-crossing point, wherein the zero-crossing square wave signal transitions in response to the zero-crossing point of the resonant current; acquiring a period of the resonant current based on the zero-crossing square wave signal; Generating an enable instruction in response to obtaining the period of the resonant current to generate drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube according to the zero-crossing square wave signal, including: counting the square wave of the zero-crossing square wave signal using a synchronous counter, wherein the synchronous signal of the synchronous counter is cleared in response to counting to its maximum count value and detecting a square wave rising edge of the zero-crossing square wave signal; and In response to the generation of the enable instruction, generating drive signals for the first power switch tube, the second power switch tube, the third power switch tube, and the fourth power switch tube according to the synchronization signal of the synchronization counter; Wherein obtaining the period of the resonant current based on the zero-crossing square wave signal includes: Capturing a rising edge of a square wave in the zero-crossing square wave signal; Determine the time length L(i) between the rising edges of two adjacent square waves; When L(i) satisfies the following formula, it is determined that the period of the resonant current has stabilized and L(i) is determined as the period of the resonant current: ， in .

5. The wireless charging device according to claim 4 , wherein the driving signal of the first power switch tube is complementary to the driving signal of the second power switch tube, and the driving signal of the third power switch tube is complementary to the driving signal of the fourth power switch tube.

6. The wireless charging device of claim 4, wherein the processor is further configured to determine a phase difference between a drive signal of the first power switch tube Q1 and a drive signal of the third power switch tube Q3 according to a duty cycle of an output voltage.

7. A motor vehicle comprising the wireless charging device according to any one of claims 4 to 6.

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